Semiconductor stress sensor

Abstract

This application discloses a semiconductor stress sensor. A piezoresistive sensor (100) includes: diffusions (104) of a first conductivity type in a well (118) of a second type; contacts (114) to islands (110) in the diffusions; interconnections (112) to the contacts; a shield (108) covering the diffusions between the contacts and extending beyond sidewalls of the diffusions between the contacts, each interconnection covering the diffusion at a corresponding contact and extending beyond an edge of the diffusion, each island being located on a side covered by its interconnection; a guard ring (102) of the second type surrounding the diffusion, the shield covering the well between the diffusion and the ring and an edge of the ring facing the diffusion, if there is a gap between the shield and the interconnection, the ring bridging the gap, and / or the edge of the diffusion being completely covered by a combination of the shield and the interconnection.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor stress sensing elements. More specifically, it relates to a stress sensor based on a piezoresistor. Background Art

[0002] A semiconductor stress sensing element includes opposing diffusion paths of a first conductivity type defined in a lightly doped well of a second conductivity type. The section in the diffusion path that must be sensitive to stress is lightly doped, while other parts that should not be stress sensitive are highly doped or even composed of a metal silicon alloy. The sheet resistance of the diffusion path is inversely proportional to the doping level. The sheet resistance of the lightly doped diffusion path is typically between 300 and 5000 ohms per square, while the sheet resistance of the highly doped region is typically between 20 and 150 ohms per square. When an alloy is formed on the surface of the highly doped region, the sheet resistance even drops to only 1 to 5 ohms per square. A typical highly doped or metal silicon alloy section is placed between the stress-sensitive lightly doped part and the interconnect to avoid stress modulation generated by the interconnect.

[0003] Such semiconductor stress sensing elements are modulated by an external electric field generated by surface charges.

[0004] The first modulation method is that surface charges located directly above the lightly doped diffusion path modulate the lightly doped section of the diffusion path.

[0005] The second modulation method is that charges located above the well next to the entire diffusion path can generate sufficient inversion on the well surface to provide leakage from one point of the diffusion path with a higher voltage to another point of the diffusion path with a lower voltage or even to another diffusion path of another resistor.

[0006] The first method of applying a conductive shield is to cover the entire piezoresistor (including the interconnect contacts) with metal. This conductive shield can not only prevent the modulation of the piezoresistor but also prevent leakage due to inversion next to the piezoresistor. This method is used in Patent Publication US9557237B2.

[0007] However, the disadvantage of this solution is that a second metal shield layer must be placed above the interconnect to cover it. This involves additional processing work. Another disadvantage is that the farther the piezoresistor is from the surface, the more significant the loss of sensitivity.

[0008] Another method is to use a shallow diffused piece covering the relatively conductive types of all piezoresistors, which is detailed in US20150008544A1. In this case, doping is restricted to avoid inversion of the shallow shielding diffused piece, otherwise breakdown will occur between the piezoresistor and the shield. Therefore, this solution will fail due to very high surface charges. Another problem is that the gap between the shielding layer and the highly doped p-diffusion layer can still provide a path for leakage current to other structures.

[0009] In some prior arts, a shielding metal is provided along the interconnect path to avoid the need for a second metal layer. An example is illustrated in US9790085. However, in this case, the metal is disposed above the film, resulting in drift due to plastic deformation of the metal, and inversion will occur again between the metal wires, which still provides a path for leakage from one resistor to another.

[0010] Therefore, it is necessary to shield the semiconductor stress sensor to avoid leakage current. Summary of the Invention

[0011] An object of embodiments of the present invention is to provide a good piezoresistor-based sensor.

[0012] The above object is achieved by the method and device according to the present invention.

[0013] Embodiments of the present invention relate to a piezoresistor-based sensor. The sensor includes at least one sensing element partially or completely disposed on a flexible structure. The sensing element includes:

[0014] At least one piezodiffusion region of a first conductivity type in a well of a second conductivity type, the second conductivity type being different from the first conductivity type,

[0015] Two or more contacts in electrical contact with an island in the piezodiffusion region, the piezodiffusion region extending between the two or more contacts, wherein the island has a doping of the first conductivity type higher than that of the piezodiffusion region,

[0016] A conductive interconnect structure for each contact for electrically biasing the piezodiffusion region through the contact.

[0017] In addition, the sensing element includes a conductive shield that covers the piezodiffusion region between the contacts and extends beyond the sidewalls of the piezodiffusion region between the contacts.

[0018] Each conductive interconnect structure covers the piezodiffusion region at the corresponding contact and extends beyond the edge of the piezodiffusion region at the corresponding contact.

[0019] Each island is covered on one side by its corresponding conductive interconnect structure.

[0020] In an embodiment of the present invention, the sensing element includes a guard ring of the second conductivity type surrounding the piezoelectric diffusion region, with a distance between the guard ring and the piezoelectric diffusion region. The conductive shield covers the well between the piezoelectric diffusion region and the guard ring and the edge of the guard ring facing the piezoelectric diffusion region, and wherein. If there is a gap between the conductive shield and the interconnect structure, the guard ring bridges the gap.

[0021] The guard ring is not necessarily required. In an alternative embodiment of the present invention, the edge of the piezoelectric diffusion region is completely covered by the combination of the conductive shield and the interconnect structure.

[0022] An advantage of the embodiment of the present invention is that it can prevent leakage current that may occur between adjacent piezoelectric diffusion regions due to bulk inversion between these piezoelectric diffusion regions.

[0023] This is achieved by providing an electrical contact in the piezoelectric diffusion region that contacts the highly doped island, wherein the sensor also has a guard ring extending from below the conductive shield to below the interconnect, wherein, if there is a gap between the shield and the interconnect, the ring bridges the gap, or wherein the edge of the piezoelectric diffusion region between the interconnect structures is completely covered by the shield.

[0024] An advantage of the embodiment of the present invention is the modulation caused by the charge above the well region next to the piezoelectric diffusion region, which generates sufficient inversion on the well surface to provide leakage from a point on a diffusion path with a higher voltage to another point on a diffusion path with a lower voltage or even to another diffusion path of another resistor, which can occur in the absence of a guard ring and can be reduced by providing a guard ring to prevent the inversion.

[0025] The shielding region can be formed in the flexible structure or can be above the flexible structure.

[0026] In an embodiment of the present invention, the distance between the guard ring and the piezoelectric diffusion region is less than 5 μm.

[0027] In an embodiment of the present invention, the distance can even be less than 2 μm. In an embodiment of the present invention, the distance between the guard ring and the piezoelectric diffuser is preferably as small as possible but large enough to prevent breakdown. In an embodiment of the present invention, the distance can be, for example, in the range of 1 μm to 5 μm.

[0028] In an embodiment of the present invention, the conductive shield is electrically connected to the guard ring.

[0029] Keeping the shield floating will allow it to charge and then cause leakage or resistor modulation. Therefore, it is in contact with a stable voltage. By definition, the guard ring always has the substrate voltage and is low-ohmic, so it is a very stable voltage that is always present. This minimizes the interconnection of the shield. In the case of an n+ shield, no contacts are required. Such a shield can only be at the same voltage as the well or the guard ring.

[0030] In an embodiment of the present invention, the conductive shield is made of the same material as the conductive interconnect structure, and wherein the conductive shield is isolated from the conductive interconnect structure.

[0031] An advantage of the embodiment of the present invention is that the conductive shield and the conductive interconnect structure can be made of the same material and can be obtained using the same process steps.

[0032] In an embodiment of the present invention, the conductive shield is separated from the conductive interconnect structure by a gap of at least 10 μm.

[0033] In an embodiment of the present invention, the gap can be greater than 20 μm, even greater than 50 μm.

[0034] In an embodiment of the present invention, each island extends from its corresponding conductive interconnect structure to the conductive shield such that at least a portion of it is covered by the conductive shield.

[0035] An advantage of the embodiment of the present invention is that piezoelectric diffusion modulation can be reduced by adding highly doped islands that extend such that they are covered by the conductive interconnect structure on one side and by the conductive shield on the other side.

[0036] In an embodiment of the present invention, the conductive interconnect structure covers a portion of the well between the guard ring and the piezoelectric diffusion region.

[0037] Since there must be isolation between the interconnect structures, the interconnect structures cannot cover the entire well. In an embodiment of the present invention, the interconnect structures cover the well outside the flexible structure. The flexible structure can be, for example, a membrane, where the membrane is part of the sensor and has a reduced thickness to enable stress measurement.

[0038] Advantageously, the interconnect (which can be metal, for example) is not present on the membrane because this can cause drift due to plastic deformation of the metal.

[0039] In an embodiment of the present invention, the piezoelectric diffusion region has approximately the same electric potential as the conductive interconnect structure.

[0040] In an embodiment of the present invention, the conductive shield is made of a material different from that of the conductive interconnect structure.

[0041] In an embodiment of the present invention, the conductive shield covers the piezoelectric diffusion region, except for the islands.

[0042] In an embodiment of the present invention, the conductive shield covers the piezoelectric diffusion region, except for the islands and the spacing around the islands.

[0043] For example, for an n-type shield, polysilicon CMOS, it is required that the spacing around the islands is also not covered by the shield.

[0044] In an embodiment of the present invention, the conductive shield covers the entire well between the piezoelectric diffusion regions and covers the edge of the guard ring facing the piezoelectric diffusion region.

[0045] In an embodiment of the present invention, the conductive shield includes a lightly doped region of a second conductivity type.

[0046] In an embodiment of the present invention, the conductive shield is made of polysilicon.

[0047] Specific and preferred aspects of the present invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be combined appropriately with the features of the independent claims and with the features of other dependent claims, not only as explicitly set forth in the claims.

[0048] These and other aspects of the present invention will be apparent from the (multiple) embodiments described hereinafter, and these and other aspects of the present invention are elucidated with reference to these embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A top view of a piezoresistor-based sensor including an n-type conductive shield according to an embodiment of the present invention is shown.

[0050] Figure 2 A cross-section of a piezoresistor-based sensor including an n-type conductive shield according to an embodiment of the present invention is shown.

[0051] Figure 3 A layout of a dual-resistor-based sensor including an n-type conductive shield according to an embodiment of the present invention is shown.

[0052] Figure 4 A top view of a piezoresistor-based sensor including a CMOS polysilicon shield according to an embodiment of the present invention is shown.

[0053] Figure 5 A cross-section of a piezoresistor-based sensor including a CMOS polysilicon shield according to an embodiment of the present invention is shown.

[0054] Figure 6Shows the layout of a dual-resistor-based sensor including a CMOS polycrystalline shield according to an embodiment of the present invention.

[0055] Figure 7 Shows a top view of a piezoresistor-based sensor including a non-CMOS polycrystalline shield according to an embodiment of the present invention.

[0056] Figure 8 Shows a cross-section of a piezoresistor-based sensor including a non-CMOS polycrystalline shield according to an embodiment of the present invention.

[0057] Figure 9 Shows the layout of a dual-resistor-based sensor including a non-CMOS polycrystalline shield according to an embodiment of the present invention.

[0058] Figure 10 Shows a top view of a piezoresistor-based sensor including a single metal shield according to an embodiment of the present invention.

[0059] Figure 11 Shows a cross-section of a piezoresistor-based sensor including a single metal shield according to an embodiment of the present invention.

[0060] Figure 12 Shows the layout of a dual-resistor-based sensor including a single metal shield according to an embodiment of the present invention.

[0061] Figure 13 Shows a top view of an alternative piezoresistor-based sensor without a guard ring and including an n-type conductive shield according to an embodiment of the present invention.

[0062] Figure 14 Shows a cross-section of an alternative piezoresistor-based sensor without a guard ring and including an n-type conductive shield according to an embodiment of the present invention.

[0063] Figure 15 Shows a top view of an alternative dual-resistor-based sensor without a guard ring and including an n-type conductive shield according to an embodiment of the present invention.

[0064] Any reference signs in the claims shall not be construed as limiting the scope.

[0065] In different drawings, the same reference signs refer to the same or similar elements. Detailed Description

[0066] The present invention will be described with reference to specific embodiments and specific drawings, but the present invention is not limited thereto and is only defined by the claims. The described drawings are only schematic and non-limiting. In the drawings, for illustrative purposes, the dimensions of some of the elements may be enlarged and not drawn to scale. The scales and relative scales do not correspond to the actual reduction in the practice of the present invention.

[0067] It should be noted that the term "comprising" used in the claims should not be construed as being limited to the devices listed thereafter; it does not exclude other elements or steps. Thus, this term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of a statement of an apparatus "comprising apparatus A and apparatus B" should not be limited to an apparatus consisting only of components A and B. It means that the only relevant components of the apparatus for the purposes of the present invention are A and B.

[0068] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, as will be apparent to those of ordinary skill in the art through the present disclosure, the particular features, structures, or characteristics can be combined in any suitable manner.

[0069] Similarly, it should be understood that in the description of the exemplary embodiments of the present invention, for the purpose of streamlining the present disclosure and facilitating the understanding of one or more of the various inventive aspects, the various features of the present invention are sometimes grouped together in a single embodiment, drawing, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the inventive aspects lie in less than all of the features of a single foregoing disclosed embodiment. Thus, the appended claims following the detailed description are hereby expressly incorporated into the detailed description, where each claim itself represents a separate embodiment of the present invention.

[0070] In addition, although some of the embodiments described herein include some features included in other embodiments but not other features included in other embodiments, as will be understood by those skilled in the art, combinations of features of different embodiments are intended to fall within the scope of the present invention and form different embodiments. For example, in the appended claims, any of the claimed embodiments can be used in any combination.

[0071] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other examples, well-known methods, structures, and techniques are not shown in detail to avoid confusing the understanding of this description.

[0072] In embodiments of the invention where a well of the second conductivity type is mentioned, what is mentioned is a well or bulk having a doping opposite to the doping of the piezoelectric diffusion region. The well may be, for example, a p-type well in an n-type substrate, or may be, for example, a p-type substrate in which an n-type piezoelectric diffusion region is present.

[0073] In the introduction, different modulation methods are cited. The first modulation method can be completely suppressed by providing a conductive shield over the low-doped section of the diffusion path.

[0074] The second modulation method can only be completely suppressed by providing a conductive shield covering all edges of the entire diffusion path.

[0075] A third modulation method is that the charges above the well next to the diffusion path can cause an inversion and allow holes to flow from the diffusion path into the well, then recombine and cause leakage current to the substrate. This effect is small because it depends on the concentration difference of holes in the piezoelectric diffuser layer and the inversion layer. For very strong inversion holes can even flow from the well into the diffuser.

[0076] A conductive shield should be provided covering the entire diffusion path and all its edges, where:

[0077] a) is not electrically connected to the sensor's interconnect, but is electrically connected to the substrate,

[0078] b) does not reduce sensitivity by adding additional layers above the sensor membrane,

[0079] c) will not change its internal stresses over time (e.g., metal creep, plastic deformation) causing long-term drift.

[0080] Embodiments of the present invention relate to sensors based on piezoresistors. A schematic diagram of a sensor based on piezoresistors according to an embodiment of the present invention is shown in FIG. Figures 1 to 12 The reference numerals in the specification refer to the reference numerals in these figures. The sensor 100 includes at least one sensing element disposed on a flexible structure. The sensing element includes:

[0081] at least one piezoelectric diffusion region 104 of a first conductivity type in a well 118 of a second conductivity type, the second conductivity type being different from the first conductivity type;

[0082] Two or more contacts 114 that are in electrical contact with the islands 110 in the piezoelectric diffusion region 104, the piezoelectric diffusion region 104 extending between the two or more contacts 114, and the islands 110 having a doping of a first conduction type that is higher than the doping of the piezoelectric diffusion region 104; there are at least two islands 110 and each island has at least one contact 114;

[0083] A conductive interconnect structure 112 for each contact 114, for electrically biasing the piezoelectric diffusion region 104 through the contact 114,

[0084] Conductive shields 108, 208, 308 that cover the piezoelectric diffusion region 104 between the contacts 114 and extend beyond the sidewalls of the piezoelectric diffusion region 104 between the contacts 114, and each conductive interconnect structure 112 covers the piezoelectric diffusion region 104 at the corresponding contact and extends beyond the edge of the piezoelectric diffusion region 104 at the corresponding contact, and each island 110 is covered by its corresponding conductive interconnect structure 112 on one side.

[0085] Furthermore, in an embodiment of the present invention, the sensing element further includes a guard ring 102 of a second conduction type surrounding the piezoelectric diffusion region 104, there is a distance 103 between the guard ring 102 and the piezoelectric diffusion region 104, wherein the conductive shields 108, 208, 308 cover the well between the piezoelectric diffusion region 104 and the guard ring 102 and the edge of the guard ring 102 facing the piezoelectric diffusion region 104, and wherein if there is a gap between the conductive shields 108, 208, 308 and the interconnect structure 112, the guard ring 102 bridges the gap. This is particularly advantageous when the conductive shields 208 and the interconnect structure 112 are made of the same conductive layer. In this case, a gap is required between the conductive shield and the interconnect structure. In an embodiment of the present invention, the guard ring is present where the conductive shield and the interconnect structure do not overlap. The distance between the guard ring 102 and the piezoelectric diffusion region 104 is not necessarily constant. It can vary along the edge of the piezoelectric diffuser.

[0086] In an alternative embodiment of the present invention, the edge of the piezoelectric diffusion region 104 is completely covered by a combination of the conductive shields 108, 308 and the interconnect structure 112. This is particularly advantageous when the conductive shields 108, 308 and the interconnect structure 112 are made of different conductive layers. In this case, the conductive shields are extended such that no edge of the piezoelectric diffusion region 104 is not covered. In these embodiments, the guard ring is not necessary. In the case where the interconnect structure is made of a different layer from the conductive shield, the interconnect structure can overlap with the conductive shield. In this case, there is no gap that must be bridged by the guard ring.

[0087] In both cases (the guard ring case and the full coverage case), leakage current between piezoresistive regions is prevented by preventing body inversion.

[0088] According to an embodiment of the present invention, a piezoelectric-based sensor includes a diffusion path 104 of a first conductivity type on a well 118 of a second conductivity type, wherein the diffusion path includes a highly doped island 110 of the first conductivity type and a lightly doped region for stress sensing. The diffusion path is located in a lightly doped well / bulk 118 of opposite doping.

[0089] The island has a doping of the first conductivity type that is higher than the doping of the piezoelectric diffusion region. In an embodiment of the present invention, silicide can be implemented in the highly doped island to reduce sheet resistance. In an embodiment of the present invention, the doping level of the island is such that its combination with silicide metal doping provides a sheet resistance of less than 150 ohms per square or even less than 5 ohms per square, while the doping level of the piezoresistive portion of the piezoelectric diffuser preferably provides a sheet resistance of higher than 300 ohms per square to obtain sufficient sensitivity.

[0090] In an embodiment of the present invention, the island is formed inside the piezoelectric diffuser, and its outer edge is separated from the edge of the piezoelectric diffuser (i.e., the distance from the sidewall of the piezoelectric diffuser) by a minimum distance 109. This distance is typically between 1 μm and 10 μm, and should be large enough such that the edge of the shield can be implemented outside the island and still inside the piezoelectric diffuser. This distance is typically between 1 μm and 10 μm because at greater distances, capacitance and leakage current will increase but sensitivity will not increase, and at distances less than 1 μm, the breakdown voltage between the piezoelectric diffuser and the bulk will decrease.

[0091] In addition to the shielding structure, protection against the second modulation method is provided by providing a guard ring 102 of the second conductivity type tightly surrounding the diffusion path / piezoresistor 104, in particular by making inversion in this ring 102 impossible. In an embodiment of the present invention, the proposed guard ring structure 102 introduces a solution that does not provide shielding but makes the region immune to inversion. In an embodiment of the present invention, a specific combination of a guard ring and a shield is formed. When the well between the piezoelectric diffusion region and the guard ring is not covered, charges or a vertical electric field above this region can generate charges in this well, which can generate a parasitic current parallel to the diffusion region and thus modulate the resistance of the diffusion region. Therefore, shielding this region makes the resistor more stable. The guard ring ensures that the current must remain within this region, but the current can still flow parallel to the guard ring between the guard ring and the piezoelectric diffuser, thereby reducing the actual piezoresistance.

[0092] In an embodiment of the present invention, the guard ring 102 is highly doped or even has a silicon-metal alloy such that inversion does not occur in this layer. Then, the inversion caused by surface charges that would provide a leakage path from one piezoelectric element to another piezoelectric element will stop at the guard ring 102 and can only flow in the minimum space between the guard ring and the piezoelectric diffuser.

[0093] As disclosed previously, the guard ring 102 is not necessary in all embodiments of the present invention but can provide additional protection. Thus, in the following description, two cases are described for 4 different embodiments that relate to limitations of available features during the manufacturing process.

[0094] In an embodiment of the present invention, typically more than 90% of the resistance is generated by the lower doped section of the diffusion path 104 (also referred to as the piezoelectric diffusion region). Thus, the leakage current parallel to the p++ section is very small compared to the main current (e.g., the p++ section) through the highly doped island 110 because the resistance of the island 110 is typically 20 times lower than the resistance of the diffusion path 104. Therefore, the leakage current in the region having length 106 and width 116 can be neglected compared to the current in the adjacent highly doped island 110 (e.g., this can be the p++ portion).

[0095] In some embodiments of the present invention, the conductive shield 108 can be formed of a different layer than the conductive interconnect structure 112. In such embodiments, the interconnect structure 112 can be provided as a second conductive layer. They can be formed, for example, of a metal layer. They are located above the conductive shield, which is provided as a first conductive layer. The interconnect structure 112 is used for at least the contact layer from / to the piezoelectric diffuser layer 104. In such embodiments, silicide can be implemented in the highly doped island 110 (e.g., the p++ region) within the piezoelectric diffusion region 104 to reduce its resistance and thus improve the performance of the sensor. In an embodiment of the present invention, the conductive shield can be formed such that it does not cover the silicide. In an embodiment of the present invention, more specifically, in those embodiments where the conductive shield 108 does not cover the island 110, these islands are formed inside the piezoelectric diffuser such that they are separated from the sidewall of the piezoelectric diffuser by a distance 109. In an embodiment of the present invention, the breakdown voltage is determined by the doping level of the diffusion facing the bulk (e.g., p diffusion). Thus, the breakdown voltage defined by the piezoelectric diffusion layer 104 can be maintained by providing islands (e.g., p++ islands) with an increased doping level in the diffusion region and maintaining a distance 109 between the islands with the increased doping level and the edge of the diffusion region. Without this distance, the breakdown voltage would be significantly reduced.

[0096] In an embodiment of the present invention, the outer edge of the piezoelectric diffusion layer 104 is covered by a shielding member. Note that shielding the edge of the piezoelectric diffusion member or providing silicide for an island (e.g., p++ island) does not significantly change the breakdown voltage.

[0097] In an embodiment of the present invention, the first conduction type may be p-type and the second conduction type may be n-type, or the first conduction type may be n-type and the second conduction type may be p-type.

[0098] In the following example, it is assumed that the first conduction type is p-type and the second conduction type is n-type. In this case, the conductive shielding member may be, for example, an n-type conductive shielding member. Thus, shielding using a p-n junction (n-type shielding) is obtained. Figures 1 to 3 Examples thereof are given. The n-doped layer 108 covering the piezoelectric diffusion member 104 is the first conductive layer 108 providing the shielding function. In this example, a p++ region with or without silicide exists inside the piezoelectric diffusion member, and the outer edge of the piezoelectric diffusion member is covered by the shielding member. For the n-type shielding member 108, there is a minimum distance to the p++ layer (island 110) with silicide inside the piezoelectric diffusion member.

[0099] When an n++ diffusion member exists around the piezoelectric diffusion path 104 and the conductive shielding member overlaps above the entire inner edge of the n++ diffusion member, an optimal contact to the conductive shielding 108 (n-type shielding in this example) is achieved. This is because the conductive shielding member 108 does not have a direct metal contact, but is electrically connected to the bulk and preferably electrically connected to n++.

[0100] In this exemplary embodiment of the present invention, the guard ring 102 improves the substrate contact to the second conductive layer (interconnection structure 112), but this is not mandatory.

[0101] Figure 1 and Figure 2 shows a schematic diagram of a piezoresistor-based sensor according to an exemplary embodiment of the present invention. In Figure 1 a top view is shown. In Figure 2 A a longitudinal cross-section is shown. In Figure 2 B a transverse cross-section is shown. In this example, the conductive shielding member 108 is a shallow diffusion member of a conductive type opposite to that of the diffusion path 104. In Figure 1 for illustrative purposes, the first conduction type of the diffusion path is selected to be p-type and thus the second conduction type is n-type. Since the conductive shielding member 108 is n-type, an ohmic connection can be provided between the conductive shielding member 108 and the protective layer 102 by extending it to overlap with the guard ring 102 (n++). Since the conductive shielding member 108 and the diffusion path 104 are fabricated on the same silicon, the dielectric layer 120 covers the conductive shielding member 108.Figure 3 The layout of a dual resistor with such an n-type shield is shown, which has a longitudinal resistor 132, a lateral resistor 131, and a film edge 135.

[0102] Where no highly doped region 110 (e.g., p++ or p++ with a sintered silicon-metal alloy) is placed in the diffusion path 104, the diffusion path is covered by the shield 108 to prevent the modulation of the surface charge of the lightly doped section of the diffusion path 104 below the shield. Here, the shield not only covers the diffusion path 104 but also the gap between the diffusion path 104 and the guard ring 102. Therefore, no current can flow parallel to the diffusion path 104 between the diffusion path and the guard ring 102 provided with the shield.

[0103] Where the island 110 (p++ or p++ with a silicon-metal alloy) is placed in the diffusion path 104, due to technical reasons, the diffusion path usually cannot be covered by the shield. As a result, current can be modulated in the narrow region of the piezoelectric diffuser between the island (e.g., p++ island) and the shield. But here, these current modulations are in parallel with the current passing through the island 110 (e.g., p++ or sintered p++). Since the ratio of the sheet resistance between the island 110 (p++ or sintered p++ region) and the piezoelectric diffuser 104 is very low, and the gap between the shield 108 and the p++ island 110 is minimized (e.g., between 1 μm - 5 μm), the influence of these currents can be ignored. In this example, in addition to the island 110 and the spacer 107 surrounding the island, the conductive shield 108 covers the piezoelectric diffusion region 104.

[0104] Where the metal interconnect 112 covers the contact 114 to the island 110 (p++ or p++ with a silicon-metal alloy) in the diffusion path 104, the metal must not only cover the contact but also the diffusion path 104 and the gap between the diffusion path 104 and at least part of the guard ring 102. Therefore, at the contact of the current passing through the diffusion path 104, the metal interconnect 112 acts as a shield and thus bridges the gap between the guard ring 102 and the diffusion path 104.

[0105] In an embodiment of the present invention, the piezoelectric diffused member 104 may have a typical depth of 0.3 μm to 1.5 μm, while the island 110 (e.g., p++ island) may typically have a depth of only between 0.1 μm and 0.7 μm. The island 110 (e.g., p++ island) needs to be highly doped at the top to form a good ohmic contact with the conductive interconnect structure 112 (e.g., metal), and thus it is not necessary to provide high doping far from the surface. The diffused member after implantation is always much shorter than the diffused member for piezoelectric implantation. Therefore, the cross-section shows an island 110 (e.g., p+) and a shielding diffused member 108 having the same depth. It is advantageous to use the same diffused member for the p+ region 110 and the n-type shield 108. Obviously, the shielding diffused member should be very shallow at the surface, otherwise the piezoelectric diffused member 104 under the shielding diffused member 108 will become too thin. Therefore, for the shielding diffused member 108, it has a typical thickness of 0.1 μm to 0.4 μm.

[0106] In another embodiment of the present invention, the conductive shield 108 is a polysilicon shield. For CMOS compatibility, in this example, the polysilicon shield does not cover the island 110 and the spacer around the island. In Figures 4 to 6 is shown in this example. Figure 4 A top view is shown, Figure 5 A shows a longitudinal cross-section, Figure 5 B shows a transverse cross-section, and Figure 6 shows a top view of a piezoresistor-based structure on a membrane. In this example, a polysilicon layer is present above the p-substrate / piezoelectric diffused member 104 and the insulating layer. It is the first conductive layer. When manufacturing the sensor using a standard CMOS process, it is not allowed to place polysilicon above the silicide of the island 110. Also in this example, the island 110 (p++ region with silicide) is within the piezoelectric diffusion region, and the outer edge of the piezoelectric diffusion region 104 is covered by the shield 108. There is also a guard ring 102 in this instance. However, strictly speaking, this guard ring is not necessary, but it is a further improvement for preventing bulk inversion.

[0107] In Figures 4 to 6 In the exemplary embodiment of the present invention shown, a conductive shield 308 is constructed using polysilicon on top of the dielectric layer 120. The conductivity of the polysilicon layer can be enhanced with high doping or even a metal-silicon alloy. Due to CMOS design rules, the polysilicon shield cannot overlap with the island 110 (e.g., p++ doped island). A guard ring 102 is provided to further improve shielding.

[0108] In the embodiments cited above, a shielding solution that does not cover the island 110 (e.g., p++ doped island) is provided. In the case of an n-type shield, this is done because the island 110 (p+ doped island) is not compatible with the n-type shield due to its low breakdown voltage. In the case of a CMOS polysilicon shield, this is done because the doping of the island is not compatible with standard CMOS, in which source-drain implantation is only carried out after polysilicon deposition. In these embodiments, a piezoelectric diffused region surrounds the island 110 (e.g., p++ diffused region).

[0109] In these embodiments, there is a gap between the island 110 (e.g., p++ diffused region) and the shields 108, 308, and the edges of the shields 108, 308 surrounding the island 110 (e.g., p++ region) are still within the piezoelectric diffused region 104. The gap between the n-type shield 108 and the island 110 (p+ region) prevents breakdown between the n-type shield 108 and the island 110 (p+ region), so the n-type shield 108 has no breakdown constraints or doping constraints, which allows for high doping of the n-type shield diffused region, thus providing better shielding. The doping level of the n-type shield can be as high as or even higher than that of the island 110 (p+ region). In these embodiments, the piezoelectric diffused region 104 exists around the island 110 (e.g., p+ region), and the outer edge of this piezoelectric diffused region is shielded.

[0110] Figures 7 to 9 Another exemplary embodiment of the present invention is shown, in which the conductive shield 108 is a polysilicon shield with protection above the island 110 (non-CMOS). In such embodiments, without additional processing steps, it is not possible for the island to have silicide. In this exemplary embodiment of the present invention, there is an overlap between conductive layers (such as a metal with a polycrystalline shield). This overlap provides protection for the fully inverted bulk through the extreme exposure of ions at the surface. In this exemplary embodiment of the present invention, all bulk regions adjacent to the diffusion path are covered by one of the two conductive layers (conductive interconnect structure or conductive shield). Also in this example, a guard ring is not strictly required, but it improves the protection effect.

[0111] In Figure 7 and Figure 8In the schematic diagram, for example, a conductive shield 308 is constructed on top of the dielectric layer 120 using polysilicon. The conductivity of the polysilicon layer can be enhanced with high doping or even a metal-silicon alloy. In the case shown in the figure, when the polysilicon 308 does not have a silicide, the polysilicon 308 can cover the island 110 (e.g., a p++ region). Thus, except for the contacts to the island 110, the entire diffusion path 104 is covered by the polysilicon shield 308. However, here, by ensuring that the interconnect structure 112 covers the opening in the polysilicon shield 308, the interconnect structure 112 (e.g., metal) in contact with the diffusion path 104 can provide complete shielding. Figure 9 The layout of a dual resistor with such a polysilicon shield 308 is shown, which has a longitudinal resistor 132, a lateral resistor 131, and a film edge 135. The shield 308 is connected to the guard ring 102 through a contact 138.

[0112] In some embodiments of the present invention, the conductive shield 208 can be formed from the same layer as the conductive interconnect structure 112. In these embodiments, the conductive layer is used to shield and interconnect the sensors. In these embodiments, a guard ring is required to prevent leakage from one location of the piezoelectric diffusion element 104 to another location of the piezoelectric diffusion element 104 or to another piezoelectric diffusion element, because essentially different metal structures require a gap due to their different voltages. In these embodiments, the distance from the guard ring 102 to the piezoelectric diffusion path 104 should be kept as small as possible, but large enough to prevent breakdown. For example, the distance can be between 1 μm and 5 μm.

[0113] In these embodiments, the conductive shield 208 is isolated from the conductive interconnect structure 112. An example of this is shown in Figures 10 to 12 .

[0114] The current passing through the piezoelectric diffusion region 104 essentially flows from a contact 114 at one end of the highly doped region 110 in the piezoelectric diffusion region 104 through the highly doped region to the low-doped region 104 at the other end of the highly doped region. The low-doped portion 104 of the piezoelectric diffusion region is a piezoresistive region designed to change resistance as the film deforms. Once through this piezoresistive region, the current flows into one end of another highly doped region 110 and then through this region to its other end, where it leaves the highly doped region through a second contact 114.

[0115] In this exemplary embodiment of the present invention, a guard ring 102 of a second conductivity type is formed around the entire piezoelectric diffusion region 104. Preferably, the shield 208 bridges the gap between the piezoelectric diffusion region 104 and the guard ring 102. However, the conductive shield 208 above the piezoresistive region 104 has a bias different from that of the interconnect structure 112 at the contact 114. These biases at the contacts 114 are also different. For some applications, especially when the interconnect 112 is not covered by passivation, it is necessary to leave a gap 106 greater than 10 μm, 20 μm or even 50 μm between the metal structures to avoid surface leakage current between the metal structures. Between these gaps 106, the influence of the external electric field must be kept as small as possible.

[0116] Modulation of the piezoelectric diffuser 104 can be prevented by placing highly doped islands 110 that start below the conductive interconnect structure 112 (e.g., a metal structure) that provides a contact extending from the metal contacting the piezoelectric diffuser 104 to the conductive shield 208 and then extending below the conductive shield 208, which (e.g., a metal structure) serves as a shield for the piezoresistive region 104.

[0117] The voltage drop between the contact hole 114 and the edge of the metal structure 112 covering the contact is small because the resistance of the highly doped region 110 is much smaller than that of the low-doped piezoresistive region 104. Therefore, it can be said that the voltage of the metal 112 providing the contact and covering the gap between the piezoresistive region 104 and the guard ring 102 around the contact is substantially the same as that of the piezoresistive region 104 below the metal. It can be said that the voltage difference between the metal contacting the piezoelectric diffusion region 104 and the metal covering the gap towards the guard ring 102 is less than 10% or even less than 5% or even less than 10% of the voltage across the piezoresistor.

[0118] Leakage from the piezoelectric diffusion region 104 can only occur from the diffusion region not covered by the shields 208, 112. Therefore, there are gaps between the metal structures 208, 112. Therefore, the guard ring 102 must also extend below the edge of one metal structure (conductive interconnect structure 112) to below the edge of another metal structure (conductive shield 208). Leakage current can still flow between the guard ring 102 and the piezoelectric diffusion region 104, but the leakage current can be reduced by keeping the gap between the guard ring and the piezoelectric diffusion region as small as possible. Compared with the current flowing through the highly doped region parallel to the narrow space between the guard ring and the piezoelectric diffusion region, the current caused by inversion in these narrow spaces can be neglected. The leakage current can be reduced by reducing the gap size and by reducing the resistance of the highly doped region.

[0119] In the following paragraphs, it will be discussed in more detail Figure 10and Figure 11 the embodiments shown in. In these embodiments, a conductive shield 208 is constructed on top of the dielectric layer 120 using the same layers as those used for the conductive interconnect structure 110. Now, a gap 106 is required between the metal structures 112, 208 because the conductive shield 208 is typically in contact with the substrate, while the resistor connection (interconnect structure 112) is connected to another node having another voltage. Metal cannot provide shielding in the gap, but it can be ensured that these gaps are bridged by highly doped regions 110 that are hardly modulated by the external electric field, and the guard ring 102 keeps the region that can be inverted as small as possible. The gap 106 between the metal structures is a compromise between effective shielding and the risk of surface conduction between the metal structures. Inversion of the non-covered region between the shield 208 and the guard ring 102 will not generate leakage current because the guard ring 102 prevents this current from flowing out of the diffusion path 104. Figure 12 The layout of a dual resistor with such a metal shield 208 is shown, which has a longitudinal resistor 132, a lateral resistor 131, a film edge 131, and a gap 106 between the metal structures (conductive shield 208 and conductive interconnect structure 112). The shield 208 is connected to the guard ring 102 through a contact 138.

[0120] Diffusion elements are typically made by a combination of ion implantation followed by a high-temperature diffusion step. Depending on the amount of ions implanted per cm 2 of ions, a single implantation can achieve a sheet resistance of approximately 25 ohms per square to 5000 ohms per square. Typical doping ions are boron (p-type dopant), phosphorus (n-type dopant), and arsenic (n-type dopant). In addition, a so-called silicide step can be added, in which a metal (such as Ti, Pt, Ni, or Co) is directly deposited on the doped region, followed by a high-temperature annealing step in which the metal starts to mix with silicon. The metal that has not diffused into silicon is typically etched using selective etching, which etches the deposited metal rather than the resulting silicide. Such a silicide step is typically used to improve the electrical contact between the metal and silicon. After adding the silicide, the sheet resistance is further reduced to only a few ohms per square.

[0121] The guard ring 102 can be fabricated in a manner similar to the substrate contact region by using the same ion implantation and annealing as the substrate contact region. The guard ring can contain a metal silicon alloy 122 by using the same silicide process as that used to enhance the silicon-metal contact. Typically, the dopant concentration of the guard ring 102 and the substrate contact 114 is similar to or higher than that of the island 110 having a sheet resistance, which may vary between 20 ohms per square and 200 ohms per square without silicide and between 1 ohm per square and 5 ohms per square when the silicide covers the diffusion element. An advantage of the embodiments of the present invention is that the substrate contact and the guard ring can be achieved simultaneously.

[0122] 100 semiconductor device

[0123] 102 n++ diffusion element

[0124] 103 Distance between the protection ring 102 and the piezoelectric diffusion region 104

[0125] 104 piezoelectric diffusion element

[0126] 106 Length of the bulk silicon between the conductive layers

[0127] 107 Gap between the n+ shield and the p++ diffusion element

[0128] 108 n+ shield; 208 metal shield; 308 polysilicon shield

[0129] 109 Gap between the edge p++ diffusion element and the piezoelectric diffusion element

[0130] 110 p++ diffusion element

[0131] 112 metal

[0132] 114 Metal - silicon contact

[0133] 116 Width of the bulk silicon between the conductive layers

[0134] 118 n - type bulk or n - type well substrate

[0135] 120 dielectric layer

[0136] 131 Lateral piezoresistor

[0137] 132 Longitudinal piezoresistor

[0138] 135 Film edge

[0139] 138 Make the shield contact the substrate

Claims

1. A piezoresistive stress sensor (100) based on a piezoresistor, comprising at least one sensing element disposed on a flexible structure, the sensing element comprising: At least one piezodiffusion region (104) of a first conductivity type in a well (118) of a second conductivity type, the second conductivity type being different from the first conductivity type, Two or more contacts (114) in electrical contact with an island (110) in the piezodiffusion region, the piezodiffusion region (104) extending between the two or more contacts (114), wherein the island (110) has a higher doping of the first conductivity type than the piezodiffusion region (104), A conductive interconnect structure (112) for each contact (114) to electrically bias the piezodiffusion region (104) through the contact (114), Wherein a conductive shield (108, 208, 308) covers the piezodiffusion region (104) between the contacts (114) and extends beyond the sidewalls of the piezodiffusion region (104) between the contacts (114), and wherein each conductive interconnect structure (112) covers the piezodiffusion region (104) at the corresponding contact and extends beyond the edge of the piezodiffusion region (104) at the corresponding contact, and wherein each island (110) is covered on one side by its corresponding conductive interconnect structure (112), Characterized in that the sensing element comprises a guard ring (102) of the second conductivity type surrounding the piezodiffusion region (104), there being a distance (103) between the guard ring (102) and the piezodiffusion region (104), wherein the conductive shield (208) covers the well between the piezodiffusion region (104) and the guard ring (102) and the edge of the guard ring (102) facing the piezodiffusion region (104), and wherein if there is a gap between the conductive shield (208) and the interconnect structure (112), the guard ring (102) bridges the gap, Or characterized in that the edge of the piezodiffusion region (104) is completely covered by a combination of the conductive shields (108, 308) and the interconnect structure (112).

2. The piezoresistive stress sensor (100) according to claim 1, characterized in that, In the case where the edge of the piezodiffusion region (104) is completely covered by a combination of the conductive shields (108, 308) and the interconnect structure (112), the sensing element comprises a guard ring (102) of the second conductivity type surrounding the piezodiffusion region (104), there being a distance (103) between the guard ring (102) and the piezodiffusion region (104), wherein the conductive shields (108, 308) cover the well between the piezodiffusion region (104) and the guard ring (102) and the edge of the guard ring (102) facing the piezodiffusion region (104).

3. The piezoresistive stress sensor (100) according to claim 1, characterized in that, In the case where the sensing element includes the guard ring (102), the distance (103) between the guard ring (102) and the piezoelectric diffusion region (104) is less than 5 μm.

4. The piezoresistor-based stress sensor (100) according to claim 1, characterized in that, The conductive shields (108, 208, 308) are electrically connected to the guard ring (102).

5. The piezoresistive stress sensor (100) according to claim 1, characterized in that, The conductive shield (208) is made of the same material as the conductive interconnect structure (112), and wherein the conductive shield (208) is isolated from the conductive interconnect structure (112).

6. The piezoresistive stress sensor (100) according to claim 5, characterized in that, The conductive shield (208) is separated from the conductive interconnect structure (112) by a gap of at least 10 μm.

7. The piezoresistive stress sensor (100) according to claim 5, characterized in that, Each island (110) extends from its corresponding conductive interconnect structure (112) to the conductive shield such that at least a portion thereof is covered by the conductive shield (208).

8. The piezoresistive stress sensor (100) according to claim 1, characterized in that, In the case where the sensing element includes the guard ring (102), the conductive interconnect structure (112) covers a portion of the well between the guard ring (102) and the piezoelectric diffusion region (104).

9. The piezoresistive stress sensor (100) according to claim 1, characterized in that, The conductive shields (108, 308) are made of a material different from that of the conductive interconnect structure (112).

10. The piezoresistive stress sensor (100) according to claim 9, characterized in that, The conductive shields (108, 308) cover the piezoelectric diffusion region (104), except for the islands (110).

11. The piezoresistive stress sensor (100) according to claim 9, characterized in that, The conductive shields (108, 308) cover the piezoelectric diffusion region (104), except for the islands (110) and the spacing (107) surrounding the islands.

12. The piezoresistive stress sensor (100) according to claim 9, characterized in that, The conductive shield includes a lightly doped region of the second conductivity type.

13. The piezoresistive stress sensor (100) according to claim 9, characterized in that, The conductive shield is made of polysilicon.

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