Semiconductor device

Abstract

A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities having a first conductivity type, and a concentration of the impurities in the connection doped region is higher than a concentration of the impurities in the first well regions. The first well regions extend to a depth in the substrate that is greater than a depth in the substrate to which the connection doped region extends. A first portion of the connection doped region is disposed in the first well regions, and a second portion of the connection doped region contacts the substrate.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0160286, filed on December 5, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including electrostatic discharge (ESD) protection circuitry for integrated circuits.

[0004] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). To meet the growing demand for semiconductor devices with small pattern sizes and simplified design rules, the size of MOSFETs is being miniaturized. Various studies are underway to overcome the technological limitations associated with the miniaturization of semiconductor devices and to achieve high-performance semiconductor devices. For example, fin-type field-effect transistors with three-dimensional channel structures and multi-bridge field-effect transistors are being used to realize highly integrated semiconductor devices. Semiconductor devices also include electrostatic discharge (ESD) protection circuitry to protect internal circuitry from electrostatic discharge currents. Recently, much research has been conducted to provide highly reliable ESD protection circuitry compatible with field-effect transistors with three-dimensional channel structures. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a semiconductor device with a highly reliable ESD protection circuit (or device).

[0006] Some exemplary embodiments of the present invention provide a semiconductor device including an ESD protection device that can be easily integrated with a field-effect transistor having a three-dimensional channel structure.

[0007] According to embodiments of the present invention, a semiconductor device may include: first well regions disposed in a substrate and spaced apart from each other; interconnect doped regions disposed between the first well regions to connect the first well regions; and a first interconnect line electrically connected to the interconnect doped regions via a first contact. The first well regions and the interconnect doped regions may include impurities having a first conductivity type, and the concentration of impurities in the interconnect doped regions may be higher than the concentration of impurities in the first well regions. The first well regions may extend into the substrate to have a greater depth than the depth to which the interconnect doped regions extend into the substrate. The interconnect doped regions include a first portion, a second portion opposite to the first portion, and a third portion between the first portion and the second portion, wherein the first and second portions of the interconnect doped regions may be disposed in the first well regions, and the third portion of the interconnect doped regions may contact the substrate.

[0008] According to embodiments of the inventive concept, a semiconductor device can include a substrate including an active fin protruding upward from the substrate and extending in a first direction; first well regions disposed in the substrate and spaced apart from each other in the first direction; a connection doping region disposed in the active fin between the first well regions; and a first interconnection line electrically connected to the connection doping region through a first contact. The first well regions and the connection doping region can include impurities having a first conductivity type, and a concentration of the impurities in the connection doping region can be higher than a concentration of the impurities in the first well regions. The connection doping region includes a first portion, a second portion opposite the first portion, and a third portion between the first portion and the second portion, the first and second portions of the connection doping region can be disposed in the first well regions, and the third portion of the connection doping region can contact the substrate.

[0009] According to embodiments of the inventive concept, a semiconductor device can include a substrate including impurities having a first conductivity type; a first first well region and a second first well region disposed in the substrate and spaced apart from each other in a first direction; a connection doping region disposed between the first first well region and the second first well region; a first first doping region disposed in the first first well region and a second first doping region disposed in the second first well region; and a first interconnection line electrically connected to the connection doping region and the first and second first doping regions through a first contact. Each of the first and second first well regions, the connection doping region, and the first and second first doping regions can include impurities having a second conductivity type different from the first conductivity type. A concentration of the impurities in each of the connection doping region and the first and second first doping regions can be higher than a concentration of the impurities in each of the first and second first well regions. A first portion of the connection doping region can be disposed in the first first well region, a second portion of the connection doping region opposite the first portion can be disposed in the second first well region, and a third portion of the connection doping region between the first and second portions can contact the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0010] The example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. The drawings represent non-limiting, example embodiments described herein.

[0011] Figure 1 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 2 is a cross-sectional view taken along line A-A’ of Figure 1 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0013] Figure 3 is a cross-sectional view taken along line A-A’ ofFigure 1 The cross-sectional views taken from lines B-B', C-C', and D-D'.

[0014] Figure 4 This illustrates the edge of a semiconductor device according to an embodiment of the concept of the present invention. Figure 1 A cross-sectional view taken from line A-A'.

[0015] Figures 5 to 10 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] Figure 11 This illustrates the edge of a semiconductor device according to an embodiment of the concept of the present invention. Figure 1 A cross-sectional view taken from line A-A'.

[0017] Figure 12 This illustrates the edge of a semiconductor device according to an embodiment of the concept of the present invention. Figure 1 The cross-sectional views taken from lines B-B', C-C', and D-D'.

[0018] Figures 13 to 18 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0019] Figure 19 This is a conceptual diagram illustrating a semiconductor device according to an embodiment of the present invention.

[0020] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and do not precisely reflect the exact structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or characteristics contained in the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0021] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0022] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 2 According to the example embodiment along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 According to the example embodiment along Figure 1 The cross-sectional views taken from lines B-B', C-C', and D-D'.

[0023] Referring to Figures 1 to 3 The first well regions 110 can be disposed in the substrate 100. The first well regions 110 can be spaced apart from each other along a first direction D1 and can extend along a second direction D2 that intersects the first direction D1. The first direction D1 and the second direction D2 can be parallel to a bottom surface 100B of the substrate 100. The substrate 100 can be a semiconductor wafer (e.g., a silicon wafer or a silicon-on-insulator (SOI) wafer). The first well regions 110 can have a first conductivity type, and the substrate 100 can have a second conductivity type different from the first conductivity type. In an embodiment, the first conductivity type can be n-type, and the second conductivity type can be p-type. The first well regions 110 can include impurities having the first conductivity type.

[0024] The second well regions 120 can be disposed in the substrate 100. The second well regions 120 can be spaced apart from each other along the first direction D1 with the first well regions 110 interposed therebetween, and can extend along the second direction D2. The first well regions 110 can be disposed between the second well regions 120 and can be spaced apart from the second well regions 120. The second well regions 120 can have the same conductivity type (e.g., the first conductivity type) as the first well regions 110. The second well regions 120 can include impurities having the first conductivity type.

[0025] The device isolation patterns ST can be disposed in the substrate 100. The substrate 100 can include active patterns 102 defined by the device isolation patterns ST. The device isolation patterns ST can extend along the first direction D1 to intersect the first well regions 110 and the second well regions 120 and can be spaced apart from each other along the second direction D2. The device isolation patterns ST can be formed of or include at least one of oxide, nitride, and / or oxynitride. Each of the active patterns 102 can be interposed between corresponding ones of the device isolation patterns ST. The active patterns 102 can protrude upward from the substrate 100 along a third direction D3 that is perpendicular to the bottom surface 100B of the substrate 100. The active patterns 102 can extend along the first direction D1 and can be spaced apart from each other along the second direction D2. Each of the active patterns 102 can include the first well regions 110 and the second well regions 120. In an embodiment, the first well regions 110 and the second well regions 120 can extend to regions below the device isolation patterns ST.

[0026] A device isolation pattern ST can be provided to expose an upper portion of the active pattern 102. Each of the active patterns 102 can include an upper portion (hereinafter, an active fin AF) exposed by a corresponding device isolation pattern ST. A top surface of the active fin AF can be higher in height than a top surface of the device isolation pattern ST, and a side surface of the active fin AF can be exposed by the corresponding device isolation pattern ST. In this specification, height can refer to a distance from a bottom surface 100B of the substrate 100.

[0027] A connection doped region 140 can be disposed in the active fin AF between the first well regions 110. The connection doped region 140 can be connected to the first well regions 110 and can have a same conductivity type (e.g., the first conductivity type) as the first well regions 110. It will be understood that when referring to one element being “connected” to another element or on another element, the one element can be directly connected to or directly on the other element.

[0028] The connection doped region 140 can include a first portion, a second portion opposite the first portion, and a third portion between the first portion and the second portion. In some embodiments, the first and second portions of the connection doped region 140 can be disposed in the first well regions 110, and the third portion of the connection doped region 140 can be connected to the substrate 100. In some examples, the first portion of the connection doped region 140 is disposed in a first one of the first well regions 110 (left side in FIG. 1A), the second portion of the connection doped region 140 is disposed in a second one of the first well regions 110 (right side in FIG. 1A), and the third portion of the connection doped region 140 contacts the substrate 100 without passing through the first well regions 110. Figure 2 The first and second portions of the connection doped region 140 can be disposed in the first well regions 110, and the third portion of the connection doped region 140 can be connected to the substrate 100. In some examples, the first portion of the connection doped region 140 is disposed in a first one of the first well regions 110 (left side in FIG. 1A), the second portion of the connection doped region 140 is disposed in a second one of the first well regions 110 (right side in FIG. 1A), and the third portion of the connection doped region 140 contacts the substrate 100 without passing through the first well regions 110. Figure 2 The first and second portions of the connection doped region 140 can be disposed in the first well regions 110, and the third portion of the connection doped region 140 can be connected to the substrate 100. In some examples, the first portion of the connection doped region 140 is disposed in a first one of the first well regions 110 (left side in FIG. 1A), the second portion of the connection doped region 140 is disposed in a second one of the first well regions 110 (right side in FIG. 1A), and the third portion of the connection doped region 140 contacts the substrate 100 without passing through the first well regions 110.

[0029] The connection doped region 140 can include impurities having the first conductivity type. A concentration of the impurities in the connection doped region 140 can be greater than a concentration of the impurities in the first well regions 110. The first well regions 110 can extend into the substrate 100 to have a depth that is deeper than a depth to which the connection doped region 140 extends into the substrate 100. The connection doped region 140 can form a PN junction with a portion of the substrate 100 (e.g., a corresponding one of the active patterns 102) between the first well regions 110.

[0030] The first doped regions 112 can be disposed in the active fin AF and in the first well regions 110, respectively. The first doped regions 112 can be connected to the first well regions 110, respectively. The connecting doped region 140 can be disposed between and spaced apart from the first doped regions 112. In embodiments, each of the first well regions 110 can extend into the active fin AF between each of the first doped regions 112 and the connecting doped region 140. For example, a portion of each of the first well regions 110 can be between each of the first doped regions 112 and the connecting doped region 140. The first doped regions 112 can have the same conductivity type as the first well regions 110 (e.g., the first conductivity type). The first doped regions 112 can include impurities having the first conductivity type, and a concentration of the impurities in the first doped regions 112 can be higher than a concentration of the impurities in the first well regions 110.

[0031] The second doped regions 122 can be disposed in the active fin AF and in the second well regions 120, respectively. The second doped regions 122 can be connected to the second well regions 120, respectively. The second doped regions 122 can be spaced apart from each other along the first direction Dl, with the connecting doped region 140 and the first doped regions 112 being between the second doped regions 122. The second doped regions 122 can be spaced apart from the first doped regions 112, respectively. The second doped regions 122 can have the same conductivity type as the second well regions 120 (e.g., the first conductivity type). The second doped regions 122 can include impurities having the first conductivity type, and a concentration of the impurities in the second doped regions 122 can be higher than a concentration of the impurities in the second well regions 120. In embodiments, the second well regions 120 can be omitted. In this case, the second doped regions 122 can be disposed in the active fin AF and can be connected to a portion of the substrate 100 (i.e., the corresponding active pattern 102).

[0032] The insulating pattern 150 can be disposed between each of the first doped regions 112 and a corresponding one of the second doped regions 122. The insulating pattern 150 can be disposed in the active fin AF and can extend along the second direction D2 to cross the plurality of active fins AF. In embodiments, a height of a bottommost surface 150L of the insulating pattern 150 can be substantially equal to a height of a bottommost surface 140L of the connecting doped region 140. The insulating pattern 150 can be formed of or include at least one of an oxide, a nitride, and / or an oxynitride.

[0033] The third doped regions 132 can be disposed in the active fin AF. The third doped regions 132 can be spaced apart from each other along the first direction D1, and the connecting doped region 140, the first doped regions 112, and the second doped regions 122 can be interposed between the third doped regions 132. The third doped regions 132 can be spaced apart from each of the second doped regions 122, and can be connected to the substrate 100 (i.e., the corresponding active pattern 102). The third doped regions 132 can have the same conductivity type as the substrate 100 (e.g., the second conductivity type). The third doped regions 132 can include impurities having the second conductivity type.

[0034] In an embodiment, the connecting doped region 140, and each of the first doped regions 112, the second doped regions 122, and the third doped regions 132 can be disposed locally in the active fin AF. In this case, the connecting doped region 140, and the first doped regions 112, the second doped regions 122, and the third doped regions 132 can have bottom surfaces that are located at or above the height of the top surface of the device isolation pattern ST. In another embodiment, differently from what is shown in the drawings, the connecting doped region 140, and the first doped regions 112, the second doped regions 122, and the third doped regions 132 can partially extend into the respective portions of the active pattern 102 under the active fin AF. In this case, the bottom surfaces of the connecting doped region 140, and the first doped regions 112, the second doped regions 122, and the third doped regions 132 can be located below the height of the top surface of the device isolation pattern ST.

[0035] The gate structures GS can be disposed on the substrate 100 to cross the active fin AF. The gate structures GS can extend along the second direction D2 and can be spaced apart from each other along the first direction D1. The gate structures GS can be disposed on the first well regions 110, respectively. The connecting doped region 140 can be disposed in the active fin AF between the gate structures GS. The connecting doped region 140 can be disposed on one side of each of the gate structures GS, and each of the first doped regions 112 can be disposed on the opposite side of each of the gate structures GS. In an embodiment, the gate structures GS can be dummy gate structures in an electrically floating state. In another embodiment, the gate structures GS can be connected to a ground electrode Vss.

[0036] Each of the gate structures GS can include a gate electrode GE extending along the second direction D2 to cross the active fin AF, a gate insulation pattern GI between the gate electrode GE and the active fin AF, a gate side wall GSP on a side surface of the gate electrode GE, and a gate cap pattern CAP on a top surface of the gate electrode GE. The gate electrode GE can cover an exposed side surface of the active fin AF and can extend to a top surface of the device isolation pattern ST. The gate insulation pattern GI can be between the gate electrode GE and the exposed side surface of the active fin AF and between the gate electrode GE and the top surface of the device isolation pattern ST. The gate insulation pattern GI can extend to an area between the gate electrode GE and the gate side wall GSP, and a topmost surface of the gate insulation pattern GI can be substantially coplanar with the top surface of the gate electrode GE. In an embodiment, the gate side wall GSP can extend to cover a side surface of the gate cap pattern CAP.

[0037] The gate electrode GE can be formed of or include at least one of a doped semiconductor material, a conductive metal nitride, and / or a metal. The gate insulation pattern GI can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. The high-k dielectric material can be formed of or include at least one of a material having a dielectric constant higher than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)). Each of the gate side wall GSP and the gate cap pattern CAP can be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0038] The first interlayer insulation layer 160 can be disposed on the substrate 100 to cover the gate structures GS and the active fins AF. The first interlayer insulation layer 160 can cover an exposed side surface of the active fin AF and a top surface of the device isolation pattern ST. The first interlayer insulation layer 160 can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. A top surface of the gate cap pattern CAP of each of the gate structures GS can be substantially coplanar with a top surface of the first interlayer insulation layer 160. The gate side wall GSP of each of the gate structures GS can be between the gate cap pattern CAP and the first interlayer insulation layer 160.

[0039] A second interlayer insulating layer 165 can be disposed on the first interlayer insulating layer 160. The second interlayer insulating layer 165 can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. The second interlayer insulating layer 165 can cover a top surface of the gate cap pattern CAP of each of the gate structures GS.

[0040] The contact plugs 170 can be disposed in the first interlayer insulating layer 160 and can extend into the second interlayer insulating layer 165. Each of the contact plugs 170 can include a conductive pattern 172 penetrating the first interlayer insulating layer 160 and the second interlayer insulating layer 165 and a barrier pattern 174 covering side surfaces and a bottom surface of the conductive pattern 172. In an embodiment, the conductive pattern 172 can be formed of or include at least one of a metal material, and the barrier pattern 174 can be formed of or include at least one of a conductive metal nitride. A top surface of the contact plug 170 can be located at substantially the same height as a top surface of the second interlayer insulating layer 165. Each of the contact plugs 170 can be disposed to penetrate the first interlayer insulating layer 160 and the second interlayer insulating layer 165 and can be connected to a corresponding one of the connection doped regions 140, the first doped regions 112, the second doped regions 122, and the third doped regions 132.

[0041] The contact plugs 170 can include first contact plugs 170a connected to the connection doped regions 140 and the first doped regions 112, respectively, and second contact plugs 170b connected to the second doped regions 122 and the third doped regions 132, respectively.

[0042] One of the first contact plugs 170a can be disposed between the gate structures GS and can be connected to the connection doped region 140. Other ones of the first contact plugs 170a can be spaced apart from each other along the first direction D1 with the gate structures GS interposed therebetween and can be connected to the first doped regions 112, respectively. The first contact plugs 170a and the gate structures GS can be alternately disposed along the first direction D1. In an embodiment, each of the first contact plugs 170a can be a strip pattern extending along the second direction D2 and crossing the active fins AF. In this case, one of the first contact plugs 170a can connect the connection doped regions 140 adjacent to each other along the second direction D2 to each other, and each of the other ones of the first contact plugs 170a can connect the first doped regions 112 adjacent to each other along the second direction D2 to each other. Each of the first well regions 110 can be connected to a corresponding one of the first contact plugs 170a through a corresponding one of the first doped regions 112.

[0043] In an embodiment, each of the second contact plugs 170b can be a strip structure extending along the second direction D2 and can be disposed to cross the plurality of active fins AF. In this case, one of the second contact plugs 170b can connect the plurality of second doped regions 122 adjacent to each other along the second direction D2 to each other, and another one of the second contact plugs 170b can connect the plurality of third doped regions 132 adjacent to each other along the second direction D2 to each other. Each of the second well regions 120 can be connected to a corresponding one of the second contact plugs 170b through each of the second doped regions 122. The substrate 100 can be connected to a corresponding one of the second contact plugs 170b through the third doped region 132. In an embodiment, the second well regions 120 can be omitted, and in this case, the substrate 100 can be connected to the second contact plugs 170b through the second doped regions 122 and the third doped regions 132.

[0044] A third interlayer insulating layer 180 can be disposed on the second interlayer insulating layer 165 to cover the top surfaces of the contact plugs 170. The third interlayer insulating layer 180 can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. The vias 185 can be disposed in the third interlayer insulating layer 180 and can be connected to the contact plugs 170, respectively. The interconnection lines 190 can be disposed on the third interlayer insulating layer 180. The first contact plug 170a can be connected to a corresponding one of the interconnection lines 190 through the corresponding via 185 and can be connected to the pad PAD (or pin) through the corresponding interconnection line 190. The semiconductor device can be electrically connected to an external device (e.g., a central processing unit (CPU) or a memory controller) through the pad PAD. The semiconductor device can receive a signal including a command CMD and / or an address ADDR from the external device through the pad PAD. The second contact plug 170b can be connected to a corresponding one of the interconnection lines 190 through the corresponding via 185 and can be connected to the ground electrode Vss through the corresponding interconnection line 190.

[0045] The first well region 110, the first doped region 112, the connection doped region 140, and the first contact plug 170a can constitute a collector of a lateral bipolar junction transistor. The second well region 120, the second doped region 122, the third doped region 132, and the second contact plug 170b can constitute an emitter of the lateral bipolar junction transistor. The lateral bipolar junction transistor can be an electrostatic discharge (ESD) protection device (or ESD protection circuit) for protecting an integrated circuit on the substrate 100 from an electrostatic discharge (ESD) phenomenon. An ESD current I that can be supplied from the pad PAD during operation of the lateral bipolar junction transistor can be discharged through the lateral bipolar junction transistor to the ground electrode Vss. In an embodiment, the second well region 120 can be omitted, and in this case, the second doped region 122, the third doped region 132, and the second contact plug 170b can constitute the emitter of the lateral bipolar junction transistor.

[0046] In an embodiment, the connection doped region 140 can constitute a direct PN junction with a portion of the substrate 100 between the first well region 110. In this case, a large portion of the ESD current I can be discharged through the PN junction structure composed of the connection doped region 140 and the portion of the substrate 100, instead of being discharged through the PN junction structure composed of the first doped region 112, the first well region 110, and the substrate 100, and thus a trigger voltage for operation of the lateral bipolar junction transistor can be reduced.

[0047] The first well region 110 can extend into the substrate 100 to have a depth deeper than a depth to which the connection doped region 140 extends into the substrate 100. In this case, a discharge path of the ESD current I can be formed at a position spaced apart from the first doped region 112 adjacent to the connection doped region 140, and thus a leakage current between a collector and an emitter of the lateral bipolar junction transistor can be reduced.

[0048] Further, the active fin AF and the gate structure GS can have a structure similar to a structure of a fin field effect transistor. Thus, the lateral bipolar junction transistor can have a structure easily integrated together with a field effect transistor having a three-dimensional channel structure.

[0049] Thus, a highly reliable ESD protection device whose structure is easily integrated together with a field effect transistor having a three-dimensional channel structure can be provided.

[0050] Figure 4 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept taken along a line A-A' of Figure 1 FIG. 1. For a clear description, the following description will mainly refer to technical features different from those described with reference to Figures 1 to 3 the semiconductor device.

[0051] With reference to Figure 1 and Figure 4 , an insulating pattern 150 can be disposed between each of the first doped regions 112 and a corresponding one of the second doped regions 122. The insulating pattern 150 can be disposed in the active fin AF and can extend into the substrate 100 between each of the first well regions 110 and a corresponding one of the second well regions 120. The insulating pattern 150 can extend along the second direction D2 to cross the active fin AF. In an embodiment, a height of a lowermost surface 150L of the insulating pattern 150 can be lower than a height of a lowermost surface 140L of the connection doped region 140. In certain embodiments, the height of the lowermost surface 150L of the insulating pattern 150 can be substantially equal to a height of a lowermost surface of the first well regions 110 and the second well regions 120. The insulating pattern 150 can be formed of or include at least one of an oxide, a nitride, and / or an oxynitride.

[0052] According to the present embodiment, the insulating pattern 150 can extend into the substrate 100 from a region between the active fins AF. In this case, even if an amount of the ESD current I supplied from the pad PAD increases, the ESD protection device can have high reliability.

[0053] Figures 5 to 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. For example,Figure 5 , Figure 7 and Figure 9 are cross-sectional views taken along a line A-A' of Figure 1 , and Figure 6 , Figure 8 and Figure 10 are cross-sectional views taken along a line B-B', a line C-C', and a line D-D' of Figure 1 . For the sake of concise description, the following description will mainly relate to technical features different from those described with reference to Figures 1 to 4 .

[0054] Referring to Figure 1 , Figure 5 and Figure 6 , first well regions 110 and second well regions 120 can be formed in a substrate 100. The first well regions 110 can be spaced apart from each other along a first direction D1 and can extend along a second direction D2 crossing the first direction D1. The second well regions 120 can be spaced apart from each other along the first direction D1 with the first well regions 110 interposed therebetween, and can extend along the second direction D2. The first well regions 110 and the second well regions 120 can be formed by implanting impurities having a first conductivity type into the substrate 100. The substrate 100 can have a second conductivity type different from the first conductivity type. In an embodiment, the formation of the second well regions 120 is omitted.

[0055] Active patterns 102 can be formed in the substrate 100. The forming of the active patterns 102 can include patterning an upper portion of the substrate 100 to form trenches T defining the active patterns 102 in the substrate 100. The trenches T can extend along the first direction D1 to cross the first well regions 110 and the second well regions 120 and can be spaced apart from each other along the second direction D2. The active patterns 102 can protrude from the substrate 100 along a third direction D3 perpendicular to a bottom surface 100B of the substrate 100. The active patterns 102 can extend along the first direction D1 and can be spaced apart from each other along the second direction D2. Each of the active patterns 102 can include the first well regions 110 and the second well regions 120.

[0056] A device isolation pattern ST can be formed in the substrate 100. The forming of the device isolation pattern ST can include forming a device isolation layer to fill the trenches T and recessing the device isolation layer to expose upper portions of the active patterns 102. Due to the recessing of the device isolation layer, each of the active patterns 102 can include an upper portion (hereinafter, an active fin AF) exposed by the device isolation pattern ST.

[0057] The insulating pattern 150 can be formed in the active fins AF to cross the active fins AF. The insulating pattern 150 can extend along the second direction D2 to cross the active fins AF. In an embodiment, forming the insulating pattern 150 can include removing a portion of the active fins AF to form the empty region 150R in the active fins AF, forming an insulating layer to fill the empty region 150R, and planarizing the insulating layer to expose the top surfaces of the active fins AF. In another embodiment, as described with reference to FIGS. 1A and 1B, the insulating pattern 150 can be formed to extend from the regions between the active fins AF into the substrate 100. In this case, the empty region 150R can be formed by removing a portion of the active fins AF and an upper portion of the substrate 100 (e.g., corresponding to at least a portion of the active pattern 102). Figure 4

[0058] The sacrificial gate structures SGS can be formed on the substrate 100 to cross the active fins AF. The sacrificial gate structures SGS can extend along the second direction D2 and can be spaced apart from each other along the first direction D1. The sacrificial gate structures SGS can be formed on the first well regions 110, respectively.

[0059] Each of the sacrificial gate structures SGS can include the etch stop pattern 202, the sacrificial gate pattern 204, and the gate mask pattern 206 sequentially stacked on the substrate 100. The sacrificial gate pattern 204 can extend along the second direction D2 to cross the active fins AF. The sacrificial gate pattern 204 can be formed to cover the top and side surfaces of the active fins AF and can extend to cover the top surface of the device isolation pattern ST. The etch stop pattern 202 can be interposed between the sacrificial gate pattern 204 and the top and side surfaces of the active fins AF and between the sacrificial gate pattern 204 and the top surface of the device isolation pattern ST. The gate mask pattern 206 can extend along the top surface of the sacrificial gate pattern 204.

[0060] ​Forming the sacrificial gate pattern 204 and the etch stop pattern 202 can include sequentially forming an etch stop layer (not shown) and a sacrificial gate layer (not shown) on the substrate 100, forming a gate mask pattern 206 that defines the location and shape of the sacrificial gate pattern 204 on the sacrificial gate layer, and sequentially patterning the sacrificial gate layer and the etch stop layer using the gate mask pattern 206 as an etch mask. The etch stop layer can be formed of or include, for example, silicon oxide. The sacrificial gate layer can include a material that is etch-selective with respect to the etch stop layer. For example, the sacrificial gate layer can be formed of or include polysilicon. The sacrificial gate pattern 204 can be formed by patterning the sacrificial gate layer using the gate mask pattern 206 as an etch mask. Patterning the sacrificial gate layer can include performing an etch process using an etch recipe that is selected to be etch-selective with respect to the etch stop layer. After forming the sacrificial gate pattern 204, portions of the etch stop layer that are located on both sides of the sacrificial gate pattern 204 can be removed to locally form the etch stop pattern 202 under the sacrificial gate pattern 204.

[0061] Each of the sacrificial gate structures SGS can also include a gate side wall GSP disposed on both sides of the sacrificial gate pattern 204. Forming the gate side wall GSP can include forming a gate side wall layer (not shown) on the substrate 100 to cover the gate mask pattern 206, the sacrificial gate pattern 204, and the etch stop pattern 202, and then anisotropically etching the gate side wall layer. The gate mask pattern 206 and the gate side wall GSP can be formed of or include, for example, silicon nitride.

[0062] Referring to Figure 1 , Figure 7 and Figure 8 A connection dopant region 140 can be formed in the active fin AF between the sacrificial gate structures SGS. In an embodiment, forming the connection dopant region 140 can include implanting impurities having a first conductivity type into the active fin AF between the sacrificial gate structures SGS. In another embodiment, forming the connection dopant region 140 can include removing portions of the active fin AF between the sacrificial gate structures SGS to expose a top surface of a corresponding active pattern 102, performing a selective epitaxial growth process (where the exposed top surface of the corresponding active pattern 102 serves as a seed layer) to form an epitaxial pattern, and implanting impurities having the first conductivity type into the epitaxial pattern, and here, the implantation of the impurities can be performed during or after the selective epitaxial growth process. The concentration of the impurities in the connection dopant region 140 can be higher than the concentration of the impurities in the first well region 110.

[0063] The first doped regions 112 can be formed in the active fins AF and in the first well regions 110, respectively. The first doped regions 112 can be connected to the first well regions 110, respectively. In an embodiment, forming the first doped regions 112 can include implanting impurities having the first conductivity type into the active fins AF in the first well regions 110. In another embodiment, forming the first doped regions 112 can include removing portions of the active fins AF in the first well regions 110 to expose top surfaces of the corresponding active patterns 102, performing a selective epitaxial growth process (where the exposed top surfaces of the corresponding active patterns 102 serve as seed layers) to form epitaxial patterns, and implanting impurities having the first conductivity type into the epitaxial patterns, and here, the implantation of the impurities can be performed during or after the selective epitaxial growth process. The concentration of the impurities in the first doped regions 112 can be higher than the concentration of the impurities in the first well regions 110.

[0064] The second doped regions 122 can be formed in the active fins AF and in the second well regions 120, respectively. The second doped regions 122 can be connected to the second well regions 120, respectively. In an embodiment, forming the second doped regions 122 can include implanting impurities having the first conductivity type into the active fins AF in the second well regions 120. In another embodiment, forming the second doped regions 122 can include removing portions of the active fins AF in the second well regions 120 to expose top surfaces of the corresponding active patterns 102, performing a selective epitaxial growth process (where the exposed top surfaces of the corresponding active patterns 102 serve as seed layers) to form epitaxial patterns, and implanting impurities having the first conductivity type into the epitaxial patterns, and here, the implantation of the impurities can be performed during or after the selective epitaxial growth process. The concentration of the impurities in the second doped regions 122 can be higher than the concentration of the impurities in the second well regions 120.

[0065] A third doped region 132 can be formed in the active fin AF. The third doped regions 132 can be spaced apart from each other along the first direction D1, and the connecting doped region 140, the first doped regions 112, and the second doped regions 122 can be interposed between the third doped regions 132. In an embodiment, forming the third doped regions 132 can include implanting impurities having the second conductivity type into the active fin AF. The concentration of the impurities in each of the third doped regions 132 can be higher than the concentration of the impurities in the substrate 100. In another embodiment, forming the third doped regions 132 can include removing portions of the active fin AF to expose top surfaces of the corresponding active patterns 102, performing a selective epitaxial growth process (where the exposed top surfaces of the corresponding active patterns 102 serve as seed layers) to form epitaxial patterns, and implanting impurities having the second conductivity type into the epitaxial patterns, and here, the implantation of the impurities can be performed during or after the selective epitaxial growth process.

[0066] In an embodiment, the connecting doped region 140, and each of the first doped regions 112, the second doped regions 122, and the third doped regions 132 can be locally formed in the active fin AF, but the inventive concept is not limited to this example. In another embodiment, unlike shown in the drawings, the connecting doped region 140, and each of the first doped regions 112, the second doped regions 122, and the third doped regions 132 can be formed to extend into the corresponding active pattern 102 below the active fin AF.

[0067] A first interlayer insulating layer 160 can be formed on the substrate 100 to cover the sacrificial gate structure SGS and the active fin AF. The first interlayer insulating layer 160 can be formed to cover the connecting doped region 140, the first doped regions 112, the second doped regions 122, and the third doped regions 132, and the insulating pattern 150. The first interlayer insulating layer 160 can be planarized until the sacrificial gate pattern 204 is exposed. The gate mask pattern 206 can be removed by a planarization process.

[0068] Referring to Figure 1 , Figure 9 and Figure 10 The sacrificial gate pattern 204 and the etch stop pattern 202 can be removed, and thus the gap regions 210 can be formed in the first interlayer insulating layer 160. Each of the gap regions 210 can be an empty region between the gate side walls GSP. Each of the gap regions 210 can be formed to expose the active fin AF. Forming the gap regions 210 can include selectively etching the sacrificial gate pattern 204 using an etching recipe having an etching selectivity with respect to the gate side walls GSP, the first interlayer insulating layer 160, and the etch stop pattern 202, and then removing the etch stop pattern 202 to expose the active fin AF.

[0069] The gate insulating pattern GI and the gate electrode GE can be formed to fill each of the gap regions 210. Forming the gate insulating pattern GI and the gate electrode GE can include forming a gate insulating layer to conformally cover inner surfaces of each of the gap regions 210, forming a gate conductive layer to fill remaining areas of each of the gap regions 210, and performing a planarization process to expose the first interlayer insulating layer 160 and locally form the gate insulating pattern GI and the gate electrode GE in each of the gap regions 210. In an embodiment, upper portions of the gate insulating pattern GI and the gate electrode GE can be recessed to form a recessed region between the gate side walls GSP. A gate cap pattern CAP can be formed in the recessed region. Forming the gate cap pattern CAP can include forming a gate cap layer on the first interlayer insulating layer 160 to fill the recessed region, and then planarizing the gate cap layer to expose the first interlayer insulating layer 160. The gate insulating pattern GI, the gate electrode GE, the gate cap pattern CAP, and the gate side walls GSP can constitute a gate structure GS.

[0070] Referring to Figures 1 to 3 , a second interlayer insulating layer 165 can be formed on the first interlayer insulating layer 160. Contact plugs 170 can be formed in the first interlayer insulating layer 160 and the second interlayer insulating layer 165. Each of the contact plugs 170 can include a conductive pattern 172 formed to penetrate the first interlayer insulating layer 160 and the second interlayer insulating layer 165, and a barrier pattern 174 formed to cover side surfaces and a bottom surface of the conductive pattern 172. In an embodiment, forming the contact plugs 170 can include forming contact holes to penetrate the first interlayer insulating layer 160 and the second interlayer insulating layer 165, forming a barrier layer to partially fill each of the contact holes, forming a conductive layer to fill remaining areas of each of the contact holes, and planarizing the conductive layer and the barrier layer to expose the second interlayer insulating layer 165. Due to the planarization process, the conductive pattern 172 and the barrier pattern 174 can be locally formed in each of the contact holes. Each of the contact plugs 170 can be disposed to penetrate the first interlayer insulating layer 160 and the second interlayer insulating layer 165, and can be connected to a corresponding one of the connection doped region 140, the first doped region 112, the second doped region 122, and the third doped region 132.

[0071] A third interlayer insulating layer 180 can be formed on the second interlayer insulating layer 165 to cover top surfaces of the contact plugs 170. A via 185 can be formed in the third interlayer insulating layer 180. Each of the vias 185 can be disposed to penetrate the third interlayer insulating layer 180 and can be connected to a corresponding one of the contact plugs 170. An interconnection line 190 can be formed on the third interlayer insulating layer 180 and can be connected to a corresponding one of the vias 185. Although not shown, each of the interconnection lines 190 can be connected to the pad PAD or the ground electrode Vss through an additional interconnection structure.

[0072] Figure 11 is a cross-sectional view taken along a line A-A' of the semiconductor device according to an embodiment of the inventive concept. Figure 1 Figure 12 is a cross-sectional view taken along a line B-B', a line C-C', and a line D-D' of the semiconductor device according to an embodiment of the inventive concept. For a concise description, the following description will mainly relate to technical features different from those described with reference to Figure 1 Figures 1 to 4

[0073] Referring to Figure 1 , Figure 11 and Figure 12 , first well regions 110 and second well regions 120 can be disposed in the substrate 100. The first well regions 110 can be spaced apart from each other along a first direction D1 and can extend along a second direction D2. The second well regions 120 can be spaced apart from each other along the first direction D1 with the first well regions 110 interposed therebetween and can extend along the second direction D2. The first well regions 110 and the second well regions 120 can include impurities having a first conductivity type, and the substrate 100 can have a second conductivity type different from the first conductivity type. In an embodiment, the second well regions 120 can be omitted.

[0074] A device isolation pattern ST can be disposed in the substrate 100. The substrate 100 can include active patterns 102 defined by the device isolation pattern ST. The device isolation pattern ST can extend along the first direction D1 to cross the first well regions 110 and the second well regions 120 and can be spaced apart from each other along the second direction D2. Each of the active patterns 102 can be interposed between corresponding ones of the device isolation patterns ST. Each of the active patterns 102 can include the first well regions 110 and the second well regions 120.

[0075] ​​​An active fin AF can be disposed on each of the active patterns 102. In embodiments, the active fin AF can include a sacrificial pattern 104 and a semiconductor pattern 106 that are alternately stacked on each of the active patterns 102 along the third direction D3. The sacrificial pattern 104 can be formed of or include a different material from the semiconductor pattern 106. For example, the semiconductor pattern 106 can be formed of or include silicon (Si), while the sacrificial pattern 104 can be formed of or include silicon germanium (SiGe).

[0076] A connection doped region 140 can be disposed in the active fin AF between the first well regions 110. The connection doped region 140 can penetrate the active fin AF and can be in direct contact with portions of the substrate 100 (e.g., the corresponding active pattern 102) between the first well regions 110. In embodiments, the connection doped region 140 can be an epitaxial pattern grown using the active fin AF and the corresponding active pattern 102 as a seed layer. The connection doped region 140 can be connected to the first well regions 110 and can include impurities having the first conductivity type. The concentration of the impurities in the connection doped region 140 can be higher than the concentration of the impurities in the first well regions 110. The connection doped region 140 can constitute a PN junction with the portions of the substrate 100 between the first well regions 110.

[0077] The first doped regions 112 can be disposed in the active fin AF and on the first well regions 110, respectively. The first doped regions 112 can be connected to the first well regions 110, respectively. The connection doped region 140 can be disposed between and spaced apart from the first doped regions 112. Each of the first doped regions 112 can penetrate the active fin AF and can be in contact with a corresponding one of the first well regions 110. Each of the first doped regions 112 can be an epitaxial pattern grown using the active fin AF and the corresponding active pattern 102 as a seed layer. The first doped regions 112 can include impurities having the first conductivity type, and the concentration of the impurities in the first doped regions 112 can be higher than the concentration of the impurities in the first well regions 110.

[0078] The second doped regions 122 can be disposed in the active fin AF and on the second well regions 120, respectively. The second doped regions 122 can be connected to the second well regions 120, respectively. The first doped regions 112 can be disposed between the second doped regions 122, and the second doped regions 122 can be spaced apart from each of the first doped regions 112. Each of the second doped regions 122 can penetrate the active fin AF and can be in contact with a corresponding one of the second well regions 120. Each of the second doped regions 122 can be an epitaxial pattern grown using the active fin AF and the corresponding active pattern 102 as a seed layer. The second doped regions 122 can include impurities of the first conductivity type, and a concentration of the impurities in the second doped regions 122 can be higher than a concentration of the impurities in the second well regions 120.

[0079] The insulating pattern 150 can be disposed between each of the first doped regions 112 and a corresponding one of the second doped regions 122. The insulating pattern 150 can be disposed in the active fin AF and can extend along the second direction D2 to cross the plurality of active fins AF. In an embodiment, a height of a bottommost surface 150L of the insulating pattern 150 can be substantially equal to a height of the bottommost surface 140L of the connection doped region 140. In another embodiment, as described with reference to FIG. 1, the height of the bottommost surface 150L of the insulating pattern 150 can be lower than the height of the bottommost surface 140L of the connection doped region 140. Figure 4

[0080] The third doped regions 132 can be disposed in the active fin AF. The second doped regions 122 can be disposed between the third doped regions 132, and the third doped regions 132 can be spaced apart from each of the second doped regions 122. Each of the third doped regions 132 can penetrate the active fin AF and can be in contact with the substrate 100 (e.g., a corresponding active pattern 102). Each of the third doped regions 132 can be an epitaxial pattern grown using the active fin AF and the corresponding active pattern 102 as a seed layer. The third doped regions 132 can include impurities of the second conductivity type.

[0081] The gate structures GS can be disposed on the substrate 100 to cross the active fin AF. The gate structures GS can extend along the second direction D2 and can be spaced apart from each other along the first direction Dl. The gate structures GS can be disposed on the first well regions 110, respectively. The connection doped region 140 can be disposed in the active fin AF between the gate structures GS. In an embodiment, the gate structures GS can be dummy gate structures in an electrically floating state.

[0082] ​Each of the gate structures GS can include a gate electrode GE extending along the second direction D2 to cross the active fin AF, a gate insulating pattern GI between the gate electrode GE and the active fin AF, a gate side wall GSP on a side surface of the gate electrode GE, and a gate cap pattern CAP on a top surface of the gate electrode GE. The gate electrode GE can cover a top surface and a side surface of the active fin AF, and can extend into a region between the semiconductor patterns 106 of the active fin AF and a region between the active fin AF and the corresponding active pattern 102. The gate insulating pattern GI can extend into a region between each of the semiconductor patterns 106 and the gate electrode GE and a region between the corresponding active pattern 102 and the gate electrode GE. The semiconductor patterns 106 can be spaced apart from the gate electrode GE with the gate insulating pattern GI interposed therebetween. The gate insulating pattern GI can extend into a region between the gate electrode GE and the gate side wall GSP, and a topmost surface of the gate insulating pattern GI can be substantially coplanar with a top surface of the gate electrode GE. In an embodiment, the gate side wall GSP can extend to cover a side surface of the gate cap pattern CAP.

[0083] In addition to the above-described differences, the semiconductor device according to the present embodiment can be substantially the same as the semiconductor device described with reference to Figures 1 to 4 .

[0084] According to the present embodiment, the active fin AF and the gate structure GS can have a structure similar to that of a multi-bridge channel field effect transistor. Thus, the lateral bipolar junction transistor can have a structure that is easily integrated with a field effect transistor having a three-dimensional structure in its channel region.

[0085] Figures 13 to 18 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present inventive concept. Figure 13 , Figure 15 and Figure 17 are cross-sectional views taken along line A-A' of Figure 1 , and Figure 14 , Figure 16 and Figure 18 are cross-sectional views taken along line B-B', line C-C', and line D-D' of Figure 1 . For a concise description, the following description will mainly relate to technical features that are different from those in the method of manufacturing a semiconductor device described with reference to Figures 5 to 10 .

[0086] Reference is made to Figure 1 , Figure 13 and Figure 14The first well region 110 and the second well region 120 can be formed in the substrate 100. The first well region 110 and the second well region 120 can be formed by implanting impurities having a first conductivity type into the substrate 100. The substrate 100 can have a second conductivity type different from the first conductivity type. In an embodiment, the formation of the second well region 120 is omitted.

[0087] The active patterns 102 can be formed in the substrate 100, and the active fins AF can be formed on each of the active patterns 102. In an embodiment, forming the active fins AF can include alternately and repeatedly stacking a sacrificial layer and a semiconductor layer on the substrate 100, and sequentially patterning the sacrificial layer and the semiconductor layer. As the sacrificial layer and the semiconductor layer are patterned, the sacrificial patterns 104 and the semiconductor patterns 106 can be formed on the substrate 100. The active fins AF can include the sacrificial patterns 104 and the semiconductor patterns 106 alternately stacked on the substrate 100.

[0088] Forming the active patterns 102 can include patterning an upper portion of the substrate 100 to form trenches T in the substrate 100 that define the active patterns 102. The trenches T can extend along the first direction D1 to cross the first well regions 110 and the second well regions 120 and can be spaced apart from each other along the second direction D2. The active patterns 102 can protrude from the substrate 100 along a third direction D3 perpendicular to a bottom surface 100B of the substrate 100. The active patterns 102 can extend along the first direction D1 and can be spaced apart from each other along the second direction D2. Each of the active patterns 102 can include the first well region 110 and the second well region 120.

[0089] The device isolation pattern ST can be formed in the substrate 100. Forming the device isolation pattern ST can include forming a device isolation layer to fill the trenches T, and recessing the device isolation layer to expose the active fins AF. In an embodiment, recessing the device isolation layer can be performed to expose not only top surfaces of the active fins AF but also side surfaces of the active fins AF (e.g., side surfaces of the sacrificial patterns 104 and the semiconductor patterns 106).

[0090] The insulating patterns 150 can be formed in the active fins AF to cross the active fins AF. The insulating patterns 150 can extend along the second direction D2 to cross the active fins AF. In an embodiment, forming the insulating patterns 150 can include removing a portion of the active fins AF to form empty regions 150R in the active fins AF, forming an insulating layer to fill the empty regions 150R, and planarizing the insulating layer to expose top surfaces of the active fins AF. Forming the empty regions 150R in the active fins AF can include removing portions of the sacrificial patterns 104 and the semiconductor patterns 106 to expose top surfaces of the corresponding active patterns 102. In another embodiment, as referred to in FIG. 2, the insulating patterns 150 can be formed in the active fins AF to cross the active fins AF. The insulating patterns 150 can extend along the second direction D2 to cross the active fins AF. In an embodiment, forming the insulating patterns 150 can include removing a portion of the active fins AF to form empty regions 150R in the active fins AF, forming an insulating layer to fill the empty regions 150R, and planarizing the insulating layer to expose top surfaces of the active fins AF. Forming the empty regions 150R in the active fins AF can include removing portions of the sacrificial patterns 104 and the semiconductor patterns 106 to expose top surfaces of the corresponding active patterns 102. Figure 4The insulating pattern 150 can be formed to extend from the regions between the active fins AF into the substrate 100. In this case, the empty regions 150R can be formed by removing a portion of the active fins AF and an upper portion of the substrate 100 (e.g., at least a portion of the corresponding active pattern 102).

[0091] The sacrificial gate structures SGS can be formed on the substrate 100 to cross the active fins AF. The sacrificial gate structures SGS can be formed on the first well regions 110, respectively. Each of the sacrificial gate structures SGS can include the etch stop pattern 202, the sacrificial gate pattern 204, and the gate mask pattern 206 sequentially stacked on the substrate 100. The sacrificial gate pattern 204 can be formed to cover the top and side surfaces of the active fins AF and can extend to cover the top surface of the device isolation pattern ST. The etch stop pattern 202 can be interposed between the sacrificial gate pattern 204 and the active fins AF and can extend into the regions between the sacrificial gate pattern 204 and the device isolation pattern ST. The gate mask pattern 206 can extend along the top surface of the sacrificial gate pattern 204. Each of the sacrificial gate structures SGS can further include the gate side wall GSP disposed on both sides of the sacrificial gate pattern 204. The sacrificial gate structures SGS can be formed by substantially the same method as the method for forming the device isolation pattern ST described with reference to FIGS. 1A to 1C. Figures 5 to 10 The sacrificial gate structures SGS can be formed by substantially the same method as the method for forming the device isolation pattern ST described with reference to FIGS. 1A to 1C.

[0092] Referring to FIG. 1A, Figure 1 , Figure 15 and Figure 16 The connection doping regions 140 can be formed in the active fins AF between the sacrificial gate structures SGS. In an embodiment, forming the connection doping regions 140 can include removing portions of the active fins AF between the sacrificial gate structures SGS to expose the top surfaces of the corresponding active patterns 102, performing a selective epitaxial growth process (in which the exposed top surfaces of the corresponding active patterns 102 serve as seed layers) to form epitaxial patterns, and implanting impurities having the first conductivity type into the epitaxial patterns, and here, the implantation of the impurities can be performed during or after the selective epitaxial growth process. The concentration of the impurities in the connection doping regions 140 can be higher than the concentration of the impurities in the first well regions 110.

[0093] The first doped regions 112 can be formed in the active fins AF and on the first well regions 110, respectively. The first doped regions 112 can be connected to the first well regions 110, respectively. The second doped regions 122 can be formed in the active fins AF and on the second well regions 120, respectively. The second doped regions 122 can be connected to the second well regions 120, respectively. The first doped regions 112 and the second doped regions 122 can be formed by substantially the same method as that for the connected doped regions 140. The concentration of impurities in the first doped regions 112 can be higher than that in the first well regions 110, and the concentration of impurities in the second doped regions 122 can be higher than that in the second well regions 120.

[0094] The third doped regions 132 can be formed in the active fins AF. The third doped regions 132 can be formed by substantially the same method as that for the connected doped regions 140, except that forming the third doped regions 132 can include implanting impurities having the second conductivity type into the epitaxial pattern.

[0095] The first interlayer insulating layer 160 can be formed on the substrate 100 to cover the sacrificial gate structures SGS and the active fins AF. The first interlayer insulating layer 160 can be formed to cover the connected doped regions 140, the first doped regions 112, the second doped regions 122, and the third doped regions 132, as well as the insulating pattern 150. The first interlayer insulating layer 160 can be planarized until the sacrificial gate pattern 204 is exposed, and the gate mask pattern 206 can be removed by a planarization process.

[0096] Referring to Figure 1 , Figure 17 and Figure 18 , the sacrificial gate pattern 204 and the etch stop pattern 202 can be removed, and thus the gap regions 210 can be formed in the first interlayer insulating layer 160. The gate insulating patterns GI, the gate electrodes GE, and the gate cap patterns CAP can be formed to fill each of the gap regions 210. The gate insulating patterns GI, the gate electrodes GE, the gate cap patterns CAP, and the gate side wall patterns GSP can constitute the gate structures GS. The gate structures GS can be formed by substantially the same method as that described with reference to Figures 5 to 10 .

[0097] Except for the above-described differences, the method of manufacturing a semiconductor device according to the present embodiment can be substantially the same as that described with reference to Figures 5 to 10 .

[0098] Figure 19 is a conceptual diagram illustrating a semiconductor device according to an embodiment of the present inventive concept.

[0099] Referring to Figure 19, the semiconductor device 1000 can include an integrated circuit portion IC having an integrated circuit, a pad PAD connected to an external terminal, and an ESD protection device (or ESD protection circuit) 1100 connected to the integrated circuit portion IC and the pad PAD. The integrated circuit portion IC can be composed of a field effect transistor (FET). In an embodiment, the integrated circuit portion IC can be composed of at least one of a planar field effect transistor (planar FET) having a planar channel structure, a fin field effect transistor (Fin-FET) having a three-dimensional channel structure, a multi-bridge channel field effect transistor (MBC-FET), a gate-all-around field effect transistor (GAA FET), a vertical FET having a vertical channel structure, and a negative capacitance FET (NC FET) using negative capacitance. The ESD protection device 1100 can be configured to have substantially the same structure as the lateral bipolar junction transistor described in the related art Figures 1 to 4 and Figure 11 and Figure 12 The ESD current I supplied from the pad PAD during operation of the ESD protection device 1100 can be discharged to a ground electrode Vss.

[0100] According to an embodiment of the inventive concept, the ESD protection device 1100 and the field effect transistor having a three-dimensional channel structure can be easily provided on a single substrate, and the electrical characteristics of the ESD protection device 1100 can be improved.

[0101] According to an embodiment of the inventive concept, a semiconductor device including a highly reliable ESD protection device having a structure integrated with a field effect transistor having a three-dimensional channel structure can be provided.

[0102] While example embodiments of the inventive concept have been particularly shown and described, ordinary skilled in the art will understand that changes can be made in form and detail without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The first well regions are disposed in the substrate and spaced apart from each other; Connecting doped regions are disposed between the first well regions; as well as The first interconnect is electrically connected to the connection doped region via a first contact. The first well region and the connection doped region include impurities having a first conductivity type. The concentration of impurities in the connection doped region is higher than the concentration of impurities in the first well region. Wherein, the depth to which the first well region extends into the substrate is greater than the depth to which the connection doped region extends into the substrate, and The connection doped region includes a first portion, a second portion opposite to the first portion, and a third portion between the first portion and the second portion. The first portion and the second portion of the connection doped region are disposed in the first well region, and the third portion of the connection doped region contacts the substrate.

2. The semiconductor device according to claim 1, wherein, The substrate has a second conductivity type different from the first conductivity type, and The connection doped region, together with a portion of the substrate, forms a PN junction.

3. The semiconductor device according to claim 1, further comprising: The first doped regions are respectively disposed in the first well region. The connecting doped regions are disposed between the first doped regions and spaced apart from the first doped regions. The first doped region includes impurities having the first conductivity type. Wherein, the concentration of impurities in the first doped region is higher than the concentration of impurities in the first well region, and The first interconnect is electrically connected to the first doped region via an additional first contact.

4. The semiconductor device according to claim 3, wherein, Each of the first well regions extends into the region between each of the first doped regions and the connecting doped region.

5. The semiconductor device according to claim 3, further comprising: A gate structure is located on the substrate. The gate structure is disposed on the corresponding first well region in the first well region. The connection doped region is disposed on one side of the gate structure, and One of the first doped regions is disposed on the opposite side of the gate structure.

6. The semiconductor device according to claim 1, further comprising: A second well region is disposed in the substrate and spaced apart from the corresponding first well region in the first well region. The second well region is separated from the connection doped region, wherein the corresponding first well region in the first well region is located between the second well region and the connection doped region.

7. The semiconductor device according to claim 6, further comprising: The second doped region, within the second well region, Wherein, the second well region and the second doped region include impurities having the first conductivity type, and The concentration of impurities in the second doped region is higher than the concentration of impurities in the second well region.

8. The semiconductor device according to claim 7, further comprising: A third doped region is disposed in the substrate and spaced apart from the second well region and the second doped region; as well as The second interconnect is connected to the second doped region and the third doped region via a second contact. Wherein, the third doped region is spaced apart from the corresponding first well region in the first well region, and the second well region and the second doped region are located between the third doped region and the corresponding first well region. The third doped region includes impurities having a second conductivity type different from the first conductivity type.

9. The semiconductor device according to claim 6, further comprising: An insulating pattern is formed between the corresponding first well region and the second well region within the first well region. The height of the bottom surface of the insulating pattern is equal to or lower than the height of the bottom surface of the connection doped region.

10. A semiconductor device, comprising: A substrate, including active fins that project upward from the substrate and extend along a first direction; A first well region is located in the substrate and spaced apart from each other along the first direction; Connecting doped regions are disposed in the active fin between the first well regions; as well as The first interconnect is electrically connected to the connection doped region via a first contact. The first well region and the connection doped region include impurities having a first conductivity type. The concentration of impurities in the connection doped region is higher than the concentration of impurities in the first well region, and The connection doped region includes a first portion, a second portion opposite to the first portion, and a third portion between the first portion and the second portion. The first portion and the second portion of the connection doped region are disposed in the first well region, and the third portion of the connection doped region contacts the substrate.

11. The semiconductor device according to claim 10, wherein, The substrate has a second conductivity type different from the first conductivity type, and The connection doped region, together with a portion of the substrate, forms a PN junction.

12. The semiconductor device according to claim 10, further comprising: A first doped region is disposed within the active fin and the first well region. The connecting doped regions are disposed between the first doped regions and spaced apart from the first doped regions. The first doped region includes impurities having the first conductivity type. Wherein, the concentration of impurities in the first doped region is higher than the concentration of impurities in the first well region, and The first interconnect is electrically connected to the first doped region via an additional first contact.

13. The semiconductor device according to claim 12, wherein, Each of the first well regions extends into the region between each of the first doped regions and the connecting doped region.

14. The semiconductor device according to claim 12, further comprising: A grid structure is provided on the active fin to intersect with the active fin; The connection doped region is disposed on one side of the gate structure, and One of the first doped regions is disposed on the opposite side of the gate structure.

15. The semiconductor device according to claim 12, further comprising: A second well region is located in the substrate and is spaced apart from the corresponding first well region in the first well region along the first direction. Wherein, the second well region is spaced apart from the connection doped region, and the corresponding first well region in the first well region is located between the second well region and the connection doped region, and The second well region includes impurities having the first conductivity type.

16. The semiconductor device of claim 15, further comprising: The second doped region is located within the active fin and the second well region. Wherein, the second doped region is spaced apart from the corresponding first doped region in the first doped region along the first direction. Wherein, the second doped region includes impurities having the first conductivity type, and The concentration of impurities in the second doped region is higher than the concentration of impurities in the second well region.

17. The semiconductor device of claim 16, further comprising: A third doped region is located in the active fin and is spaced apart from the second doped region along the first direction; The second interconnect is electrically connected to the second doped region and the third doped region via a second contact. Wherein, the second doped region is located between the corresponding first doped region and the third doped region in the first doped region, and The third doped region includes impurities having a second conductivity type different from the first conductivity type.

18. The semiconductor device of claim 16, further comprising: An insulating pattern, within the active fin and between the corresponding first doped region and the second doped region in the first doped region. The height of the bottom surface of the insulating pattern is equal to or lower than the height of the bottom surface of the connection doped region.

19. A semiconductor device, comprising: The substrate includes impurities having a first conductivity type; A first well region is disposed in the substrate, the first well region comprising a first first well region and a second first well region spaced apart from each other along a first direction; A connecting doped region is disposed between the first first well region and the second first well region; The first doped region is disposed in the first well region, and the first doped region includes a first first doped region disposed in the first first well region and a second first doped region disposed in the second first well region; as well as The first interconnect is electrically connected to the connection doped region, the first first doped region, and the second first doped region via a first contact. Wherein, each of the first first well region and the second first well region, the connection doped region, and the first first doped region and the second first doped region includes an impurity having a second conductivity type different from the first conductivity type. Wherein, the impurity concentration in the connection doped region and in each of the first and second first doped regions is higher than the impurity concentration in each of the first and second first well regions, and The first portion of the connection doped region is disposed in the first first well region, the second portion of the connection doped region opposite to the first portion is disposed in the second first well region, and the third portion of the connection doped region between the first portion and the second portion contacts the substrate.

20. The semiconductor device of claim 19, further comprising: The second well region is spaced apart from the first first doped region; The second doped region is disposed in the second well region; as well as The second interconnect is electrically connected to the second doped region via a second contact. Each of the second well region and the second doped region includes an impurity having the first conductivity type, and The concentration of impurities in the second doped region is higher than the concentration of impurities in the second well region.

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