Apparatus and method for generating amplitude and rate offsets at a phase comparator

Abstract

The present disclosure relates to apparatuses and methods for generating amplitude and rate offsets at a phase comparator. An example implementation includes a method that obtains an input voltage of a power converter and a system voltage of a power converter circuit; obtains a voltage rate gain based on an aggregate inductance of the power converter circuit; and generates a rate offset voltage based on the voltage rate gain and a system voltage difference in accordance with a determination that the input voltage and the system voltage are not equal. An example implementation also includes an apparatus having a rate predictor device operatively coupled to an input voltage node and a system voltage node, and the rate predictor device is configured to obtain an input voltage of a power converter circuit and a system voltage of the power converter circuit; obtain a voltage rate gain based on an aggregate inductance of the power converter circuit; and generate a rate offset voltage based on the voltage rate gain and a system voltage difference in accordance with a determination that the input voltage and the system voltage are not equal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 944,594, filed December 6, 2019, entitled “PHASE COMPARATOR”, the entire contents of which are incorporated herein by reference and used for all purposes set forth herein in their entirety. Technical Field

[0003] This implementation generally relates to electrical chargers, and more particularly to generating amplitude and rate offsets at a phase comparator device. Background Technology

[0004] Constant power delivery in environments with rapidly changing power demands is becoming increasingly critical for the operation of systems comprising both electrical and electronic components. As an example, electronic computing systems are subjected to rapid and unpredictable changes in power and load demands from power sources in response to "hot-swappable" peripherals. However, conventional systems cannot effectively manage changes in voltage amplitude and frequency to maintain constant power characteristics for the system load. Therefore, a technical solution for generating amplitude and rate offsets at phase comparator devices is desired. Summary of the Invention

[0005] An example implementation includes a method that obtains the input voltage and system voltage of a power converter circuit; obtains a voltage rate gain based on the aggregate inductance of the power converter circuit; and generates a rate offset voltage based on the voltage rate gain and the system voltage difference, provided that the input voltage and system voltage are determined to be unequal.

[0006] The example implementation also includes a device having a rate predictor device operatively coupled to an input voltage node and a system voltage node, and the rate predictor device being configured to: acquire the input voltage of the power converter circuit and the system voltage of the power converter circuit; acquire a voltage rate gain based on the aggregate inductance of the power converter circuit; and generate a rate offset voltage based on the voltage rate gain and the system voltage difference, provided that the input voltage and the system voltage are determined to be unequal.

[0007] The example implementation also includes a device having a rate predictor and a comparator. The rate predictor includes a memory device and is operatively coupled to an input voltage node and a system voltage node, and is configured to: acquire the input voltage of the power converter circuit and the system voltage of the power converter circuit; acquire a voltage rate gain from the memory device based on the aggregate inductance of the power converter circuit; and generate a rate offset voltage based on the voltage rate gain and the system voltage difference, depending on whether the input voltage and system voltage are determined to be unequal. The comparator has a rate offset input, is operatively coupled to the rate predictor device, and is configured to receive the rate offset voltage at the rate offset input. Attached Figure Description

[0008] These and other aspects and features of this implementation will become apparent to those skilled in the art from a review of the description of the specific implementation below in conjunction with the accompanying drawings, wherein:

[0009] Figure 1 An example system based on this implementation is illustrated.

[0010] Figure 2 An example phase comparator device according to this implementation is illustrated.

[0011] Figure 3 An example timing diagram for an example phase comparator device according to this implementation is shown.

[0012] Figure 4 An example method for compensating the phase comparator voltage according to this implementation is illustrated.

[0013] Figure 5 The diagram illustrates the following steps according to this implementation. Figure 4 This method further compensates for the phase comparator voltage. Detailed Implementation

[0014] The present implementation will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of implementations to enable those skilled in the art to practice the implementation and alternatives that are obvious to them. It should be noted that the following drawings and examples are not intended to limit the scope of the present implementation to a single implementation, but rather, other implementations are possible by exchanging some or all of the elements described or illustrated. Furthermore, certain elements of the present implementation may be implemented partially or entirely using known components, and only those parts of such known components necessary for understanding the present implementation will be described, while detailed descriptions of other parts of such known components will be omitted so as not to obscure the present implementation. An implementation described as being implemented in software should not be considered limiting, but may include implementations implemented in hardware, and vice versa, as will be obvious to those skilled in the art, unless otherwise specified herein. In this specification, an implementation showing a single component should not be considered limiting, but rather, this disclosure is intended to cover other implementations that include multiple identical components, and vice versa, unless expressly stated otherwise herein. Furthermore, the applicant does not intend any terminology in the specification and claims to be uncommon or special in meaning unless expressly stated as such. Furthermore, this implementation covers the current and future known equivalents of the known components referred to herein as illustrative references.

[0015] It should be understood that a phase comparator system can withstand voltage variations based on load differences. As an example, load changes caused by the connection and disconnection of electronic devices at various power levels can affect the operation of an example phase comparator device. To continue and maintain constant operation in response to changes in load conditions, the example phase comparator can compensate for such changes by modifying at least one output compensation voltage generated by the phase comparator. In some implementations, the phase comparator according to this implementation is operable to compensate for changes in the magnitude and rate of change of its current or voltage. It will be further understood that the example phase comparator can operate in discontinuous conduction mode (DCM), and changes in its system voltage or other internal voltages can interfere with the operation of the phase comparator, including causing the phase comparator to exit DCM and enter continuous conduction mode (CCM). Therefore, in some implementations, the example phase comparator device and system according to this implementation are operable to compensate solely based on the rate of change of current or voltage, or based on both the rate of change of current or voltage and the magnitude of the change in current or voltage.

[0016] Figure 1 The illustration shows a sample system implemented according to this invention. As an example, in... Figure 1 As illustrated, the example system 100 includes an input 102, an output 104, a charger 106, a charger compensator 108, and a phase comparator 100.

[0017] Input 102 is, includes, or is operatively coupled to a source of electrical power, such as voltage or current, for supplying power to system 100. In some embodiments, input 102 includes, but is not limited to, 120V AC regulated power, 220V AC regulated power, 5V DC power, 12V DC power, etc. In some implementations, input 102 includes wired power connections, wireless direct-contact power connections, wireless and contactless power connections, etc. In some implementations, input 102 includes one or more USB terminals or ports (e.g., USB-C, USB-PD).

[0018] Output 104 is, includes, or is operatively coupled to one or more electrical, electronic, electromechanical, electrochemical, or similar devices or systems for receiving power, voltage, current, etc., from charger 106 to perform one or more actions. In some implementations, output 104 includes at least one battery, electronic display, electronic computer, electronic output device, electromechanical input device, electronic output device, electromechanical output device, etc. Examples of such devices include notebook computers, desktop computers, tablets, smartphones, printers, scanners, telephone terminals, video conferencing terminals, keyboards, mice, trackpads, gaming peripherals, monitors, televisions, etc. In some implementations, output 104 includes one or more devices that are partially or completely separable from system 100. In some implementations, output 104 includes one or more devices that are partially or completely integrated into or can be integrated into system 100, or can be separable from system 100.

[0019] Charger 106 is or includes one or more electrical, electronic, electromechanical, electrochemical, or similar devices or systems for charging output 104. In some implementations, charger 106 is or includes an inductive charger. In some implementations, the inductive charger is a buck charger, a boost charger, a buck-boost charger, a combination of the foregoing, etc.

[0020] In response to feedback received from at least one of input 102, output 104, and charger 106, charger compensator 108 is operable to apply one or more compensating electrical outputs. In some implementations, charger compensator 108 includes one or more analog or digital logic or electronic devices, including but not limited to operational amplifiers, comparators, integrated circuits, logic gates, bistable flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device, or component associated with charger compensator 108, may also be associated with, integrated with, replaced by, supplemented by, complemented by, etc., a system processor or any component thereof.

[0021] The system processor is operable to execute one or more instructions associated with at least one input from input 102, output 104, and charger 106. In some implementations, the system processor is an electronic processor, integrated circuit, etc., including one or more digital logic, analog logic, digital sensors, analog sensors, communication buses, volatile memory, non-volatile memory, etc. In some implementations, the system processor includes, but is not limited to, at least one microcontroller unit (MCU), microprocessor unit (MPU), central processing unit (CPU), graphics processing unit (GPU), physical processing unit (PPU), embedded processor (EC), etc. In some implementations, the system processor includes memory operable to store, or store, one or more instructions for operating the system processor and operating components operatively coupled to the system processor. In some implementations, the one or more instructions include at least one of firmware, software, hardware, operating system, embedded operating system, etc.

[0022] Figure 2 An example phase comparator device according to this implementation is illustrated. As an example, in... Figure 2 As illustrated, the example phase comparator device 200 includes an input 102, an output 104, a charger 106, and a charger compensator 108.

[0023] In some implementations, input 102 includes voltage source 202. In some implementations, input 102 is operatively coupled to a charger compensator via input feedback line 258. In some implementations, output 104 includes output node 204.

[0024] Voltage source 202 is operable to supply at least one input voltage, including at least one of direct current (DC) and alternating current (AC). In some implementations, the voltage source is operatively coupled to at least one of the input of inductor 210 and the input of rate predictor 250.

[0025] In some implementations, power supply 106 includes an inductor 210, a high-side boost transistor Q4 212, a low-side boost transistor Q3 214, and an output capacitor 220. In some implementations, the high-side boost transistor Q4 212 has an inductor 216, and the low-side boost transistor Q3 has an inductor 218.

[0026] Inductor 210 is replaceable, configurable, selectable, etc., to have a specific inductance to meet the specific power requirements of at least one of charger 106 and charger compensator 108. In some implementations, inductor 210 may be replaced with a specific inductor compatible with the gain ratio associated with rate predictor 250. In some implementations, inductor 210 may be replaced with a specific inductor that satisfies the gain ratio with rate predictor 250. In some implementations, the rate of change of current at inductor 210 is described by Equation 1, where VSYS is the output voltage at the output node, V in It is the input voltage at voltage source 202, L is the inductance at inductor 210, and It is the rate of change of the current:

[0027]

[0028] High-side boost transistor Q4 212 is operatively coupled to output node 204 and inductor 210. Low-side boost transistor Q3 214 is operatively coupled to inductor 210 and ground node. In some implementations, high-side boost transistor Q4 212 and low-side boost transistor Q3 214 are field-effect transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), etc. In some implementations, inductor 210, high-side boost transistor Q4 212, and low-side boost transistor Q3 214 are arranged in a boost-mode DC-DC converter. Inductors 216 and 218 are parasitic inductances associated with high-side boost transistor Q4 212 and low-side boost transistor Q3 214, respectively. In some implementations, the rate of change of current at the high-side boost transistor Q4212 is described by Equation 2, where VLs is the parasitic voltage at the high-side boost transistor Q4212, Ls is the parasitic inductance at the high-side boost transistor Q4212, and... It is the rate of change of the current:

[0029]

[0030] In some implementations, the charger compensator 108 includes a system voltage comparator 230, an amplitude compensator 240, a rate predictor 250, and a compensation generator 260.

[0031] System voltage comparator 230 is operable to determine the difference between the system voltage and the inductor output voltage. In some implementations, the system voltage is the voltage at output 104 or an equivalent thereto. In some implementations, the inductor output voltage is the voltage at the inductor output node or an equivalent thereto. In some implementations, the inductor output node is operatively coupled to the boost-side terminal of inductor 210. In some implementations, the inductor output node is directly or operatively coupled to inductor 210, high-side boost transistor Q4, and low-side boost transistor 214. In some implementations, system voltage comparator 230 is or includes an operational amplifier. In some implementations, system voltage comparator 230 receives the system voltage at the non-inverting input and the inductor output at the inverting input. Therefore, in some implementations, the system voltage comparator is operable to subtract the input voltage from the system voltage.

[0032] In some implementations, the system voltage comparator 230 includes one or more analog or digital logic or electronic devices, including but not limited to operational amplifiers, comparators, integrated circuits, logic gates, bistable flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device, or component associated with the system voltage comparator 230, may also be associated with, integrated with, replaced by, supplemented by, complemented by, etc., the system processor or any of its components. In some implementations, the system voltage comparator 230 is operatively coupled to the output node 204 via system output feedback line 232 and to the inductor 210 via inductor output feedback line 234.

[0033] Amplitude compensator 240 is operable to apply an offset voltage based on the difference between the system voltage and the inductor output voltage, and the voltage drop across the high-side boost transistor Q4 212. In some implementations, amplitude compensator 240 is operable to apply a positive offset voltage according to a first voltage condition and a negative offset voltage according to a second voltage condition. In some implementations, the first voltage condition is satisfied when the inductor output voltage is less than the system voltage. In some implementations, the amplitude compensator is operable to apply a voltage at one or more discrete voltage levels, defined by a counter, adder, etc., including one or more bits indicating a specific voltage level, step size, etc. In some implementations, the second voltage condition is satisfied when the inductor output voltage equals the system voltage plus the voltage drop across the high-side boost transistor Q4 212. In some implementations, amplitude compensator 240 responds to delayed feedback. In some implementations, the delay is up to 32 switching cycles of charger 106.

[0034] In some implementations, amplitude compensator 240 includes one or more analog or digital logic or electronic devices, including but not limited to operational amplifiers, comparators, integrated circuits, logic gates, bistable triggers, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device, or component associated with amplitude compensator 240, may also be associated with, integrated with, replaced by, supplemented by, or complemented by a system processor or any of its components. In some implementations, amplitude compensator 240 is operatively coupled to inductor 210 via inductor output feedback line 242, to the high-voltage side of high-voltage transistor Q4 212 via high-voltage-side transistor feedback line 244, and to the low-voltage side of high-voltage transistor Q4 212 via low-voltage-side transistor feedback line 246. In some implementations, the amplitude compensator detects the voltage drop across high-voltage-side boost transistor Q4 212 by detecting the voltages at high-voltage-side transistor feedback line 244 and low-voltage-side transistor feedback line 246 and taking the difference between the two.

[0035] Rate predictor 250 is operable to apply an offset voltage at the output of charger 106 based on the rate of change of the current through high-side boost transistor 212. In some implementations, the rate predictor includes a non-volatile memory, register, bistable multivibrator, gate array, programmable gate array, etc., operable to store at least one value of gain K. In some implementations, gain K is predetermined to identify, indicate, support, or be compatible with a specific inductance of inductor 210. In some implementations, gain K stores the ratio of the inductance of inductor 210 to the parasitic inductance of high-side boost transistor 212. In some implementations, rate predictor 250 includes one or more analog or digital logic or electronic devices, including but not limited to operational amplifiers, comparators, integrated circuits, logic gates, bistable multivibrators, gate arrays, programmable gate arrays, etc. In some implementations, rate predictor 250 responds instantaneously to changes in the rate of change of current, voltage, etc., to generate the offset voltage. It should be understood that any electrical, electronic, or similar device, or component associated with the rate predictor 250, may also be associated with, integrated with, replace, supplement, complement, etc., of the system processor or any of its components. In some implementations, the rate predictor 250 is operatively coupled to the output node via system output feedback line 252 and operatively coupled to the voltage source 202 via system input feedback line 254. In some implementations, the rate predictor is operable to store and retrieve the gain K based at least in part on the parasitic inductance of inductor 210 and the high-side boost transistor Q4 212 (as described in Equations 1 and 2). In some implementations, the relationship between the parasitic voltage VLs, the system voltage VSYS, the input voltage Vin, the inductance of inductor 210, and the parasitic inductance of the high-side boost transistor Q4 212 is described by Equation 3, and the gain K is described by Equation 4.

[0036]

[0037] V Lo =K(V) sys -V in ),in

[0038] Compensation generator 260 is operable to arithmetically combine one or more voltage values ​​or offsets, and to generate a total offset voltage. In some implementations, compensation generator 260 includes one or more analog or digital logic or electronic devices, including but not limited to operational amplifiers, comparators, integrated circuits, logic gates, bistable triggers, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device, or component associated with compensation generator 260, may also be associated with, integrated with, replaced by, supplemented by, complemented by, etc., a system processor or any component thereof. In some implementations, a first non-inverting input of compensation generator 260 is operatively coupled to the output of system voltage comparator 230, an inverting input of compensation generator 260 is operatively coupled to the output of amplitude comparator 240, and a second non-inverting input of compensation generator 260 is operatively coupled to the output of rate predictor 250. In some embodiments, the output 262 of compensation generator is operatively coupled to control logic operable to drive at least one or more of transistors 212 and 214 according to the present implementation.

[0039] Figure 3 The illustration shows an example timing diagram for an example phase comparator device according to this implementation. As an example... Figure 3 As illustrated, example timing diagram 300 includes a low-side boost transistor Q3 voltage timing waveform 320, a high-side boost transistor Q4 voltage timing waveform 330, an inductor L current timing waveform 340, and a compensation generator voltage timing waveform 350. In some implementations, at least one of example system 100 and example device 200 performs operation according to example timing diagram 300. In some implementations, the example phase comparator device starts operating in discontinuous conduction mode (DCM). In some implementations, the example phase comparator device starts operating at time 302 of example timing diagram 300. In some implementations, low-side boost transistor Q3, high-side boost transistor Q4, inductor L, and compensation generator correspond to transistor 214, transistor 212, inductor 210, and compensation generator 260, respectively. According to this implementation, the example phase comparator device includes operations performed by amplitude comparator 240 and rate predictor 250 to achieve operation according to example timing diagram 300.

[0040] In some implementations, the phase comparator device is operable at least at a low DCM voltage approximately equal to zero, a discrete DCM voltage greater than zero, and a jittery DCM voltage greater than the low DCM voltage and less than the discrete DCM voltage. In some implementations, the discrete DCM voltage is stable at a first voltage level. In some implementations, the discrete DCM voltage is stable at a DC voltage level. In some implementations, the discrete DCM voltage is at least on average higher than the jittery DCM voltage. In some implementations, the jittery DCM voltage is variable within a predetermined range of a second voltage level. In some implementations, the first voltage level is higher than the second voltage level. In some implementations, the mean of the first voltage level is higher than the mean of the second voltage level. In some implementations, the mean of one or more of the first and second voltages is an average voltage, root mean square voltage (VRMS), etc.

[0041] At time 302, transistor Q3 begins pulse 322, having a high voltage state at or above its activation voltage. Concurrently, transistor Q4 is in a low voltage state between pulses, having a voltage state below its activation voltage. In response to the states of transistors Q3 and Q4 at 302, inductor L increases the current I passing through it along ramp 342 toward the first peak current. Concurrently, the compensation generator is in a low DCM voltage between pulses. In some implementations, at time 302, transistors Q3 and Q4 concurrently, simultaneously, or similarly switch to their respective high and low states.

[0042] At time 304, transistor Q3 ends pulse 322 and enters a low-voltage state below its activation voltage. Concurrently, transistor Q4 begins its first pulse 332 and enters a high-voltage state at or above its activation voltage. In response to the states of transistors Q3 and Q4 at 304, inductor L reduces its current I from its first peak current along ramp 344 toward zero current. In some implementations, inductor L reaches its first peak current at time 304, at the transition between the end of the first charging period at time 304 and the start of the first discharging period at time 304. Concurrently, the compensation generator begins the first DCM pulse 352 and has a voltage state corresponding to the discrete DCM voltage. In some implementations, at time 304, transistors Q3 and Q4 concurrently, simultaneously, or similarly switch to their respective high and low states. In some implementations, the period between times 302 and 304 has a first duration, which depends on the operation of the charger 106 in at least one of buck mode, boost mode, and buck-boost mode. In some implementations, the period between times 302 and 304 corresponds to the length of pulse 322.

[0043] At time 306, transistor Q3 remains in a low-voltage state below its activation voltage. Concurrently, transistor Q4 enters a low-voltage state below its activation voltage. In response to the states of transistors Q3 and Q4 at 306, inductor L reduces its current I from its first peak current toward zero current and maintains a low inductor current 362 that is substantially equal to zero. In some implementations, the low inductor current 362 varies within a predetermined range centered on zero voltage. In some implementations, inductor L reaches its first zero current at time 306, at the transition between the end of the first discharge period at time 306 and the beginning of the first discontinuous period at time 306. Concurrently, the compensation generator begins the second DCM pulse 354 and has a voltage state corresponding to the jittered DCM voltage. In some implementations, the period between times 304 and 306 has a duration corresponding in length to the first duration. In some implementations, the period between times 304 and 306 corresponds to the length of the time between pulses 332 and 322.

[0044] At time 308, transistor Q3 begins the second pulse 322 and enters its high-voltage state. Concurrently, transistor Q4 remains in its low-voltage state. In response to the states of transistors Q3 and Q4 at 308, inductor L increases its current along ramp 346 toward the second peak current. Concurrently, the compensation generator ends the second DCM pulse and has a voltage state corresponding to the low DCM voltage. In some implementations, the period between times 306 and 308 has a second duration shorter than the first duration; in some implementations, the period between times 306 and 308 corresponds to the length of pulse 322.

[0045] At time 310, transistor Q3 ends pulse 322 and enters its low-voltage state. Concurrently, transistor Q4 begins its second pulse 334 and enters its high-voltage state. In response to the states of transistors Q3 and Q4 at 310, inductor L reduces its current I from its second peak current along ramp 348 toward zero current. In some implementations, inductor L reaches its second peak current at time 310, at the transition between the end of the second charging period at time 310 and the start of the second discharging period at time 310. Concurrently, the compensation generator begins a third DCM pulse 356 and has a voltage state corresponding to the discrete DCM voltage. In some implementations, the third DCM pulse has a shorter period than the period corresponding to the first DCM pulse 352. Here, the shorter second DCM pulse 356 responds to the shorter Q4 pulse 334, while the longer first DCM pulse 352 responds to the correspondingly longer Q4 pulse 332. In some implementations, at time 310, transistors Q3 and Q4 concurrently, simultaneously, or similarly switch to their respective high and low states. In some implementations, the period between times 308 and 310 has a first duration. In some implementations, the period between times 308 and 310 corresponds to the length of the second pulse 322.

[0046] At time 312, transistor Q3 remains in its low-voltage state. Concurrently, transistor Q4 enters its low-voltage state. In response to the states of transistors Q3 and Q4 at 312, inductor L reduces its current I from its second peak current toward zero current and maintains a low inductor current 362 that is substantially equal to zero. In some implementations, the low inductor current 362 varies within a predetermined range centered on zero voltage. In some implementations, inductor L reaches its second zero current at time 312, at the transition between the end of the second discharge period at time 312 and the start of the second discontinuous period at time 312. Concurrently, the compensation generator begins the fourth DCM pulse 358 and has a voltage state corresponding to the jitter DCM voltage. In some implementations, the period between times 310 and 312 has a third duration that is shorter than the first duration and longer than the second duration. In some implementations, the period between times 310 and 312 corresponds to the length of the time between pulses 334 and 322. In some implementations, the third duration is longer than the second duration in response to the shorter pulse 334 before pulse 358, compared to the longer pulse 332 before pulse 354.

[0047] At time 314, transistor Q3 begins its third pulse 322 and enters its high-voltage state. Concurrently, transistor Q4 remains in its low-voltage state. In response to the states of transistors Q3 and Q4 at 314, inductor L increases its current along ramp 346 toward the second peak current. Concurrently, the compensation generator ends its fourth DCM pulse and has a voltage state corresponding to the low DCM voltage. In some implementations, the period between times 312 and 314 has a third duration. In some implementations, the period between times 312 and 314 corresponds to the length of pulse 322.

[0048] At time 316, transistor Q3 ends pulse 322 and enters its low-voltage state. Concurrently, transistor Q4 begins its third pulse 334 and enters its high-voltage state. In response to the states of transistors Q3 and Q4 at 316, inductor L reduces its current I from its second peak current along ramp 348 toward zero current. In some implementations, inductor L reaches its second peak current at time 316, at the transition between the end of the third charging period at time 316 and the start of the third discharging period at time 316. Concurrently, the compensation generator begins the fifth DCM pulse 352 and has a voltage state corresponding to the discrete DCM voltage. In some implementations, at time 316, transistors Q3 and Q4 concurrently, simultaneously, or similarly switch to their respective high and low states. In some implementations, the period between times 314 and 316 has a first duration. In some implementations, the period between times 314 and 316 corresponds to the length of pulse 322.

[0049] At time 318, the example phase comparator device operates according to its operation at time 306. After time 318, the example phase comparator continues to operate in a loop. In some implementations, the loop corresponds to the periodic operation of an inductor charger in at least one of buck mode, boost mode, and buck-boost mode. In some implementations, the example phase comparator device operates periodically by entering states corresponding to at least one of times 302, 308, and 304.

[0050] Figure 4 An example method for compensating a phase comparator voltage according to this implementation is illustrated. In some implementations, at least one of example system 100 and example device 200 performs method 400 according to this implementation. In some implementations, method 400 begins at step 410.

[0051] In some implementations, the example system deactivates the high-side inductor transistor Q4. In some implementations, the charger 106 activates the high-side inductor transistor Q4 212 according to its operation in buck mode, boost mode, or buck-boost mode, which is electronically controlled. Method 400 then proceeds to step 412. At step 412, the example system deactivates the low-side inductor transistor Q3. In some implementations, the charger 106 activates the high-side inductor transistor Q3 214 according to its operation in buck mode, boost mode, or buck-boost mode, which is electronically controlled. Method 400 then proceeds to step 420. At step 420, the example system acquires the inductor voltage IL at inductor L. In some implementations, inductor L is inductor 210. In some implementations, the system voltage comparator 230 and amplitude compensator 240 acquire the inductor voltage IL at their respective inputs via feedback lines 242 and 252, respectively.

[0052] At step 430, the example system determines whether Q4 deactivates after L reaches 0V. In some implementations, the charger compensator 108 determines whether Q4 deactivates after L reaches 0V by determining whether a first voltage condition is met. Based on the determination that Q4 deactivates after L reaches 0V, method 400 continues to step 450. Alternatively, based on the determination that Q4 does not deactivate after L reaches 0V, method 400 continues to step 432. At step 432, the example system determines whether Q4 deactivates before L reaches 0V. In some implementations, the charger compensator 108 determines whether Q4 deactivates before L reaches 0V by determining whether a second voltage condition is met. Based on the determination that Q4 deactivates before L reaches 0V, method 400 continues to step 440. Alternatively, based on the determination that Q4 does not deactivate after L reaches 0V, method 400 continues to step 434. At step 434, the example system prevents, abandons, or performs similar actions in generating any offset voltage at the example system. In some implementations, at step 434, neither the amplitude compensator 240 nor the rate predictor 250 generates any offset voltage or a value based on the operation of the example system. In some implementations, method 400 terminates at step 434.

[0053] At step 440, the example system generates a negative amplitude offset voltage VOFF. In some implementations, at least one of the charger compensator 108 and the amplitude compensator 240 generates a negative amplitude offset voltage VOFF. Method 400 then proceeds to step 460. At step 450, the example system generates a positive amplitude offset voltage VOFF. In some implementations, at least one of the charger compensator 108 and the amplitude compensator 240 generates a positive amplitude offset voltage VOFF. Method 400 then proceeds to step 460. At step 460, the example system applies the offset voltage VOFF to the phase comparator. In some implementations, the amplitude compensator 240 outputs a positive or negative amplitude offset voltage VOFF to the inverting input of the compensation generator 260. Method 400 then proceeds to step 510.

[0054] Figure 5 The diagram illustrates the following steps according to this implementation. Figure 4 The method further compensates the phase comparator voltage. In some implementations, at least one of example system 100 and example device 200 performs method 500 according to this implementation. In some implementations, method 500 begins at step 510. Method 500 then continues to step 520.

[0055] At step 520, the example system obtains the system voltage difference VDIFF from the system voltage VSYS and the input voltage VIN. In some implementations, the system voltage comparator 230 generates the system voltage difference VDIFF. In some implementations, the rate predictor 250 also generates the system voltage difference VDIFF independently of the system voltage comparator 230. Method 500 then continues to step 530.

[0056] At step 530, the example system obtains the voltage rate gain K from the ratio of L to LS. In some implementations, the rate predictor 250 obtains the gain K from a programming operation that sets the value of its rate gain at a memory device, component, etc. In some implementations, the rate predictor obtains the gain K from its stored value in response to programming, setting, etc., of the value during the manufacturing time of the example system or during operations such as diagnostics, testing, and debugging of the example system. Method 500 then proceeds to step 540. At step 540, the example system determines whether the voltage difference VDIFF is equal to zero. In some implementations, the rate predictor 250 determines whether the voltage difference VDIFF is equal to zero. Based on the determination that the voltage difference VDIFF is equal to zero, method 500 proceeds to step 434. Alternatively, based on the determination that the voltage difference VDIFF is not equal to zero, method 500 proceeds to step 550.

[0057] At step 550, the example system generates a rate offset voltage VLs based at least in part on the voltage rate gain K and the system voltage difference VDIFF. In some implementations, the rate predictor 250 generates the rate offset voltage VLs based on the voltage rate gain K stored therewith and the voltage difference VDIFF detected therefrom. In some implementations, step 550 includes step 552. At step 522, the example system generates the rate offset voltage VLs incidentally. In some implementations, the rate predictor 250 generates the rate offset voltage VLs incidentally as the input voltage or system voltage level changes. Method 500 then continues to step 560. At step 560, the example system applies the rate offset voltage VLs to the phase comparator. In some implementations, the compensation generator 260 generates the output 262 of the compensation generator as an arithmetic sum of the outputs of the system voltage comparator 230, the amplitude comparator 240, and the rate predictor 250. In some implementations, method 500 ends at step 560.

[0058] The technical solutions described herein illustrate different components contained in or connected to different other components. It should be understood that the architectures depicted are illustrative, and many other architectures can indeed achieve the same functionality. Conceptually, any arrangement of components to achieve the same functionality is effectively “associated” to enable the desired functionality to be achieved. Therefore, any two components combined in this document to achieve a specific functionality can be considered “associated” with each other to enable the desired functionality, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered to be “operably connected” or “operably coupled” to each other to achieve the desired functionality, and any two components that can be suchly associated can also be considered to be “operably coupled” to each other to achieve the desired functionality. Specific examples of operably coupled components include, but are not limited to, physically pairable and / or physically interacting components, and / or wirelessly interacting and / or logically interacting components.

[0059] Regarding the use of plural and / or singular terms in this document, those skilled in the art can convert from plural to singular and / or from singular to plural as appropriate for the context and / or application. For clarity, various singular / plural substitutions may be explicitly stated herein.

[0060] Those skilled in the art will understand that, generally, the terms used herein, and especially in the claims (e.g., the body of the claims), are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least one”, the term “comprising” should be interpreted as “including but not limited to”, etc.).

[0061] Although the accompanying drawings and descriptions may illustrate the order of specific method steps, such order may differ from that depicted and described unless otherwise specified above. Similarly, two or more steps may be performed concurrently or partially concurrently unless otherwise specified above. Such variations may depend, for example, on the chosen software and hardware system, and on the designer's choice. All such variations are within the scope of this disclosure. Likewise, the software implementation of the described methods can be achieved using standard programming techniques, employing rule-based logic and other logic to achieve various connection steps, processing steps, comparison steps, and decision steps.

[0062] Those skilled in the art will further understand that if the intent is to introduce a specific number of claim statements, such intent will be explicitly stated in the claims, and in the absence of such statements, such intent does not exist. For example, to aid understanding, a claim may include the use of the introductory phrases “at least one” and “one or more” to introduce the claim statement. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any specific claim containing such an introductory claim statement to contain only one such statement, even when the same claim includes the introductory phrases “at least one” and “one or more” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” should typically be interpreted as meaning “at least one” or “one or more”); the same applies to definite articles used to introduce the claim statement. Furthermore, even if a specific number of claims is explicitly stated, those skilled in the art will recognize that such a statement should typically be interpreted as meaning at least the stated number (e.g., a statement of "two statements" without other modifiers typically means at least two statements, or two or more statements).

[0063] Furthermore, in instances where the conventional usage of "at least one of A, B, and C" is used, such a construction is generally intended to have a meaning that will be understood by a person skilled in the art (e.g., "having at least one of A, B, and C" includes, but is not limited to, having A alone, having B alone, having C alone, having A and B together, having A and C together, having B and C together, and / or, a system of A, B, and C together, etc.). In instances where the conventional usage of "at least one of A, B, or C" is used, such a construction is generally intended to have a meaning that will be understood by a person skilled in the art (e.g., "having at least one of A, B, or C" includes, but is not limited to, having A alone, having B alone, having C alone, having A and B together, having A and C together, having B and C together, and / or, a system of A, B, and C together, etc.). Those skilled in the art will further understand that, substantially, any separate words and / or phrases presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to account for the possibility of including one of these terms, any one of these terms, or both terms. For example, the phrase “A or B” will be understood as including “A” or “B” or “A and B”.

[0064] In addition, unless otherwise noted, the words “approximately,” “around,” “around,” “basically,” etc., mean plus or minus 10 percent.

[0065] The illustrative description of the implementations above has been presented for purposes of explanation and description. The precise form disclosed is not intended to be exhaustive or limiting, and modifications and variations are possible based on the foregoing teachings, or may be obtained from the practice of the disclosed implementations. The scope of the invention is defined herein by the claims and their equivalents.

Claims

1. A method for compensating the voltage of a phase comparator, the method comprising: Obtain the input voltage of the charger circuit and the system voltage supplied by the charger circuit to the output; Based on the internal inductance of the charger circuit, a voltage rate gain relating to the rate of change of voltage is obtained, wherein the internal inductance includes the inductance of the inductor of the charger circuit and the parasitic inductance of the high-voltage side inductor transistor of the charger circuit. as well as Based on the determination that the input voltage and the system voltage are not equal, a rate offset voltage is generated based on the voltage rate gain and the system voltage difference obtained from the system voltage and the input voltage; The rate offset voltage is applied to the phase comparator to maintain the operation of the charger circuit in discontinuous conduction mode.

2. The method of claim 1, wherein the voltage rate gain is based on the ratio of the inductance of the inductor of the charger circuit to the parasitic inductance of the high-voltage side inductor transistor of the charger circuit.

3. The method according to claim 1, wherein the voltage rate gain has a predetermined value.

4. The method of claim 1, wherein the generating the rate offset voltage comprises: The rate offset voltage is generated in response to the change in the system voltage.

5. The method of claim 1, wherein the generating the rate offset voltage comprises: The rate offset voltage is generated instantaneously in response to a change in the system voltage.

6. The method according to claim 1, further comprising: Based on the determination that the inductor voltage across the inductor in the charger circuit is essentially 0 V at a time that satisfies the deactivation time threshold, an offset voltage with a predetermined amplitude is generated.

7. The method of claim 6, wherein the deactivation time threshold is prior to the deactivation time of the high-voltage side inductor transistor of the charger circuit, and the predetermined amplitude is negative.

8. The method of claim 6, wherein the deactivation time threshold is after the deactivation time of the high-voltage side inductor transistor of the charger circuit, and the predetermined amplitude is positive.

9. The method according to claim 6, further comprising: The system voltage difference, the rate offset voltage, and the offset voltage are aggregated into a compensation voltage.

10. The method of claim 9, further comprising: The compensation voltage is applied to the charger circuit to maintain its operation in discontinuous conduction mode.

11. A phase comparator device, comprising: A rate predictor device is operatively coupled to an input voltage node and a system voltage node, and the rate predictor device is configured to: Obtain the input voltage of the charger circuit and the system voltage supplied by the charger circuit to the output; A voltage rate gain relating to the rate of change of voltage is obtained based on the internal inductance of the charger circuit, wherein the internal inductance includes the inductance of the inductor of the charger circuit and the parasitic inductance of the high-voltage side inductor transistor of the charger circuit. as well as Based on the determination that the input voltage and the system voltage are not equal, a rate offset voltage is generated based on the voltage rate gain and the system voltage difference obtained from the system voltage and the input voltage. A compensation generator having a rate offset input is operably coupled to the rate predictor device and configured to receive the rate offset voltage at the rate offset input to maintain the operation of the charger circuit in discontinuous conduction mode based on the rate offset voltage.

12. The device of claim 11, wherein the voltage rate gain is based on the ratio of the inductance of the inductor of the charger circuit to the parasitic inductance of the high-voltage side inductor transistor of the charger circuit.

13. The device of claim 11, wherein the rate predictor is further configured to store the voltage rate gain as a predetermined value in a non-volatile memory together with the rate predictor.

14. The device of claim 11, wherein the rate predictor is further configured to generate the rate offset voltage in response to a change in the system voltage.

15. The device of claim 11, wherein the rate predictor is further configured to generate the rate offset voltage instantaneously in response to a change in the system voltage.

16. The device of claim 11, wherein the rate predictor is further configured to generate an offset voltage of a predetermined amplitude based on determining that the inductor voltage across the inductor of the charger circuit is substantially 0 V at a time that satisfies a deactivation time threshold.

17. The device of claim 16, wherein the deactivation time threshold is prior to the deactivation time of the high-voltage side inductor transistor of the charger circuit, and the predetermined amplitude is negative.

18. The device of claim 16, wherein the deactivation time threshold is after the deactivation time of the high-voltage side inductor transistor of the charger circuit, and the predetermined amplitude is positive.

19. The device of claim 16, wherein the compensation generator is configured to: aggregate the system voltage difference, the rate offset voltage, and the offset voltage into a compensation voltage, and apply the compensation voltage to the charger circuit to maintain operation of the charger circuit in a discontinuous conduction mode.

20. A phase comparator system, comprising: A rate predictor device, including a memory device, and said rate predictor device is operatively coupled to an input voltage node and a system voltage node, and is configured to: Obtain the input voltage of the charger circuit and the system voltage supplied by the charger circuit to the output; Based on the internal inductance of the charger circuit, a voltage rate gain relating to the rate of change of voltage is obtained from the memory device, wherein the internal inductance includes the inductance of the inductor of the charger circuit and the parasitic inductance of the high-side inductor transistor of the charger circuit. as well as Based on the determination that the input voltage and the system voltage are not equal, a rate offset voltage is generated based on the voltage rate gain and the system voltage difference obtained from the system voltage and the input voltage; as well as A compensation generator having a rate offset input is operably coupled to the rate predictor device and configured to receive the rate offset voltage at the rate offset input to maintain the operation of the charger circuit in discontinuous conduction mode based on the rate offset voltage.

Images