Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate, the substrate including an adjacent first region and a second region; forming a floating gate layer on the substrate of the first region and on the substrate of the second region; forming a hard mask layer on the floating gate layer, the top of the hard mask layer in the first region being lower than the top of the hard mask layer in the second region; forming a first oxide layer on the hard mask layer in the first region and on the hard mask layer in the second region; etching the first oxide layer, the hard mask layer, the floating gate layer and the substrate to form a plurality of first grooves in the first region and a plurality of second grooves in the second region; forming a second oxide layer filling the first grooves and the second grooves; etching the second oxide layer and the first oxide layer until the top surface of the hard mask layer in the second region is exposed, and the remaining first oxide layer covering the top of the hard mask layer in the first region. The present invention helps to improve the consistency of the top surface height of the second oxide layer in each of the first grooves.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] At present, flash memory, also known as flash storage, has become the mainstream of non-volatile memory (NVM). According to different structures, flash memory can be divided into NOR flash and NAND flash. The main features of flash memory are that it can maintain the stored information for a long time without power supply, and has advantages such as high integration, fast storage speed, easy erasure and rewriting, etc. Therefore, it has been widely used in many fields such as microcomputers and automation control.

[0003] Due to the advantages of NAND flash memory devices such as high cell density, high storage density, fast write and erase speeds, etc., it has gradually become a relatively commonly used structure in flash memory, and is currently mainly used in flash memory cards for digital cameras and MP3 players.

[0004] However, the performance of current NAND flash memory devices still needs to be improved. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which helps to improve the consistency of the top surface height of the second oxide layer in each of the first grooves and increase the read / write times of the NAND flash memory device.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including an adjacent first region and second region; forming a floating gate layer on the substrate of the first region and the substrate of the second region; forming a hard mask layer on the floating gate layer, the top of the hard mask layer in the first region being lower than the top of the hard mask layer in the second region; forming a first oxide layer on the hard mask layer in the first region and the hard mask layer in the second region; etching the first oxide layer, the hard mask layer, the floating gate layer and the substrate to form a plurality of first grooves in the first region and a plurality of second grooves in the second region; forming a second oxide layer filling the first grooves and the second grooves; etching the second oxide layer and the first oxide layer until the top surface of the hard mask layer in the second region is exposed, and the remaining first oxide layer covering the top of the hard mask layer in the first region.

[0007] Optionally, the second oxide layer and the first oxide layer are made of the same material.

[0008] Optionally, a chemical mechanical polishing process is used to etch the second oxide layer and the first oxide layer.

[0009] Optionally, the difference between the top of the hard mask layer in the first region and the top of the hard mask layer in the second region is

[0010] Optionally, before forming the floating gate layer, it further includes: forming a gate oxide layer on the surfaces of the substrates in the first region and the second region.

[0011] Optionally, before forming the floating gate layer, the top of the gate oxide layer in the first region is flush with the top of the gate oxide layer in the second region.

[0012] Optionally, the process of forming the hard mask layer includes: forming an initial hard mask layer on the floating gate layer by chemical vapor deposition; forming a photoresist layer on the top of the initial hard mask layer in the second region; etching away a part of the thickness of the initial hard mask layer in the first region to form the hard mask layer; removing the photoresist layer.

[0013] Optionally, the second region includes an intermediate region and an edge region, and the intermediate region is located between the first region and the edge region; in the process of forming the gate oxide layer, the top of the gate oxide layer in the first region is flush with the top of the gate oxide layer in the intermediate region, and the top of the gate oxide layer in the intermediate region is lower than the top of the gate oxide layer in the edge region.

[0014] Optionally, the thickness of the gate oxide layer in the first region and the thickness of the gate oxide layer in the intermediate region are both a first thickness, and the thickness of the gate oxide layer in the edge region is a second thickness, and the first thickness is less than the second thickness.

[0015] Optionally, the gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The gate oxide layers in the first region and the intermediate region serve as the first sub-gate oxide layer, and the gate oxide layer in the edge region serves as the second sub-gate oxide layer; the process of forming the gate oxide layer includes: forming a first insulating layer on the top of the substrates in the first region and the intermediate region; etching a part of the thickness of the substrate in the edge region; performing a first oxidation treatment on the surface of the top of the substrate in the edge region to form the second sub-gate oxide layer; removing the first insulating layer; forming a second insulating layer on the top of the substrate in the edge region, and the second insulating layer exposes the top of the substrates in the first region and the intermediate region; performing a second oxidation treatment on the surface of the top of the substrate exposed by the second insulating layer to form the first sub-gate oxide layer.

[0016] Optionally, the difference between the top of the gate oxide layer in the first region and the top of the gate oxide layer in the edge region is

[0017] Optionally, the floating gate layer is formed by a furnace tube process.

[0018] Optionally, the hard mask layer is formed by a furnace tube process or a chemical vapor deposition process.

[0019] Correspondingly, the present invention further provides a semiconductor structure, including: a substrate, the substrate includes an adjacent first region and a second region; a floating gate layer, the floating gate layer is located on the substrate of the first region and the substrate of the second region; a hard mask layer, the hard mask layer is located on the floating gate layer, the top of the hard mask layer in the first region is lower than the top of the hard mask layer in the second region; a first oxide layer, the first oxide layer covers the top of the hard mask layer in the first region; a first groove, the first groove is located in the first region; a second groove, the second groove is located in the second region; a second oxide layer, the second oxide layer fills the first groove and the second groove.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] Since the top of the hard mask layer in the first region is lower than the top of the hard mask layer in the second region, in the process of etching the second oxide layer and the first oxide layer, the top surface of the hard mask layer in the second region can be used as an etching stop surface for the etching process, which helps to improve the consistency of the top surface height of the second oxide layer in each of the first grooves, and avoid the situation that the top surface height of the second oxide layer in each of the first grooves varies too much after the etching process ends. The good consistency of the top surface height of the second oxide layer in each of the first grooves helps to improve the uniformity of the turn-on voltage in each byte in the first region and increase the read / write times of the NAND flash memory device. Description of the Drawings

[0022] Figures 1 to 3 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0023] Figures 4 to 12 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention;

[0024] Figures 13 to 20 is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments

[0025] As can be seen from the background art, the performance of the existing semiconductor structure still needs to be improved.

[0026] Now, an analysis is carried out in combination with a method for forming a semiconductor structure. Figures 1 to 3 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure. The process steps for forming the semiconductor structure mainly include:

[0027] Refer to Figure 1, a base 10 is provided, and the base 10 includes an adjacent first region ⅰ and a second region ⅱ; a floating gate layer 30 is formed on the base 10 of the first region ⅰ and the base 10 of the second region ⅱ; a hard mask layer 50 is formed on the floating gate layer 30, and the top of the hard mask layer 50 in the first region ⅰ is flush with the top of the hard mask layer 50 in the second region ⅱ.

[0028] Among them, the first region ⅰ is a cell, and the second region ⅱ is a periphery.

[0029] Reference Figure 2 , etch the hard mask layer 50, the floating gate layer 30 and the base 10 to form a plurality of first grooves 71 in the first region ⅰ and a plurality of second grooves 72 in the second region ⅱ, and the width of the second grooves 72 is greater than the width of the first grooves 71; form an oxide layer 60 filling the first grooves 71 and the second grooves 72, and the oxide layer 60 covers the top of the hard mask layer 50.

[0030] Reference Figure 3 , use a chemical mechanical polishing process to remove the oxide layer 60 covering the top of the hard mask layer 50.

[0031] Since the materials of the hard mask layer 50 and the oxide layer 60 are different, during the chemical mechanical polishing process, the polishing rates of the hard mask layer 50 and the oxide layer 60 are different. The hard mask layer 50 and the oxide layer 60 with different polishing rates are polished simultaneously, resulting in a dish-shaped opening of the oxide layer 60 in the first grooves 71 and the second grooves 72 after the chemical mechanical polishing process, and the depths of the dish-shaped openings formed by the oxide layer 60 in different first grooves 71 are different, causing a large difference in the surface height of the top of the oxide layer 60 in each of the first grooves 71. The large difference in the surface height of the top of the oxide layer 60 in each of the first grooves 71 results in poor uniformity of the turn-on voltage (VT) in each byte (bit) in the first region i, affecting the read / write times of the NAND flash device.

[0032] The inventor studied the formation method of the above semiconductor structure. Through creative labor, the inventor noticed that during the formation of the hard mask layer, the top of the hard mask layer in the first region is lower than the top of the hard mask layer in the second region. During the chemical mechanical polishing process, by stopping the polishing at the top of the hard mask layer in the second region, it is possible to avoid polishing the hard mask layer in the first region, which helps to improve the consistency of the surface height of the top of the second oxide layer in each of the first grooves.

[0033] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following provides a detailed description of specific embodiments of the present invention with reference to the accompanying drawings.

[0034] Figures 4 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0035] Referring to Figure 4 , a substrate 100 is provided, and the substrate 100 includes an adjacent first region Ⅰ and a second region Ⅱ.

[0036] The material of the substrate 100 is silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; in this embodiment, the substrate 100 is a silicon substrate.

[0037] In this embodiment, the top of the substrate 100 in the first region Ⅰ is flush with the top of the substrate 100 in the second region Ⅱ.

[0038] In this embodiment, the first region Ⅰ is a cell, and the second region Ⅱ is a periphery.

[0039] Referring to Figure 5 , a floating gate layer 300 is formed on the substrate 100 in the first region Ⅰ and the substrate 100 in the second region Ⅱ.

[0040] In this embodiment, the top of the floating gate layer 300 in the first region Ⅰ is flush with the top of the floating gate layer 300 in the second region Ⅱ.

[0041] In this embodiment, before forming the floating gate layer 300, it further includes: forming a gate oxide layer 200 on the surfaces of the substrate 100 in the first region Ⅰ and the substrate 100 in the second region Ⅱ.

[0042] The material of the gate oxide layer 200 is silicon oxide or germanium oxide. In this embodiment, the material of the gate oxide layer 200 is silicon oxide.

[0043] In this embodiment, before forming the floating gate layer 300, the top of the gate oxide layer 200 in the first region Ⅰ is flush with the top of the gate oxide layer 200 in the second region Ⅱ.

[0044] In this embodiment, the material of the floating gate layer 300 is polysilicon.

[0045] Referring to Figures 6 to 8 , a hard mask layer 500 is formed on the floating gate layer 300, and the top of the hard mask layer 500 in the first region Ⅰ is lower than the top of the hard mask layer 500 in the second region Ⅱ.

[0046] The process of forming the hard mask layer 500 includes: asFigure 6 As shown, an initial hard mask layer 510 is formed on the floating gate layer 300 by a chemical vapor deposition process; a photoresist layer 520 is formed on the top of the initial hard mask layer 510 in the second region II; as Figure 7 shown, part of the thickness of the initial hard mask layer 510 in the first region I is etched away to form a hard mask layer 500; as Figure 8 shown, the photoresist layer 520 is removed.

[0047] In this embodiment, the material of the initial hard mask layer 510 is silicon nitride. In other embodiments, the material of the initial hard mask layer 510 is silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride or boron carbonitride.

[0048] In this embodiment, after the initial hard mask layer 510 is formed by a chemical vapor deposition process and before the photoresist layer 520 is formed, it further includes: planarizing the initial hard mask layer 510 so that the top of the initial hard mask layer 510 in the first region I is flush with the top of the initial hard mask layer 510 in the second region II.

[0049] Among them, the initial hard mask layer 510 is planarized by a chemical mechanical polishing process.

[0050] The photoresist layer 520 is used to protect the top surface of the initial hard mask layer 510 in the second region II, so that the etching process only etches away part of the thickness of the initial hard mask layer 510 in the first region I, so that the top of the initial hard mask layer 510 in the first region I is lower than the top of the initial hard mask layer 510 in the second region II, thereby forming the hard mask layer 500.

[0051] The top of the hard mask layer 500 in the first region I is lower than the top of the hard mask layer 500 in the second region II. Subsequently, the top surface of the hard mask layer 500 in the second region II can be used as an etch stop layer to prevent the etching process from etching to the top surface of the hard mask layer 500 in the first region I.

[0052] In this embodiment, a dry etching process is used to etch away part of the thickness of the initial hard mask layer 510 in the first region I. In other embodiments, a wet etching process is used to etch away part of the thickness of the initial hard mask layer 510 in the first region I.

[0053] In this embodiment, the difference between the top of the hard mask layer 500 in the first region I and the top of the hard mask layer 500 in the second region II is If the difference between the top of the hard mask layer 500 in the first region I and the top of the hard mask layer 500 in the second region II is too small, it will affect the protection effect of the difference on the surface of the top of the hard mask layer 500 in the first region I. If the difference between the top of the hard mask layer 500 in the first region I and the top of the hard mask layer 500 in the second region II is too large, it will cause the height of the hard mask layer 500 in the second region II to be too high, increasing the risk of the hard mask layer 500 in the second region II toppling over.

[0054] In this embodiment, before forming the hard mask layer 500, it further includes: forming an adhesion layer 400 on the surfaces of the floating gate layer 300 in the first region I and the floating gate layer 300 in the second region II.

[0055] The adhesion layer 400 is used to improve the bonding force between the hard mask layer 500 and the floating gate layer 300, and prevent voids from appearing between the surface of the hard mask layer 500 and the surface of the floating gate layer 300.

[0056] In this embodiment, the material of the adhesion layer 400 is silicon oxide.

[0057] In this embodiment, the top of the adhesion layer 400 in the first region I is flush with the top of the adhesion layer 400 in the second region II.

[0058] Reference Figure 9 , forming a first oxide layer 610 on the hard mask layer 500 in the first region I and the hard mask layer 500 in the second region II.

[0059] In this embodiment, the material of the first oxide layer 610 is silicon oxide. In other embodiments, the material of the first oxide layer 610 is germanium oxide.

[0060] In this embodiment, the formation process of the first oxide layer 610 includes: forming a first oxide film by chemical vapor deposition; performing planarization treatment on the first oxide film to form the first oxide layer 610, and the top of the first oxide layer 610 in the first region I is flush with the top of the first oxide layer 610 in the second region II.

[0061] Among them, chemical mechanical polishing process is used to perform planarization treatment on the first oxide film.

[0062] Reference Figure 10 , etching the first oxide layer 610, the hard mask layer 500, the floating gate layer 300 and the substrate 100 to form a plurality of first grooves 710 in the first region I and a plurality of second grooves 720 in the second region II.

[0063] The first groove 710 serves as the isolation trench in the first region I.

[0064] In this embodiment, the width L1 of the first groove 710 is less than the width L2 of the second groove 720. The spacing between adjacent first grooves 710 is less than the spacing between adjacent second grooves 720. The density of the first grooves 710 in the first region Ⅰ is greater than the density of the second grooves 720 in the second region Ⅱ.

[0065] In this embodiment, the first groove 710 and the second groove 720 are formed in the same process step.

[0066] In this embodiment, the first groove 710 and the second groove 720 are formed by a wet etching process. In other embodiments, the first groove 710 and the second groove 720 are formed by a dry etching process.

[0067] In this embodiment, the etching process for forming the first groove 710 and the second groove 720 consumes a part of the thickness of the first oxide layer 610, so that before and after the formation of the first groove 710 and the second groove 720 (refer to Figure 9 ), the thickness of the first oxide layer 610 decreases.

[0068] Refer to Figure 11 , and a second oxide layer 620 that fills the first groove 710 and the second groove 720 is formed.

[0069] In this embodiment, the material of the second oxide layer 620 is silicon oxide.

[0070] In this embodiment, the second oxide layer 620 covers the top of the first oxide layer 610 in the first region Ⅰ and the top of the first oxide layer 610 in the second region Ⅱ.

[0071] In this embodiment, the second oxide layer 620 is formed by a chemical vapor deposition process.

[0072] Refer to Figure 12 , etch the second oxide layer 620 and the first oxide layer 610 until the top surface of the hard mask layer 500 in the second region Ⅱ is exposed, and the remaining first oxide layer 610 covers the top of the hard mask layer 500 in the first region Ⅰ.

[0073] Since the top of the hard mask layer 500 in the first region Ⅰ is lower than the top of the hard mask layer 500 in the second region Ⅱ, in the process of etching the second oxide layer 620 and the first oxide layer 610, the top surface of the hard mask layer 500 in the second region Ⅱ can be used as an etching stop surface to avoid etching the top surface of the hard mask layer 500 in the first region Ⅰ.

[0074] Since the etching process stops immediately after the top surface of the hard mask layer 500 in the second region II is exposed, a certain thickness of the first oxide layer 610 still covers the top of the hard mask layer 500 in the first region I, while the first oxide layer 610 on the top surface of the hard mask layer 500 in the second region II is completely etched away. Since the first oxide layer 610 and the second oxide layer 620 are made of the same material, the etching rates of the first oxide layer 610 and the second oxide layer 620 are the same in the etching process. After the etching process is completed, the top surface of the first oxide layer 610 is substantially flush with the top surface of the second oxide layer 620 in the first groove 710, thereby improving the consistency of the top surface height of the second oxide layer 620 in each of the first grooves 710. The good consistency of the top surface height of the second oxide layer 620 in each of the first grooves 710 helps to improve the uniformity of the turn-on voltage in each byte in the first region and increase the read / write times of the NAND flash device.

[0075] In this embodiment, a chemical mechanical polishing process is used to etch the second oxide layer 620 and the first oxide layer 610.

[0076] Figures 13 to 20 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0077] Reference Figure 13 , a substrate 100 is provided, and the substrate 100 includes an adjacent first region I and a second region II.

[0078] In this embodiment, the first region I is a cell, and the second region II is a periphery.

[0079] In this embodiment, the second region II includes an intermediate region III and an edge region IV, and the intermediate region III is located between the first region I and the edge region IV.

[0080] Subsequently, a semiconductor structure is formed, a first voltage is applied to the first region I and the intermediate region III, a second voltage is applied to the edge region IV, and the first voltage is less than the second voltage.

[0081] The material of the substrate 100 is silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; in this embodiment, the substrate 100 is a silicon substrate.

[0082] Reference Figure 14, a gate oxide layer 200 is formed on the surfaces of the substrates 100 in the first region I, the intermediate region III, and the edge region IV. The top of the gate oxide layer 200 in the first region I is flush with the top of the gate oxide layer 200 in the intermediate region III, and the top of the gate oxide layer 200 in the intermediate region III is lower than the top of the gate oxide layer 200 in the edge region IV.

[0083] The material of the gate oxide layer 200 is silicon oxide or germanium oxide. In this embodiment, the material of the gate oxide layer 200 is silicon oxide.

[0084] In this embodiment, the thickness of the gate oxide layer 200 in the first region I is the first thickness d1. The thickness of the gate oxide layer 200 in the intermediate region III is also the first thickness d1. The thickness of the gate oxide layer 200 in the edge region IV is the second thickness d2, and the first thickness d1 is less than the second thickness d2.

[0085] In this embodiment, the difference between the second thickness d2 and the first thickness d1 is

[0086] In this embodiment, the gate oxide layer 200 includes a first sub-gate oxide layer 210 with the first thickness d1 and a second sub-gate oxide layer 220 with the second thickness d2.

[0087] In this embodiment, the gate oxide layer 200 in the first region I and the gate oxide layer 200 in the intermediate region III serve as the first sub-gate oxide layer 210, and the gate oxide layer 200 in the edge region IV serves as the second sub-gate oxide layer 220.

[0088] The formation process of the gate oxide layer 200 includes: forming a first insulating layer (not shown in the figure) on the top of the substrate 100 in the first region I and the intermediate region III; etching a part of the thickness of the substrate 100 in the edge region IV; performing a first oxidation treatment on the top surface of the substrate 100 in the edge region IV to form the second sub-gate oxide layer 220; removing the first insulating layer; performing a second oxidation treatment on the top surface of the substrate 100 exposed by the second insulating layer to form the first sub-gate oxide layer 210.

[0089] In this embodiment, the material of the first insulating layer is silicon nitride. In other embodiments, the material of the first insulating layer is silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0090] The material of the second insulating layer is silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride. In this embodiment, the material of the second insulating layer is silicon nitride.

[0091] In this embodiment, the first oxidation treatment and the second oxidation treatment are carried out step by step. By controlling the process time of the first oxidation treatment and the process time of the second oxidation treatment, the process time of the second oxidation treatment is made longer than that of the first oxidation treatment, so as to ensure that the thickness of the second sub-gate oxide layer 220 is greater than that of the first sub-gate oxide layer 210, and further make the top of the gate oxide layer 200 in the edge region IV higher than the top of the gate oxide layer 200 in the first region I and the middle region III.

[0092] Reference Figure 15 , a floating gate layer 300 is formed on the surfaces of the gate oxide layer 200 in the first region I, the gate oxide layer 200 in the middle region III, and the gate oxide layer 200 in the edge region IV.

[0093] In this embodiment, the top of the floating gate layer 300 in the edge region IV is higher than the top of the floating gate layer 300 in the first region I and the middle region III.

[0094] In this embodiment, the material of the floating gate layer 300 is polysilicon.

[0095] In this embodiment, the floating gate layer 300 is formed by using a furnace tube process.

[0096] Forming the floating gate layer 300 by using the furnace tube process helps to ensure that the thicknesses of the floating gate layers 300 in the first region I, the middle region III, and the edge region IV are consistent, so that the top of the floating gate layer 300 in the edge region IV is higher than the top of the floating gate layer 300 in the first region I and the middle region III.

[0097] Reference Figure 16 , a hard mask layer 500 is formed on the floating gate layer 300, and the top of the hard mask layer 500 in the edge region IV is higher than the top of the hard mask layer 500 in the first region I and the middle region III.

[0098] In this embodiment, the material of the hard mask layer 500 is silicon nitride. In other embodiments, the material of the hard mask layer 500 is silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, or carbon boron nitride.

[0099] In this embodiment, the hard mask layer 500 is formed by using a furnace tube process. In other embodiments, the hard mask layer 500 can also be formed by using a chemical vapor deposition process.

[0100] Forming the hard mask layer 500 by using the furnace tube process helps to ensure that the thickness of the hard mask layer 500 in the first region I, the intermediate region III, and the edge region IV is consistent, so that the top of the hard mask layer 500 in the edge region IV is higher than the top of the hard mask layer 500 in the first region I and the intermediate region III.

[0101] In this embodiment, before forming the hard mask layer 500, it further includes: forming an adhesion layer (not shown in the figure) on the surface of the floating gate layer 300 in the first region I and the floating gate layer 300 in the second region II, and the top of the adhesion layer 400 in the edge region IV is higher than the top of the adhesion layer in the first region I and the intermediate region III.

[0102] In this embodiment, the difference between the top of the hard mask layer 500 in the first region I and the top of the hard mask layer 500 in the second region II is

[0103] Subsequently, the top surface of the hard mask layer 500 in the second region II can be used as an etch stop layer to prevent the etch process from etching the top surface of the hard mask layer 500 in the first region I.

[0104] Reference Figure 17 , form a first oxide layer 610 on the hard mask layer 500 in the first region I and the hard mask layer 500 in the second region II.

[0105] In this embodiment, the material of the first oxide layer 610 is silicon oxide. In other embodiments, the material of the first oxide layer 610 is germanium oxide.

[0106] Reference Figure 18 , etch the first oxide layer 610, the hard mask layer 500, the floating gate layer 300, and the substrate 100 to form a plurality of first grooves 710 in the first region I and a plurality of second grooves 720 in the second region II.

[0107] In this embodiment, the first grooves 710 and the second grooves 720 are formed in the same process step.

[0108] In this embodiment, the width L1 of the first grooves 710 is smaller than the width L2 of the second grooves 720.

[0109] Reference Figure 19 , form a second oxide layer 620 that fills the first grooves 710 and the second grooves 720.

[0110] In this embodiment, the material of the second oxide layer 620 is silicon oxide.

[0111] Reference Figure 20, etch the second oxide layer 620 and the first oxide layer 610 until the top surface of the hard mask layer 500 in the second region II is exposed, and leave the first oxide layer 610 covering the top of the hard mask layer 500 in the first region I.

[0112] In this embodiment, a chemical mechanical polishing process is used to etch the second oxide layer 620 and the first oxide layer 610.

[0113] In the process of etching the second oxide layer 620 and the first oxide layer 610, the top surface of the hard mask layer 500 in the second region II can be used as an etch stop surface. After the etching process is completed, in the first region I, the top surface of the hard mask layer 500 is covered with a certain thickness of the first oxide layer 610, and the top surface of the first oxide layer 610 is flush with the top surface of the second oxide layer 620 in the first groove 710. The top surfaces of the second oxide layer 620 in each of the first grooves 710 are substantially flush, having good consistency.

[0114] Refer to Figure 12 , the present invention also provides a semiconductor structure obtained by using the above formation method. The semiconductor structure includes: a substrate 100, the substrate 100 includes an adjacent first region I and a second region II; a floating gate layer 300, the floating gate layer 300 is located on the substrate 100 in the first region I and on the substrate 100 in the second region II; a hard mask layer 500, the hard mask layer 500 is located on the floating gate layer 300, and the top of the hard mask layer 500 in the first region I is lower than the top of the hard mask layer 500 in the second region II; a first oxide layer 610, the first oxide layer 610 covers the top of the hard mask layer 500 in the first region I; a first groove 710, the first groove 710 is located in the first region I; a second groove 720, the second groove 720 is located in the second region II; a second oxide layer 620, the second oxide layer 620 fills the first groove 710 and the second groove 720.

[0115] In this embodiment, the top of the second oxide layer 620 in the first region I is flush with the top of the first oxide layer 610.

[0116] The semiconductor structure further includes: a gate oxide layer 200 located between the substrate 100 and the floating gate layer 300.

[0117] In this embodiment, the top of the gate oxide layer 200 in the first region I is flush with the top of the gate oxide layer 200 in the second region II.

[0118] In this embodiment, the top of the floating gate layer 300 in the first region I is flush with the top of the floating gate layer 300 in the second region II.

[0119] The semiconductor structure further includes: an adhesion layer 400 located between the floating gate layer 300 and the hard mask layer 500.

[0120] In this embodiment, the top of the adhesion layer 400 in the first region I is flush with the top of the adhesion layer 400 in the second region II.

[0121] Reference Figure 20 , in other embodiments, the second region II includes an intermediate region III and an edge region IV, and the intermediate region III is located between the first region I and the edge region IV.

[0122] In this embodiment, the top of the second oxide layer 620 in the first region I is flush with the top of the first oxide layer 610.

[0123] In this embodiment, the semiconductor structure further includes: a gate oxide layer 200 located between the substrate 100 and the floating gate layer 300. The top of the gate oxide layer 200 in the first region I is flush with the top of the gate oxide layer 200 in the intermediate region III, and the top of the gate oxide layer 200 in the intermediate region III is lower than the top of the gate oxide layer 200 in the edge region IV.

[0124] In this embodiment, the thickness of the gate oxide layer 200 in the first region I is a first thickness, and the thickness of the gate oxide layer 200 in the intermediate region III is also the first thickness. The thickness of the gate oxide layer 200 in the edge region IV is a second thickness, and the first thickness is less than the second thickness.

[0125] In this embodiment, the top of the floating gate layer 300 in the edge region IV is higher than the top of the floating gate layer 300 in the first region I and the intermediate region III. The thicknesses of the floating gate layers 300 in the first region I, the intermediate region III, and the edge region IV are equal.

[0126] In this embodiment, the top of the hard mask layer 500 in the edge region IV is higher than the top of the hard mask layer 500 in the first region I and the intermediate region III. The thicknesses of the hard mask layers 500 in the first region I, the intermediate region III, and the edge region IV are equal.

[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate, the substrate including an adjacent first region and a second region; forming a floating gate layer on the substrate of the first region and the substrate of the second region; forming a hard mask layer on the floating gate layer, the top of the hard mask layer in the first region being lower than the top of the hard mask layer in the second region; forming a first oxide layer on the hard mask layer in the first region and the hard mask layer in the second region; etching the first oxide layer, the hard mask layer, the floating gate layer and the substrate to form a plurality of first grooves in the first region and a plurality of second grooves in the second region; forming a second oxide layer filling the first grooves and the second grooves; etching the second oxide layer and the first oxide layer until the top surface of the hard mask layer in the second region is exposed, and the remaining first oxide layer covering the top of the hard mask layer in the first region; wherein, the first region is a cell and the second region is a peripheral region; in the etching process, the etching rates of the first oxide layer and the second oxide layer are the same.

2. The forming method according to claim 1, characterized in that, the second oxide layer and the first oxide layer are made of the same material.

3. The forming method according to claim 1, characterized in that, a chemical mechanical polishing process is used to etch the second oxide layer and the first oxide layer.

4. The forming method according to claim 1, characterized in that, the difference between the top of the hard mask layer in the first region and the top of the hard mask layer in the second region is 100 Å to 150 Å.

5. The forming method according to claim 1, characterized in that, before forming the floating gate layer, further comprising: forming a gate oxide layer on the surfaces of the substrate in the first region and the substrate in the second region.

6. The forming method according to claim 5, characterized in that, before forming the floating gate layer, the top of the gate oxide layer in the first region is flush with the top of the gate oxide layer in the second region.

7. The forming method according to claim 6, characterized in that, the process of forming the hard mask layer includes: forming an initial hard mask layer on the floating gate layer by chemical vapor deposition; forming a photoresist layer on the top of the initial hard mask layer in the second region; etching and removing a part of the thickness of the initial hard mask layer in the first region to form a hard mask layer; removing the photoresist layer.

8. The forming method according to claim 5, characterized in that, the second region includes an intermediate region and an edge region, and the intermediate region is located between the first region and the edge region; in the process of forming the gate oxide layer, the top of the gate oxide layer in the first region is flush with the top of the gate oxide layer in the intermediate region, and the top of the gate oxide layer in the intermediate region is lower than the top of the gate oxide layer in the edge region.

9. The forming method according to claim 8, characterized in that, the thicknesses of the gate oxide layers in the first region and the intermediate region are both a first thickness, and the thickness of the gate oxide layer in the edge region is a second thickness, and the first thickness is less than the second thickness.

10. The forming method according to claim 9, characterized in that, The gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The gate oxide layers in the first region and the intermediate region serve as the first sub-gate oxide layer, and the gate oxide layer in the edge region serves as the second sub-gate oxide layer. The formation process of the gate oxide layer includes: Form a first insulating layer on the top of the substrate in the first region and the intermediate region; Etch part of the thickness of the substrate in the edge region; Perform a first oxidation treatment on the top surface of the substrate in the edge region to form the second sub-gate oxide layer; Remove the first insulating layer; Form a second insulating layer on the top of the substrate in the edge region, and the second insulating layer exposes the top of the substrate in the first region and the intermediate region; Perform a second oxidation treatment on the top surface of the substrate exposed by the second insulating layer to form the first sub-gate oxide layer.

11. The forming method according to claim 8, wherein, The difference between the top of the gate oxide layer in the first region and the top of the gate oxide layer in the edge region is 100 Å to 150 Å.

12. The forming method according to claim 8, wherein, The floating gate layer is formed by a furnace tube process.

13. The forming method according to claim 8, wherein, The hard mask layer is formed by a furnace tube process or a chemical vapor deposition process.

14. A semiconductor structure formed by the forming method of the semiconductor structure according to any one of claims 1 to 13, wherein, including: A substrate, the substrate includes an adjacent first region and a second region; the first region is a cell, and the second region is a peripheral region; A floating gate layer, the floating gate layer is located on the substrate in the first region and the substrate in the second region; A hard mask layer, the hard mask layer is located on the floating gate layer, and the top of the hard mask layer in the first region is lower than the top of the hard mask layer in the second region; A first oxide layer, the first oxide layer covers the top of the hard mask layer in the first region; A first groove, the first groove is located in the first region; A second groove, the second groove is located in the second region; A second oxide layer, the second oxide layer fills the first groove and the second groove.

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