Semiconductor device

Abstract

A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and first and second regions formed in the substrate on opposite sides adjacent to the gate electrode, the first region including a first N-well region in the substrate and a second N-well region, a first impurity region, and a second impurity region in the first N-well region, the second region including a third impurity region in the substrate and a fourth impurity region in the third impurity region, the second N-well region having a higher doping concentration than the first N-well region, and the second impurity region having a higher doping concentration than the second N-well region.

Description

[0001] Cross-reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0051163, filed on April 28, 2020, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2019-0164000, filed on December 10, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to electrostatic discharge protection layers and semiconductor devices including thereto. Background Technology

[0004] Installing electrostatic discharge (ESD) protection devices reduces or prevents product damage or degradation caused by static electricity. When semiconductor integrated circuits come into contact with a human body or machine, static electricity generated from the human body or machine can be discharged into the semiconductor device through the input / output pads and external pins. Therefore, electrostatic current can flow into the internal circuitry of the semiconductor, potentially causing significant damage. Summary of the Invention

[0005] Example embodiments provide an electrostatic discharge (ESD) protection device and a semiconductor device including the ESD protection device, which can distribute the discharge current more uniformly to reduce the temperature of the junction portion and provide improved electrostatic characteristics even in a small area.

[0006] According to an example embodiment, a semiconductor memory device includes a substrate, an isolation region in the substrate, an electrostatic discharge protection element, an internal integrated circuit electrically connected to the electrostatic discharge protection element, and first and second pads electrically connected to the electrostatic discharge protection element and the internal integrated circuit. The electrostatic discharge protection element includes a P-well region in the substrate, a gate electrode having first and second side surfaces opposite to each other, the gate electrode being on the substrate, a gate dielectric layer between the gate electrode and the substrate, a first region in the substrate adjacent to the first side surface of the gate electrode, and a second region in the substrate adjacent to the second side surface of the gate electrode. The first and second regions have N-type conductivity. The first region includes a first N-well region in the substrate, a second N-well region in the first N-well region, a first impurity region overlapping the second N-well region in the first N-well region in a vertical direction, and a second impurity region in the first impurity region. The second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region. The vertical direction is perpendicular to an upper surface of the substrate. A distance between the upper surface of the substrate and a lower surface of the second N-well region is greater than a distance between the upper surface of the substrate and a lower surface of the isolation region.

[0007] According to an example embodiment, a semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and first and second regions formed in the substrate adjacent to opposite sides of the gate electrode. The first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, and a second impurity region in the first N-well region. The second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region. A doping concentration of the second N-well region is greater than a doping concentration of the first N-well region. A doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.

[0008] According to an example embodiment, a semiconductor device includes an electrostatic discharge (ESD) protection element and an internal integrated circuit electrically connected to the ESD protection element. The ESD protection element includes: a P-well region located in a substrate; a gate electrode located on the substrate; and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode. The first region includes a first N-well region located in the substrate, and a second N-well region, a first impurity region, and a second impurity region located within the first N-well region. The second region includes a third impurity region located in the substrate and a fourth impurity region located within the third impurity region. The ESD protection element includes a plurality of parasitic bipolar junction transistors (BJTs). In the plurality of parasitic BJTs, the P-well region serves as the base, and the second region serves as the emitter. The plurality of parasitic BJTs includes: at least one first parasitic BJT, which allows current to flow from the first N-well region to the second region by using the first N-well region as a collector; at least one second parasitic BJT, which allows current to flow from the first impurity region to the second region by using the first impurity region as a collector; and at least one third parasitic BJT, which allows current to flow from the second N-well region to the second region by using the second N-well region as a collector. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram of a semiconductor device including an electrostatic discharge protection element according to an example embodiment.

[0011] Figure 2A This is a top view of an electrostatic discharge protection element according to an example embodiment.

[0012] Figure 2B This is a cross-sectional view of an electrostatic discharge protection element according to an example embodiment.

[0013] Figure 3A This is a top view of an electrostatic discharge protection element according to an example embodiment.

[0014] Figure 3B This is a cross-sectional view of an electrostatic discharge protection element according to an example embodiment.

[0015] Figure 4 and Figure 5 A graph showing the measured voltage and current of an electrostatic discharge protection element according to an example embodiment is shown.

[0016] Figures 6A to 6G This is a block diagram of a semiconductor device that includes an electrostatic discharge protection element according to an example embodiment.

[0017] Figure 7A This is a top view of the transistors of the internal integrated circuit of a semiconductor device according to an example embodiment.

[0018] Figure 7B This is a cross-sectional view of a transistor in the internal integrated circuit of a semiconductor device according to an example embodiment. Detailed Implementation

[0019] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0020] Reference Figure 1 The semiconductor device 1000 may include a substrate 101, an electrostatic discharge protection element 100, an internal integrated circuit 200, a first pad 300, and / or a second pad 400. The first pad 300 may be a power supply voltage pad and / or an input / output pad. The second pad 400 may be a ground voltage pad.

[0021] When static electricity is introduced into the first pad 300, the electrostatic current induced by the static electricity can flow to the electrostatic discharge protection element 100. The electrostatic discharge protection element 100 can be selectively turned on by the static electricity introduced into the first pad 300. When the electrostatic discharge protection element 100 is turned on, the electrostatic current can flow to the electrostatic discharge protection element 100, and the electrostatic current flowing to the internal integrated circuit 200 can be potentially significantly reduced. Therefore, damage to the internal integrated circuit 200 by electrostatic current can be reduced or prevented. The electrostatic discharge protection element 100 can protect high-voltage components used in power clamp terminals from the effects of static electricity.

[0022] When static current flows into the drain region, the voltage in the drain region increases, and avalanche breakdown may occur due to the reverse bias between the drain and the body. Holes in the electron-hole pairs (EHP) generated by avalanche breakdown flow into the body, potentially causing a voltage drop due to parasitic resistance, thus increasing the voltage in the body. As the voltage rises until the PN junction between the body and the source is forward biased, the parasitic NPN bipolar junction transistor (BJT) turns on, allowing the static current to flow to the ground terminal for discharge. The ground terminal can be a single ground terminal, with the gate, source, and body connected to this single ground terminal.

[0023] The electrostatic discharge (ESD) protection element 100 can remain in the OFF state during normal operation when static electricity is not introduced into the circuit, etc., and can have no effect on the operation of the internal integrated circuit 200. When static electricity is introduced into the input / output pads and / or power supply voltage pads, the ESD protection element 100 can be turned on to provide an ESD discharge path. Current generated from static electricity can flow through the ESD discharge path. Therefore, the internal integrated circuit 200 can be protected from the effects of current generated from static electricity.

[0024] The electrostatic discharge protection element 100 may include a MOS transistor, a diode, or a silicon controlled rectifier (SCR).

[0025] exist Figure 1 In the example embodiment shown, the electrostatic discharge protection element 100 can be a gate-grounded NMOS (GGNMOS), i.e., a structure in which the gate electrode, source region, and body are connected to a ground voltage pad. However, according to the example embodiment, the electrostatic discharge protection element 100 can be implemented as a gate-coupled NMOS (GCNMOS), a soft-gate coupled NMOS (SGCNMOS), etc.

[0026] Semiconductor device 1000 can be a device performing various functions. For example, semiconductor device 1000 can be a memory device or a display driver IC. When semiconductor device 1000 is a memory device, internal integrated circuit 200 can be a memory controller that controls memory operations. Internal integrated circuit 200 can include peripheral circuitry for a memory cell array and can receive control signals to control the memory cells included in the memory cell array. For example, internal integrated circuit 200 can be a memory comprising cells, each cell storing data. Internal integrated circuit 200 can include multiple transistors having source / drain regions S and D. When semiconductor device 1000 is a display driver IC, electrostatic discharge protection element 100 can be connected to internal integrated circuit 200, including source drivers, gate drivers, etc., to protect the source drivers, gate drivers, etc., from electrostatic discharge.

[0027] Figure 2A This is a top view of an electrostatic discharge protection element according to an example embodiment.

[0028] Figure 2B This is a cross-sectional view of an electrostatic discharge protection element according to an example embodiment. Figure 2B It shows along Figure 2A The cross-section of the electrostatic discharge protection element is taken from line I-I' in the diagram.

[0029] Reference Figure 2A and Figure 2BThe electrostatic discharge protection element 100 may include a substrate 101 and a gate structure 150 located on the substrate 101. The substrate 101 may include a P-well region 110, a first region 120 and / or a second region 130 located in the P-well region 110 on opposite sides adjacent to the gate structure 150, and may include a P-type impurity region 140. The gate structure 150 may include a gate dielectric layer 152, a gate electrode 154 and / or a spacer 156.

[0030] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 101 may be provided as a bulk wafer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0031] The P-well region 110 can be formed by implanting a P-type impurity into a region of the substrate 101. The P-type impurity can be, for example, boron (B), aluminum (Al), etc. In the electrostatic discharge protection element 100, the P-well region 110 can be provided as the body of a MOS transistor.

[0032] The first region 120 may include a first N-well region 121, a second N-well region 122, a first impurity region 123, and / or a second impurity region 124. The first N-well region 121, the second N-well region 122, the first impurity region 123, and / or the second impurity region 124 may all have N-type conductivity. The first N-well region 121, the second N-well region 122, the first impurity region 123, and / or the second impurity region 124 may be regions formed by implanting N-type impurities into one region of the P-well region of the substrate 101. The N-type impurities may be, for example, phosphorus (P), arsenic (As), etc.

[0033] In some example embodiments, the first N-well region 121, the second N-well region 122, the first impurity region 123, and the second impurity region 124 may have different doping concentrations. For example, the doping concentration of the second impurity region 124 may be greater than the doping concentration of the first impurity region 123. The doping concentration of the second impurity region 124 may be greater than the doping concentration of the second N-well region 122. The doping concentration of the second impurity region 124 may be greater than the doping concentration of the first N-well region 121. For example, the doping concentration of the first impurity region 123 may be greater than the doping concentration of the second N-well region 122. The doping concentration of the first impurity region 123 may be greater than the doping concentration of the first N-well region 121. For example, the doping concentration of the second N-well region 122 may be greater than the doping concentration of the first N-well region 121.

[0034] In some example embodiments, the second impurity region 124 can be N+ Type I impurities are heavily doped to achieve a relatively high doping concentration, and the first impurity region 123 can be N-type impurity heavily doped. - Lightly doped with impurities to achieve a relatively low doping concentration.

[0035] In some example embodiments, the impurity concentrations of the first N-well region 121, the second N-well region 122, the first impurity region 123, and / or the second impurity region 124 may be increased in the direction toward the upper surface of the substrate 101.

[0036] In the example embodiment, both the first N-well region 121 and the second N-well region 122 may include multiple regions with different doping concentrations. Both the first N-well region 121 and the second N-well region 122 may have a concentration gradient in which the doping concentration decreases in the direction toward the P-well region 110.

[0037] In some example embodiments, a first impurity region 123 and a second impurity region 124 may be formed in a first N-well region 121. The first impurity region 123 and the second impurity region 124 may be disposed on a second N-well region 122. Figure 2B As shown, the first impurity region 123 and the second impurity region 124 can be formed in the second N-well region 122. The second N-well region 122 can be formed in the first N-well region 121. The second N-well region 122 can be formed in a region of the first N-well region 121 with a relatively low doping concentration.

[0038] In some example embodiments, the first impurity region 123 may overlap with the second N-well region 122 in the first N-well region 121 in the vertical direction. The second impurity region 124 may overlap with the second N-well region 122 in the first N-well region 121 in the vertical direction. The vertical direction may be perpendicular to the upper surface of the substrate 101.

[0039] In some example embodiments, the first N-well region 121 and the second N-well region 122 may provide deep junction regions. The deep junction regions may extend downwards at the lower portion of the gate structure 150 and the lower portion of the isolation region 160. Because the first N-well region 121 and the second N-well region 122 provide deep junction regions, the area of ​​the first region 120 can be increased.

[0040] In some example embodiments, the width of the second N-well region 122 may be smaller than the width of the first N-well region 121, and may also be smaller than the width of the first impurity region 123. The second N-well region 122 may or may not overlap with the gate electrode 154 in the vertical direction.

[0041] In some example embodiments, when viewed from above, the side surface of the second N-well region 122 adjacent to the gate electrode 154 may have a horizontal spacing distance D1 from the first side surface of the gate electrode 154 adjacent to the second N-well region 122. The horizontal direction may be parallel to the upper surface of the substrate 101. According to example embodiments, the first spacing distance D1 may be varied. Therefore, the characteristics of the electrostatic discharge protection element 100 may also be varied.

[0042] The second region 130 may include a third impurity region 131 and / or a fourth impurity region 132. Both the third impurity region 131 and the fourth impurity region 132 may have N-type conductivity. The third impurity region 131 and / or the fourth impurity region 132 may be formed by implanting N-type impurities into one region of the P-well region 110 of the substrate 101.

[0043] In some example embodiments, the third impurity region 131 and / or the fourth impurity region 132 may have different doping concentrations than each other. For example, the doping concentration of the third impurity region 131 may be lower than the doping concentration of the fourth impurity region 132. For example, the doping concentration of the fourth impurity region 132 may be greater than the doping concentration of the third impurity region 131. The doping concentration of the third impurity region 131 may be greater than the doping concentration of the first N-well region 121 and the second N-well region 122. The doping concentration of the fourth impurity region 132 is greater than the doping concentration of the first N-well region 121 and the second N-well region 122.

[0044] In some example embodiments, the fourth impurity region 132 can be N + Type I impurities are heavily doped to achieve a relatively high doping concentration, and the third impurity region 131 can be N-type impurity heavily doped. - Lightly doped with impurities to achieve a relatively low doping concentration.

[0045] In some example embodiments, the impurity concentrations of the third impurity region 131 and the fourth impurity region 132 may be increased in the direction toward the upper surface of the substrate 101.

[0046] In some example embodiments, the third impurity region 131 and / or the fourth impurity region 132 may each comprise a plurality of regions having different doping concentrations from each other. Both the third impurity region 131 and the fourth impurity region 132 may have a concentration gradient in which the doping concentration decreases in the direction toward the P-well region 110.

[0047] In some example embodiments, the third impurity region 131 and the fourth impurity region 132 may be formed in the P-well region 110.

[0048] In some example embodiments, a portion of the third impurity region 131 may overlap with the isolation region 160 in the vertical direction.

[0049] In some example embodiments, the fourth impurity region 132 may contact the side surface of the isolation region 160.

[0050] The depth of the first region 120 from the upper surface of the substrate 101 can be greater than the depth of the second region 130 from the upper surface of the substrate 101. The depth of the third impurity region 131 from the upper surface of the substrate 101 can be less than the depth of the second N-well region 122 from the upper surface of the substrate 101.

[0051] One side surface of the first impurity region 123 adjacent to the gate electrode 154 may be spaced apart from the second region 130 by a first interval, and one side surface of the second N-well region 122 adjacent to the gate electrode 154 may be spaced apart from the second region 130 by a second interval greater than the first interval.

[0052] A P-type impurity region 140 may be formed in the P-well region 110. The P-type impurity region 140 may be formed by implanting a P-type impurity into a region of the P-well region 110 of the substrate 101. The P-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0053] In some example embodiments, the P-well region 110 and / or the P-type impurity region 140 may have different doping concentrations than each other. For example, the doping concentration of the P-well region 110 may be lower than that of the P-type impurity region 140.

[0054] In some example embodiments, the impurity concentration of the P-well region and / or P-type impurity region 140 may be increased in the direction toward the upper surface of the substrate 101.

[0055] In some example embodiments, both the P-well region 110 and the P-type impurity region 140 may include multiple regions with different doping concentrations.

[0056] In some example embodiments, the P-type impurity region 140 may be disposed on at least one side of the first region 120 and at least one side of the second region 130. The P-type impurity region 140 may be isolated from the first region 120 and / or the second region 130 by an isolation region 160.

[0057] The gate structure 150 may include a gate dielectric layer 152, a gate electrode 154, and / or a spacer 156. The gate structure 150 may be configured to extend in one direction.

[0058] In some example embodiments, a gate dielectric layer 152 may be disposed between the substrate 101 and the gate electrode 154. The gate electrode 154 may be disposed on the gate dielectric layer 152. A spacer 156 may be disposed on the opposite side adjacent to the gate electrode 154 and may extend in a direction perpendicular to the upper surface of the substrate 101. The spacer 156 may insulate the first region 120 and the second region 130 from the gate electrode 154.

[0059] In some example embodiments, the gate dielectric layer 152 may include an oxide, a nitride, or a high-k material. A high-k material can refer to a dielectric material having a higher dielectric constant than silicon oxide (SiO2). High-k materials may include, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) and praseodymium oxide (Pr2O3).

[0060] In some example embodiments, the gate electrode 154 may have a first side surface and a second side surface opposite to each other on the substrate 101. The gate electrode 154 may include a conductive material. The gate electrode 154 may include metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polycrystalline silicon. The gate electrode 154 may have a multilayer structure comprising two or more layers.

[0061] In some example embodiments, the width of the gate electrode 154 may be greater than that of the transistor TR of the internal integrated circuit 200 (see...). Figure 7B The gate electrode 254 of the circuit is large. The width of the gate electrode 154 can be, for example, about 600 μm, but the width of the gate electrode 154 is not limited to this.

[0062] In some example embodiments, the spacer 156 may be formed of at least one of oxides, nitrides, and oxynitrides, specifically, it may be formed of a low-k material. According to example embodiments, the spacer 156 may be formed to have a multilayer structure.

[0063] The electrostatic discharge protection element 100 may also include an isolation region 160, an interlayer insulation layer 170, and / or contact plugs 120P, 130P, 140P, and 150P.

[0064] The isolation region 160 can isolate the first region 120 and the P-type impurity region 140 from each other. The isolation region 160 can also isolate the second region 130 and the P-type impurity region 140 from each other. The isolation region 160 can be formed of an insulating material. The isolation region 160 can include, for example, oxides, nitrides, or combinations thereof.

[0065] The isolation region 160 may overlap with a portion of the first N-well region 121 in the vertical direction. In some example embodiments, the isolation region 160 may overlap with a portion of the first impurity region 123 in the vertical direction. In example embodiments, the first impurity region 123 may contact the side surface of the isolation region 160.

[0066] The arrangement of the lower surface of the isolation region 160 is not limited to that shown in the figures and can be varied according to the exemplary embodiments. For example, the lower surface of the isolation region 160 may extend downwards on a portion of the lower surface of the first impurity region 123.

[0067] The distance between the upper surface of substrate 101 and the lower surface of the first N-well region 121 can be greater than the distance between the upper surface of substrate 101 and the lower surface of isolation region 160. The distance between the upper surface of substrate 101 and the lower surface of the second N-well region 122 can be greater than the distance between the upper surface of substrate 101 and the lower surface of isolation region 160. The distance between the upper surface of substrate 101 and the lower surface of the first impurity region 123 can be greater than the distance between the upper surface of substrate 101 and the lower surface of isolation region 160.

[0068] In some example embodiments, the isolation region 160 may be formed around an active region including a first region 120 and a second region 130. As an example, the isolation region 160 may have a rectangular shape surrounding at least one side of the first region 120 and at least one side of the second region 130. The isolation region 160 may be disposed in the substrate 101 to surround the edges of the first region 120 and the second region 130. In an example embodiment, a gate structure 150 may be disposed on a region within the isolation region 160.

[0069] In some example embodiments, the isolation region 160 may have a rectangular shape surrounding at least one side of the P-type impurity region 140. The isolation region 160 may be disposed in the substrate 101 to surround the edge of the P-type impurity region 140.

[0070] The interlayer insulating layer 170 may be configured to cover the upper surface of the first region 120, the second region 130, the isolation region 160, and / or the gate structure 150. The interlayer insulating layer 170 may include at least one of, for example, oxides, nitrides, and oxynitrides, and may include a low-k material.

[0071] Contact plugs 120P, 130P, 140P and / or 150P may penetrate the interlayer insulating layer 170. Contact plugs 120P, 130P, 140P and / or 150P include a first contact plug 120P electrically connected to a first region 120, a second contact plug 130P electrically connected to a second region 130, a third contact plug 140P electrically connected to a P-type impurity region 140, and a fourth contact plug 150P electrically connected to a gate electrode 154 of the gate structure 150.

[0072] Contact plugs 120P, 130P, 140P, and 150P may each include a metal-semiconductor compound layer, a conductive barrier layer, and a conductive layer surrounded by the conductive barrier layer. The metal-semiconductor compound layer may be formed of materials such as CoSi, NiSi, or TiSi. The conductive barrier layer may be formed of metal nitrides such as TiN, TaN, or WN. The conductive layer may be formed of tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof. A first region 120 may be electrically connected to input / output pads and / or power pads via the first contact plug 120P. Power supply voltage V DD It can be applied to the first region 120 through the first contact plug 120P.

[0073] The second to fourth contact plugs, 130P, 140P, and 150P, can be electrically connected to the ground power pad. Ground voltage V SS The second region 130, the P-well region 110, and the gate electrode 154 can be applied by the second to fourth contact plugs 130P, 140P, and 150P.

[0074] The electrostatic discharge protection element 100 may include: a first metal line M1a, electrically connected to a first region 120 via a first contact plug 120P on a substrate 101; and a second metal line M1b, commonly connected to second to fourth contact plugs 130P, 140P and 150P on a substrate 101 and electrically connected to a second region 130, a P-type impurity region 140 and / or a gate electrode 154.

[0075] The first metal wire M1a can be disposed on the first contact plug 120P and can extend in one direction. The first metal wire M1a can be electrically connected to the first pad 300 (see...). Figure 1The first pad 300 can be an input / output pad and / or a power pad. In this case, when static electricity is generated in the first pad 300, the first metal line M1a can allow the current generated by the static electricity to flow from the first pad 300 to the first region 120, so that the electrostatic discharge protection element 100 can operate.

[0076] The second metal wire M1b can be disposed on the second to fourth contact plugs 130P, 140P, and 150P, and can extend in one direction. The second metal wire M1b can be electrically connected to the second pad 400 (see...). Figure 1 Grounding voltage V SS The second metal line M1b can be applied to the second region 130, the P-type impurity region 140, and the gate electrode 154.

[0077] In some example embodiments, the electrostatic discharge protection element 100 may further include an electrical connection to a third contact plug 140P to transmit the ground voltage V. CC A third metal line M1c is applied to the P-type impurity region 140. According to the example embodiment, more third contact plugs 140P and third metal lines M1c can be provided compared to those shown in the figures.

[0078] In the electrostatic discharge protection element 100, when a positive-level static electricity is generated in the first region 120, the first region 120 and the P-well region 110 are reverse-biased. When the voltage of the first region 120 reaches the avalanche breakdown voltage caused by static electricity, current can flow from the first region 120 to the P-well region 110 of the electrostatic discharge protection element 100. In an example embodiment, the voltage of the P-well region 110 may be increased due to the current introduced from the first region 120.

[0079] The P-well region 110, the first region 120, and the second region 130 of the electrostatic discharge protection element 100 can form an NPN junction. When the voltage of the first region 120 increases due to static electricity and the voltage of the P-well region 110 increases due to the current introduced from the first region 120, the bias conditions of the P-well region 110, the first region 120, and the second region 130 of the electrostatic discharge protection element 100 as an NPN BJT can be satisfied.

[0080] For example, the second region 130 of the electrostatic discharge protection element 100 can be used as the emitter of an NPN BJT, the P-well region 110 can be used as the base, and the first region 120 can be used as the collector. Based on the voltage difference between the P-well region 110 and the second region 130 of the electrostatic discharge protection element 100, current can flow from the first region 120 to the second region 130 of the electrostatic discharge protection element 100.

[0081] When current flows from the first region 120 to the second region 130 of the electrostatic discharge protection element 100, the current density distribution may be affected by the impurity concentration on the side surface of the first region 120 adjacent to the P-well region 110. For example, when the side surface of the first region 120 adjacent to the P-well region 110 has a more uniform impurity concentration distribution according to depth, the current introduced from the first region 120 due to electrostatic discharge can be distributed vertically and more uniformly, and can flow to the second region 130. For example, since the current can flow while being distributed, the heating caused by current concentration (Joule heating) can be reduced or prevented, thereby lowering the temperature in the junction region of the first region 120. Therefore, the electrostatic discharge protection element 100 does not deteriorate. Thus, an electrostatic discharge protection element with improved electrostatic discharge robustness characteristics can be provided.

[0082] According to the present invention, the electrostatic discharge protection element 100 may further include a second N-well region 122 (i.e., a deep junction region) located within the first N-well region 121, such that the side surface of the first region 120 has a more uniform impurity concentration distribution according to depth. Therefore, localized concentration of current density on the side surface of the first region 120 can be reduced or prevented, and the temperature in the junction region can be reduced by allowing current to flow simultaneously with distribution. Thus, the electrostatic discharge protection element 100 can be used as an electrostatic discharge protection element without damage even when a large current of static electricity is introduced into the first region 120. For example, an electrostatic discharge protection element with high electrostatic discharge robustness can be provided. Because a new current path for distributing static current can be formed without increasing the size of the electrostatic discharge protection element 100, an electrostatic discharge protection element with improved electrostatic discharge robustness relative to width can be provided. Referring later... Figure 4 and Figure 5 This will be described in more detail.

[0083] It will be understood that various current paths can be formed between the first region 120, the P-well region 110, and the second region 130 to reduce or prevent local current concentration, thus the electrostatic discharge protection element 100 can have improved electrostatic discharge robustness.

[0084] Reference Figure 2B Multiple parasitic BJTs may exist in the electrostatic discharge protection element 100. These multiple parasitic BJTs may include a first parasitic BJT 10, a second parasitic BJT 20, and a third parasitic BJT 30, and can be represented as an equivalent circuit, such as... Figure 2BAs shown. As an example, each parasitic BJT may have a collector provided by the drain of the electrostatic discharge protection element 100, an emitter provided by the source of the electrostatic discharge protection element 100, and a base provided by the P-well region of the electrostatic discharge protection element 100. Therefore, the first parasitic BJT 10, the second parasitic BJT 20, and the third parasitic BJT 30 can be used as NPN BJTs.

[0085] The first parasitic BJT 10 can form a current path between the first N-well region 121, the P-well region 110, and the second region 130. The second parasitic BJT 20 can form a current path between the first impurity region 123, the P-well region 110, and the second region 130. The third parasitic BJT 30 can form a current path between the second N-well region 122, the P-well region 110, and the second region 130.

[0086] In the first parasitic BJT 10, the first N-well region 121 can be used as the collector, the P-well region 110 can be used as the base, and the second region 130 can be used as the emitter. In the second parasitic BJT 20, the first impurity region 123 can act as the collector, the P-well region 110 can be used as the base, and the second region 130 can be used as the emitter. In the third parasitic BJT 30, the second N-well region 122 can be used as the collector, the P-well region 110 can be used as the base, and the second region 130 can be used as the emitter.

[0087] The first parasitic BJT 10 allows current to flow from the first N-well region 121 to the second region 130. The second parasitic BJT 20 allows current to flow from the first impurity region 123 to the second region 130. The third parasitic BJT 30 allows current to flow from the second N-well region 122 to the second region 130.

[0088] When the electrostatic discharge protection element 100 does not include the second N-well region 122, a current path can be formed through the first parasitic BJT 10 and the second parasitic BJT 20 to reduce or prevent static electricity. When the electrostatic discharge protection element 100 includes the second N-well region 122, the third parasitic BJT 30 can form a new current path to reduce or prevent current concentration in the first region 120.

[0089] The electrostatic discharge protection element 100 may include a plurality of parasitic BJTs connected in parallel to provide a path for electrostatic current. Therefore, when the electrostatic discharge protection element 100 does not include the second N-well region 122, the third parasitic BJT 30 may not be formed, and thus, electrostatic current may flow simultaneously in the first parasitic BJT 10 and the second parasitic BJT 20, with localized concentration. According to the present invention, since the second N-well region 122 is formed in the first region 120 of the electrostatic discharge protection element 100, the three parasitic BJTs can be connected in parallel to distribute the stress caused by the electrostatic current.

[0090] The regions where the first parasitic BJT 10, the second parasitic BJT 20, and the third parasitic BJT 30 are formed are not limited to... Figure 2B The area shown, and its position may vary depending on the example embodiment.

[0091] The electrostatic discharge protection element 100 is shown as a planar MOSFET, but is not limited thereto.

[0092] In some example embodiments, in the case where the transistor of the internal integrated circuit 200 has a three-dimensional FinFET structure, the electrostatic discharge protection element 100 can be formed to have a FinFET structure.

[0093] In some example embodiments, the transistors in the internal integrated circuit 200 have a three-dimensional structure, such as FinFETs or multi-bridge channel FETs (MBCFETs). TM In the case of electrostatic discharge protection element 100, it may have a planar MOSFET structure.

[0094] In some example embodiments, the transistors in the internal integrated circuit 200 can be formed as MBCFETs. TM During the process, an electrostatic discharge protection element 100 is formed together. For example, the transistor of the internal integrated circuit 200 is formed as an MBCFET. TM Furthermore, the electrostatic discharge protection element 100 may include semiconductor layers in which silicon and silicon-germanium layers are stacked alternately and repeatedly. For example, in the electrostatic discharge protection element 100, the portion of the substrate 101 disposed below the first region 120, the second region 130, and / or the gate electrode 154 may include semiconductor layers in which silicon and silicon-germanium layers are stacked alternately and repeatedly.

[0095] Figure 3A This is a top view of an electrostatic discharge protection element according to an example embodiment.

[0096] Figure 3B This is a cross-sectional view of an electrostatic discharge protection element according to an example embodiment. Figure 3B It shows along Figure 3AThe cross-section of the electrostatic discharge protection element is taken from line I-I' in the diagram.

[0097] Reference Figure 3A and Figure 3B The electrostatic discharge protection element 100a may include second metal lines M1b_1 and M1b_2 spaced apart from each other. The second metal lines M1b_1 and M1b_2 may include a second ground metal line M1b_1 and a second gate metal line M1b_2.

[0098] The second ground metal line M1b_1 can be commonly connected to the second contact plug 130P and the third contact plug 140P on the substrate 101. The second ground metal line M1b_1 can be electrically connected to the second region 130 and the P-type impurity region 140. The second ground metal line M1b_1 can be electrically connected to the second pad 400 (see...). Figure 1 ), to ground voltage V SS It is applied to the second region 130 and the P-type impurity region 140.

[0099] The second gate metal line M1b_2 can be electrically connected to the fourth contact plug 150P on the substrate 101. The second gate metal line M1b_2 can also be electrically connected to the gate electrode 154 via the fourth contact plug 150P. The second gate metal line M1b_2 can be electrically connected to a resistor R, a capacitor C, the source / drain region of other transistors, or an inverter (see [link to relevant documentation]). Figures 6A to 6C and Figures 6E to 6G ).

[0100] Figure 4 A graph showing the measured voltage and current of an electrostatic discharge protection element according to an example embodiment is shown.

[0101] Reference Figure 2A and Figure 4 When the first distance D1 of the electrostatic discharge protection element 100 changes, the electrostatic discharge robustness characteristics of the electrostatic discharge protection element 100 can be analyzed.

[0102] Experimental examples show cases where the first distance D1 is approximately 0.2 μm, approximately 0.4 μm, approximately 0.6 μm, approximately 0.8 μm, approximately 1.0 μm, approximately 1.2 μm, and approximately 1.4 μm. As a comparative example, the voltage and current of the drain region excluding the electrostatic discharge protection element of the second N-well region 122 were measured.

[0103] Compared to the comparative example, in all experimental examples, there were periods of increased current relative to a specific voltage. It can be seen that by forming a second N-well region 122 in the first N-well region 121, an electrostatic current path is formed through the parasitic BJT, thereby improving the electrostatic discharge robustness of the electrostatic discharge protection element 100.

[0104] In some example embodiments, the first distance D1 may be less than approximately 1.5 μm. The first distance D1 may be in the range of approximately 0.1 μm to approximately 1.4 μm. The first distance D1 may be in the range of approximately 0.1 μm to approximately 0.3 μm. The first distance D1 may be in the range of approximately 0.15 μm to approximately 0.25 μm.

[0105] When the first distance D1 is within the aforementioned range, the electrostatic discharge robustness of the electrostatic discharge protection element 100 can be improved. When the first distance D1 is greater than approximately 1.5 μm, the third parasitic BJT 30 may not operate due to the increased resistance. When the first distance D1 is less than approximately 0.1 μm, the breakdown voltage BV of the gate dielectric layer 152 decreases, resulting in an increase in leakage current.

[0106] Figure 5 This is a graph showing a comparison between the electrostatic discharge robustness characteristics of a comparative example of an electrostatic discharge protection element excluding the second N-well region and the electrostatic discharge robustness characteristics of an inventive example including the second N-well region.

[0107] Reference Figure 5 Compared to the comparative example, when the electrostatic discharge protection element 100 includes a second N-well region 122, the electrostatic characteristics relative to the width can be improved.

[0108] Curve C1 represents the experimental results excluding the second N-well region of the electrostatic discharge (ESD) protection element. It can be seen that a strong snapback is induced at an ESD current of approximately 1.1 A when static electricity is generated. In the example embodiment according to the comparative example, based on the total width of the ESD protection element, the ESD protection element can have an ESD robustness of approximately 1.8 mA / μm.

[0109] The second curve C2 represents the experimental results of the electrostatic discharge protection element 100, including the second N-well region 122. The first distance D1 of the second N-well region 122 can be approximately 0.2 μm. It can be seen that when static electricity is generated, a strong foldback can be caused by an electrostatic current of approximately 2.1 A. Based on the total width of the electrostatic discharge protection element 100, the electrostatic discharge protection element 100 can have an electrostatic discharge robustness of approximately 3.5 mA / μm.

[0110] Because a second N-well region 122 is additionally formed, the parasitic BJT allows electrostatic current to flow simultaneously with the distribution, and can reduce or prevent heat generation caused by current concentration, thereby lowering the temperature in the junction region. Therefore, an electrostatic discharge protection element 100 with improved electrostatic discharge robustness characteristics can be provided. Compared to the comparative example, the effect of the third parasitic BJT 30 in the second N-well region 122 on improving electrostatic current robustness characteristics can be understood by increasing the current relative to the same voltage value.

[0111] Figures 6A to 6G This is a block diagram of a semiconductor device that includes an electrostatic discharge protection element according to an example embodiment.

[0112] Reference Figure 6A The semiconductor device 1000a may include an electrostatic discharge protection element 100a, an internal integrated circuit 200, a first pad 300, a second pad 400, a resistor R, and / or a capacitor C.

[0113] An RC circuit can be configured by connecting a capacitor C between the gate electrode 154 of the electrostatic discharge protection element 100a and the first pad 300, and connecting a resistor R between the gate electrode 154 of the electrostatic discharge protection element 100a and the second pad 400. The electrostatic discharge protection element 100a may have a gate-coupled NMOS (GCNMOS) structure.

[0114] When static electricity is generated, the electrostatic discharge protection element 100a can be biased by an RC circuit. After avalanche breakdown occurs at a lower voltage between the drain region and the body due to the voltage applied to the drain region, the electrostatic discharge protection element can be turned on to release the static electricity.

[0115] Reference Figure 6B The semiconductor device 1000b may include an electrostatic discharge (ESD) protection element 100a, an internal integrated circuit 200, a first pad 300, a second pad 400, and / or a resistor R. The resistor R may be connected between the gate electrode 154 of the ESD protection element 100a and the second pad 400. The ESD protection element 100a may have a soft-gate coupled NMOS (SGCNMOS) structure.

[0116] Reference Figure 6C The semiconductor device 1000c may include an electrostatic discharge protection element 100a, an internal integrated circuit 200, a first pad 300, a second pad 400, an NMOS transistor, a resistor R, and / or a capacitor C.

[0117] The gate electrode of the NMOS transistor can be electrically connected to a resistor R and a capacitor C. The gate electrode 154 of the electrostatic discharge protection element 100a can be electrically connected to the source and / or drain regions of the NMOS transistor.

[0118] Reference Figure 6D The semiconductor device 1000d may include an electrostatic discharge protection element 100, an internal integrated circuit 200, a first pad 300, a second pad 400, and / or an NMOS transistor.

[0119] Reference Figure 6E The semiconductor device 1000e may include an NMOS transistor, a PMOS transistor, an internal integrated circuit 200, a first pad 300, a second pad 400, and / or a third pad 500. The NMOS transistor may be an electrostatic discharge (ESD) protection element 100a. The ESD protection element 100a may have a floating gate electrode 154. The first pad 300 may be a power supply voltage pad. The second pad 400 may be a ground voltage pad. The third pad 500 may be an input / output pad.

[0120] When static electricity is generated in the first pad 300 or the third pad 500, the NMOS transistor can be used as an electrostatic discharge protection element to introduce the current generated by the static electricity into the NMOS transistor for discharge through the second pad 400.

[0121] Reference Figure 6F The semiconductor device 1000f may include an electrostatic discharge protection element 100, an internal integrated circuit 200, an NMOS transistor, a PMOS transistor, a first pad 300, a second pad 400, and / or a third pad 500.

[0122] The NMOS transistor can be used as an electrostatic discharge protection element 100a, which introduces the current generated by static electricity in the third pad 500 (i.e., the input / output pad) to the ground terminal to protect the internal integrated circuit 200.

[0123] In addition, the electrostatic discharge protection element 100 can also be connected between the first pad 300 and the second pad 400 to introduce the current generated by static electricity in the first pad 300 to the ground terminal to protect the internal integrated circuit 200.

[0124] Reference Figure 6G The semiconductor device 1000g may include an electrostatic discharge protection element 100a, an internal integrated circuit 200, an inverter, a resistor R, a capacitor C, a first pad 300 and / or a second pad 400.

[0125] The gate electrode 154 of the electrostatic discharge protection element 100a can be connected to an inverter.

[0126] Figure 7A This is a top view of the transistors of the internal integrated circuit of a semiconductor device according to an example embodiment.

[0127] Figure 7B This is a cross-sectional view of a transistor in the internal integrated circuit of a semiconductor device according to an example embodiment. Figure 7B It shows along Figure 7A The cross-section of the transistor is taken from line II-II' in the diagram. Figure 7A and Figure 7B The diagram shows an NMOS transistor among transistors.

[0128] Reference Figure 7A and Figure 7B The internal integrated circuit 200 may include a plurality of transistors TR. The plurality of transistors TR may include a circuit active region 205, a circuit gate structure 250 located on the circuit active region 205, and / or a circuit source / drain region formed on the opposite side adjacent to the circuit gate electrode 254. The circuit source / drain region 230 may be formed in the circuit N-well region 222.

[0129] The transistor TR can include NMOS and / or PMOS. The transistor TR can be a planar MOSFET. Each transistor TR can be a FinFET with an active fin structure in which the active region protrudes, and can be a multi-bridge channel FET (MBCFET) comprising multiple channel layers vertically spaced apart from each other on the active region. TM ).

[0130] The active region 205 of the circuit can be disposed on the substrate 101. The substrate 101 can be the same as the reference. Figure 2B The substrate 101 in the described electrostatic discharge protection element 100 is the same substrate. Substrate 101 may include a P-well region 110. Circuit active region 205 may be defined by device isolation region 210. Circuit active region 205 may be disposed above substrate 101 and below circuit gate structure 250. According to an example embodiment, circuit active region 205 may include impurities, and at least a portion of circuit active region 205 may include impurities of different conductivity types from each other, but this disclosure is not limited thereto.

[0131] In some example embodiments, the active circuit region 205 may have a structure protruding from the substrate 101. The upper end of the active circuit region 205 may be configured to protrude from the upper surface of the device isolation region 210 at a predetermined or optionally desired height. In example embodiments, the transistor TR of the internal integrated circuit 200 may have a fin structure in the active circuit region 205, and the active circuit region 205 may be a FinFET, i.e., a transistor whose channel region is formed in the active circuit region 205 intersecting with the circuit gate structure 250.

[0132] The circuit source / drain region 230 may be configured to be adjacent to the circuit active region 205 on the opposite side to the circuit gate structure 250. The circuit source / drain region 230 may be the source or drain region of a transistor. The circuit source / drain region 230 may be a semiconductor layer comprising silicon (Si). The circuit source / drain region 230 may include impurities of different types and / or different concentrations. For example, the circuit source / drain region 230 may include N-type doped silicon (Si) and / or P-type doped silicon germanium (SiGe). In an example embodiment, the circuit source / drain region 230 may include multiple regions comprising elements with different concentrations and / or doping elements.

[0133] In some example embodiments, the width of the circuit source / drain region 230 may be smaller than that of the electrostatic discharge protection element 100 (see...). Figure 2B The width of the second impurity region 124 and the width of the fourth impurity region 132.

[0134] In some example embodiments, the circuit source / drain region 230 may be disposed on the opposite side of the circuit active region 205 adjacent to the circuit gate structure 250. The circuit source / drain region 230 may be configured to cover the upper surface of the circuit active region 205 located below the opposite side of the circuit gate structure 250. The circuit source / drain region 230 may be disposed by recessing a portion of the upper part of the circuit active region 205, but according to example embodiments, various variations may be made regarding whether the upper part is recessed and the depth of the recess.

[0135] The circuit gate structure 250 may intersect the circuit active region 205 above the circuit active region 205 to extend in one direction. The circuit gate structure 250 may include a circuit gate electrode 254, a circuit gate dielectric layer 252 located between the circuit gate electrode 254 and the circuit active region 205, and / or a circuit gate spacer 256 located on the side surface of the circuit gate electrode 254.

[0136] The circuit gate dielectric layer 252 may be configured to cover at least a portion of the surface of the circuit gate electrode 254. For example, the circuit gate dielectric layer 252 may be configured to surround all surfaces except the uppermost surface of the circuit gate electrode 254. The circuit gate dielectric layer 252 may include oxides, nitrides, or high-k materials.

[0137] In some example embodiments, the thickness of the circuit gate dielectric layer 252 may differ from that of the electrostatic discharge protection element 100 (see...). Figure 2B The thickness of the gate dielectric layer 152. For example, the circuit gate dielectric layer 252 may have a smaller thickness than the gate dielectric layer 152. The circuit gate dielectric layer 252 covering the active region 205 may have a smaller width than the gate dielectric layer 152 covering the substrate 101.

[0138] A circuit gate electrode 254 may be disposed on the active region 205. The circuit gate electrode 254 may be spaced apart from the active region 205 by a circuit gate dielectric layer 252. The circuit gate electrode 254 may include a conductive material, such as a metal nitride like titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metallic material like aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material like doped polycrystalline silicon. The circuit gate electrode 254 may have a multilayer structure comprising two or more layers.

[0139] A gate spacer 256 may be disposed on the opposite side surface of the gate electrode 254. The gate spacer 256 may insulate the source / drain region 230 from the gate electrode 254. The gate spacer 256 may have a multilayer structure. The gate spacer 256 may be formed of oxides, nitrides, and oxide oxynitrides, and specifically, may be formed of a low-k material.

[0140] The circuit N-well region 222 can have N-type conductivity. The circuit N-well region 222 can be formed by implanting an N-type impurity into a region of the P-well region 110 of the substrate 101.

[0141] In some example embodiments, the circuit N-well region 222 may be a well region formed corresponding to the first N-well region 121 and / or the second N-well region 122 of the electrostatic discharge protection element 100. The maximum depth of the circuit N-well region 222 may be substantially the same as the maximum depth of the second N-well region 122, but this disclosure is not limited thereto.

[0142] In some example embodiments, the doping concentration of the circuit source / drain region 230 may be greater than the doping concentration of the circuit N-well region 222. The impurity concentration of the circuit N-well region 222 may increase in the direction toward the upper surface of the substrate 101. The circuit N-well region 222 may include multiple regions with different doping concentrations than each other.

[0143] The source / drain region 230 of the circuit can be formed in the N-well region 222 of the circuit. The N-well region 222 of the circuit can overlap with the source / drain region 230 of the circuit in the vertical direction.

[0144] In some example embodiments, the circuit N-well region 222 may provide a deep junction region. The deep junction region may extend downwards from the lower portion of the circuit gate structure 250 and the lower portion of the device isolation region 210.

[0145] The transistor TR of the internal integrated circuit 200 may also include an interlayer insulating layer 270, a circuit contact plug 230P electrically connected to the source / drain region 230 of the circuit through the interlayer insulating layer 270, and a circuit metal line M1d electrically connected to the circuit contact plug 230P.

[0146] The interlayer insulating layer 270 may be configured to cover the upper surface of the circuit source / drain region 230, the device isolation region 210, and the circuit gate structure 250. The interlayer insulating layer 270 may include at least one of, for example, oxides, nitrides, and oxynitrides, and may include a low-k material.

[0147] The circuit contact plug 230P can be electrically connected to the circuit source / drain region 230 respectively. At least a portion of the circuit contact plug 230P can be connected to the circuit source region in the circuit source / drain region 230, and the circuit metal line M1d electrically connected thereto can be electrically connected to the second metal line M1b of the electrostatic discharge protection element 100, thereby electrically connecting to the second region 130.

[0148] In some example embodiments, when the transistor TR of the internal integrated circuit 200 is PMOS, the source region S of the circuit (see...) Figure 1 The circuit can be electrically connected to the first region 120 via the first metal wire M1a of the circuit contact plug 230P and the electrostatic discharge protection element 100.

[0149] The circuit metal wire M1d can be set on the circuit contact plug 230P and can extend in one direction.

[0150] As described above, electrostatic discharge (ESD) protection devices and semiconductor devices including such ESD protection devices can be provided, which can distribute discharge current more uniformly to reduce the temperature of the junction portion and achieve improved ESD robustness even in a small area.

[0151] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; An isolation region, wherein the isolation region is located in the substrate; Electrostatic discharge protection components; An internal integrated circuit, which is electrically connected to the electrostatic discharge protection element; as well as First pad and second pad, the first pad and the second pad being electrically connected to the electrostatic discharge protection element and the internal integrated circuit. The electrostatic discharge protection element includes: The P-well region is located in the substrate; A gate electrode having a first side surface and a second side surface opposite to each other, the gate electrode being located on the substrate; A gate dielectric layer is located between the gate electrode and the substrate; A first region, wherein the first region is adjacent to the first side surface of the gate electrode in the substrate; and A second region, the second region being adjacent to the second side surface of the gate electrode in the substrate, and The first region and the second region have N-type conductivity. The first region includes a first N-well region located in the substrate, a second N-well region located within the first N-well region, a first impurity region overlapping the second N-well region within the first N-well region in the vertical direction, and a second impurity region located within the first impurity region. The second region includes a third impurity region located in the substrate and a fourth impurity region located in the third impurity region. The vertical direction is perpendicular to the upper surface of the substrate, and The distance between the upper surface of the substrate and the lower surface of the second N-well region is greater than the distance between the upper surface of the substrate and the lower surface of the isolation region. The depth of the first region from the upper surface of the substrate is greater than the depth of the second region from the upper surface of the substrate. The depth of the third impurity region from the upper surface of the substrate is less than the depth of the second N-well region from the upper surface of the substrate.

2. The semiconductor device according to claim 1, wherein, The doping concentration of the second impurity region is greater than that of the first impurity region and the second N-well region.

3. The semiconductor device according to claim 1, wherein, The doping concentration of the second N-well region is greater than that of the first N-well region.

4. The semiconductor device according to claim 1, wherein, When viewed from above, one side surface of the second N-well region adjacent to the gate electrode is horizontally spaced from the first side surface of the gate electrode adjacent to the second N-well region by a first distance, and The horizontal direction is parallel to the upper surface of the substrate.

5. The semiconductor device according to claim 4, wherein, The first distance is less than 1.5 μm.

6. The semiconductor device according to claim 4, wherein, The first distance is in the range of 0.1 μm to 0.3 μm.

7. The semiconductor device according to claim 4, wherein, The width of the first N-well region is greater than the width of the second N-well region.

8. The semiconductor device according to claim 1, wherein, The distance between the upper surface of the substrate and the lower surface of the first N-well region is greater than the distance between the upper surface of the substrate and the lower surface of the isolation region. A portion of the first N-well region overlaps with the isolation region in the vertical direction.

9. The semiconductor device according to claim 1, wherein, The electrostatic discharge protection element further includes: In the first parasitic BJT, the first N-well region is used as the collector, the P-well region is used as the base, and the second region is used as the emitter. A second parasitic BJT, wherein the first impurity region serves as the collector, the P-well region serves as the base, and the second region serves as the emitter; and The third parasitic BJT, wherein the second N-well region serves as the collector, the P-well region serves as the base, and the second region serves as the emitter.

10. The semiconductor device according to claim 1, wherein, The electrostatic discharge protection element further includes: P-type impurity region, the P-type impurity region surrounding the first region and the second region; A first contact plug, the first contact plug being electrically connected to the first region; The second contact plug is electrically connected to the second region; A third contact plug, the third contact plug being electrically connected to the P-type impurity region; A fourth contact plug, which is electrically connected to the gate electrode; A first metal wire, the first metal wire being located on the first contact plug and electrically connected to the first region via the first contact plug; and A second metal wire, which is commonly connected to the second contact plug, the third contact plug, and the fourth contact plug, applies a ground voltage to the second region, the P-type impurity region, and the gate electrode through the second, third, and fourth contact plugs. The first metal wire is electrically connected to the first pad. The second metal wire is electrically connected to the second pad. The first contact plug contacts the second impurity region in the first region, and The second contact plug contacts the fourth impurity region in the second region.

11. The semiconductor device according to claim 10, wherein, The internal integrated circuit includes multiple transistors. Each of the plurality of transistors includes a circuit active region, a circuit gate electrode located on the circuit active region, a circuit gate dielectric layer located between the circuit gate electrode and the substrate, and a circuit source / drain region located on the circuit active region on the opposite side adjacent to the circuit gate electrode. The plurality of transistors includes a first transistor. The width of the gate electrode of the first transistor is smaller than the width of the gate electrode of the electrostatic discharge protection element, and The thickness of the gate dielectric layer of the first transistor is less than the thickness of the gate dielectric layer of the electrostatic discharge protection element.

12. The semiconductor device according to claim 11, wherein, The source region of the circuit source / drain region of the internal integrated circuit is electrically connected to the second region of the electrostatic discharge protection element via the second metal line.

13. The semiconductor device according to claim 11, wherein, The width of each source / drain region of the internal integrated circuit is smaller than the width of the second impurity region and the width of the fourth impurity region of the electrostatic discharge protection element.

14. The semiconductor device according to claim 11, wherein, The source / drain regions of the internal integrated circuit are located in the N-well region of the circuit, and The maximum depth of the N-well region of the circuit is the same as the maximum depth of the second N-well region.

15. A semiconductor device, the semiconductor device comprising: Substrate, the substrate including a P-well region; A gate electrode, wherein the gate electrode is located on the substrate; as well as A first region and a second region are formed in the substrate on opposite sides adjacent to the gate electrode. The first region includes a first N-well region located in the substrate, and a second N-well region, a first impurity region, and a second impurity region located within the first N-well region. The second region includes a third impurity region located in the substrate and a fourth impurity region located in the third impurity region. The doping concentration of the second N-well region is greater than that of the first N-well region, and The doping concentration of the second impurity region is greater than that of the second N-well region. The depth of the first region from the upper surface of the substrate is greater than the depth of the second region from the upper surface of the substrate. The depth of the third impurity region from the upper surface of the substrate is less than the depth of the second N-well region from the upper surface of the substrate.

16. The semiconductor device according to claim 15, wherein, The second N-well region does not overlap with the gate electrode in the vertical direction, and the vertical direction is perpendicular to the upper surface of the substrate.

17. The semiconductor device according to claim 15, wherein, When viewed from above, the side surface of the second N-well region adjacent to the gate electrode is horizontally spaced apart from the side surface of the gate electrode adjacent to the second N-well region by a first distance. The horizontal direction is parallel to the upper surface of the substrate, and The first distance is in the range of 0.1 μm to 1.4 μm.

18. The semiconductor device of claim 15, further comprising: A first contact plug, the first contact plug being electrically connected to the second impurity region; The second contact plug is electrically connected to the fourth impurity region; A third contact plug, which is electrically connected to the P-well region; A fourth contact plug, which is electrically connected to the gate electrode; A first metal line, which is electrically connected to the second impurity region via a first contact plug and extends in one direction on the substrate; as well as The second metal line is electrically connected to the fourth impurity region and the P-well region via the third and fourth contact plugs and extends on the substrate in one direction.

19. A semiconductor device, the semiconductor device comprising: Electrostatic discharge protection components; as well as An internal integrated circuit, which is electrically connected to the electrostatic discharge protection element, The electrostatic discharge protection element includes: The P-well region is located in the substrate; Gate electrode, the gate electrode being located on the substrate; and A first region and a second region are formed in the substrate on opposite sides adjacent to the gate electrode. The first region includes a first N-well region located in the substrate, and a second N-well region, a first impurity region, and a second impurity region located within the first N-well region. The second region includes a third impurity region located in the substrate and a fourth impurity region located in the third impurity region. The electrostatic discharge protection element includes multiple parasitic BJTs. In the plurality of parasitic BJTs, the P-well region serves as the base, and the second region serves as the emitter. The plurality of parasitic BJTs include: At least one first parasitic BJT, which allows current to flow from the first N-well region to the second region by using the first N-well region as a collector; At least one second parasitic BJT, wherein the at least one second parasitic BJT allows current to flow from the first impurity region to the second region by using the first impurity region as a collector; and At least one third parasitic BJT, which allows current to flow from the second N-well region to the second region by using the second N-well region as a collector. Wherein, the depth of the first region from the upper surface of the substrate is greater than the depth of the second region from the upper surface of the substrate. The depth of the third impurity region from the upper surface of the substrate is less than the depth of the second N-well region from the upper surface of the substrate.

20. The semiconductor device according to claim 19, wherein, The doping concentration of the first impurity region is greater than the doping concentration of the second N-well region. The doping concentration of the second N-well region is greater than that of the first N-well region. One side surface of the first impurity region adjacent to the gate electrode is spaced apart from the second region by a first distance, and One side surface of the second N-well region adjacent to the gate electrode is spaced apart from the second region by a second distance greater than the first distance.

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