Semiconductor device

Abstract

A semiconductor device is provided, the semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure intersecting the active region and extending in a second direction; a source / drain region located on at least one side of the gate structure over the active region; a contact plug located on the at least one side of the gate structure over the source / drain region; and a contact insulating layer located on a sidewall of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source / drain region.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0163652, filed on Dec. 10, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device. Background Art

[0003] As the demand for relatively high performance, relatively high speed, and / or multi-functionality of semiconductor devices increases, the demand for the integration degree of semiconductor devices also increases. To fabricate semiconductor devices having fine patterns corresponding to relatively high integration, equipment for fabricating patterns having fine widths or fine pitch distances is required. In addition, in order to overcome the limitations of operating characteristics caused by the reduction in the size of planar metal oxide semiconductor field effect transistors (MOSFETs), efforts have been made to develop semiconductor devices including FinFETs having three-dimensional channels. Summary of the Invention

[0004] Aspects of the inventive concept provide a semiconductor device having improved electrical characteristics.

[0005] According to some aspects of the inventive concept, a semiconductor device includes: a substrate including an active region extending in a first direction; a gate structure intersecting the active region and extending in a second direction; source / drain regions on the active region and on at least one side of the gate structure; contact plugs on the source / drain regions and on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plugs, wherein a lower end of the contact plug is positioned closer to the substrate than a lower end of the source / drain region.

[0006] According to some aspects of the inventive concept, a semiconductor device includes: a substrate having a first region and a second region and including an active region extending in a first direction; a gate structure respectively located on the first region and the second region, crossing the active region, and extending in a second direction; a source / drain region located on at least one side of the gate structure over the active region and including a metal-semiconductor layer in an upper end; a contact plug located on at least one side of the gate structure, having a portion of an outer surface contacting the source / drain region, and having a lower end positioned at a level lower than a lower end of the source / drain region; and a contact insulating layer located on sidewalls of the contact plug, wherein each gate structure includes a gate insulating layer and a gate electrode layer sequentially stacked on the substrate and a gate spacer layer on sidewalls of the gate electrode layer in the first direction, and wherein a first distance between the gate electrode layer in the first region and each contact plug adjacent to the gate electrode layer is shorter than a second distance between the gate electrode layer in the second region and each contact plug adjacent to the gate electrode layer.

[0007] According to some aspects of the inventive concept, a semiconductor device includes: a substrate including an active region extending in a first direction; a gate structure including a gate electrode layer crossing the active region and extending in a second direction; a source / drain region located on at least one side of the gate structure over the active region; a contact plug located on at least one side of the gate structure over the source / drain region; a contact insulating layer contacting the gate structure and surrounding sidewalls of the contact plug; and a sidewall insulating layer contacting a portion of an outer surface of the source / drain region and contacting the contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan view showing a semiconductor device according to some example embodiments.

[0010] Figures 2A to 2C is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0011] Figure 3 is a plan view showing a semiconductor device according to some example embodiments.

[0012] Figure 4A and Figure 4B is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0013] Figure 5 is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0014] Figure 6A and Figure 6B is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0015] Figure 7 is a plan view showing a semiconductor device according to some example embodiments.

[0016] Figure 8 is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0017] Figures 9A to 9C is a cross-sectional view of a semiconductor device according to some example embodiments.

[0018] Figures 10A to 10K is a view showing a method of manufacturing a semiconductor device according to some example embodiments. Detailed Description

[0019] Hereinafter, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0020] Figure 1 is a plan view showing a semiconductor device according to some example embodiments. Figures 2A to 2C is a cross-sectional view showing a semiconductor device according to some example embodiments. Figures 2A to 2C respectively show cross-sectional views taken along Figure 1 lines I-I', II-II', and III-III' of the semiconductor device. For ease of description, only the main components of the semiconductor device may be shown in Figures 1 to 2C the drawings.

[0021] Referring to Figures 1 to 2C , the semiconductor device 100 may include a substrate 101, an active region 105, a device isolation layer 110, source / drain regions 150, a gate structure 160, a contact insulating layer 170, contact plugs 180, and an interlayer insulating layer 190. The semiconductor device 100 may include FinFET devices, and the FinFET devices may be transistors in which the active region 105 has a fin structure. The FinFET devices may include transistors disposed around the active region 105 and the gate structure 160 that cross each other.

[0022] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material (such as a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI compound semiconductor). For example, the Group-IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0023] As shown inFigure 2B and Figure 2C As best seen in Figure 2C , the device isolation layer 110 may define an active region 105 in the substrate 101. The device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. In some example embodiments, the device isolation layer 110 may include a region that extends deeply into the lower part of the substrate 101. As the device isolation layer 110 gets closer to the active region 105, the device isolation layer 110 may have an upper surface with a curved shape and a relatively high level, but the shape of the upper surface of the device isolation layer 110 is not limited thereto. The device isolation layer 110 may be made of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0024] The active region 105 may be defined by the device isolation layer 110 in the substrate 101 and may extend in a first direction. The first direction may be, for example, the X direction. The active region 105 may have a structure that protrudes from the substrate 101. The upper end of the active region 105 may protrude from the upper surface of the device isolation layer 110 to a predetermined height. The active region 105 may be formed as a part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. For the purpose of this description, the substrate 101 may be considered to include the active region 105, or the active region 105 may be considered to be on the substrate 101. The active region 105 on the substrate 101 may be partially recessed on both sides of the gate structure 160, and the source / drain regions 150 may be located in the recesses of the active region 105. In some example embodiments, the active region 105 may have a doped region including impurities. For example, the active region 105 may include impurities diffused from the source / drain regions 150 in the regions contacting the source / drain regions 150. In some example embodiments, the active region 105 may include a first semiconductor layer and a second semiconductor layer alternately stacked in the upper region located beside the source / drain regions 150 along the X direction. In some example embodiments, the active region 105 may have a structure with a planar upper surface instead of a fin structure.

[0025] As discussed, the source / drain regions 150 may be located on both sides of the gate structure 160, and the source / drain regions 150 may be located in the recessed regions of the active region 105. The recessed regions of the active region 105 may extend between the gate structures 160 along the X direction. The source / drain regions 150 may be provided as the source or drain regions of a transistor. The source / drain regions 150 may include a metal-semiconductor layer 155 disposed on the upper ends of the source / drain regions 150.

[0026] As Figure 2AAs shown, when observed in a cross-sectional view along the X direction, the upper surface of the source / drain region 150 can be substantially planar, and the upper surface of the source / drain region 150 can be substantially coplanar with the upper surface of the substrate 101. When observed in a cross-sectional view along the X direction, the upper surface of the source / drain region 150 can be positioned at the same or a similar height level as the lower surface of the gate structure 160. Within different exemplary embodiments, the relative heights of the source / drain region 150 and the gate structure 160 can be different. For example, when the metal-semiconductor layer 155 of the source / drain region 150 is formed to protrude from the substrate 101, the source / drain region 150 can have a raised source / drain shape such that the upper surface of the source / drain region 150 is positioned higher than the lower surface of the gate structure 160. The source / drain region 150 can be located below the outer surface of the gate spacer layer 164, such that it does not overlap with the gate structure 160 between adjacent gate structures 160, but the present disclosure is not limited thereto. For example, the source / drain region 150 can have a shape that extends below the gate structure 160 in the X direction.

[0027] The source / drain region 150 can have a curved shape (such as a part of a circle, a part of an ellipse, or a similar shape) below the upper surface having a planar shape. In some exemplary embodiments, depending on the distance between adjacent gate structures 160, the height of the active region 105, etc., the shape below the upper surface can be different in various exemplary embodiments. The upper surface of the source / drain region 150 can be covered by the contact insulating layer 170 and the contact plug 180, and in some exemplary embodiments, the upper surface of the source / drain region 150 can be completely covered by the contact insulating layer 170 and the contact plug 180. Thus, on the upper surface of the source / drain region 150, the width of one of the source / drain regions 150 in the X direction can be substantially equal to the sum of the width of the contact plug 180 disposed thereon and the two widths of the contact insulating layers 170 disposed on both sides of the contact plug 180.

[0028] As Figure 2B shown, when observed in a cross-sectional view along the Y direction, the source / drain region 150 can have a pentagonal shape or a similar shape. In some exemplary embodiments, the source / drain region 150 can have any one of a variety of shapes. For example, the source / drain region 150 can have the shape of any polygon (such as a rectangle), a circle, or an ellipse. As Figure 2BAs shown, the outer surface of the source / drain region 150 may have an inclined shape. Specifically, the outer surface of the source / drain region 150 may have a first surface and a second surface. The first surface has a slope that increases the width in the Y direction and extends obliquely upward from the active region 105. The second surface has a slope that decreases the width in the Y direction and extends obliquely upward from the first surface. The second surface may be referred to as the upper surface. The outer first surface among the first surfaces may be in contact with the sidewall insulating layer 170R, and the second surface may be in contact with the contact plug 180. The sidewall insulating layer 170R may not be disposed on or in contact with the inner first surface among the first surfaces, where the inner first surface is located between the active regions 105.

[0029] As Figure 2B shown, the source / drain regions 150 may be connected to each other between the active regions 105 adjacent to each other in the Y direction, but the present disclosure is not limited thereto. According to some exemplary embodiments, the source / drain regions 150 may not be connected through the metal-semiconductor layer 155 between the active regions 105 adjacent to each other in the Y direction, but may have a form of connection through a region other than the metal-semiconductor layer 155. An air gap region AG between the source / drain region 150 and the device isolation layer 110 may exist below the region where the source / drain regions 150 are connected to each other between the adjacent active regions 105, but the present disclosure is not limited thereto. For example, the air gap region AG may also be provided below the outer first surface on which the sidewall insulating layer 170R is provided.

[0030] The metal-semiconductor layer 155 may be located on the source / drain region 150 to form the upper surface of the source / drain region 150. Accordingly, the metal-semiconductor layer 155 may be in direct contact with the contact plug 180 through the upper surface of the source / drain region 150. The metal-semiconductor layer 155 may reduce the contact resistance between the source / drain region 150 and the contact plug 180. In some exemplary embodiments, the upper surface of the metal-semiconductor layer 155 may have a shape that partially protrudes from the substrate 101. In some exemplary embodiments, the arrangement of the metal-semiconductor layer 155 in the source / drain region 150 may be variously changed. In some exemplary embodiments, as Figure 2B shown in the cross-sectional view of, the metal-semiconductor layer 155 may not be located in the lower portion of the source / drain region 150 including the first surface, but may be located only in the upper portion of the source / drain region 150.

[0031] The source / drain region 150 may be formed of an epitaxial layer and may include, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). The source / drain region 150 may also include impurities such as arsenic (As) and / or phosphorus (P). In some example embodiments, the source / drain region 150 may include a plurality of regions including different concentrations of elements and / or doped elements. The metal-semiconductor layer 155 may include a metal element and a semiconductor element included in a lower region of the source / drain region 150. The metal-semiconductor layer 155 may include, for example, titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), tungsten silicide (WSi), or other metal silicides, and may also include germanium (Ge) or silicon germanium (SiGe) without including silicon (Si).

[0032] The gate structure 160 may cross the active region 105 in an upper portion of the active region 105. The gate structure 160 may extend in one direction (e.g., the Y direction). The channel region of the transistor may be formed in the active region 105 that crosses the gate structure 160. The "channel region" may refer to a region including a depletion region of the transistor and may refer to a region of the active region 105 that crosses and is adjacent to the gate structure 160. The gate structure 160 may include a gate insulating layer 162, a gate electrode layer 165, a gate spacer layer 164, and a gate capping layer 166, respectively.

[0033] The gate insulating layer 162 may be located between the active region 105 and the gate electrode layer 165. In an example embodiment, the gate insulating layer 162 may be formed of a plurality of layers or may extend onto a side surface of the gate electrode layer 165. The gate insulating layer 162 may include an oxide, a nitride, or a high dielectric constant (high-k) material. The high dielectric constant material may refer to a dielectric material having a dielectric constant higher than that of silicon dioxide (SiO2). The high dielectric constant material may be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicate (ZrSi x O y )、hafnium oxide (HfO2), hafnium silicate (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminate (LaAl x O y ), lanthanum hafnium (LaHf x O y ), hafnium aluminate (HfAl x O y ), and praseodymium oxide (Pr2O3).

[0034] The gate electrode layer 165 may include a conductive material and may include, for example, metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc., metal materials such as aluminum (Al), tungsten (W), molybdenum (Mo), etc., and / or semiconductor materials such as doped polysilicon. The gate electrode layer 165 may include two or more layers. According to the structure of the semiconductor device 100, the gate electrode layer 165 may be separated and disposed between at least parts of adjacent transistors.

[0035] The gate spacer layer 164 may be located on two side surfaces of the gate electrode layer 165. The gate spacer layer 164 may insulate the source / drain regions 150 from the gate electrode layer 165. According to some example embodiments, the gate spacer layer 164 may be formed to have a multi-layer structure, and in various example embodiments, the slopes of the outer surfaces of the gate spacer layer 164 may also be different. The gate spacer layer 164 may be formed of an oxide, a nitride, and an oxynitride, and specifically, may be formed of a low dielectric constant film. The gate spacer layer 164 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0036] The gate capping layer 166 may be disposed on the gate electrode layer 165, and the lower surface and the side surfaces of the gate capping layer 166 may be surrounded by the gate electrode layer 165 and the gate spacer layer 164, respectively.

[0037] The contact plug 180 may extend from the upper part of the semiconductor device 100 toward the substrate 101 to connect to the source / drain regions 150, and may apply an electrical signal to the source / drain regions 150. As Figure 2A and Figure 2B shown, the contact plug 180 may be located on the source / drain regions 150 to contact the upper surface of the source / drain regions 150 without causing the source / drain regions 150 to be recessed. The lower surface of the contact plug 180 may be positioned at a height level substantially the same as the height level of the lower surface of the gate structure 160, or may be positioned at a level higher than the level of the lower surface of the gate structure 160. The contact plug 180 may be connected to a via or a wiring (not shown) in its upper part.

[0038] The contact plug 180 may have a width greater than 10 nm in the X direction, for example, a width in the range of about 10 nm to about 100 nm, respectively. When the width of each of the contact plugs 180 is smaller than the above-defined range, the contact resistance increases and the process difficulty increases. When the width of each of the contact plugs 180 is greater than the above-defined range, the size of the semiconductor device 100 increases.

[0039] The contact plug 180 may have a length greater than the length of the source / drain regions 150 in the Y direction. For example, asFigure 2B As shown, when observed in a cross-sectional view along the Y direction, the two ends of the contact plug 180 can be spaced apart from the two ends of the source / drain region 150 externally and can completely cover the source / drain region 150. Thus, the contact plug 180 can extend relatively deeper than the source / drain region 150. For example, the lower end 180LE or the lowermost surface of the contact plug 180 can be positioned at a level or height lower than the lower end 150LE or the lowermost surface of the source / drain region 150. For example, the lower end 180LE of the contact plug 180 can be positioned below the first surface of the source / drain region 150. The parasitic capacitance between the contact plug 180 and the gate electrode layer 165 can be considered to determine or select the length of the contact plug 180 in the Y direction. The contact plug 180 can have an inclined side surface in which, according to the aspect ratio, the length of the lower part of the contact plug 180 can be less than the length of the upper part of the contact plug 180, but the present disclosure is not limited thereto. The contact plug 180 can include a conductive material, for example, a metal material such as tungsten (W), aluminum (Al), copper (Cu), etc. or a semiconductor material such as doped polysilicon.

[0040] Since the contact plug 180 can substantially not cause the source / drain region 150 to be recessed, the profile of the source / drain region 150 is maintained as described above and as Figure 2B shown, the contact plug 180 can be arranged along the profile of the second surface of the source / drain region 150, so that the contact area can be maximized to reduce the contact resistance. Even when the source / drain region 150 is used to control the mobility of charges in the channel region of the transistor by applying stress, the source / drain region 150 can not be recessed, so that the stress can not be released.

[0041] The contact insulating layer 170 can be arranged on the two sidewalls of the contact plug 180 along the X direction. The contact insulating layer 170 can fill the area or region between the contact plug 180 and the gate structure 160 and between the contact plug 180 and the interlayer insulating layer 190. When observed in a plan view, as Figure 1 shown, the contact insulating layer 170 can have a hollow shape to completely surround the entire sidewall of each of the contact plugs 180. The contact insulating layer 170 can surround the contact plug 180 with a substantially uniform thickness. Specifically, the contact insulating layer 170 can fill the region between adjacent gate structures 160 together with the contact plug 180 and can contact the gate spacer layer 164 of each of the gate structures 160. The lower surface of the contact insulating layer 170 can contact the upper surface of the metal-semiconductor layer 155. The contact insulating layer 170 can be spaced apart from the end of the source / drain region 150 in the Y direction to the outside of the source / drain region 150.

[0042] The sidewall of the contact insulating layer 170 may have a slope or curvature along the shape of the gate spacer layer 164. In the drawings, the side surface of the contact insulating layer 170 that contacts the contact plug 180 is shown perpendicular to the upper surface of the substrate 101, but the present disclosure is not limited thereto. The contact insulating layer 170 may include an insulating material, for example, silicon oxide, silicon oxynitride, or silicon nitride. In an embodiment, the contact insulating layer 170 may be formed of an air gap.

[0043] As Figure 2B shown, the sidewall insulating layer 170R may be located on the outer first surface of the source / drain region 150 among the first surfaces of the source / drain region 150 that is positioned outside in the Y direction. The sidewall insulating layer 170R may bend from the outer first surface and extend onto the device isolation layer 110 adjacent to the source / drain region 150. The sidewall insulating layer 170R may be a layer formed on the outer surface of the source / drain region 150 together with the contact insulating layer 170, and may be retained without being removed. Therefore, the sidewall insulating layer 170R may be made of the same material as the material of the contact insulating layer 170, and may be positioned to overlap with the source / drain region 150 when observed in a plan view. The thickness, shape, and arrangement of the sidewall insulating layer 170R that contacts the source / drain region 150 and the device isolation layer 110 may vary according to different exemplary embodiments.

[0044] The interlayer insulating layer 190 may be located on the substrate 101 and the device isolation layer 110 outside the contact insulating layer 170, and may extend to the upper portions (not shown) of the gate structure 160 and the contact plug 180. The interlayer insulating layer 190 may include at least one of, for example, an oxide, a nitride, and a nitrogen oxide, and may include a low dielectric constant material. In some exemplary embodiments, the interlayer insulating layer 190 may be formed of multiple layers formed by different operations according to a manufacturing process.

[0045] Figure 3 is a plan view showing a semiconductor device according to some exemplary embodiments.

[0046] Figure 4A and Figure 4B is a cross-sectional view showing a semiconductor device according to some exemplary embodiments. Figure 4A shows Figure 3 a cross-sectional view of the semiconductor device taken along lines IV-IV' and V-V', Figure 4B shows Figure 3 a cross-sectional view of the semiconductor device taken along line VI-VI'. For ease of description, only the main components of the semiconductor device may be shown in Figures 3 to 4B the drawings.

[0047] Referring to Figures 3 to 4B, the semiconductor device 100a may include a substrate 101 having a first region R1 and a second region R2, an active region 105, a device isolation layer 110, a first source / drain region 150A, a second source / drain region 150B, a gate structure 160, a contact insulating layer 170, a contact plug 180, and an interlayer insulating layer 190. The semiconductor device 100a may include transistors disposed around the active region 105 and the gate structure 160 that cross each other. For example, PMOS transistors may be provided in the first region R1. NMOS transistors may be provided in the second region R2. Hereinafter, the Figures 3 to 4B description overlapping with the above reference to Figures 1 to 2C description may be omitted.

[0048] The substrate 101 and the active region 105 may include impurities of different conductive types in the first region R1 and the second region R2. The first source / drain region 150A and the second source / drain region 150B may include different materials. Specifically, the first metal-semiconductor layer 155A of the first source / drain region 150A and the second metal-semiconductor layer 155B of the second source / drain region 150B may be made of different materials in the first region R1 and the second region R2, respectively. For example, the first metal-semiconductor layer 155A in the first region R1 may include nickel silicide (NiSi), and the second metal-semiconductor layer 155B in the second region R2 may be titanium silicide (TiSi). In some exemplary embodiments, the gate electrode layer 165 may also include different metal materials in the first region R1 and the second region R2, respectively.

[0049] A first distance D1 in the X direction between the gate electrode layer 165 and the contact plug 180 in the first region R1 may be shorter than a second distance D2 in the X direction between the gate electrode layer 165 and the contact plug 180 in the second region R2. This may optimize the parasitic capacitance between the contact plug 180 and the gate electrode layer 165 in transistors of different conductive types.

[0050] Specifically, in this exemplary embodiment and other exemplary embodiments, the thickness of the contact insulating layer 170 in the X direction may be substantially constant in the first region R1 and the second region R2, and the thicknesses of the gate spacer layers 164 may be different from each other. For example, the gate spacer layer 164 may have a first thickness T1 in the first region R1, and may have a second thickness T2 that is thicker or larger than the first thickness T1 in the second region R2. Hereinafter, the distance, thickness, or width may refer to an average value or a value at the same height or level. In some exemplary embodiments, the gate spacer layer 164 in the first region R1 may include a first layer, and the gate spacer layer 164 in the second region R2 may include a first layer and a second layer formed on the first layer. The contact plug 180 may have a first width W1 in the X direction in the first region R1, and may have a second width W2 in the X direction in the second region R2 that is narrower than the first width W1, but the present disclosure is not limited thereto.

[0051] Figure 5 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments. Figure 5 shows the region corresponding to Figure 4A the region of.

[0052] Referring to Figure 5 in the semiconductor device 100b, the thickness of the gate spacer layer 164 in the X direction may be substantially constant in the first region R1 and the second region R2, and the contact insulating layer 170 may have different thicknesses. For example, the contact insulating layer 170 may have a third thickness T3 in the X direction in the first region R1, and may have a fourth thickness T4 in the X direction in the second region R2 that is thicker or larger than the third thickness T3. The contact plug 180 may have a first width W1 in the X direction in the first region R1, and may have a second width W2 in the X direction in the second region R2 that is narrower or smaller than the first width W1. However, the present disclosure is not limited thereto, and in some exemplary embodiments, the widths may be substantially the same.

[0053] In the semiconductor device 100b, the distance between the gate electrode layer 165 and the contact plug 180 in the X direction in the first region R1 may be shorter than the distance between the gate electrode layer 165 and the contact plug 180 in the X direction in the second region R2.

[0054] Figure 6A and Figure 6B is a cross-sectional view showing a semiconductor device according to some exemplary embodiments. Figure 6A and Figure 6B show a cross-sectional view along the Y direction at the boundary between the first region R1 and the second region R2.

[0055] Referring to Figure 6A, in the semiconductor device 100c, portions of the contact insulating layer 170 may contact each other at the boundary between the first region R1 and the second region R2. The contact insulating layer 170 at the end of the first region R1 and the contact insulating layer 170 at the end of the second region R2 may contact each other. In this case, the thickness of either the contact insulating layer 170 at the end of the first region R1 or the contact insulating layer 170 at the end of the second region R2 may be thinner or smaller than that of the other.

[0056] Referring to Figure 6B , in the semiconductor device 100d, the side surface of the contact plug 180 may have a certain slope to reduce the width of the contact plug 180 from the upper part of the contact plug 180 toward the substrate 101. At the boundary between the first region R1 and the second region R2, the contact insulating layer 170 at the end of the first region R1 may contact the contact insulating layer 170 at the end of the second region R2 and may be a partial structure 170P or a partially retained structure. Such a structure may be formed by partially removing the contact insulating layer 170 previously formed in the first region R1 when forming the contact insulating layer 170 in the second region R2. In different exemplary embodiments, the height and shape of the contact insulating layer 170 retained in the first region R1 may be different.

[0057] Figure 7 is a plan view showing a semiconductor device according to some exemplary embodiments.

[0058] Figure 8 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments. Figure 8 shows Figure 7 a cross-sectional view of the semiconductor device taken along lines VII-VII' and VIII-VIII'.

[0059] Referring to Figure 7 and Figure 8 , the semiconductor device 100e may include a substrate 101 having a third region R3 and a fourth region R4, an active region 105, a device isolation layer 110, source / drain regions 150, a first gate structure 160A, a second gate structure 160B, a contact insulating layer 170, a contact plug 180, and an interlayer insulating layer 190. The semiconductor device 100e may include transistors disposed around the active region 105 and the first gate structure 160A that cross each other and around the active region 105 and the second gate structure 160B that cross each other. For example, the transistors in the third region R3 and the fourth region R4 may have different spacings and thus may have channel regions of different lengths. In this case, the transistors in the third region R3 and the fourth region R4 may be transistors driven at different threshold voltages.

[0060] The gate electrode layer 165 may have a third width W3 in the third region R3 in the X direction and may have a fourth width W4 in the fourth region R4 in the X direction that is wider or larger than the third width W3. The thickness of the contact insulating layer 170 may be different in the third region R3 and the fourth region R4. For example, the contact insulating layer 170 may have a fifth thickness T5 in the third region R3 and may have a sixth thickness T6 in the fourth region R4 that is thicker or larger than the fifth thickness T5. The contact plug 180 may have a fifth width W5 in the third region R3 in the X direction and may have a sixth width W6 in the fourth region R4 in the X direction that is wider than the fifth width W5, but the present disclosure is not limited thereto. The thickness of the gate spacer layer 164 in the X direction may be substantially the same in the third region R3 and the fourth region R4, but the present disclosure is not limited thereto. Accordingly, in the semiconductor device 100e, a first distance D1 in the X direction between the gate electrode layer 165 and the contact plug 180 in the third region R3 may be shorter than a third distance D3 in the X direction between the gate electrode layer 165 and the contact plug 180 in the fourth region R4.

[0061] Figures 9A to 9C is a cross-sectional view of a semiconductor device according to some example embodiments. Figures 9A to 9C shows the region corresponding to Figures 2A to 2C .

[0062] Referring to Figures 9A to 9C , the semiconductor device 100f may include a substrate 101, an active region 105 on the substrate 101, a channel structure 140 including a plurality of channel layers 141, 142, and 143 disposed on the active region 105 to be spaced apart from each other and stacked on top of each other, a source region / drain region 150 contacting the plurality of channel layers 141, 142, and 143, a gate structure 160f intersecting and extending across the active region 105, a contact insulating layer 170, and a contact plug 180 connected to the source region / drain region 150. The semiconductor device 100f may include a transistor having a gate-all-around structure, wherein the gate structure 160f is located between the active region 105 and the channel structure 140 and between the plurality of nano-sheet channel layers 141, 142, and 143 of the channel structure 140, that is, the gate structure 160f surrounds the plurality of nano-sheet channel layers 141, 142, and 143 of the channel structure 140. The semiconductor device 100f may include a transistor having a multi-bridge-channel FET (MBCFET TM ) structure with the channel structure 140, the source region / drain region 150, and the gate structure 160f.

[0063] The channel structure 140 may include a first channel layer 141, a second channel layer 142, and a third channel layer 143. The first channel layer 141, the second channel layer 142, and the third channel layer 143 are at least two channel layers disposed on the active region 105 and spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 (e.g., along the Z direction). The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be connected to the source / drain region 150 and may be spaced apart from the upper surface of the active region 105. The first channel layer 141, the second channel layer 142, and the third channel layer 143 may have a width that is the same as or similar to the width of the active region 105 in the Y direction and may have a width that is the same as or similar to the width of the gate structure 160f in the X direction. According to some example embodiments, the first channel layer 141, the second channel layer 142, and the third channel layer 143 may have a reduced width such that the side surfaces of the first channel layer 141, the second channel layer 142, and the third channel layer 143 in the X direction are located below the gate structure 160f.

[0064] The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be formed of a semiconductor material and may include at least one of, for example, silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be made of, for example, the same material as the material of the substrate 101. In different example embodiments, the number and shape of the channel layers 141, 142, and 143 that make up one of the plurality of channel structures 140 may vary. For example, the channel layer may also be located in the upper portion of the active region 105 below the gate electrode layer 165.

[0065] The gate structure 160f may cross the active region 105 and the channel structure 140 over the active region 105 and the channel structure 140, and the gate structure 160f may extend in one direction (e.g., the Y direction). The channel region of the transistor may be formed in the active region 105 and the channel structure 140 that cross the gate structure 160f. Each gate structure 160f may include a gate electrode layer 165, a gate insulating layer 162 between the gate electrode layer 165 and the plurality of channel layers 141, 142, and 143, a gate spacer layer 164 on the gate electrode layer 165, and a gate capping layer 166 on the upper surface of the gate electrode layer 165.

[0066] The gate insulating layer 162 may be located between the active region 105 and the gate electrode layer 165, may be located between the channel structure 140 and the gate electrode layer 165, and may cover at least a portion of the surface of the gate electrode layer 165. For example, the gate insulating layer 162 may surround the surface of the gate electrode layer 165, and in some examples, may surround the entire surface of the gate electrode layer 165 except for the uppermost surface of the gate electrode layer 165.

[0067] The gate electrode layer 165 may fill the space or region between the channel layers 141, 142, and 143 over the active region 105 and may extend to the upper portion of the channel structure 140. The gate electrode layer 165 may be spaced apart from the plurality of channel layers 141, 142, and 143 by the gate insulating layer 162.

[0068] The inner spacer layer 130 may be parallel to the gate electrode layer 165 between the channel structures 140. The gate electrode layer 165 may be spaced apart from and electrically isolated from the source / drain region 150 by the inner spacer layer 130. The inner spacer layer 130 may have a shape in which a side surface facing the gate electrode layer 165 is convexly rounded in an intermediate direction toward the gate electrode layer 165, but the present disclosure is not limited thereto. The inner spacer layer 130 may be formed of an oxide, a nitride, and a nitrogen oxide, and specifically, may be formed of a low dielectric constant film.

[0069] In some example embodiments, the transistor having the MBCFET MT structure may be additionally provided in the region of the semiconductor device described above with reference to Figures 1 to 8 the description.

[0070] Figures 10A to 10K is a view showing a method of manufacturing a semiconductor device according to some example embodiments. Figures 10A to 10K shows an example embodiment of an operation of a method of manufacturing Figures 3 to 4B the semiconductor device. Figures 10A to 10E and Figures 10G to 10K shows a cross-sectional view corresponding to Figure 4A and Figure 10F shows a cross-sectional view corresponding to Figure 4B the description.

[0071] Referring to Figure 10A , the active region 105 may be formed by patterning the substrate 101 and forming the device isolation layer 110. Thereafter, the sacrificial gate structure SG and the gate spacer layer 164 may be formed.

[0072] First, the active region 105 may be formed by anisotropically etching the substrate 101 using a mask layer to form a trench region. The substrate 101 may include a first region R1 and a second region R2, and the active region 105 may include impurities of different conductivity types in the first region R1 and the second region R2. Since the trench region has a relatively high aspect ratio, the width of the trench region may be narrower in the downward direction or may be narrowed or reduced moving from the upper portion of the trench region toward the substrate 101, and the active region 105 may have a shape that is narrowed in the upward direction. The device isolation layer 110 may be formed by filling the trench region with an insulating material and then planarizing the filled trench region along the upper surface of the active region 105.

[0073] Next, a sacrificial gate structure SG having a linear shape extending in the Y direction to cross the active region 105 can be formed on the active region 105. The sacrificial gate structure SG can be formed in a region where the gate structure 160 is arranged as shown in the subsequent process. The sacrificial gate structure SG can include a first sacrificial gate layer SG1, a second sacrificial gate layer SG2, and a third sacrificial gate layer SG3. The first sacrificial gate layer SG1 and the second sacrificial gate layer SG2 can be an insulating layer and a conductive layer respectively, but the present disclosure is not limited thereto. The first sacrificial gate layer SG1 and the second sacrificial gate layer SG2 can be provided as a single layer. For example, the first sacrificial gate layer SG1 can include silicon oxide, and the second sacrificial gate layer SG2 can include polysilicon. The third sacrificial gate layer SG3 can be used to pattern the first sacrificial gate layer SG1 and the second sacrificial gate layer SG2, and can include silicon oxide and / or silicon nitride. The configuration of the sacrificial gate structure SG can be different in different exemplary embodiments. Figure 4A A gate spacer layer 164 can be formed on the sidewalls of the sacrificial gate structure SG, and a part of the gate spacer layer 164 can remain on the active region 105. An interlayer insulating layer 190 covering the sacrificial gate structure SG and the substrate 101 can be formed on the sacrificial gate structure SG. In different exemplary embodiments, the thickness of the interlayer insulating layer 190 can vary. For example, the upper surface of the interlayer insulating layer 190 can be at the same height or a similar height as the upper surface of the sacrificial gate structure SG.

[0074] Referring to

[0075] In the first region R1, the interlayer insulating layer 190 can be removed from both sides of the sacrificial gate structure SG to form a first opening OP1, and the active region 105 exposed between the sacrificial gate structures SG can be recessed to form a second opening OP2. Figure 10B First, a separate mask layer can be used to expose the region in the first region R1 where the first source / drain region 150A, the contact insulating layer 170, and the contact plug 180 shown in

[0076] are to be arranged. The exposed region can be a region having a rectangular shape, and the sacrificial gate structure SG is placed between the regions. Figure 4A The interlayer insulating layer 190 and the active region 105 can be sequentially removed between the sacrificial gate structures SG using different etchants. For example, in some exemplary embodiments, the region where the first source / drain region 150A is to be formed and the region where the contact plug 180 is to be formed can be etched and formed simultaneously or sequentially. The second opening OP2 can be formed between the gate spacer layers 164 to be as shown in

[0077] The second opening OP2 can be formed between the gate spacer layers 164 to be as shown in Figure 10Bextends from the outer surface of the gate spacer layer 164 as shown, or may be formed to extend to the lower portion of the gate spacer layer 164 or the lower portion of the sacrificial gate structure SG. Optionally, after forming the second opening OP2, a process of curing the surface of the recessed active region 105 may be performed by a separate process.

[0078] Referring to Figure 10C , a first source / drain region 150A may be formed in the second opening OP2.

[0079] The first source / drain region 150A may be, for example, an epitaxial layer formed by growing from the active region 105 using a selective epitaxial growth (SEG) process. In some example embodiments, the first source / drain region 150A may include impurities through an in-situ doping process.

[0080] Referring to Figure 10D , a portion of the first source / drain region 150A may be metallized to form a first metal-semiconductor layer 155A of the first source / drain region 150A.

[0081] For example, when the first source / drain region 150A includes silicon (Si), the first metal-semiconductor layer 155A may be formed as a metal silicide layer through a metallization process. For example, the first metal-semiconductor layer 155A may include nickel silicide (NiSi).

[0082] According to the thickness of the first metal-semiconductor layer 155A to be formed, the upper surface of the first metal-semiconductor layer 155A may be formed to be substantially coplanar with the upper surface of the active region 105, or may be formed to be higher than the upper surface of the active region 105. When the thickness of the first metal-semiconductor layer 155A is too thick, the parasitic capacitance will increase. When the first metal-semiconductor layer 155A is formed lower than the upper end of the second opening OP2, the stress in the first source / drain region 150A will be reduced.

[0083] According to some example embodiments, the first metal-semiconductor layer 155A may be formed after forming the contact insulating layer 170, which will be described below with reference to Figure 10E . In this case, since the sidewall insulating layer 170R is formed first (see Figure 10F ), the first metal-semiconductor layer 155A may not be formed at least on the outer first surface among the first surfaces of the first source / drain region 150A. When the first source / drain region 150A is formed to be connected on the adjacent active region 105, the first metal-semiconductor layer 155A may not be formed at least on the inner first surface among the first surfaces of the first source / drain region 150A.

[0084] Referring to Figure 10E and Figure 10F, a contact insulating layer 170 may be formed on the side surfaces of the interlayer insulating layer 190 and the side surfaces of the gate spacer layer 164 in the first opening OP1.

[0085] The contact insulating layer 170 may have a liner shape and / or may be conformal to the sidewalls of the side surfaces of the gate spacer layer 164 in the first opening OP1. The contact insulating layer 170 may be formed by forming an insulating material in the exposed area with a uniform thickness and partially removing the insulating material in the Z direction to expose the upper surface of the first source / drain region 150A. The contact insulating layer 170 may include silicon nitride or silicon oxide. When the contact insulating layer 170 is made of a material having a relatively low dielectric constant, this is advantageous in terms of parasitic capacitance. Although all side surfaces of the contact insulating layer 170 are shown as vertical for convenience, the contact insulating layer 170 may have a shape along the contour of the gate spacer layer 164.

[0086] As Figure 10F shown, in the region between the sacrificial gate structures SG, a first opening OP1 may be formed to expose the first source / drain region 150A and the device isolation layer 110, and the contact insulating layer 170 may be respectively formed on the side surfaces of the interlayer insulating layer 190 that are outwardly spaced apart from both ends of the first source / drain region 150A. Specifically, as shown by the dashed line, the contact insulating layer 170 may first be formed to surround all surfaces of the first source / drain region 150A, and then may be removed from the upward direction to a predetermined thickness such that at least a part of the contact insulating layer 170 remains on the outer first surface in the lower part of the first source / drain region 150A to form a sidewall insulating layer 170R. In addition, the contact insulating layer 170 may be formed on the upper surface of the device isolation layer 110 and then may be removed in a region that does not overlap with the first source / drain region 150A. For example, according to this operation, when observed in a plan view, the sidewall insulating layer 170R may be located below the first source / drain region 150A and on the upper surface of the device isolation layer 110 in the region overlapping with the first source / drain region 150A (for example, the sidewall insulating layer 170R may completely overlap with the first source / drain region 150A).

[0087] Referring to Figure 10G , a contact plug 180 may be formed between the contact insulating layers 170 and on the first source / drain region 150A, and then an upper interlayer insulating layer 195 may be formed thereon, and a first opening OP1' and a second opening OP2' may be formed in the second region R2.

[0088] First, the contact plug 180 can be formed by depositing a conductive material between the contact insulating layers 170 and performing a planarization operation. In the planarization operation, the third sacrificial gate layer SG3 can be used as a stop layer. Next, the upper interlayer insulating layer 195 can be formed on the contact plug 180.

[0089] Thus, the contact plug 180 can be formed not by etching the layer on the first source / drain region 150A, but by filling the opening region including the first opening OP1, so that it can be formed without causing the first source / drain region 150A to be recessed. Therefore, since the contact area with the first source / drain region 150A can be ensured and the width at the lower end of the contact plug 180 can be ensured, the release of stress or the increase in contact resistance of the first source / drain region 150A can be prevented. In addition, the size of the contact plug 180 can be controlled to prevent the occurrence of defects in contact with the subsequently formed gate structure 160.

[0090] The first opening OP1' and the second opening OP2' can be formed in the same manner as described above with reference to Figure 10B In the second region R2, the interlayer insulating layer 190 can be removed from both sides of the sacrificial gate structure SG to form the first opening OP1', and the active region 105 exposed between the sacrificial gate structures SG can be recessed to form the second opening OP2'.

[0091] Referring to Figure 10H , the second source / drain region 150B can be formed in the second opening OP2', and a part of the second source / drain region 150B can be metallized to form the second metal-semiconductor layer 155B of the second source / drain region 150B.

[0092] The second source / drain region 150B and the second metal-semiconductor layer 155B can be formed in the same manner as described above with reference to Figure 10C and Figure 10D . The second source / drain region 150B can include a material different from that of the first source / drain region 150A, and the second metal-semiconductor layer 155B can also include a material different from that of the first metal-semiconductor layer 155A. For example, the second metal-semiconductor layer 155B can be formed to include titanium silicide (TiSi).

[0093] Referring to Figure 10I , the contact insulating layer 170 can be formed on the side surfaces of the interlayer insulating layer 190 and the gate spacer layer 164 in the first opening OP1'.

[0094] The contact insulating layer 170 can be formed in the same manner as described above with reference to Figure 10E and Figure 10Fformed in the same manner as the described manner. As above, in a cross-sectional view along the Y direction, the sidewall insulating layer 170R can be formed on the outer surface of the lower portion of the second source / drain region 150B and on the device isolation layer 110.

[0095] Referring to Figure 10J , a contact plug 180 can be formed on the second source / drain region 150B between the contact insulating layers 170, and then a planarization operation can be performed.

[0096] The contact plug 180 can be formed in the same manner as the manner described above with reference to Figure 10G Next, a planarization operation can be performed on the first region R1 and the second region R2 to remove the upper interlayer insulating layer 195. In an embodiment, during the planarization operation, the sacrificial gate structure SG, the contact insulating layer 170, the contact plug 180, and the interlayer insulating layer 190 can be partially removed from the upper portion.

[0097] In some exemplary embodiments, when the contact insulating layer 170 is formed as an air gap, the material of the contact insulating layer 170 deposited in this operation can be selectively removed.

[0098] Referring to Figure 10K , in the first region R1 and the second region R2, the sacrificial gate structure SG can be removed to form a third opening OP3.

[0099] The sacrificial gate structure SG can be selectively removed with respect to the active region 105 and the device isolation layer 110 below the sacrificial gate structure SG. The removal operation of the sacrificial gate structure SG can use at least one of a dry etching process and a wet etching process.

[0100] Next, referring to Figure 4A and Figure 4B together, a gate insulating layer 162, a gate electrode layer 165, and a gate capping layer 166 can be formed in the third opening OP3 to finally form a gate structure 160.

[0101] The gate insulating layer 162 can be formed along the lower surface of the third opening OP3 and can be formed to extend along the side surface of the third opening OP3 in the upward direction. After forming the gate insulating layer 162, the gate electrode layer 165, and the gate capping layer 166, a planarization process such as a chemical mechanical polishing (CMP) process can be used to remove the material remaining on the interlayer insulating layer 190. In this operation, the gate capping layer 166 and the gate spacer layer 164 can also be partially removed from their upper portions to their lower heights. In some exemplary embodiments, the operation of forming the gate structure 160 can be performed before the steps of forming the first opening OP1 and the second opening OP2 described with reference to Figure 10B .

[0102] After forming source / drain regions, a contact insulating layer and a contact plug may be sequentially formed on the source / drain regions to provide a semiconductor device having improved electrical characteristics.

[0103] The various advantages and effects of the inventive concept are not limited to the above description, and the above description is provided to facilitate an easy understanding of the inventive concept in the process of describing specific exemplary embodiments of the inventive concept. Accordingly, while some examples of the embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate having a first region and a second region, and including an active region extending in a first direction; Gate structures respectively located on the first region and the second region, intersecting the active region, and extending in a second direction; Source / drain regions located on at least one side of the gate structures on the active region, and including a metal-semiconductor layer in an upper end; Contact plugs located on the at least one side of the gate structures, a part of an outer surface of the contact plugs being in contact with the source / drain regions, and a lower end of the contact plugs being positioned closer to the substrate than a lower end of the source / drain regions; And A contact insulating layer located on sidewalls of the contact plugs, Wherein each of the gate structures includes a gate insulating layer and a gate electrode layer sequentially stacked on the substrate, and a gate spacer layer located on sidewalls of the gate electrode layer in the first direction; Wherein a first distance between the gate electrode layer and each adjacent contact plug in the first region is shorter than a second distance between the gate electrode layer and each adjacent contact plug in the second region; In a plan view, the contact insulating layer completely surrounds sidewalls of each contact plug.

2. The semiconductor device according to claim 1, wherein, The contact insulating layer is in contact with the gate spacer layer in the first direction.

3. The semiconductor device according to claim 1, wherein, A lower surface of the contact insulating layer is in contact with the metal-semiconductor layer.

4. The semiconductor device according to claim 1, wherein The gate spacer layer has a first thickness in the first direction in the first region, and the gate spacer layer has a second thickness greater than the first thickness in the first direction in the second region.

5. The semiconductor device according to claim 1, wherein, The contact insulating layer has a third thickness in the first direction in the first region, and the contact insulating layer has a fourth thickness greater than the third thickness in the first direction in the second region.

6. The semiconductor device according to claim 1, wherein, The contact plug has a first width in the first direction in the first region, and the contact plug has a second width smaller than the first width in the first direction in the second region.

7. The semiconductor device according to claim 1, wherein, At a boundary between the first region and the second region, the contact insulating layer in the first region is in contact with the contact insulating layer in the second region.

8. The semiconductor device according to claim 1, wherein, The gate electrode layer has a third width in the first direction in the first region, and the gate electrode layer has a fourth width greater than the third width in the first direction in the second region.

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