Semiconductor device

Abstract

The semiconductor device includes: a buried region (20) of a second conductivity type, which is buried in a part of the upper surface of a semiconductor substrate (10) of a first conductivity type; a first semiconductor region (30) of the second conductivity type, which is disposed above the semiconductor substrate (10) so as to cover the buried region (20), and has an impurity concentration lower than that of the buried region (20); a connection region (40) of the first conductivity type, which is buried in a part of the upper surface of the semiconductor substrate (10) in a remaining region of the region where the first semiconductor region (30) is disposed, and has a side surface connected to an extension region (31) which is a part of the lower portion of the first semiconductor region (30); and a second semiconductor region (50) of the first conductivity type, which is disposed on the upper surface of the connection region (40), and has a side surface connected to the first semiconductor region (30). The extension region (31) of the first semiconductor region (30) extends below an end portion of the second semiconductor region (50) and abuts against the side surface of the connection region (40).

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which a current path of a main current is parallel to a main surface. Background Art

[0002] In order to improve the breakdown voltage of a semiconductor device, various countermeasures have been studied. For example, a structure in which a field plate is disposed between a gate and a drain region of a MOSFET (metal oxide semiconductor field effect transistor) is disclosed (see Patent Document 1). In the invention described in Patent Document 1, the breakdown voltage of the semiconductor device is improved by disposing a field plate on a thermal oxide film formed between the gate and the drain region.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2001-7327 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In recent years, the requirement for the breakdown voltage of semiconductor devices has increased. On the other hand, it is difficult to achieve sufficient breakdown voltage for a semiconductor device in which a main current flowing during a conduction operation is parallel to a main surface of a semiconductor substrate (hereinafter, referred to as a "lateral semiconductor device"). An object of the present invention is to provide a lateral semiconductor device capable of improving the breakdown voltage.

[0008] Means for Solving the Problems

[0009] According to one aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate of a first conductivity type; a buried region of a second conductivity type buried in a part of an upper surface of the semiconductor substrate; a first semiconductor region of a second conductivity type selectively disposed above the semiconductor substrate so as to cover the buried region and having an impurity concentration lower than that of the buried region; a connection region of a first conductivity type buried in a part of an upper surface of the semiconductor substrate in a remaining region of a region where the first semiconductor region is disposed and having a side surface connected to an extension region which is a part of a lower portion of the first semiconductor region; and a second semiconductor region of a first conductivity type disposed on an upper surface of the connection region and having a side surface connected to the first semiconductor region, wherein the extension region of the first semiconductor region extends below an end portion of the second semiconductor region and abuts on a side surface of the connection region.

[0010] Advantages of the Invention

[0011] According to the present invention, a lateral semiconductor device capable of improving the breakdown voltage can be provided. Brief Description of the Drawings

[0012] Figure 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 2 is a schematic cross-sectional view (part 1) for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0014] Figure 3 is a schematic cross-sectional view (part 2) for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] Figure 4 is a schematic cross-sectional view (part 3) for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] Figure 5 is a schematic cross-sectional view (part 4) for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] Figure 6 is a schematic cross-sectional view showing the structure of a semiconductor device according to another embodiment of the present invention. Detailed Embodiments

[0018] Next, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the ratios of the thicknesses of the respective layers are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, there are of course also parts where the dimensional relationships and ratios are different between the drawings.

[0019] In addition, the embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention, and the embodiments of the present invention do not specify the materials, shapes, structures, configurations, etc. of the constituent parts as described below. The embodiments of the present invention can be variously modified in the claims.

[0020] As Figure 1 shown, a semiconductor device according to an embodiment of the present invention includes: a buried region 20 of a second conductivity type, which is buried in a part of the upper surface of a semiconductor substrate 10 of a first conductivity type; and a first semiconductor region 30 of a second conductivity type, which covers the buried region 20 and is selectively disposed above the semiconductor substrate 10. The buried region 20 is in contact with the semiconductor substrate 10, and in a region where the buried region 20 is not disposed, the first semiconductor region 30 is in contact with the semiconductor substrate 10. The impurity concentration of the first semiconductor region 30 is set lower than the impurity concentration of the buried region 20.

[0021] Figure 1 The semiconductor device shown also includes: a connection region 40 of a first conductivity type, which is buried in a part of the upper surface of the semiconductor substrate 10 in the remaining region of the region where the first semiconductor region 30 is disposed; and a second semiconductor region 50 of the first conductivity type, which is disposed on the upper surface of the connection region 40. The side surface of the second semiconductor region 50 is connected to the first semiconductor region 30. As Figure 1 shown, an extension region 31, which is a part of the lower portion of the first semiconductor region 30, is connected to the side surface of the connection region 40. That is, the extension region 31 of the first semiconductor region 30 extends below the end portion of the second semiconductor region 50 and is connected to the side surface of the connection region 40.

[0022] In addition, a drain region 60 of a second conductivity type is disposed on a part of the upper surface of the first semiconductor region 30, and a source region 70 of the second conductivity type is disposed on a part of the upper surface of the second semiconductor region 50. And, between the drain region 60 and the source region 70, a gate 90 is disposed above the second semiconductor region 50 with a gate insulating film 80 therebetween.

[0023] In addition, Figure 1 in the semiconductor device shown, a back gate region 100 of the first conductivity type is disposed on a part of the upper surface of the second semiconductor region 50. The back gate region 100 is electrically connected to the semiconductor substrate 10 via the second semiconductor region 50 and the connection region 40.

[0024] In addition, the first conductivity type and the second conductivity type are opposite conductivity types to each other. That is, if the first conductivity type is p-type, the second conductivity type is n-type, and if the first conductivity type is n-type, the second conductivity type is p-type. Hereinafter, the case where the first conductivity type is p-type and the second conductivity type is n-type will be illustratively described.

[0025] Figure 1 The semiconductor device shown is a lateral transistor in which a main current flows parallel to the main surface of the semiconductor substrate 10 between the source region 70 and the drain region 60 during a conduction operation. Hereinafter, Figure 1 the basic operation of the semiconductor device shown will be described.

[0026] Taking the potential of the source region 70 as a reference, when a positive potential is applied to the drain region 60 and the potential of the gate 90 is controlled, the semiconductor device performs a conduction operation. That is, by making the voltage between the gate 90 and the source region 70 be equal to or higher than a specified threshold voltage, a channel is formed in the second semiconductor region 50 below the gate 90. Thereby, a main current flows between the source region 70 and the drain region 60. Hereinafter, the region where the channel is formed will be referred to as a "channel formation region". In addition, the end portion on the side of the second semiconductor region 50 of the buried region 20 is located between the channel formation region and the drain region 60.

[0027] On the other hand, in the turn-off operation, the voltage between the gate 90 and the source region 70 is made lower than a specified threshold voltage. As a result, the channel disappears and the main current is cut off.

[0028] In the turn-off operation, the depletion layer expands from the pn junctions at the interfaces between the first-conductivity-type semiconductor substrate 10, the second semiconductor region 50, and the connection region 40 and the first semiconductor region 30 and the buried region 20 of the second conductivity type. Since the impurity concentration of the buried region 20 is higher than that of the first semiconductor region 30, the depletion layer extends longer toward the semiconductor substrate 10 side at the interface between the buried region 20 and the semiconductor substrate 10 than at the interface between the first semiconductor region 30 and the semiconductor substrate 10. Therefore, compared with a semiconductor device without the buried region 20, the Figure 1 breakdown voltage can be increased in the semiconductor device shown.

[0029] The closer the end of the buried region 20 is to the second semiconductor region 50, the longer the ratio of the distance of the interface between the buried region 20 and the semiconductor substrate 10 to the distance of the interface between the first semiconductor region 30 and the semiconductor substrate 10 becomes. Therefore, the breakdown voltage of the semiconductor device increases. However, if the end of the buried region 20 extends toward the gate 90 side and becomes too close to the second semiconductor region 50, the lateral expansion of the depletion layer formed between the first semiconductor region 30 and the second semiconductor region 50 is suppressed. Therefore, breakdown occurs between the first semiconductor region 30 and the second semiconductor region 50 before the depletion layer is sufficiently expanded, and the breakdown voltage of the semiconductor device decreases.

[0030] Therefore, it is preferable that the end of the buried region 20 facing the second semiconductor region 50 is located closer to the drain region 60 than the interface where the first semiconductor region 30 and the second semiconductor region 50 are connected. In the Figure 1 semiconductor device shown, the position of the end of the buried region 20 facing the second semiconductor region 50 is between the gate 90 and the drain region 60.

[0031] In addition, in the Figure 1 semiconductor device shown, the extended region 31 of the first semiconductor region 30 extends under the end of the second semiconductor region 50 and is connected to the side surface of the connection region 40. Therefore, the depletion layer near the surface can be extended. As a result, the electric field concentration near the surface can be avoided, the breakdown voltage of the semiconductor device can be further increased, and the reliability can be improved.

[0032] Hereinafter, a method for manufacturing the Figure 1 semiconductor device shown will be described with reference to the drawings. In addition, the method for manufacturing the semiconductor device described below is an example, and it can be realized by various other manufacturing methods including modified examples thereof.

[0033] First, prepare a semiconductor substrate 10 of a first conductivity type. For example, a p-type silicon substrate is used for the semiconductor substrate 10. The impurity concentration of the semiconductor substrate 10 is about 5.0×10 13 to 4.5×10 14 cm -3 or so. In addition, a substrate other than a silicon substrate may be used for the semiconductor substrate 10.

[0034] Then, as Figure 2 shown, form a buried region 20 and a connection region 40 in such a manner as to be buried in a part of the upper surface of the semiconductor substrate 10. For example, using a mask material formed by photolithography technology, n-type impurities are selectively ion-implanted into a part of the upper surface of the semiconductor substrate 10, and the buried region 20 is formed at a specified position. The n-type impurities are, for example, arsenic, phosphorus, etc. The film thickness of the buried region 20 is about 15 to 25 μm, and the impurity concentration is about 1.1×10 15 to 1.5×10 15 cm -3 or so. Similarly, p-type impurities are selectively ion-implanted into a part of the upper surface of the semiconductor substrate 10, and the connection region 40 is formed at a specified position. The p-type impurities are, for example, boron, etc. The film thickness of the connection region 40 is about 8 to 15 μm, and the impurity concentration is about 5.0×10 16 to 1.0×10 18 cm -3 or so.

[0035] Next, as Figure 3 shown, form a first semiconductor region 30 on the entire surface above the semiconductor substrate 10 so as to cover the buried region 20 and the connection region 40. For example, the first semiconductor region 30 is formed using an epitaxial growth method. The film thickness of the first semiconductor region 30 is about 5 to 10 μm, and the impurity concentration is about 8.0×10 14 to 1.0×10 15 cm -3 or so.

[0036] Next, as Figure 4 shown, selectively ion-implant p-type impurities into a part of the first semiconductor region 30 to form a second semiconductor region 50. At this time, the second semiconductor region 50 is formed so as to reach the upper surface of the semiconductor substrate 10. The film thickness of the second semiconductor region 50 is about 3 to 8 μm, and the impurity concentration is about 5.0×10 15 to 1.0×10 18 cm -3 or so. In addition, as Figure 4 shown, the connection region 40 and the second semiconductor region 50 are formed in such a manner that the end of the second semiconductor region 50 protrudes closer to the buried region 20 side than the end of the connection region 40.

[0037] Then, as Figure 5 shown, a drain region 60 and a source region 70 are formed. For example, by an ion implantation method using a mask material patterned by a photolithography technique as a mask, an n-type impurity is selectively implanted into a part of the upper portion of the first semiconductor region 30 to form the drain region 60. Similarly, an n-type impurity is selectively implanted into a part of the upper portion of the second semiconductor region 50 to form the source region 70. Then, a p-type impurity is selectively implanted into a part of the upper portion of the second semiconductor region 50 to form the back gate region 100. In addition, a gate insulating film 80 and a gate 90 are formed at a predetermined position to complete Figure 1 the semiconductor device shown.

[0038] In addition, due to the influence of heat treatment in the manufacturing process after forming the buried region 20 and the connection region 40, etc., the impurities in the buried region 20 and the connection region 40 diffuse to the surroundings. Therefore, the upper portions of the buried region 20 and the connection region 40 extend upward, and the interfaces of the buried region 20 and the connection region 40 with the first semiconductor region 30 are located above the interface of the semiconductor substrate 10 and the first semiconductor region 30.

[0039] (Other Embodiments)

[0040] As described above, the present invention has been described by embodiments, but the discussions and drawings forming a part of this disclosure should not be construed as limiting the present invention. Based on this disclosure, those skilled in the art can clarify various alternative embodiments, examples, and application techniques.

[0041] For example, as Figure 6 shown, a field insulating film 110 may also be formed on the upper surface of the first semiconductor region 30 between the drain region 60 and the gate 90, and a field plate 120 may be disposed on the upper surface of the field insulating film 110. By setting the field plate 120 to a predetermined potential, the electric field concentration at the end of the gate 90 near the drain region 60 can be alleviated, and the breakdown voltage of the semiconductor device can be further improved.

[0042] In the above description, the case where the semiconductor device is a MOSFET has been described. However, the semiconductor device may also be a transistor of other structures. For example, when the semiconductor device is a JFET, the present invention can also be applied.

[0043] Thus, the present invention naturally includes various embodiments not described herein, etc.

[0044] Industrial Applicability

[0045] The semiconductor device of the present invention can be used in the electronic device industry including the manufacturing industry of manufacturing lateral semiconductor devices.

[0046] Description of Reference Numerals

[0047] 10: Semiconductor substrate;

[0048] 20: Buried region;

[0049] 30: First semiconductor region;

[0050] 40: Connection region;

[0051] 50: Second semiconductor region;

[0052] 60: Drain region;

[0053] 70: Source region;

[0054] 80: Gate insulating film;

[0055] 90: Gate electrode.

Claims

1. A semiconductor device, characterized in that, It includes: A semiconductor substrate of a first conductivity type; A buried region of a second conductivity type, which is buried in a part of the upper surface of the semiconductor substrate; A first semiconductor region of a second conductivity type, which covers the buried region and is selectively disposed above the semiconductor substrate, and has an impurity concentration lower than that of the buried region; A connection region of a first conductivity type, which is buried in a part of the upper surface of the semiconductor substrate at the remaining region of the region where the first semiconductor region is disposed, and its side surface is connected to an extension region, which is a part of the lower portion of the first semiconductor region; A second semiconductor region of a first conductivity type, which is disposed on the upper surface of the connection region, and its side surface is connected to the first semiconductor region; A drain region of a second conductivity type, which is disposed on a part of the upper surface of the first semiconductor region; A source region of a second conductivity type, which is disposed on a part of the upper surface of the second semiconductor region; And A gate, which is disposed above the second semiconductor region between the drain region and the source region, The end portion of the second semiconductor region protrudes closer to the buried region side than the end portion of the connection region, the protruding end portion of the second semiconductor region is in contact with the side surface of the connection region, the extension region of the first semiconductor region extends below the end portion of the second semiconductor region and is in contact with the side surface of the connection region, and only the semiconductor substrate exists below the extended first semiconductor region, The film thickness of the buried region is equal to or greater than the film thickness of the connection region.

2. The semiconductor device according to claim 1, wherein The end portion of the buried region facing the second semiconductor region is located closer to the drain region than the interface where the first semiconductor region is connected to the second semiconductor region.

3. The semiconductor device according to claim 1, wherein The end portion of the buried region facing the second semiconductor region is located between the gate and the drain region.

Images