Electronic detonator collector circuitry

Abstract

The application discloses an electronic detonator collector circuit system, which comprises a collector communication modulation circuit, a collector voltage modulation control circuit and a collector single-line USART transceiving circuit which are electrically connected in sequence, wherein the collector communication modulation circuit comprises a Q4A, Q7A and Q4B, Q7B switch group for controlling a communication positive voltage signal and a Q9A, Q9B switch group for controlling a communication negative voltage signal. The electronic detonator collector circuit system breaks through the existing technical barriers, can completely independently control and design the communication mode, ensures the data safety and reliability and is not easily interfered with the communication by other modes, adopts the single-line USART mode, reduces the number of communication cables, makes the equipment docking interface simpler, makes the mold and the docking module easier to design, and better realizes the data encryption transmission by the single-line serial port data transmission, and the transceiving data is mixed on a communication cable, thereby improving the communication safety.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of civilian explosives, in particular to an electronic detonator collector circuit system. BACKGROUND

[0002] The electronic detonator collector is responsible for collecting detonator related information and storing it, and after collecting all the detonator information used in this batch, it is transmitted to the interfaced detonator initiator at one time.

[0003] The electronic detonator collector, hereinafter referred to as the collector, has its exclusive detonator communication circuit, detonator initiator communication circuit, voltage control circuit, etc. The collector uses a unique detonator communication circuit modulation mechanism to communicate with the electronic detonator to obtain the relevant information of the electronic detonator. SUMMARY

[0004] The technical problem to be solved by the present application is to overcome the existing defects and provide an electronic detonator collector circuit system, a completely self-designed electronic detonator communication circuit and method, which breaks through the existing technical barriers and can completely independently control and design the communication method, ensuring data security and reliability and being less likely to be disturbed by other methods. The problems in the background art can be effectively solved.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical scheme: an electronic detonator collector circuit system, comprising a collector communication modulation circuit, a collector voltage modulation control circuit and a collector single-wire USART transceiver circuit connected in sequence, the collector communication modulation circuit comprising a Q4A, Q7A and Q4B, Q7B switch group for controlling the positive voltage signal of communication and a Q9A, Q9B switch group for controlling the negative voltage signal of communication, the collector communication modulation circuit being provided with an LG1 interface for communicating with the detonator and a CURR_TEST module for reading the feedback data of the detonator;

[0006] The collector voltage modulation control circuit is provided with an electronic detonator power-on switch POW_ON_C, which is powered by a battery VBAT, and is also provided with an SX1308 chip for voltage boosting of the circuit, and the reference voltage output by VPWM is used to control the voltage value of the voltage ultimately boosted by the SX1308, and AN_VDD is used to supply power to the electronic detonator;

[0007] The collector single-wire USART transceiver circuit is provided with a data receiving end RXD3, a data sending end TXD3, an external communication serial port line USART, a switch group Q2A and Q2B.

[0008] As a preferred technical scheme of the present application, the Q7A switch driving circuit is composed of resistors R27, R32 and MOS tube Q4A for front pole driving, the Q4A switch is in default off state, the control pins 5 and 6 are in off state, and the control pin 1 is pulled down to the ground GND level by R27, the Q7B switch driving circuit has the same principle as the Q7A part, the input control signal is OUTBH, and the output signal is OUTB.

[0009] As a preferred technical scheme of the present application, the Q4A, Q4B, Q9A and Q9B are NMOS tubes, and the Q7A and Q7B are PMOS tubes.

[0010] As a preferred technical scheme of the present application, the collector voltage modulation control circuit is provided with MOS tubes Q10A and Q11B for composing a power input switch circuit, Q11B, R63 and R66 compose a control circuit of Q10A, Q11B is turned on by the input high level of POW_ON_C, then the Q10A control end level is pulled down to turn on Q10A, and the battery voltage VBAT is input to the 5-pin input end of the boost chip SX1308 through Q10A.

[0011] As a preferred technical scheme of the present application, the collector voltage modulation control circuit is provided with a boost output voltage VDD, which is controlled by the chip FB feedback end, the VPWM control signal is input to the FB pin for boost control after being filtered by resistors R65, R64 and capacitor C32, and the VDD is dynamically adjusted according to the duty cycle value of the VPWM signal, and the corresponding adjustment is made in actual use in cooperation with the boost value.

[0012] As a preferred technical scheme of the present application, the data receiving end RXD3 is connected with USART through resistor R9, and is in default data receiving state, R17, R19 and Q2B compose a first-stage driving circuit, and R12, R16 and Q2A compose a second-stage driving circuit.

[0013] As a preferred technical scheme of the present application, the switch group Q2A and Q2B are NMOS switch tubes, which are turned on by input high level and are in default off state in the circuit.

[0014] Compared with the prior art, the present application has the beneficial effects that: the electronic detonator collector circuit system is completely independently designed, breaks through the existing technical barriers, can completely independently control and design the communication mode, ensures the data safety and reliability and is not easy to be disturbed in communication by other modes, adopts single-line USART mode, reduces the number of communication cables, makes the equipment docking interface simpler, the mold and the docking module easier to design, the single-line serial port transmission data can better realize data encryption transmission, the transmission and reception data are mixed on one communication cable, and the communication safety is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] Fig. 1 The schematic diagram of the communication modulation circuit structure of the collector of the application is shown in Fig. 1.

[0016] Fig. 2 The schematic diagram of the voltage modulation control circuit structure of the collector of the application is shown in Fig. 2.

[0017] Fig. 3 The schematic diagram of the single-line USART transceiver circuit structure of the collector of the application is shown in Fig. 3. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0019] Please refer to Figs. 1-3The application provides a technical scheme: an electronic detonator collector circuit system, which comprises a collector communication modulation circuit, a collector voltage modulation control circuit and a collector single-wire USART transceiving circuit which are electrically connected in sequence, the collector communication modulation circuit comprises a Q4A, Q7A and Q4B, Q7B switch group for controlling a communication positive voltage signal and a Q9A, Q9B switch group for controlling a communication negative voltage signal, Q4A, Q4B, Q9A and Q9B are NMOS tubes, the switch principle of which is that the control foot inputs high level to turn on and low level to turn off, for example, Q4A, the control foot 1 of which is in a default low level off state, the control foot 5 and the control foot 6 of which are turned on when a high level signal is input, which is equivalent to a switch, the on-off state of which is realized by inputting high and low levels to the control foot, Q7A and Q7B are PMOS tubes, the switch principle of which is opposite to that of the NMOS tube, the control foot inputs low level to turn on and high level to turn off, for example, Q7A, the control foot 1 of which is in a default high level off state, the control foot 5 and the control foot 6 of which are turned on when a low level signal is input, the Q7A switch drive circuit is composed of a resistance R27, a resistance R32 and a MOS tube Q4A, the control foot 5 and the control foot 6 of Q4A are in an off state, the control foot 1 of which is pulled down to the ground GND level by R27, when a high level switch signal OUTAH is input, a high level signal is input to the control foot 1 of Q4A through the resistance R32, Q4A is turned on, that is, the control foot 5 and the control foot 6 of Q4A are turned on to the ground GND low level, a diode Z1, a resistance R23 and Q7A constitute a back drive circuit, at this time, a low level drive signal is input to the control foot 5 and the control foot 6 of Q7A through the resistance R25, and a VDD positive voltage is output by OUTA, the Q7B switch drive circuit has the same principle as the Q7A part, the input control signal is OUTBH, the output signal is OUTB, when the input signal OUTBH is a high level signal, Q4B and Q7B are turned on, and a VDD positive voltage is output by OUTB, the control foot 3 of Q9B is pulled down to the ground GND low level by the resistance R42 by default, the control foot 2 and the control foot 4 of Q9B are turned off, when the input signal OUTAL is a high level signal, Q9B is turned on through the resistance R38, and the current passes through the sampling resistance R45 to the ground, the voltage between the two ends of R45 is sampled by the internal sampling circuit, and the load feedback current data can be obtained, the Q9A drive part has the same principle as the Q9B part, and Q9A is turned on by the input high level signal OUTBL, in actual driving, Q7A and Q9A are turned on together, Q7B and Q9B are turned on together, and the two switch paths cannot be turned on at the same time, the LG1 interface for communicating with the detonator and the CURR_TEST module for reading the feedback data of the detonator are arranged in the collector communication modulation circuit;

[0020] When outputting positive voltage, OUTAH and OUTBL input control high level, Q7A and Q9A are turned on, OUTBH and OUTAL input control low level, Q7B and Q9B are turned off, VDD voltage is output by OUTA via Q7A, passes through electronic detonator load, flows through Q9A by OUTB, and outputs negative voltage through detection resistor R45 to ground. Conversely, Q7B and Q9B are turned on, Q7A and Q9A are turned off, the current direction of VDD is switched through R45 to ground. The CURR_TEST end of resistor R45 is used to measure the current flowing through the electronic detonator load, and the load feedback current value can be measured. Z5, Z6 and Z7 in the circuit are high-voltage protection diodes used to protect the circuit from overvoltage;

[0021] The electronic detonator power-on switch POW_ON_C is provided in the collector voltage modulation control circuit, and is powered by the battery VBAT. The SX1308 chip is also provided for voltage boosting of the circuit. In the SX1308 chip, control pin 5 is an IN voltage input pin, control pin 4 is an enable pin, high level is effective, control pin 1 is a boost voltage output, control pin 2 is a common ground, control pin 3 FB is an output voltage feedback pin. The reference voltage output by VPWM is used to control the voltage value of the final voltage boost of the SX1308. The AN_VDD path is used to supply power to the electronic detonator. MOS tubes Q10A and Q11B are provided in the collector voltage modulation control circuit to form a power input switch circuit. Q11B, R63 and R66 form the control circuit of Q10A. High level input by POW_ON_C controls Q11B to turn on, then pulls down the Q10A control end level Q10A to turn on, then pulls down the Q10A control end level Q10A to turn on. The battery voltage VBAT is input to the 5-pin input end of the boost chip SX1308 through Q10A. The collector voltage modulation control circuit is provided with a boost output voltage VDD, which is controlled by the chip FB feedback end. The VPWM control signal is filtered by resistors R65, R64 and capacitor C32, and then input to the FB pin for boost control. VDD is dynamically adjusted according to the duty cycle value of VPWM signal. In actual use, the corresponding adjustment is made in cooperation with the boost value.

[0022] The single-line USART transceiver circuit of the data acquisition unit is equipped with a data receiving end RXD3, a data transmitting end TXD3, an external communication serial port line USART, and switch groups Q2A and Q2B. The data receiving end RXD3 is connected to the USART through resistor R9 and is in data receiving mode by default. R17, R19 and Q2B form the first-stage driver circuit, and R12, R16 and Q2A form the second-stage driver circuit. Switch groups Q2A and Q2B are NMOS switches, which are turned on when the input is high and turned off by default in the circuit. When the internal microcontroller TXD3 transmits data, TXD3 outputs a high level, which controls Q2B to turn on through resistor R17. Then, the control terminal of Q2A is pulled low, and Q2A is turned off. That is, Q2A and Q2B form a two-stage directional circuit. The control terminal of Q2A is pulled high by default to maintain the conducting state. The level on the external serial port USART line is controlled by the level of the TXD3 transmitting end, realizing the combination of the transmit and receive lines.

[0023] The electronic detonator collector circuit system adopts a two-wire mechanism for communication and power supply, serving as both a power supply line and a communication line. The power line carrier communication method can easily achieve long-distance power supply and communication line sharing. The flexible detonator power supply voltage modulation method can quickly adjust the communication voltage according to different needs, merging the traditional two-wire serial port for receiving and transmitting into a single-wire serial port, enabling fast data transmission and achieving the characteristic of concealed data transmission.

Claims

1. An electronic detonator data acquisition circuit system, comprising a data acquisition communication modulation circuit, a data acquisition voltage modulation control circuit, and a data acquisition single-wire USART transceiver circuit connected in sequence, characterized in that: The acquisition unit communication modulation circuit includes Q4A, Q7A and Q4B, Q7B switch groups for controlling the positive communication voltage signal and Q9A, Q9B switch groups for controlling the negative communication voltage signal. The acquisition unit communication modulation circuit is equipped with an LG1 interface for communicating with the detonator and a CURR_TEST module for reading the detonator feedback data. The voltage modulation control circuit of the data acquisition unit is equipped with an electronic detonator power switch POW_ON_C, which is powered by the battery VBAT. It is also equipped with an SX1308 chip for circuit voltage boosting. The reference voltage output by VPWM controls the final boosted voltage value of SX1308. The electronic detonator is powered by the AN_VDD path. The single-line USART transceiver circuit of the data acquisition unit is equipped with a data receiving end RXD3, a data transmitting end TXD3, an external communication serial port line USART, and switch groups Q2A and Q2B. The data receiving terminal RXD3 is connected to the USART through resistor R9 and is in data receiving mode by default. R17, R19 and Q2B form the first-stage driving circuit, and R12, R16 and Q2A form the second-stage driving circuit. The switch groups Q2A and Q2B are NMOS switches, which are turned on when the input is high and turned off by default when pulled low in the circuit.

2. The electronic detonator acquisition circuit system according to claim 1, characterized in that: The Q7A switch driver circuit consists of resistors R27 and R32 and MOSFET Q4A as the front drive. The Q4A switch is off by default, and its control pins 5 and 6 are in the off state. Its control pin 1 is pulled down to ground level GND by R27. The Q7B switch driver circuit works in the same way as the Q7A part. The input control signal is OUTBH and the output signal is OUTB.

3. The electronic detonator acquisition circuit system according to claim 1, characterized in that: Q4A, Q4B, Q9A, and Q9B are NMOS transistors, and Q7A and Q7B are PMOS transistors.

4. The electronic detonator acquisition circuit system according to claim 1, characterized in that: The voltage modulation control circuit of the data acquisition unit includes MOSFETs Q10A and Q11B, which form a power input switch circuit. Q11B, R63, and R66 form the control circuit for Q10A. A high level input from POW_ON_C controls Q11B to conduct, and then pulls the control terminal level of Q10A low to conduct Q10A. The battery voltage VBAT is input to pin 5 of the boost chip SX1308 through Q10A.

5. The electronic detonator acquisition circuit system according to claim 1, characterized in that: The voltage modulation control circuit of the data acquisition unit is equipped with a boost output voltage VDD. This voltage is controlled by the FB feedback terminal of the chip. The VPWM control signal is filtered by resistors R65 and R64 and capacitor C32 and then input to the FB pin for boost control. VDD is dynamically adjusted according to the duty cycle of the VPWM signal. In actual use, it is adjusted accordingly in conjunction with the boost value.

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