Computing system power management device, system and method

Abstract

Embodiments of the present disclosure relate to computing system power management devices, systems, and methods. Systems and devices are provided that enable granular control of the hold or activation state of each memory circuit in a plurality of memory circuits (e.g., a plurality of memory cell arrays) within a memory. Each respective memory array in the plurality of memory arrays is coupled to a respective ballast driver and a respective activation memory signal switch for the respective memory array. One or more voltage regulators are coupled to the ballast driver gate node and a bias node of at least one memory array in the respective memory arrays. In operation, the respective activation memory signal switch for the respective memory array causes the respective memory array to transition between the activation state of the respective memory array and the hold state of the respective memory array.

Description

Technical Field

[0001] The present disclosure relates generally to digital logic power management and, more particularly, but not exclusively, to the configuration and efficient operation of computing systems and components in different power states. Background Art

[0002] Advanced systems on a chip (SoCs) may include relatively large on-chip static random access memory (SRAM) memory arrays, where such SRAM memory arrays are associated with high power requirements when active (when being accessed). During low-load conditions, a large portion of such SRAM memory arrays can be placed in a low-power state known as retention, in which the data contents of each memory array are retained without requiring the corresponding memory array to quickly respond to memory access requests. By reducing the voltage applied to the associated SRAM memory array during the retention period, leakage current associated with the associated SRAM memory array can be significantly reduced. Summary of the Invention

[0003] Conventional solutions for tracking and / or managing the holding voltage of digital logic circuits, such as SRAM memory arrays, result in various degrees of inefficiency in high leakage conditions in order to maintain the margin required to compensate for (or associated with) circuit manufacturing variations.

[0004] Systems and devices are provided that enable granular control of the hold or activation state of each digital logic circuit in a plurality of digital logic circuits, such as a plurality of memory cell arrays. For example, in an embodiment, each respective digital circuit in the plurality of digital circuits is coupled to a respective activation signal switch for a respective ballast driver and the respective digital circuit. One or more voltage regulators are coupled to the plurality of digital circuits via a bias node of at least one of the respective digital circuits. In operation, the respective activation signal switch for the respective digital circuit causes the respective digital circuit to transition between an activation state for the respective digital circuit and a hold state for the respective digital circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an exemplary configuration of static random access memory (SRAM) included within a multiprocessor computing system.

[0006] Figure 2 A known SRAM configuration is depicted, comprising multiple memory arrays of different sizes coupled together.

[0007] Figure 3A and 3B An embodiment of multiple memory arrays of different sizes coupled according to the techniques described herein is shown.

[0008] Figure 4 Additional embodiments of multiple memory arrays of different sizes coupled according to the techniques described herein are shown.

[0009] Figure 5 Additional embodiments of multiple memory arrays of different sizes coupled according to the techniques described herein are shown.

[0010] Figure 6 Additional embodiments of multiple memory arrays of different sizes coupled according to the techniques described herein are shown.

[0011] Figure 7 Additional embodiments of multiple memory arrays of different sizes coupled according to the techniques described herein are shown.

[0012] Figure 8 Additional embodiments of multiple memory arrays of different sizes coupled according to the techniques described herein are shown.

[0013] Figure 9 Depicted is a block diagram representing an exemplary memory cell array in accordance with the techniques described herein.

[0014] Figure 10 is a functional block diagram of an embodiment of an electronic device or system utilizing memory array management according to the techniques described herein. DETAILED DESCRIPTION

[0015] In the following description, certain details are set forth to provide a thorough understanding of various embodiments of devices, systems, methods, and articles. However, those skilled in the art will appreciate that other embodiments may be practiced without these details. In other instances, known structures and methods associated with circuits (e.g., transistors, integrated circuits, logic gates, memories, interfaces, bus systems, etc.) are not shown or described in detail in some of the figures to avoid unnecessarily obscuring the description of the embodiments.

[0016] Throughout this specification and the claims that follow, unless the context requires otherwise, the word "include" and variations thereof (such as "including" and "comprising") should be interpreted in an open, inclusive sense, i.e., "including but not limited to." References to "at least one" should be interpreted to mean either or both disjunctive and inclusive, unless the context dictates otherwise.

[0017] Throughout this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment or all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to obtain further embodiments.

[0018] Headings are provided for convenience only and do not interpret the scope or meaning of the disclosure.

[0019] The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not drawn to scale, and some of these elements are enlarged and positioned to improve the legibility of the drawings. Furthermore, the particular shapes of the elements as drawn are not necessarily intended to convey any information about the actual shape of the particular element and are selected merely for ease of identification in the drawings.

[0020] It should be understood that although the description of the various techniques presented herein primarily cites examples involving memory cell arrays (such as SRAM memory arrays), such techniques can be applied to a variety of memory circuits and, indeed, to a variety of other digital logic circuits in which multiple power states can be maintained and / or otherwise utilized. For example, a state machine or other digital circuit that employs one or more flip-flops to retain data can employ one or more of the techniques described herein, a system that employs multiple digital logic circuits that are maintained in different power states (e.g., power states associated with various operating modes, active states, standby states, self-test states, etc.) can employ one or more of the techniques disclosed herein, and so on.

[0021] Figure 1An exemplary configuration of an SRAM included in a multi-processor SoC 110 is depicted, wherein the SRAM is composed of an array of multiple memory cells of different sizes. As used herein, the terms memory array and memory cell array may be used interchangeably. The memory array is organized into multiple rows and columns. In the depicted configuration, a first multi-core processor 120a includes four different processing cores (identified as core 1 121, core 2 122, core 3 123, and core 4 124, respectively), each having a 64KB instruction cache and a 64KB data cache. In particular, core 1 121 is associated with instruction cache 121i and data cache 121d; core 2 122 is associated with instruction cache 122i and data cache 122d; core 3 123 is associated with instruction cache 123i and data cache 123d; and core 4 124 is associated with instruction cache 124i and data cache 124d. In addition, the multi-core processor 120 a includes a shared 256 KB instruction cache 130 i and a shared 256 KB data cache 130 d , both of which are shared by each of the cores Core 1 , Core 2 , Core 3 , and Core 4 .

[0022] Similarly, also in Figure 1 In the depicted configuration, the second multi-core processor 120b includes four additional processing cores (identified as Core 5 125, Core 6 126, Core 7 127, and Core 8 128), each of which has a 128KB instruction cache and a 128KB data cache. Specifically, Core 5 125 is associated with an instruction cache 125i and a data cache 125d; Core 6 126 is associated with an instruction cache 126i and a data cache 126d; Core 7 127 is associated with an instruction cache 127i and a data cache 127d; and Core 8 128 is associated with an instruction cache 128i and a data cache 128d. Furthermore, processor 120b includes a shared 1MB instruction cache 140i and a shared 1MB data cache 140d, both of which are shared by each of Core 5, Core 6, Core 7, and Core 8.

[0023] Thus, SoC 110 includes a total of eight 64KB SRAM memory arrays, eight 128KB SRAM memory arrays, two 256KB SRAM memory arrays, and two 1MB SRAM memory arrays for use by a total of eight different processing cores between the two multi-core processors 120a and 120b. It should be understood that SoC 110 may include additional components that are not shown for clarity (e.g., one or more graphics processing units, graphics and / or memory interfaces, I / O interfaces, secondary storage components, analog and / or digital signal processing components, etc.).

[0024] In such Figure 2 In the SoC configuration depicted in FIG, each of multiple memory arrays of different sizes can share a common bias node. In the depicted configuration, a single voltage regulator 201 is coupled to all of the multiple memory arrays (specifically, eight 64KB memory arrays 202a to 202h, eight 128KB memory arrays 204a to 204h, two 256KB memory arrays 206a to 206b, and two 1MB memory arrays 208a to 208b) via a common bias node 212, and provides current to all of the multiple memory arrays when such memory arrays are in a hold state. When the activate memory signal SW is switched to a high level via the memory activation switch 210 to release such memory arrays from hold, the common bias node 212 is pulled to ground, increasing current through all of the memory arrays and preparing them for active access. However, the feedback provided to the regulator 201 via the common bias node 212 is thereby interrupted. When the active memory signal SW transitions from high to low, the regulator must quickly return to operation, which requires a high bandwidth loop. Because the output of a single regulator 201 does not compensate for variations in process, operating voltage, and temperature, the memory cells of the memory array 204, the regulator 201, and the switch 210 are typically over-designed to operate under the worst possible conditions. Furthermore, it should be understood that in Figure 2 In a configuration of , a single memory array may not enter a hold state; instead, all coupled memory arrays are either in a hold state or in an active state, as determined by an activate memory signal SW via the memory activation switch 210.

[0025] Figure 3A and Figure 3BA partial schematic diagram of an embodiment of the technology described herein is presented, in which a plurality (twenty) of memory cell arrays of different sizes (eight 64KB memory arrays 302a-302h, eight 128KB memory arrays 310a-310h, two 256KB memory arrays 318a-318b, and two 1MB memory arrays 330a-330b) are coupled to their own respective voltage regulators 334, which have inputs coupled to bias nodes for the respective memory arrays and outputs coupled to respective gate nodes of respective ballast drivers 338. At least in the depicted embodiment, the voltage regulators 338 can be low-dropout regulators (LDOs), a type of linear voltage regulator designed to operate with an extremely low input-output voltage difference (dropout) to minimize power dissipated as heat in the device. Compared to DC-DC switching converters, LDO regulators typically do not generate ripple because they require fewer external passive components. In the depicted embodiment, corresponding voltage regulators help maintain high area efficiency across a wide range of load conditions, providing granularity for small memory array wakeup and retention by controlling distributed ballast in each of these memory arrays. This embodiment enables retention to access with efficient current leakage recovery.

[0026] In the depicted embodiment, each of the eight 64KB memory arrays 302a to 302h is coupled to a corresponding LDO 304a to 304h and an active memory signal switch 306a to 306h, which controls entry hold and exit hold for the respective coupled memory array. Each of the eight 128KB memory arrays 310a to 310h is similarly coupled to a corresponding LDO 312a to 312h and a corresponding active memory signal switch 314a to 314h. In a similar manner, each of the two 256KB memory arrays 318a to 318b is coupled to a corresponding LDO 320a to 320b and a corresponding active memory signal switch 322a to 322b; and each of the two 1MB memory arrays 330a to 330b is coupled to a corresponding LDO 332a to 332b and a corresponding active memory signal switch 338a to 338b. Figure 2 In significant contrast to the configurations of 202 a-h, 204 a-h, 206 a-b, and 208 a-b, in which a single signal SW activates or holds all or none of the memory arrays 202 a-h, 204 a-h, 206 a-b, and 208 a-b, it should be understood that each memory array in the memory arrays or instances of the depicted embodiments can be individually activated or held via its corresponding activation memory signal switch.

[0027] Figure 3B A more detailed diagram of an LDO structure 332a coupled to a 1MB memory array 330a is provided. Entry and exit to the memory array 330a are maintained by an active memory signal SW via switch 340a. 19 Memory array 330a is coupled to an LDO structure 332a, which includes a differential amplifier 334a coupled between a bias node 336a and a ballast driver 338a. Although a second 1MB memory array 308b is also depicted, the corresponding LDO structure coupled to memory array 308b is omitted for clarity. It should be understood that in this embodiment, second LDO structure 332b is coupled to second 1MB memory array 330b, and each of the corresponding LDO structures 304a-h, 312a-h, and 320a-b (coupled to separate memory arrays 302a-h, 310a-h, and 318a-b, respectively) includes structures and components similar to those depicted with respect to LDO structure 332a. Each memory instance has a small ballast driver (e.g., ballast driver 338a). As the size of the memory instance increases, the size of the coupled ballast driver transistors also increases. Small instances have smaller drivers, which helps avoid area penalties due to overdesign.

[0028] In by Figure 4 In the illustrated additional embodiment, a small ballast driver is coupled to each of the memory arrays 302a to 302h, 310a to 310h, 318a to 318b, and 330a to 330b, respectively, and is driven by a common low power differential amplifier 410. In contrast to the embodiment depicted in FIG3 , a separate respective LDO structure (including a separate differential amplifier and a respective ballast driver) is not coupled to each memory array, and therefore Figure 4 The embodiment of the present invention can achieve significant area savings while maintaining the ability to selectively determine which individual memory arrays enter the hold state. In this embodiment, it is assumed that one cluster of memory arrays (e.g., a group of memory arrays, such as the 64KB memory array 302) enters hold before the other instances and can therefore serve as a reference generator to generate V for the other clusters. bias For ease of explanation, it is assumed that the memory array cluster that enters the hold state before the other memory arrays is memory array 302. However, in some embodiments, it may be assumed that a different memory array (such as memory array 310) enters the hold state before the other memory arrays. If memory array 310 enters the hold mode before any block, then it acts as a V biasIn some embodiments, when a first memory array of the plurality of memory arrays (e.g., memory array 302, 310, 318, or 330) enters the hold phase, a switch may be provided to connect the bias node of the memory array (see Figure 6 The switches 624, 626) are coupled to the ballast driver to provide a reference voltage. A delay circuit (see Figure 7 Delay block 710) is used to stagger the timing of the memory array entering retention mode.

[0029] As shown in the figure, Figure 4 The embodiments may be viewed as providing for regulating V bias Closed-loop control (such as with respect to the 64KB memory array 302 and the differential amplifier 410) and open-loop control (such as with respect to the differential amplifier 410 in conjunction with the 128KB memory arrays 310a to 310h, the 256KB memory arrays 318a-b, and / or the 1MB memory arrays 330a to 330b) are also possible. Typically, a differential amplifier with a high operating bandwidth is employed to accommodate rapid changes in the number of memories in the retention mode.

[0030] In by Figure 5 In the illustrated additional embodiment, the plurality of memory arrays additionally includes a 1 Kb replica memory array 515 coupled to the differential amplifier 510. The replica memory array 515 can be a small memory array having a similar or identical topology to the large memory array coupled to the differential amplifier 510, and the replica memory array 515 can be utilized to maintain the LDO in an active state while biasing the node voltage V bias Maintained at a voltage close to the reference voltage required for the distributed ballast drivers. Replica array 515 operates in closed loop, providing gate bias to the distributed ballasts and setting the bias voltage for those memory arrays (memory arrays 302, 310, 318, and 330) operating in open loop mode. Figure 4 In the embodiment described above, the entry hold and exit hold of each corresponding memory array are activated by corresponding memory signals SW1 to SW 20 At least in the depicted embodiment, where source biasing of NMOS transistors 530a, 532a, 534a, 536a, and 538a is via V biasIn the embodiment of the present invention, wherein the topology of the replica memory array 515 can be substantially the same as the topology of the additional memory arrays 302a to 302h, 310a to 310h, 318a to 318b, and 330a to 330b, when the replica memory array 515 is in the retention state, the voltages at the indicated nodes 520, 522, 524, and 526 can be maintained substantially equal to the indicated GNDXD voltage at the input of the differential amplifier 510. This facilitates the use of differential amplifiers with lower operating bandwidths.

[0031] In by Figure 6In the illustrated additional embodiment, a replica memory array 615 operates in a closed loop within the LDO structure 605, with the bias nodes of the replica array 615 coupled to a common bias node or line GNDXD. The LDO structure 605 is coupled to two memory instances, shown as SRAM instances 620 and 630. The SRAM instance 620 includes a first memory array 622 and distributed ballast drivers 626a through 626n; the SRAM instance 630 includes a second memory array 632 and distributed ballast drivers 636a through 636n. Each column of the memory arrays 622 and 632 can have a corresponding distributed ballast driver 626i, 636i, respectively. The distributed ballast drivers 626i, 636i of the non-replica memory cell arrays 622 and 632 are included in the closed loop of the LDO structure 605 while these memory cell arrays are in a retention state. Feedback transistor switches 624 and 634 are coupled between the common bias node or line GNDXD of LDO structure 605 and the corresponding bias nodes or lines GNDX1 and GNDX2 of each non-replica memory cell array 622 and 632, respectively. In this embodiment, the feedback transistor switches provide better feedback loop control for LDO structure 605 by allowing physical shorting of bias node GNDXD and each of bias nodes GNDX1 and GNDX2, respectively. With respect to SRAM example 620, when source bias control SBC1 goes high and source bias control shutoff SBCO1 goes low, feedback transistor switch 624 closes, placing memory array 622 in a retention state. Conversely, when source bias control shutoff SBCO1 goes high (preparing memory array 622 for active access) and SBC1 goes low, feedback transistor switch 624 opens until memory array 622 is again in a retention state. The states of SBC1 and SBCO1 are typically controlled to prevent both switches 624 and 625 from being closed simultaneously, thereby preventing feedback interference within the LDO structure 605. Similarly, with respect to the SRAM example 630, when source bias control SBC2 goes high and source bias control OFF SBCO2 goes low, feedback transistor switch 634 is closed, thereby placing the memory array 632 in a retention state. Conversely, when source bias control OFF SBCO2 goes high (preparing the memory array 632 for active access) and SBC2 goes low, feedback transistor switch 634 is opened until the memory array 632 is again in a retention state. Again, the states of SBC2 and SBCO2 are typically controlled to prevent both switches 624 and 625 from being closed simultaneously, thereby preventing feedback interference within the coupled LDO structure 605.

[0032] In by Figure 7 In the additional embodiment shown, Figure 6The embodiment has been modified to include an optional delay circuit device block 710 in series with the control signal SBC2 of the feedback transistor switch 634. The delay circuit device block 710 provides a time buffer between the time when the memory array 632 is actively accessed and then placed in the retention state, so that the voltage V bias is allowed to settle to the holding level, thereby avoiding feedback interference with the LDO structure 605. It should be understood that in various embodiments, such a delay block may similarly be coupled in series with corresponding control signals corresponding to one or more additional memory arrays, such as in series with the control signal SBC1 of the feedback transistor switch 624, to avoid similar LDO feedback interference via the memory array 622. The delays for different memory arrays may be staggered to help avoid interference with the feedback loop by causing a large number of arrays to enter the holding state simultaneously.

[0033] In by Figure 8 In the additional embodiment shown, Figure 6 The embodiment has been modified to include optional control logic 810 in series with control signal SBC2 for feedback transistor switch 634, such as to sequence source bias control off signal SBCO2 and source bias control SBC2 (with respect to memory array 632). Control logic 810 is further coupled to comparator 815, which compares the voltage level of memory array bias node GNDX2 with feedback voltage GNDXD of LDO structure 605. Via comparator enable 818, control logic 810 enables comparator 815 when the memory cell array transitions from active access to retention (e.g., when SBCO2 goes low). In this and various other embodiments, source bias control SBC2 is not asserted until the voltage difference between GNDXD and GNDX2 is within a threshold range. In this manner, LDO feedback glitches are reduced during the transition of memory array 632 from active access to retention.

[0034] Embodiments herein are described as having multiple memory arrays of different sizes. However, embodiments may have multiple memory arrays of the same size.

[0035] Figure 9 A block diagram illustrating an exemplary memory cell array according to the techniques described herein is depicted. In particular, memory cell array 901 includes peripheral logic 910, ten separate 256KB memory arrays (identified as memory arrays 920a through 920j), and distributed ballast drivers 930a through 930e, such that the ballast drivers for memory arrays 920a through 920j are distributed and embedded within memory cell array 901.

[0036] Figure 10is a functional block diagram of an exemplary electronic device or system 1000 in which various embodiments described herein may be utilized. System 1000 may be used, for example, to implement a convolutional neural network to classify sensor data. It should be appreciated that because such neural networks can be very memory intensive, the ability to efficiently transition portions of memory into and out of a hold state as needed by the neural network can provide significant improvements in power management and overall performance of such neural networks. In various implementations, system 1000 may comprise a system on a chip.

[0037] System 1000 includes a global memory 1002 that can be used, for example, as main memory, such as for one or more neural network processing or processing clusters, and for one or more host system 1004 processing or processing clusters. Global memory 1002 includes memory management circuitry 1006 and one or more shared memory arrays 1008. It should be understood that memory array 1008 can include one or more instances of a memory cell array according to the techniques described herein, such as Figures 3A to 3B and Figures 4 and 5 Memory arrays 302, 310, 318, and 330, Figures 6 to 8 The memory arrays 622 and 632 and Figure 9 In operation, memory management circuitry 1006 employs one or more memory management routines to allocate regions of shared memory array 1008 to various processes executed by system 1000 .

[0038] As shown, system 1000 includes one or more data movers 1010, one or more memory bridges 1020, one or more sensors 1030 and corresponding sensor interfaces 1032, one or more convolution accelerator engines 1040, and one or more connection engines 1050, which can be implemented and operated to produce classification output 1060.

[0039] The data mover 1010 in operation moves data flows between IO (eg, sensor interface 1032 ), memory hierarchy (eg, global memory 1002 , memory bridge 1020 ), convolution accelerator 1040 , and connectivity engine 1050 .

[0040] In some embodiments, system 1000 may include more components than shown, may include fewer components than shown, may separate the shown components into separate components, may combine the shown components, etc., as well as various combinations thereof.

[0041] According to at least one implementation, a system-on-chip (SoC) device can be summarized as including one or more processors, a memory coupled to the one or more processors and having a plurality of memory arrays, and one or more voltage regulators coupled to a ballast driver gate node and a bias node of at least one of the respective memory arrays. Each respective memory array in the plurality of memory arrays can be coupled to a respective activation memory for the respective ballast driver and the respective memory array.

[0042] Each of the one or more voltage regulators may be a low dropout regulator (LDO).

[0043] In operation, a corresponding active memory signal switch of a corresponding memory array may toggle the corresponding memory array between an active state of the corresponding memory array and a hold state of the corresponding memory array.

[0044] Each respective memory array of the plurality of memory arrays may be coupled to a respective voltage regulator via a respective bias node of the respective memory array, and an output of the respective voltage regulator may be coupled to a gate node of a respective ballast driver of the respective memory array.

[0045] The one or more voltage regulators coupled to the plurality of memory arrays may be a common voltage regulator whose output is coupled to a respective gate node of each respective ballast driver in each memory array in the plurality of memory arrays.

[0046] The plurality of memory arrays may include a first group of memory arrays and an additional memory array. The bias nodes of the additional memory array may be coupled to a common bias node of a common voltage regulator, and in operation, the additional memory array may be maintained in a hold state. The additional memory array may have a size smaller than the size of the first group of memory arrays. The bias node of at least one memory array of the first group of memory arrays may be coupled to the common bias node via a first switch; in operation, the first switch may close in response to the opening of a corresponding activation memory signal switch of the at least one memory array. The SoC device may include a delay circuit coupled to a source node of the first transistor, such that, in operation, the delay circuit delays closing of the first switch in response to the opening of the corresponding activation memory signal switch of the at least one memory array. The SoC device may include control logic coupled to the first switch and the activation memory signal switch of the at least one memory array, such that, in operation, the control logic closes the first switch based at least in part on a voltage at the bias node of the additional memory array being within a threshold range of a voltage at the bias node of the at least one memory array.

[0047] The plurality of memory arrays may include static random access memory (SRAM).

[0048] The respective ballast drivers for the multiple memory arrays may be embedded within and distributed across the multiple memory arrays.

[0049] According to at least one other implementation, a computing system can be summarized as including one or more processors, a memory coupled to the one or more processors and having a plurality of memory arrays, and one or more voltage regulators coupled to a ballast driver gate node and a bias node of at least one of the respective memory arrays. Each respective memory array in the plurality of memory arrays can be coupled to a respective activation memory for the respective ballast driver and the respective memory array.

[0050] Each of the one or more voltage regulators may be a low dropout regulator (LDO).

[0051] Each respective memory array of the plurality of memory arrays may be coupled to a respective voltage regulator via a respective bias node of the respective memory array, and an output of the respective voltage regulator may be coupled to a gate node of a respective ballast driver of the respective memory array.

[0052] The one or more voltage regulators coupled to the plurality of memory arrays may be a single or common voltage regulator coupled to a respective gate node of each respective ballast driver in each memory array in the plurality of memory arrays.

[0053] The plurality of memory arrays may include a first group of memory arrays and an additional memory array. A bias node of the additional memory array may be coupled to a common bias node of a common voltage regulator, and in operation, the additional memory array may be maintained in a hold state. The bias node of at least one memory array of the first group of memory arrays may be coupled to the common bias node of the common voltage regulator via a first switch; in operation, the first switch may be closed in response to the opening of a corresponding activation memory signal switch of the at least one memory array.

[0054] According to at least one additional embodiment, a memory device can be summarized as including a plurality of memory arrays and one or more voltage regulators coupled to a ballast driver gate node and a bias node of at least one memory in a corresponding memory array. Each corresponding memory array in the plurality of memory arrays can be coupled to a corresponding ballast driver and a corresponding activation memory signal switch of the corresponding memory array such that, in operation, the corresponding activation memory signal switch of the corresponding memory array can cause the corresponding memory array to transition between an activation state for the corresponding memory array and a retention state for the corresponding memory array.

[0055] Each respective memory array of the plurality of memory arrays may be coupled to a respective voltage regulator via a respective bias node of the respective memory array, and an output of the respective voltage regulator may be coupled to a gate node of a respective ballast driver of the respective memory array.

[0056] The one or more voltage regulators coupled to the plurality of memory arrays may be a common voltage regulator coupled to a respective gate node of each respective ballast driver in each memory array in the plurality of memory arrays.

[0057] The plurality of memory arrays may include a first group of memory arrays and an additional memory array. A bias node of the additional memory array may be coupled to a common bias node of a common voltage regulator, and in operation, the additional memory array may be maintained in a hold state. The bias node of at least one memory array of the first group of memory arrays may be coupled to the common bias node of the common voltage regulator via a first switch, such that in operation, the first switch closes in response to the opening of a corresponding activation memory signal switch for the at least one memory array.

[0058] According to additional implementations, a system can be summarized as including one or more processors; a memory coupled to the one or more processors and having a plurality of memory arrays, the memory arrays including a first group of memory arrays and an additional memory array maintained in a retention state during operation; a voltage regulator coupled to a gate node of a corresponding ballast driver of each memory array in the plurality of memory arrays and a bias node of the additional memory array; a first switch coupled between a bias node of at least one memory array in the first group of memory arrays and a bias node of the additional memory array; and control logic coupled to the first switch and an activation memory signal switch of the at least one memory array. Each respective memory array in the plurality of memory arrays can be coupled to a corresponding ballast driver and a corresponding activation memory signal switch of the respective memory array. In operation, the control logic can turn off the first switch in response to a voltage at the bias node of the additional memory array being within a threshold range of a voltage at the bias node of the at least one memory array.

[0059] In an embodiment, a method includes executing one or more processes on a system-on-chip (SoC) having one or more processing cores and a memory having a plurality of memory arrays, wherein each respective memory array in the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch of the respective memory array; and controlling the respective active memory signal switches of the plurality of memory arrays to place the memory arrays in an active or hold mode of operation during execution of the one or more processes. In an embodiment, the memory includes a voltage regulator coupled to a ballast driver gate node and a bias node of at least one memory array in the respective memory arrays. In an embodiment, each respective memory array in the plurality of memory arrays is coupled to a respective voltage regulator via a respective bias node of the respective memory array, and an output of the respective voltage regulator is coupled to a gate node of the respective ballast driver of the respective memory array. In an embodiment, the plurality of memory arrays includes a first group of memory arrays and an additional memory array, wherein the bias node of the additional memory array is coupled to a common bias node of a common voltage regulator, and the method includes maintaining the additional memory array in a hold state during execution of the one or more processes. In an embodiment, the additional memory array has a size that is smaller than a size of any memory array in the first group of memory arrays. In an embodiment, the method includes selectively coupling a bias node of at least one memory array in a first group of memory arrays to a common bias node of the common voltage regulator in response to transitioning the at least one memory array to a retention state. In an embodiment, the method includes delaying the selective coupling. In an embodiment, the method includes coupling the bias node of the additional memory array to the bias node of the at least one memory array based on a comparison of a voltage at the bias node of the additional memory array to a voltage at the bias node of the at least one memory array.

[0060] In an embodiment, the contents of a non-transitory computer readable medium cause a computing system of a system on chip (SoC) to perform a method according to one or more embodiments of the method disclosed herein. In an embodiment, the contents include instructions that, when executed by the SoC, cause the SoC to perform the method.

[0061] Some embodiments may take the form of or include a computer program product. For example, according to an embodiment, a computer readable medium is provided, comprising a computer program suitable for performing one or more of the methods or functions described above. The medium may be a physical storage medium, such as, for example, a read-only memory (ROM) chip, or a disk, such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk, a memory, a network, or a portable medium, which may be read by an appropriate drive or via an appropriate connection, including other relevant codes encoded in one or more bar codes or stored on one or more such computer readable media and readable by an appropriate reader device.

[0062] In addition, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other manners, such as at least partially implemented or provided in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, convolution accelerators, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices employing RFID technology and various combinations thereof.

[0063] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0064] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A system-on-chip (SoC) device, comprising: one or more processors; a memory coupled to the one or more processors and having a plurality of memory circuits, the plurality of memory circuits including a first group of memory circuits, wherein each respective memory circuit in the first group of memory circuits is coupled to a respective ballast driver for the respective memory circuit and a respective activate memory signal switch; as well as a common voltage regulator coupled to a respective one of the respective ballast driver gate nodes for each of the plurality of memory circuits and a bias node of at least one of the respective memory circuits, wherein the plurality of memory circuits includes an additional memory circuit and the bias nodes of the additional memory circuits are coupled to the common bias node of the common voltage regulator and the additional memory circuits are maintained in a hold state in operation. 2 . The SoC device of claim 1 , wherein the common voltage regulator is a low dropout regulator (LDO).

3. The SoC device according to claim 1, wherein: In operation, a respective one of the activate memory signals switches for respective memory circuits of the first group of memory circuits to transition the respective one of the memory circuits between an activate state for the respective one of the memory circuits and a hold state for the respective one of the memory circuits. 4 . The SoC device of claim 1 , wherein each respective one of the plurality of memory circuits is coupled to the common voltage regulator via a respective bias node of the respective memory circuit. 5 . The SoC device of claim 1 , wherein the additional memory circuit has a size that is smaller than a size of any memory circuit in the first set of memory circuits.

6. The SoC device of claim 1 , wherein a bias node of at least one memory circuit in the first group of memory circuits is coupled to the common bias node of the common voltage regulator via a first switch, and wherein in operation, the first switch is closed in response to opening of the corresponding activate memory signal switch for the at least one memory circuit.

7. The SoC device according to claim 6, comprising: A delay circuit device is coupled to the first switch, wherein in operation, the delay circuit device delays the closing of the first switch in response to the opening of the corresponding activation memory signal switch of the at least one memory circuit.

8. A system-on-chip (SoC) device, comprising: one or more processors; a memory coupled to the one or more processors and having a plurality of memory circuits, the plurality of memory circuits including a first group of memory circuits, wherein each respective memory circuit in the first group of memory circuits is coupled to a respective ballast driver for the respective memory circuit and a respective activate memory signal switch; and a common voltage regulator coupled to a bias node of at least one corresponding memory circuit and a ballast driver gate node, wherein: the plurality of memory circuits including an additional memory circuit, a bias node of the additional memory circuit coupled to a bias node of the common voltage regulator; The additional memory circuit is maintained in a retention state during operation; The SoC device includes control logic coupled to the activate memory signal switch for at least one memory circuit of the first group of memory circuits and a first switch coupled between a bias node of the additional memory circuit and a bias node of the at least one memory circuit, and Wherein, in operation, the control logic closes the first switch based at least in part on a voltage at the bias node of the additional memory circuit being within a threshold range of a voltage at the bias node of the at least one memory circuit.

9. The SoC device of claim 8, wherein the plurality of memory circuits comprises a static random access memory (SRAM) array.

10. The SoC device of claim 8, wherein the respective ballast drivers for the plurality of memory circuits are embedded within the plurality of memory circuits and are distributed within the plurality of memory circuits.

11. A computing system comprising: one or more processors; a memory coupled to the one or more processors and having a plurality of memory circuits, the plurality of memory circuits including a first group of memory circuits, wherein each respective memory circuit in the first group of memory circuits is coupled to a respective ballast driver for a respective memory circuit of the first group of memory circuits and a respective activate memory signal switch; as well as a common voltage regulator coupled to a respective one of the respective ballast driver gate nodes for each of the plurality of memory circuits and a bias node of at least one of the respective memory circuits of the first group of memory circuits, wherein the plurality of memory circuits includes an additional memory circuit and the bias nodes of the additional memory circuits are coupled to the common bias node of the common voltage regulator and the additional memory circuits are maintained in a hold state in operation.

12. The computing system of claim 11, wherein the common voltage regulator is a low dropout regulator (LDO).

13. The computing system of claim 11, wherein each respective one of the plurality of memory circuits is coupled to the common voltage regulator via a respective bias node of the respective memory circuit.

14. The computing system of claim 11 , wherein a bias node of at least one memory circuit in the first group of memory circuits is coupled to the common bias node of the common voltage regulator via a first switch, and wherein in operation, the first switch is closed in response to opening of a corresponding activate memory signal switch for the at least one memory circuit.

15. The computing system of claim 11, wherein the plurality of memory circuits comprises a plurality of memory arrays.

16. A memory device comprising: a plurality of memory circuits, the plurality of memory circuits comprising a first group of memory circuits, wherein each respective memory circuit in the first group of memory circuits is coupled to a respective ballast driver and a respective activate memory signal switch for a respective one of the first group of memory circuits, and wherein, in operation, the respective activate memory signal switch for a respective one of the first group of memory circuits causes the respective one of the memory circuits to transition between an activate state for the respective one of the memory circuits and a hold state for the respective one of the memory circuits; and a common voltage regulator coupled to a ballast driver gate node of each memory circuit of a corresponding memory circuit in the first group of memory circuits and a bias node of at least one memory circuit of the first group of memory circuits, wherein the plurality of memory circuits includes an additional memory circuit and the bias node of the additional memory circuit is coupled to the common bias node of the common voltage regulator, and the additional memory circuit is maintained in a retention state in operation.

17. The memory device of claim 16, wherein each respective one of the plurality of memory circuits is coupled to the common voltage regulator via a respective bias node of the respective memory circuit.

18. The memory device of claim 16 , wherein a bias node of at least one memory circuit in the first group of memory circuits is coupled to the common bias node of the common voltage regulator via a first switch, and wherein in operation, the first switch is closed in response to opening of a corresponding activate memory signal switch for the at least one memory circuit.

19. A method of managing voltage in a circuit, comprising: regulating, using a common voltage regulator, a voltage provided to respective ballast driver gate nodes of a plurality of memory circuits of a system-on-chip (SoC) device, the plurality of memory circuits including a first group of memory circuits and additional memory circuits having bias nodes coupled to a common bias node of the common voltage regulator; controlling, using corresponding activation memory signal switches, a transition of corresponding memory circuits of the plurality of memory circuits between an activation state for the corresponding memory circuit and a retention state for the corresponding memory circuit; as well as The additional memory circuit is maintained in the retention state.

20. The method of claim 19, wherein each of the common voltage regulators is a low dropout regulator (LDO).

21. The method of claim 19, wherein each respective one of the plurality of memory circuits is coupled to the common voltage regulator via a respective bias node of the respective memory circuit, and wherein an output of the respective voltage regulator is coupled to a gate node of the respective ballast driver for the respective memory circuit.

22. The method of claim 19, wherein the common voltage regulator is coupled to a respective gate node of each respective ballast driver for each memory circuit of the plurality of memory circuits.

23. The method of claim 22, wherein a bias node of at least one memory circuit of the first group of memory circuits is coupled to the common bias node of the common voltage regulator via a first switch, and the method comprises: The first switch is closed in response to the opening of the corresponding activate memory signal switch for the at least one memory circuit.

24. The method according to claim 23, comprising: The closing of the first switch is delayed in response to the opening of the corresponding activate memory signal switch of the at least one memory circuit.

25. The method of claim 19, wherein the plurality of memory circuits comprises a first group of memory circuits, and additional memory circuits, the method comprising: The bias node of the additional memory circuit is selectively coupled to a bias node of at least one memory circuit of the plurality of memory circuits based on a voltage at the bias node of the additional memory circuit being within a threshold range of a voltage at the bias node of at least one memory circuit.

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