Memory device, electronic device, and method of storing data

Abstract

Memory devices, electronic devices, and methods of storing data are provided. The electronic device includes a host configured to output data and a memory device including a memory storage device configured to receive and store the data. The host is configured to generate data bus inversion (DBI) information about the data to be provided to the memory device according to a data parallelization system internal to the memory device and provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage device, the data being output from the host, the data being encoded according to the DBI information, the data being provided according to the data parallelization system.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0167984, filed on December 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Example embodiments relate to a system on chip (SoC), a memory device, an electronic device, and / or a method for storing data in an electronic device. BACKGROUND

[0003] Depending on a state of data or a frequency of data transition, data bits moved through a data bus can be sensitive to cross-talk, simultaneous switching noise (SSN), inter-symbol interference (ISI), etc. A data encoding method such as data bus inversion (DBI) can be used to reduce such adverse effects.

[0004] Meanwhile, in order to support various systems requiring high performance and low power consumption such as graphics, servers, supercomputers, and / or networks, a high bandwidth memory (HBM) using a multi-channel interface type providing wide input and output is used.

[0005] The HBM can perform DBI on a channel including a plurality of data bits, for example, based on a byte. Research is desired and / or required regarding a method for determining DBI bits to improve an operation speed of the HBM. SUMMARY

[0006] Aspects of example embodiments provide an electronic device having an improved data storage speed.

[0007] Aspects of example embodiments also provide a method for storing data in an electronic device having an improved data storage speed.

[0008] Aspects of example embodiments also provide a memory device having an improved data storage speed.

[0009] Aspects of example embodiments also provide a SoC which calculates DBI bits and provides the DBI bits to a memory device so that a data storage speed can be improved.

[0010] However, aspects of example embodiments are not limited to those set forth herein. The above and other aspects of example embodiments will become more apparent by describing in detail example embodiments given below.

[0011] According to some example embodiments, there is provided an electronic device including a host configured to output data, and a memory device including a memory storage configured to receive and store the data. The host is configured to generate data bus inversion (DBI) information about the data to be provided to the memory device according to a data parallelization system inside the memory device, and provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data being output from the host, the data being encoded according to the DBI information, the data being provided according to the data parallelization system.

[0012] According to some example embodiments, there is provided a method for storing data in an electronic device, the method including providing, by a memory device, information about a data parallelization system to a host, the information being inside the memory device; calculating, by the host, external DBI bits based on data to be provided to the memory device; providing, by the host, the external DBI bits to the memory device; encoding, by the host, data to be stored in the memory device using the external DBI bits; providing, by the host, the data to the memory device; calculating, by the host, internal DBI bits based on the data provided to the memory device and the information about the data parallelization system provided from the memory device; and providing, by the host, the internal DBI bits to the memory device.

[0013] According to some example embodiments, there is provided a memory device including a memory storage configured to store data provided through a first input port, and control logic configured to receive data from outside through a second input port, rearrange the data provided through the second input port according to a data parallelization system, and provide the data to the memory storage through the first input port. The control logic is configured to receive internal DBI bits of the data from outside, encode the data using the internal DBI bits, and provide the encoded data and the internal DBI bits to the memory storage, the internal DBI being generated based on the data parallelization system.

[0014] According to some example embodiments, there is provided a SoC including an output port configured to output a plurality of sub-data according to a first array, and a data bus inversion (DBI) controller configured to receive information about a data parallelization system from outside, generate DBI bits of the plurality of sub-data output through the output port based on the information about the provided data parallelization system, and output the generated DBI bits with the plurality of sub-data. The information about the data parallelization system is information about rearranging the plurality of sub-data into a second array different from the first array. The DBI bits are associated with decoding of the plurality of sub-data rearranged into the second array. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other aspects and features of the present disclosure will become clearer after a detailed description of example embodiments thereof, which are illustrated in the accompanying drawings:

[0016] Figure 1 is a block diagram of an electronic device according to some example embodiments;

[0017] Figure 2 is a diagram illustrating a table stored in a mode register set of Figure 1

[0018] Figure 3 is a flowchart illustrating a method for storing data in an electronic device according to some example embodiments;

[0019] Figures 4 to 10 is a diagram for explaining a method for storing data in an electronic device according to some example embodiments;

[0020] Figure 11 and Figure 12 is a diagram for explaining a method for storing data in an electronic device according to some example embodiments;

[0021] Figure 13 is a block diagram of an electronic device according to some example embodiments;

[0022] Figure 14 is a diagram for explaining an operation of an electronic device illustrated in Figure 13

[0023] Figure 15 is a block diagram of an electronic device according to some example embodiments; and

[0024] Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the technical idea according to example embodiments will be described with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of an electronic device according to some example embodiments.

[0027] Referring to Figure 1 , the electronic device 1 includes a host 100 and a memory device 200.

[0028] ​​The memory device 200 can include control logic 210 and a memory storage / memory 260. In some example embodiments, although the memory device 200 can be a high bandwidth memory (HBM) of a multi-channel interface type that provides wide input and output, some example embodiments are not limited thereto.

[0029] Although, for ease of understanding, Figure 1 Only one memory 260 included in the memory device 200 is illustrated, but some example embodiments are not limited to the illustrated embodiment. The memory 260 can be capable of storing data, and also capable of performing operations on the data. Further, if necessary, the memory device 200 can include a plurality of memories 260, and the control logic 210 can interface with the plurality of memories 260 in a multi-channel manner.

[0030] The memory 260 can include a plurality of input ports DQ0 to DQ7, an internal data bus inversion port (IDBI), a memory controller 262, and a memory cell array (MCA) 264.

[0031] The memory controller 262 can decode data provided through the plurality of input ports DQ0 to DQ7 of the memory 260 based on internal DBI information provided through the internal DBI port IDBI of the memory 260. Further, the memory controller 262 can store the decoded data in memory cells included in the memory cell array 264.

[0032] In some example embodiments, although the memory 260 includes, for example, a volatile memory such as a dynamic random access memory (DRAM), and the memory cells included in the memory cell array 264 can include, for example, DRAM cells composed of capacitors, some example embodiments are not limited thereto.

[0033] Alternatively or additionally, the memory 260 can be or include resistive random access memory (RRAM or ReRAM), phase change random access memory (PRAM), and / or ferroelectric random access memory (FRAM). Alternatively or additionally, the memory 260 can include a magnetic random access memory (MRAM) structure such as STT-MRAM (spin transfer torque magnetic random access memory), spin-RAM (spin transfer torque magnetic switching RAM), and / or SMT-RAM (spin momentum transfer).

[0034] The control logic 210 can receive data or a provision of data from an external (e.g., the host 100) through the plurality of input ports DQ0 to DQ7 of the memory device 200. Also, the control logic 210 can receive external DBI information from an external (e.g., the host 100) through the external DBI port EDBI of the memory device 200. Also, the control logic 210 can receive internal DBI information from an external (e.g., the host 100) through the internal DBI port IDBI of the memory device 200. Although the external can correspond to the host 100, example embodiments are not limited thereto.

[0035] The control logic 210 can decode data provided through the plurality of input ports DQ0 to DQ7 of the memory device 200 based on the external DBI information provided through the external DBI port EDBI of the memory device 200. Also, the control logic 210 can encode the data using the internal DBI information provided through the internal DBI port IDBI of the memory device 200. Also, the control logic 210 can rearrange the data encoded according to the internal DBI information according to information such as the data parallelization information 212 (e.g., can parallelize and rearrange the data serialized and transmitted), and then can provide the rearranged data to the plurality of input ports DQ0 to DQ7 of the memory 260.

[0036] Here, the data parallelization information 212 can be or include information about a data parallelization system that parallelizes data in an internal data bus of the memory device 200 and / or provides the data to the memory 260. In one example, the data parallelization system is internal to the memory device 200.

[0037] At this time, the control logic 210 can also transmit the internal DBI information provided from an external (e.g., from the host 100) to the internal DBI port IDBI of the memory 260, so that the memory controller 262 in the memory 260 can decode the rearranged data.

[0038] For example, according to some example embodiments, the control logic 210 of the memory device 200 does not calculate the internal DBI information about the data provided to the plurality of input ports DQ0 to DQ7 of the memory 260, but directly transmits the internal DBI information provided from an external (e.g., the host 100) to the memory 260. As a result, since the time for calculating the internal DBI information in the memory device 200 is unnecessary / unused and / or not needed, the data storage speed of the memory device 200 or the electronic device 1 can be improved.

[0039] In some example embodiments, the external DBI information includes a plurality of external DBI bits, and the internal DBI information can include a plurality of internal DBI bits. For example, the external DBI information can be constituted by a plurality of external DBI bits or can include a combination of a plurality of external DBI bits, and the internal DBI information can be constituted by a plurality of internal DBI bits or can include a combination of a plurality of internal DBI bits. Specific descriptions thereof will be provided below.

[0040] Meanwhile, although it is described for convenience, Figure 1 It is illustrated that the data parallelization information 212 is included in the control logic 210 of the memory device 200, but example embodiments are not limited thereto. In some example embodiments, the data parallelization information 212 can be stored in another region (e.g., another storage region) of the memory device 200.

[0041] The host 100 can provide data and / or a command to the memory device 200. Specifically, the host 100 can provide a command (e.g., a write command) for instructing the memory device 200 to store data, and data to be stored in the memory device 200.

[0042] In some example embodiments, the host 100 can include, for example, a SoC (System on Chip). Although not illustrated in detail, the host 100 can include a host controller for performing such an operation. In some example embodiments, although the host 100 can include, for example, a central processor (CPU), a graphics processor (GPU), an accelerated processor (APU), an application processor (AP), or the like, some example embodiments are not limited thereto.

[0043] The host 100 must include a plurality of output ports DQ0 to DQ7, an external DBI port EDBI, an internal DBI port IDBI, a DBI controller 110, and a mode register set (MRS) 120.

[0044] The host 100 can output data to be stored in the memory device 200 through the plurality of output ports DQ0 to DQ7.

[0045] The DBI controller 110 can calculate DBI information about data to be provided to the memory device 200 through the plurality of output ports DQ0 to DQ7 of the host 100, and can encode data to be provided to the device 200 according to the calculated DBI information.

[0046] In particular or for example, the DBI controller 110 can generate external DBI information for decoding data by the control logic 210 of the memory device 200, the data being provided to the plurality of input ports DQ0-DQ7 of the memory device 200 by the plurality of output ports DQ0-DQ7 of the host 100. Further, the DBI controller 110 can provide the generated external DBI information to the memory device 200 by the external DBI port EDBI of the host 100, and can use the external DBI information to encode data to be provided to the plurality of input ports DQ0-DQ7 of the memory device 200 by the plurality of output ports DQ0-DQ7 of the host 100. The data thus encoded can be provided to the memory device 200 by the plurality of output ports DQ0-DQ7 of the host 100.

[0047] For example, when the data is constituted by or corresponds to a plurality of sub-data, and the host 100 provides the plurality of sub-data to the plurality of input ports DQ0-DQ7 of the memory device 200 according to a first array (e.g., a serial array), the DBI controller 110 generates external DBI information in which the control logic 210 of the memory device 200 can decode data received by the plurality of input ports DQ0-DQ7 of the memory device 200, and the DBI controller 110 can use the external DBI information to encode data to be provided to the plurality of input ports DQ0-DQ7 of the memory device 200 by the plurality of output ports DQ0-DQ7 of the host 100. Further, the DBI controller 110 can provide the generated external DBI information to the memory device 200 by the external DBI port EDBI of the host 100, and can provide the encoded data to the memory device 200 by the plurality of output ports DQ0-DQ7 of the host 100.

[0048] Next, the DBI controller 110 can generate internal DBI information for decoding data provided to the plurality of input ports DQ0-DQ7 of the memory 260 by the memory controller 262 of the memory 260 based on the data serialization information 212. In one example, the DBI controller 110 can calculate the internal DBI information based on the data provided to the memory 260 and the data serialization information 212. Further, the DBI controller 110 can provide the generated internal DBI information to the memory device 200 by the internal DBI port IDBI of the host 100.

[0049] For example, when data consists of or corresponds to multiple sub-data, and control logic 210 provides the multiple sub-data to multiple input ports DQ0 to DQ7 of memory 260 according to a second array (e.g., a parallelized array) instead of a first array, DBI controller 110 can generate internal DBI information in which memory controller 262 of memory 260 can decode data received through the multiple input ports DQ0 to DQ7 of memory 260. Additionally or optionally, DBI controller 110 can provide the generated internal DBI information to memory device 200 via internal DBI port IDBI of host 100. Control logic 210 of memory device 200, which receives the provided internal DBI information, uses the internal DBI information when encoding data provided to memory 260, and can provide internal DBI information sent from host 100 to memory 260 to enable decoding of data received from memory 260.

[0050] In some example embodiments, although the data parallelization information 212 stored in the memory device 200 may include information about a method for converting the sub-data of the first arrangement described above into sub-data of the second arrangement, some example embodiments are not limited thereto.

[0051] The DBI controller 110 of host 100 may receive data parallelization information 212 provided from memory device 200 (e.g., may receive data parallelization information 212), and may generate internal DBI information by referring to the provided data parallelization information 212 and a table stored in mode register group 120. In the following text, reference will be made to... Figure 2 Provide more specific details.

[0052] Figure 2 Is it showing stored Figure 1 A diagram showing the tables in the mode register group.

[0053] Reference Figure 2 The mode register group 120 may store a table 122 that defines the DBI scheme according to the data parallelization system. Specifically, table 122 may include different internal DBI schemes for each data mapping case. For example, if from a memory device ( Figure 1 The memory device provided by (200) Figure 1 The internal data parallelization system of (200) is the first case (Case 1), then the DBI controller ( Figure 1 110) uses the first scheme (scheme 1) to generate internal DBI information, and if from the memory device ( Figure 1 The memory device provided by (200) Figure 1 The internal data parallelization system of (200) is the second case (case 2), then the DBI controller (Figure 1 (110) can use the second scheme (Scheme 2) to generate internal DBI information.

[0054] In some example embodiments, the DBI controller ( Figure 1 110) can be, for example, transmitted via software according to a memory device (e.g., Figure 1 The internal data parallelization system of the memory device 200 determines the internal DBI scheme. Optionally or additionally, in some example embodiments, the DBI controller (e.g., Figure 1 The DBI controller 110 may, for example, use hardware (such as fuses and / or antifuses) according to the memory device ( Figure 3 to 10 The internal data parallelization system of 200) is used to determine the internal DBI scheme.

[0055] In this way, when the electronic device 1 according to the example embodiment stores data in the memory 260, the data storage time can be reduced because the control logic 210 of the memory device 200 receives and uses pre-calculated internal DBI information from the host 100 without using its own internal DBI operations required / used for encoding the data.

[0056] In the following text, reference will be made to Figure 3 The present invention describes a method for storing data in an electronic device according to some example embodiments.

[0057] Figures 4 to 10 This is a flowchart illustrating a method for storing data in an electronic device according to some example embodiments. Figure 3 This is a diagram illustrating a method for storing data in an electronic device according to some example embodiments.

[0058] First, refer to Figure 4 Send information about the data parallelization system (S100).

[0059] For example, refer to Figure 3 When the memory device 200 is started, the memory device 200 may send information about the data parallelization system to the host 100. However, embodiments are not limited to this; alternatively or additionally, the memory device 200 may provide information about the data parallelization system to the host 100 at different times other than the start-up time.

[0060] Refer again Figure 5 Based on the data parallelization system, the DBI scheme (S200) is selected.

[0061] Figure 5is a diagram illustrating an example of a data parallelization system. Hereinafter, a method for storing data in an electronic device according to the technical idea of example embodiments will be described as an example in which an electronic device operates in the data parallelization system shown in Figure 5 for illustrative purposes, and example embodiments are not specifically limited to Figure 1 the specific arrangement of

[0062] Referring to Figure 5 and Figure 5 , the data can include, for example, a plurality of consecutive sub-data D0 to D7. Here, the sub-data D0 can be output from the host 100 earlier (at an earlier time than) than the sub-data D1, and the sub-data D1 can be output from the host 100 earlier (at an earlier time than) than the sub-data D2.

[0063] In some example embodiments, the data can be provided from the host 100 to the memory device 200, for example, on a byte basis. In this case, the sub-data D0 to D7 can be sub-components of the data constituted / corresponding to the data on a byte basis. Also, in some example embodiments, although one sub-data (e.g., D0) can define a unit burst length, example embodiments are not limited thereto.

[0064] The host 100 sequentially outputs the sub-data D0 to D7 encoded according to the external DBI information through each of the output ports DQ0 to DQ7, and the memory device 200 can receive the sub-data D0 to D7 sequentially output from the host 100 through the input ports DQ0 to DQ7.

[0065] On the other hand, the control logic 210 of the memory device 200 decodes the received sub-data D0 to D7 according to the external DBI information, and can encode the decoded data according to the internal DBI information provided from the host 100.

[0066] Optionally or additionally, the control logic 210 of the memory device 200 can rearrange the encoded data according to the internal data parallelization system, and provide the rearranged data to the input ports DQ0 to DQ7 of the memory 260. For example, the control logic 210 can parallelize the sub-data D0 to D7 received in the order of D0, D1, D2, D3, D4, D5, D6, and D7 as shown, and provide the parallelized sub-data D0 to D7 to the memory 260 as shown. That is / for example, the sub-data D0 to D7 provided from the host 100 through the input ports DQ0 to DQ7 of the memory device 200 can be rearranged by the control logic 210 according to the data parallelization information 212, and can be provided to the memory 260.

[0067] The host 100 is provided information about the data parallelization system as shown in Figure 5 The DBI controller 110 of the host 100 can select an internal DBI scheme corresponding to the data parallelization system as shown in Figure 3

[0068] Referring again to Figure 1 , the DBI information is computed (S300).

[0069] Referring back to Figure 6 , for example, the DBI controller 110 of the host 100 can perform DBI computation using the selected DBI scheme.

[0070] In some example embodiments, the DBI controller 110 can compute external DBI information for decoding data received through the input ports DQ0-DQ7 of the memory device 200 by the control logic 210. Further, the DBI controller 110 can compute internal DBI information for decoding data received through the input ports DQ0-DQ7 of the memory 260 by the memory controller 262 using the selected DBI scheme.

[0071] First, an example in which the DBI controller 110 computes external DBI information will be described with reference to Figure 1

[0072] DBI can go through the following process: first, the relationship between the data bits sent to the data bus / sent on the data bus is evaluated, and it is determined whether it is beneficial to not invert any of the data bits, some of the data bits, or all of the data bits before transmission. If it is beneficial to send the data bits in inverted state, then the DBI bit indicating that the data bits are inverted can be set high (or, alternatively, can be set low).

[0073] Referring to Figure 6 and Figure 9 , the DBI controller 110 can compute external DBI information based on whether toggling occurs between adjacent sub-data D0-D7 output through the plurality of output ports DQ0-DQ7 of the host 100. In one example, toggling between two sub-data can indicate that their values are different. For example, toggling occurs between D0 and D1 if sub-data D0 has a value of “0” and the adjacent sub-data D1 has a value of “1”, or if sub-data D0 has a value of “1” and the adjacent sub-data D1 has a value of “0”.

[0074] ​​Specifically, if the number of switches between sub-data D0 and sub-data D1 output through the multiple output ports DQ0 to DQ7 of host 100 is four or more, the DBI controller 110 may determine the external DBI bit EDBI0 constituting / corresponding to the external DBI information as high (e.g., 1). Furthermore, if the number of switches between sub-data D0 and sub-data D1 is less than four, the DBI controller 110 may determine the external DBI bit EDBI0 constituting the external DBI information as low (e.g., 0).

[0075] For example, if a switch occurs between sub-data D0 and sub-data D1 output through the output ports DQ0, DQ1, DQ2, DQ3 and DQ4 of the host 100, but no switch occurs between sub-data D0 and sub-data D1 output through the output ports DQ5, DQ6 and DQ7 of the host 100, then the DBI controller 110 can set the external DBI bit EDBI0 to 1 (high).

[0076] Similarly, if the number of switches between sub-data D4 and sub-data D5 output through the multiple output ports DQ0 to DQ7 of host 100 is 4 or more, the DBI controller 110 may set the external DBI bit EDBI4 constituting the external DBI information to 1 (high). Furthermore, if the number of switches between sub-data D4 and sub-data D5 is less than 4, the DBI controller 110 may set the external DBI bit EDBI4 constituting the external DBI information to 0 (low).

[0077] Through this processing, the DBI controller 110 can determine the external DBI bits that constitute / correspond to the external DBI information. Figure 9 EDBI0 to EDBI6). Furthermore, when using external DBI bits determined in this way ( Figure 1 When data is encoded using EDBI0 to EDBI6, the number of switching operations can be reduced during data transfer between the host 100 and the memory device 200 compared to unencoded data.

[0078] Next, refer to Figure 7 and Figure 1 The DBI controller 110 can calculate internal DBI information based on whether a switch occurs between adjacent sub-data D0 to D7 received through multiple input ports DQ0 to DQ7 of the memory 260.

[0079] Specifically, if the number of transitions occurring between the sub data D0 and the sub data D4 received through the plurality of input ports DQ0 to DQ7 of the memory 260 is four or more, the DBI controller 110 can determine the internal DBI bit IDBI0 constituting the internal DBI information to be high (e.g., 1). Also, if the number of transitions occurring between the sub data D0 and the sub data D4 is less than four, the DBI controller 110 can determine the internal DBI bit IDBI0 constituting the internal DBI information to be low (e.g., 0).

[0080] For example, if transitions occur between the sub data D0 and the sub data D4 received through the input ports DQ0, DQ1, DQ2, DQ3, and DQ4 of the memory 260, but do not occur between the sub data D0 and the sub data D4 received through the input ports DQ5, DQ6, and DQ7 of the memory 260, the DBI controller 110 can determine the internal DBI bit IDBI0 to be 1.

[0081] Next, referring to Figure 8 and Figure 9 , similarly, if the number of transitions occurring between the sub data D1 and the sub data D5 received through the plurality of input ports DQ0 to DQ7 of the memory 260 is four or more, the DBI controller 110 can determine the internal DBI bit IDBI1 constituting / corresponding to the internal DBI information to be 1. Also, if the number of transitions occurring between the sub data D1 and the sub data D5 is less than four, the DBI controller 110 can determine the internal DBI bit IDBI1 constituting / corresponding to the internal DBI information to be low (e.g., 0).

[0082] For example, if transitions occur between the sub data D1 and the sub data D5 received through the input ports DQ0, DQ1, and DQ2 of the memory 260, but do not occur between the sub data D1 and the sub data D5 received through the input ports DQ3, DQ4, DQ5, DQ6, and DQ7 of the memory 260, the DBI controller 110 can determine the internal DBI bit IDBI1 to be low (e.g., 0).

[0083] Through such processing, the DBI controller 110 can determine the internal DBI bits (IDBI0 to IDBI3) constituting / corresponding to the internal DBI information. Also, when the internal DBI bits (IDBI0 to IDBI3) determined in this manner are used, the DBI controller 110 can determine the external DBI information (DBI0 to DBI3) to be transmitted to the memory 260. Figure 9 Figure 3 ​When the data is encoded with the DBI information (IDBI0 to IDBI3), the number of toggles can be reduced in the processing of the data transfer between the control logic 210 and the memory 260 compared to the unencoded data. Although values are described as high and / or low (e.g., 1 and / or 0) as used herein, example embodiments are not limited thereto. For example, values can be described as low and / or high, respectively.

[0084] Referring again to Figure 1 The calculated DBI information and the data can be transmitted (S400).

[0085] For example, referring to Figure 9 and Figure 9 The host 100 can transmit the encoded sub data D0 to D7 using the external DBI information with the write command through the output ports DQ0 to DQ7, the external DBI information EDBI0 to EDBI6 through the external DBI port EDBI, and the internal DBI information IDBI0 to IDBI3 through the internal DBI port IDBI.

[0086] Figure 10 An example is shown as follows: the sub data D0 is transmitted at a first time t1, the sub data D1, the external DBI bit EDBI0, and the internal DBI bit IDBI0 are transmitted at a second time t2, the sub data D2, the external DBI bit EDBI1, and the internal DBI bit IDBI1 are transmitted at a third time t3, the sub data D3, the external DBI bit EDBI2, and the internal DBI bit IDBI2 are transmitted at a fourth time t4, the sub data D4, the external DBI bit EDBI3, and the internal DBI bit IDBI3 are transmitted at a fifth time t5, the sub data D5 and the external DBI bit EDBI4 are transmitted at a sixth time t6, the sub data D6 and the external DBI bit EDBI5 are transmitted at a seventh time t7, and the sub data D7 and the external DBI bit EDBI6 are transmitted at an eighth time t8. By transmitting the sub data D0 to D7, the external DBI information EDBI0 to EDBI6, and the internal DBI information IDBI0 to IDBI3 in this way, the unnecessary and / or undesired data transfer time between the host 100 and the memory device 200 can be minimized and / or reduced.

[0087] However, example embodiments are not limited thereto, and various modifications can be made to implement the transmission method. For example, referring to Figure 9 Unlike the foregoing embodiments shown in Figure 3 The host 100 can output each of the internal DBI bits IDBI0 to IDBI3 at the second time t2, the fourth time t4, the sixth time t6, and the eighth time t8. By ensuring the idle time between the transmissions of the internal DBI bits IDBI0 to IDBI3 in this way, additional information can be provided from the host 100 to the memory device 200 as needed.

[0088] Referring again to Figure 1 , the received data is decoded using the provided DBI information, and the decoded data is stored (S500).

[0089] For example, referring to Figure 6 , first, the control logic 210 can decode the data provided from the host 100 using the external DBI information. Additionally or alternatively, the control logic 210 can encode the decoded data according to the internal DBI information provided from the host 100.

[0090] Further, the control logic 210 can rearrange the encoded data according to the data parallelization information 212, and can provide the rearranged data to the memory 260 through the plurality of reception ports DQ0 to DQ7 of the memory 260.

[0091] Further, the control logic 210 can provide the internal DBI information provided from the host 100 to the memory 260 through the internal DBI port IDBI of the memory 260.

[0092] The memory controller 262 of the memory 260 can decode the data received through the plurality of reception ports DQ0 to DQ7 of the memory 260 using the internal DBI information provided from the host 100, and can store the decoded data in the memory cell array 264.

[0093] On the other hand, although Figure 11 an example in which the external DBI information is calculated based on whether switching occurs between adjacent sub data D0 to D7 output through the plurality of output ports DQ0 to DQ7 of the host 100 is described, example embodiments are not limited thereto.

[0094] Hereinafter, a method for storing data in an electronic device according to some other embodiments will be described with reference to Figure 12 and Figure 11 .

[0095] Figure 12 and Figure 1 are diagrams for explaining a method for storing data in an electronic device according to some example embodiments.

[0096] Referring to Figure 11 and Figure 12 , the DBI controller 110 can calculate the external DBI information according to a Hamming weight (e.g., the number of sub data D0 having a value 1 (e.g., a high value) among the sub data D0 output through the plurality of output ports DQ0 to DQ7 of the host 100).

[0097] Specifically, if the Hamming weight (e.g., the number of sub data D0 having a value of 1 among the sub data D0 output through the plurality of output ports DQ0 to DQ7 of the host 100) is greater than or equal to a threshold value (e.g., 4 or more), the DBI controller 110 can determine the external DBI bit EDBI0 constituting / corresponding to the external DBI information as a high value (e.g., 1). Also, if the Hamming weight (e.g., the number of sub data D0 having a value of 1) is less than the threshold value (e.g., less than 4), the DBI controller 110 can determine the external DBI bit EDBI0 constituting / corresponding to the DBI information as a low value (e.g., 0).

[0098] For example, if the sub data D0 output through the output ports DQ0, DQ1, DQ2, DQ3, and DQ4 of the host 100 have a value of 1, but the sub data D0 output through the output ports DQ5, DQ6, and DQ7 have a value of 0, the DBI controller 110 can determine the external DBI bit EDBI0 as 1.

[0099] Similarly, if the number of sub data D4 having a value of 1 among the sub data D4 output through the plurality of output ports DQ0 to DQ7 of the host 100 is greater than a threshold value (such as 4 or more), the DBI controller 110 can determine the external DBI bit EDBI4 constituting the external DBI information as 1. Also, if the number of sub data D4 having a value of 1 is less than the threshold value (such as 4), the DBI controller 110 can determine the external DBI bit EDBI4 constituting the external DBI as 0.

[0100] Through such a process, the DBI controller 110 can determine the external DBI bits EDBI0 to EDBI7 constituting / corresponding to the external DBI information. Figure 1

[0101] Next, referring to Figure 12 and Figure 13 ​In this case, the host 100 can transmit the sub data D0, the external DBI bit EDBIO, and the internal DBI bit IDBIO at a first time t1, the sub data D1, the external DBI bit EDBI1, and the internal DBI bit IDBI1 at a second time t2, the sub data D2, the external DBI bit EDBI2, and the internal DBI bit IDBI2 at a third time t3, the sub data D3, the external DBI bit EDBI3, and the internal DBI bit IDBI3 at a fourth time t4, the sub data D4 and the external DBI bit EDBI4 at a fifth time t5, the sub data D5 and the external DBI bit EDBI5 at a sixth time t6, the sub data D6 and the external DBI bit EDBI6 at a seventh time t7, and the sub data D7 and the external DBI bit EDBI7 at an eighth time t8. By transmitting the sub data D0 to D7, the external DBI information EDBIO to EDBI7, and the internal DBI information IDBIO to IDBI3 in this way, it is possible to minimize and / or reduce unnecessary / undesirable data transmission time between the host 100 and the memory device 200, and to secure a free time in which additional information can be transmitted through the internal DBI port IDBI.

[0102] Figure 14 is a block diagram of an electronic device according to some example embodiments. Figure 13 is a diagram for explaining Figure 13 the operation of the electronic device shown in

[0103] Referring to Figure 1 , the electronic device 2 includes a host 300 and a memory device 400.

[0104] The memory device 400 can include a plurality of input ports DQ0 to DQ7, an internal DBI port IDBI, a control logic 410, and a memory 460.

[0105] The control logic 410 can include data parallelization information 412. The memory 460 can include a plurality of input ports DQ0 to DQ7, an internal DBI port IDBI, a memory controller 462, and a memory cell array (MCA) 464.

[0106] The host 300 can include a plurality of output ports DQ0 to DQ7, an internal DBI port IDBI, a DBI controller 310, and a mode register set (MRS) 320.

[0107] That is, in some example embodiments, unlike the above-described embodiments, there is no external DBI port (EDBI) in the host 300 and the memory device 400. Accordingly, the external DBI information can be transmitted through the internal DBI port (IDBI) other than the external DBI port (EDBI). Figure 1 Figure 14 ​ports other than the EDBI) from the host 100 to the memory device 200.

[0108] In some example embodiments, as shown in Figure 15 The external DBI information can be provided to the memory device 200 through the plurality of output ports DQ0 to DQ7 of the host. At this time, the plurality of external DBI bits EDBI0 to EDBI7 constituting the external DBI information can be determined according to the number of sub data D0 to D7 having a value of 1 among the sub data D0 to D7 output from each of the output ports DQ0 to DQ7.

[0109] Specifically, if the Hamming weight (e.g., the number of sub data D0 to D7 having a value of 1 among the sub data D0 to D7 output through the output port DQ0 of the host 100) is greater than a threshold value (such as 4 or more), the DBI controller 310 can determine the external DBI bit EDBI0 constituting / corresponding to the external DBI information as 1. Also, if the Hamming weight (e.g., the number of sub data D0 to D7 having a value of 1) is less than the threshold value (such as less than 4), the DBI controller 310 can determine the external DBI bit EDBI0 constituting the external DBI information as 0.

[0110] For example, if the sub data D0 and D2 among the sub data D0 to D7 output through the output port DQ0 have a value of 1, but the sub data D1 and D3 to D7 have a value of 0, the DBI controller 310 can determine the external DBI bit EDBI0 as 0. Also, if the sub data D0 to D6 among the sub data D0 to D7 output through the output port DQ1 have a value of 1, but the sub data D7 has a value of 0, the DBI controller 310 can determine the external DBI bit EDBI1 as 1.

[0111] As shown, the external DBI bits EDBI0 to EDBI7 thus determined can be provided to the memory device 200 through the plurality of output ports DQ0 to DQ7 of the host to be continuous with the sub data encoded using the external DBI information.

[0112] In the case of the electronic device 2 according to some example embodiments, by reducing the number of input ports and output ports of the host 300 and the memory device 400 in this way, the size of the electronic device 2 can be reduced and / or miniaturized.

[0113] Figure 15 is a block diagram of an electronic device according to some example embodiments. Hereinafter, a repeated explanation of the above-described embodiments will not be provided, and a difference will be mainly explained.

[0114] Referring to Figure 16 , the electronic device 3 includes a host 500 and a memory device 600.

[0115] The memory device 600 can include a plurality of input ports DQ0 to DQ7, a universal DBI port UDBI, control logic 610, and a memory 660.

[0116] The control logic 610 can include data parallelization information 612. The memory 660 can include a plurality of input ports DQ0 to DQ7, a universal DBI port UDBI, a memory controller 662, and a memory cell array (MCA) 664.

[0117] The host 500 can include a plurality of output ports DQ0 to DQ7, a universal DBI port UDBI, a DBI controller 510, and a mode register set (MRS) 520.

[0118] In some example embodiments, the DBI controller 510 can receive the data parallelization information 612 (e.g., can receive a provision of the data parallelization information 612), and can output, through the universal DBI port UDBI of the host 500, universal DBI information that takes into account all of the above-mentioned external DBI information and internal DBI information. Further, the DBI controller 510 can output data encoded using the universal DBI information through the plurality of output ports DQ0 to DQ7 of the host 500.

[0119] The memory controller 662 of the memory device 600 can receive universal DBI information from the host 100 (e.g., can receive a provision of the universal DBI information from the host 100), and can decode data received through the plurality of input ports DQ0 to DQ7 of the memory device 600. Further, the memory controller 662 of the memory 660 also receives such universal DBI information, and can decode data received through the plurality of input ports DQ0 to DQ7 of the memory 660.

[0120] In the case of the electronic device 3 according to some example embodiments, by integrating DBI information for decoding data without distinguishing between internal DBI information and external DBI information as described above, the efficiency of data storage operations of the electronic device 3 can be improved.

[0121] Figure 1 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) of the aforementioned electronic device Figure 1 (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260) can employ the memory 860 illustrated in Figure 16 Figure 16 is a diagram illustrating an example of a memory included in an electronic device according to some example embodiments.

[0122] In the memory (260 of 1, Figure 13 2 of 260, and Figure 15 3 of 260

[0123] Reference Figure 16 The memory 860 may include multiple stacked memory layers 810, 820, 830, and 840. The memory 860 may be, for example, HBM. The memory layers 810, 820, 830, and 840 may form / correspond to multiple independent interfaces referred to as channels.

[0124] Each of memory layers 810, 820, 830, and 840 may include two channels 811 to 812, 821 to 822, 831 to 832, and 841 to 842. Although Figure 1 An example is shown where four memory layers 810, 820, 830, and 840 are stacked on memory 860 and configured with eight channels; however, some example embodiments are not limited to this. According to some example embodiments, two to eight memory layers may be stacked on memory 860.

[0125] Each of channels 811, 812, 821, 822, 831, 832, 841, and 842 may include a memory cell array 843 that operates independently for each channel, an I / O control unit 844 for controlling the memory cell array 843 independently for each channel, and a channel pad (or “soldering pad”) unit 845 that provides channels for the memory cell array 843.

[0126] In some example embodiments, the I / O control unit 844 can be used as the aforementioned memory controller ( Figure 13 262, Figure 15 462 and Figure 1 (662).

[0127] The memory cell array 843 includes memory cells connected to multiple word lines and bit lines, and the memory cells can be grouped into multiple memory banks and / or memory blocks. Row decoders, column decoders, sense amplifiers, etc., for accessing the memory cells can be disposed in areas of the memory cell array 843.

[0128] The I / O control unit 844 may include row address strobing (RAS) control logic, column address strobing (CAS) control logic, etc. The channel pad unit 845 may include pads arranged in a matrix format comprising multiple rows and multiple columns. Each pad in the channel pad unit 845 may be connected to an electrode 848 and a through-silicon via (TSV, also known as a through-silicon via) 870 via wiring for signal routing.

[0129] The memory 860 can further include a memory buffer 850 disposed at a lower end of the stacked memory layers 810, 820, 830, and 840. The memory buffer 850 can include input buffers (or receiving units) for receiving commands, addresses, clocks, and data from the control logic, can buffer the received commands, addresses, clocks, and data, and provide the received commands, addresses, clocks, and data to the channels 811, 812, 821, 822, 831, 832, 841, and 842. The memory buffer 850 can provide a signal distribution function and a data I / O function to the channels 811, 812, 821, 822, 831, 832, 841, and 842 through the electrode 848 and the through-silicon via 870. In some other embodiments, the memory buffer 850 can function as the aforementioned memory controller (260 of FIG. 2, Figure 13 (462 of FIG. 4, and Figure 15 (662 of FIG. 6). Figure 1

[0130] The memory buffer 850 can communicate with the control logic through a conductive device (such as a bump or a solder ball) formed on an outer surface of the memory 860.

[0131] Each of the memory layers 810, 820, 830, and 840 includes two channels 811, 812, 821, 822, 831, 832, 841, and 842, and a single channel can be composed of two pseudo channels.

[0132] Assuming that the number of data I / O DQ pads included in the channel pad unit 845 of each channel 811, 812, 821, 822, 831, 832, 841, and 842 is, for example, 128, the one hundred twenty-eight DQ pads of the channel pad unit 845 of each channel 811, 812, 821, 822, 831, 832, 841, and 842 are divided into two groups of pseudo channels 846 and 847, and the number of DQ pads of each of the pseudo channels 846 and 847 can be 64. Here, each of the channels 811, 812, 821, 822, 831, 832, 841, and 842 can receive provision of data through eight DQ pads. The eight DQ pads can correspond to the plurality of input ports (DQ0 to DQ7 of FIG. 2, Figure 13 (460 of FIG. 4, and Figure 15 (660 of FIG. 6). Figure 1 (DQ0 to DQ7 of FIG. 2, Figure 13 (DQ0 to DQ7 of FIG. 4, and Figure 15 (DQ0 to DQ7 of FIG. 6). ​

[0133] ​​The elements described herein, such as but not limited to DBI controller 110, MRS 120, control logic 210, memory controller 262, can include processing circuitry, such as hardware including logic circuitry, hardware / software combinations, such as a processor executing software, or combinations thereof. For example, processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0134] At the conclusion of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the example embodiments described herein without departing from the spirit and scope of the example embodiments. Therefore, the example embodiments of the present application disclosed are meant to be taken in a generic and descriptive sense, and not for purposes of limitation.

Claims

1. An electronic device comprising: a host configured to output data; and a memory device comprising a memory storage configured to receive and store data, wherein the host is configured to generate data bus inversion information about the data to be provided to the memory device according to information about a data parallelization system internal to the memory device, and provide the data bus inversion information to the memory device, and the memory device is configured to provide data output from the host encoded according to the data bus inversion information to the memory storage according to the data parallelization system. 2.The electronic device of claim 1, wherein, the data bus inversion information generated by the host comprises: first data bus inversion information related to the data to be provided to the memory device; and second data bus inversion information related to the data to be provided to the memory storage, the host is configured to provide the data and the first data bus inversion information to the memory device, the data being encoded using the first data bus inversion information, the memory device is configured to decode the data provided from the host based on the first data bus inversion information, the memory device is configured to provide the second data bus inversion information to the memory storage, the memory device is configured to provide data encoded using the second data bus inversion information to the memory storage according to the data parallelization system, and the memory storage is configured to decode the data provided from the memory device using the second data bus inversion information. 3.The electronic device of claim 2, wherein, the memory device is configured to provide the second data bus inversion information provided from the host to the memory storage without calculating the second data bus inversion information. 4.The electronic device of claim 1, wherein the memory device is configured to store the information about the data parallelization system, and the host is configured to store a table defining a data bus inversion scheme according to the data parallelization system. 5.The electronic device of claim 4, wherein, the memory device is configured to provide the information about the data parallelization system to the host at a start of the memory device, and the host is configured to determine the data bus inversion scheme based on the information about the data parallelization system, generate the data bus inversion information using the determined data bus inversion scheme, and provide the data bus inversion information and the data encoded with the data bus inversion information to the memory device. 6.The electronic apparatus according to any one of claims 1 to 5, wherein the host comprises a first external data bus inversion port and a first internal data bus inversion port, the memory device comprises a second external data bus inversion port configured to receive external data bus inversion bits from the host through the first external data bus inversion port, and a second internal data bus inversion port configured to receive internal data bus inversion bits from the host through the first internal data bus inversion port, and the memory storage comprises a third internal data bus inversion port configured to receive internal data bus inversion bits from the memory device through the second internal data bus inversion port. 7.The electronic device of claim 6, wherein the host comprises a first output port, the first output port comprises a first data output port to an eighth data output port, The data includes consecutive first and second sub-data output through each of the first to eighth data output ports, and The host is configured to determine the external data bus inversion bit according to the number of switches that occur between the first and second sub-data. 8.The electronic device of claim 6, wherein The host includes a first output port, The first output port includes first to eighth data output ports, The data includes consecutive first to eighth sub-data output through each of the first to eighth data output ports, and The host is configured to determine the internal data bus inversion bit based on whether a switch occurs between one of the first to eighth sub-data and another sub-data that is not consecutive to the one. 9.The electronic device of any one of claims 1 to 5, wherein, The host includes a first internal data bus inversion port, The memory device includes a second internal data bus inversion port configured to receive the internal data bus inversion bit from the host through the first internal data bus inversion port, The memory storage device includes a third internal data bus inversion port configured to receive the internal data bus inversion bit from the memory device through the second internal data bus inversion port, and The host is configured to provide the external data bus inversion bit to the memory device through a first output port of the host from which the host outputs data. 10.The electronic device of claim 9, wherein The first output port includes first to eighth data output ports, The data includes consecutive first to eighth sub-data output through each of the first to eighth data output ports, and The host is configured to determine the external data bus inversion bit according to the number of sub-data having a specific value among the first to any of the sub-data. 11.The electronic device of claim 10, wherein The host is configured to determine the internal data bus inversion bit based on whether a switch occurs between one of the first to eighth sub-data and another sub-data that is not consecutive to the one.

12. A method of storing data, comprising: providing, by a memory device, information about a data parallelization system to a host, the information being internal to the memory device; calculating, by the host, an external data bus inversion bit based on data to be provided to the memory device; providing, by the host, the external data bus inversion bit to the memory device; encoding, by the host, data to be stored in the memory device using the external data bus inversion bit; providing, by the host, the encoded data to the memory device; calculating, by the host, an internal data bus inversion bit based on the data provided to the memory device and the information about the data parallelization system provided from the memory device; and providing, by the host, the internal data bus inversion bit to the memory device. The host includes first, second, and third output ports from which data is output, an external data bus inversion bit is output, and an internal data bus inversion bit is output, respectively, and 13. The method of claim 12, wherein, Each of the first to third output ports is different. ​ 14. The method of claim 13, wherein, The data include consecutive first to eighth sub-data, and The host provides the external data bus inversion bit and the internal data bus inversion bit to the memory device while providing the first to eighth sub-data from the host to the memory device.

15. The method of claim 12, wherein, The host includes a first output port and a second output port, outputs the data and the external data bus inversion bit from the first output port, and outputs the internal data bus inversion bit from the second output port, and The first output port and the second output port are different from each other.

16. The method of any one of claims 12 to 15, wherein, The memory device includes a memory storage configured to store data, The memory device decodes the data provided from the host using the external data bus inversion bit, and The memory storage decodes the data provided from the memory device using the internal data bus inversion bit.

17. The method of any one of claims 12 to 15, wherein, The memory device provides information about the data parallelization system to the host at a time when the memory device is activated.

18. The method of claim 17, wherein, The host includes a mode register set storing a table defining a plurality of internal data bus inversion schemes, and The host selects at least one of the plurality of internal data bus inversion schemes using the information about the data parallelization system provided from the memory device, and calculates the internal data bus inversion bit using the selected internal data bus inversion scheme. 19.A memory device, comprising: a memory storage configured to store data provided through a first input port; and control logic configured to receive data from an external through a second input port, rearrange the data provided through the second input port according to a data parallelization system, and provide the data to the memory storage through the first input port, wherein the control logic is configured to receive an internal data bus inversion bit of the data from the external, encode the data using the internal data bus inversion bit, and provide the encoded data and the internal data bus inversion bit to the memory storage, the internal data bus inversion bit being generated based on information about the data parallelization system.

20. The memory device of claim 19, wherein, The data provided through the second input port include consecutive first to eighth sub-data, and The internal data bus inversion bit corresponds to whether a switch occurs between one sub-data among the first to eighth sub-data and another sub-data that is not consecutive to the one sub-data.

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