Semiconductor memory devices

Abstract

A semiconductor memory device is provided. To allow for the dense integration of a large number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump uses capacitors. The capacitors are implemented relative to the dense integration. Some components are placed below the stacked word lines, and some components are not placed below the stacked word lines. The capacitance of the capacitors not placed below the stacked word lines is partially provided by a parallel structure.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0169839, filed on December 18, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor memory device. Background Technology

[0003] To improve the integration density of multi-layered memory devices, the number of word lines stacked vertically within the memory device is being increased. Operating a vertically stacked memory device requires a high current to simultaneously apply a constant operating voltage to charge pumps on multiple word lines. As the number of stacked word lines increases, the size of the charge pump also increases. Furthermore, when the charge pump is buried under the memory cell array within the memory device, not all components of the charge pump can be buried beneath the memory cell array. Because some components of the charge pump cannot be buried under the memory cell array, the chip size of the memory device increases. Summary of the Invention

[0004] Various aspects of this disclosure provide a semiconductor memory device including a capacitor disposed in an amplification stage not buried under a memory cell array and having high area efficiency.

[0005] Various aspects of this disclosure also provide a semiconductor memory device including a charge pump, in which some amplification stages are driven at a high frequency.

[0006] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of the disclosure.

[0007] A semiconductor memory device is provided herein, the semiconductor memory device comprising: a substrate including a first region and a second region; a first lower wiring disposed in the first region of the substrate; a second lower wiring disposed in the second region of the substrate; a stacked structure disposed on the first lower wiring, and the stacked structure including interlayer insulating films and electrode pads alternately stacked in a direction perpendicular to the substrate; a vertical structure penetrating the stacked structure; a tunnel insulating layer extending along a sidewall of the vertical structure; a charge storage layer extending along a sidewall of the tunnel insulating layer; a plurality of through vias disposed on the second lower wiring, wherein the plurality of through vias are configured to electrically connect the second lower wiring and an upper wiring disposed in the second region; a first amplification stage including the first lower wiring and configured to generate a first operating voltage applied to the electrode pads; and a second amplification stage including the second lower wiring and the plurality of through vias, electrically connected to the first amplification stage and configured to generate a second operating voltage applied to the electrode pads.

[0008] A semiconductor memory device is also provided, the semiconductor memory device comprising: a memory cell array electrically connected to a plurality of word lines and electrically connected to a plurality of bit lines, wherein the memory cell array includes a plurality of memory cells stacked perpendicularly to a substrate; and a charge pump configured to generate an operating voltage applied to the plurality of word lines to operate the plurality of memory cells, wherein the charge pump includes a first amplification stage and a second amplification stage, the first amplification stage and the second amplification stage being configured to generate the operating voltage, the first amplification stage being driven by a first regulator configured to generate a first clock signal, the second amplification stage being driven by a second regulator configured to generate a second clock signal having a second frequency higher than a first frequency of the first clock signal, the first amplification stage being disposed below and stacked perpendicularly to the memory cell array, and the second amplification stage being disposed below but not stacked perpendicularly to the memory cell array.

[0009] Another semiconductor memory device is also provided, comprising: a memory cell array electrically connected to a plurality of word lines and electrically connected to a plurality of bit lines, the memory cell array including a plurality of memory cells vertically stacked from a substrate, wherein the plurality of memory cells includes a first planar memory cell and a second planar memory cell disposed on the substrate and disposed non-perpendicularly to each other; a first amplification stage disposed below and vertically stacked on the first planar memory cells, wherein the first amplification stage is configured to generate a first operating voltage applied to the plurality of word lines to operate the first planar memory cells; and a second amplification stage disposed below and vertically stacked on the second planar memory cells, wherein the second amplification stage is configured to generate a first operating voltage applied to the plurality of word lines to operate the first planar memory cells; and a second amplification stage disposed below and vertically stacked on the second planar memory cells, wherein the second amplification stage is configured to generate a first operating voltage applied to the plurality of word lines to operate the first planar memory cells. A second operating voltage is applied to the plurality of word lines to operate the second planar memory cell; and a common amplification stage is disposed below but not perpendicular to the memory cell array and disposed on a substrate, wherein the common amplification stage is configured to generate a third operating voltage applied to the plurality of word lines to operate the first planar memory cell and the second planar memory cell, wherein the first amplification stage includes a first lower wiring electrically connected to the memory cell array, the second amplification stage includes a second lower wiring electrically connected to the memory cell array, the common amplification stage includes a common lower wiring electrically connected to the memory cell array and a plurality of through vias electrically connecting the common lower wiring and an upper wiring configured to be higher than the memory cell array, and the common amplification stage is connected in series to each of the first amplification stage and the second amplification stage. Attached Figure Description

[0010] These and / or other aspects will become clearer and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a semiconductor memory device according to some embodiments;

[0012] Figure 2 It is a circuit diagram of one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments;

[0013] Figure 3 This is a block diagram of a voltage generator included in a semiconductor memory device according to some embodiments;

[0014] Figure 4A and Figure 4B This is a circuit diagram of a charge pump included in a voltage generator according to some embodiments;

[0015] Figure 5 This is a schematic perspective view of a semiconductor memory device according to some embodiments;

[0016] Figure 6 This is a planar block diagram of a semiconductor memory device including peripheral logic structures according to some embodiments;

[0017] Figure 7 yes Figure 5 A planar diagram of the cell array structure;

[0018] Figure 8 It is along Figure 6 A sectional view taken by line A-A';

[0019] Figure 9 yes Figure 8 A magnified view of part P;

[0020] Figure 10 It is along Figure 7 A sectional view taken by line B-B';

[0021] Figure 11A It shows Figure 8 Wiring and capacitors;

[0022] Figure 11B It is used to describe Figure 11A A magnified view of the k-th transistor capacitor;

[0023] Figure 12 This is a circuit diagram of a capacitor for a charge pump according to some embodiments;

[0024] Figure 13 This is a block diagram of a semiconductor memory device according to some embodiments;

[0025] Figure 14 These are schematic perspective views of a semiconductor memory device according to some embodiments; and

[0026] Figure 15 It is a planar block diagram of a peripheral logic structure included in a semiconductor memory device according to some embodiments. Detailed Implementation

[0027] In the following description, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0028] Figure 1 This is a block diagram of a semiconductor memory device 10 according to an embodiment.

[0029] Reference Figure 1 The semiconductor memory device 10 according to the embodiment may include a memory cell array 20 and peripheral circuitry 30.

[0030] The memory cell array 20 may include multiple memory cell blocks BLK1 to BLKn (where n is an integer greater than 1). Each of the memory cell blocks BLK1 to BLKn may include multiple memory cells. The memory cell blocks BLK1 to BLKn may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, at least one string select line SSL, and at least one ground select line GSL.

[0031] Specifically, memory cell blocks BLK1 to BLKn can be connected to the row decoder 33 via word line WL, at least one string select line SSL, and at least one ground select line GSL. Furthermore, memory cell blocks BLK1 to BLKn can be connected to the page buffer 35 via bit line BL.

[0032] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from outside the semiconductor memory device 10, and send and receive data DATA from devices located outside the semiconductor memory device 10. Peripheral circuitry 30 may include control logic 37, a row decoder 33, a page buffer 35, and a voltage generator 38 for generating various voltages required for operation.

[0033] Although not shown, the peripheral circuit 30 may also include various sub-circuits, such as input / output circuits and error correction circuits for correcting errors in data DATA read from the memory cell array 20 of the semiconductor memory device 10.

[0034] Control logic 37 can be connected to line decoder 33, voltage generator 38, and input / output circuitry. Control logic 37 can control the overall operation of semiconductor memory device 10. In response to control signal CTRL, control logic 37 can generate various internal control signals used in semiconductor memory device 10.

[0035] For example, control logic 37 can adjust the levels of the voltages supplied to the word line WL and bit line BL during memory operations (such as programming or erasing operations).

[0036] The row decoder 33 can select at least one of the memory cell blocks BLK1 to BLKn in response to the address ADDR, and select at least one word line WL, at least one serial select line SSL, and at least one ground select line GSL of the selected memory cell block. The row decoder 33 can apply a voltage for performing memory operations to the word line WL of the selected memory cell block.

[0037] Page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can operate as a write driver or a sense amplifier. Specifically, during programming operations, page buffer 35 can operate as a write driver and apply a voltage corresponding to the data DATA to be stored in memory cell array 20 to bit line BL. During read operations, page buffer 35 can operate as a sense amplifier and read the data DATA stored in memory cell array 20.

[0038] Figure 2 This is a circuit diagram of one of the memory cell blocks BLK1 to BLKn in the semiconductor memory device 10 according to an embodiment.

[0039] Reference Figure 2 According to the embodiment, the memory cell block may include a common source line CSL, multiple bit lines BL (BL0 to BL2), and multiple cell strings CSTR disposed between the common source line CSL and the bit lines BL (BL0 to BL2).

[0040] The cell string CSTR can be connected in parallel to each of the bit lines BL0 to BL2. The cell strings CSTR can also be connected together to the common source line CSL. That is, the cell string CSTR can be positioned between a common source line CSL and the bit lines BL0 to BL2. Multiple common source lines CSL can also be configured, and they can be arranged in two dimensions. In this case, the same electrically identical voltage can be applied to the common source line CSL, or each common source line CSL can be electrically controlled.

[0041] For example, each cell string CSTR can consist of series-connected string select transistors SST1 and SST2, series-connected memory cells MCT, and ground select transistor GST. Furthermore, each memory cell MCT includes a data storage element.

[0042] In the example, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series. The second string select transistor SST2 may be connected to one of the bit lines BL0 to BL2, and the ground select transistor GST may be connected to the common source line CSL. The memory cell MCT may be connected in series between the first string select transistor SST1 and the ground select transistor GST.

[0043] Furthermore, each cell string CSTR may also include a dummy cell DMC connected between the first string select transistor SST1 and the memory cell MCT. Although not shown in the figures, the dummy cell DMC may also be connected between the ground select transistor GST and the memory cell MCT. In another example, in each cell string CSTR, the ground select transistor GST, like the first string select transistor SST1 and the second string select transistor SST2, may consist of a plurality of metal-oxide-semiconductor (MOS) transistors connected in series. In yet another example, each cell string CSTR may include a single string select transistor.

[0044] According to an embodiment, the first string select transistor SST1 can be controlled via the first string select line SSL1, and the second string select transistor SST2 can be controlled via the second string select line SSL2. The memory cell MCT can be controlled via multiple word lines WL0 to WLn (where n is an integer greater than 0), and the dummy cell DMC can be controlled via the dummy word line DWL. Furthermore, the ground select transistor GST can be controlled via ground select lines GSL (GSL0 to GSL2). The common-source line CSL can be connected to the source of the ground select transistor GST.

[0045] A cell string (CSTR) can be composed of multiple memory cells (MCTs) located at different distances from the common-source line (CSL). Furthermore, word lines WL0 to WLn can be positioned between the common-source line (CSL) and bit lines BL0 to BL2.

[0046] The gate electrodes of a memory cell MCT located at approximately the same distance from the common-source line CSL can be commonly connected to one of the word lines WL0 to WLn, and thus can be in an equipotential state. Alternatively, even if the gate electrodes of the memory cell MCT are located at approximately the same level from the common-source line CSL, gate electrodes located in different rows or columns can be independently controlled.

[0047] Ground select lines GSL0 to GSL2 and serial select lines SSL1 and SSL2 can extend in the same direction as, for example, word lines WL0 to WLn and dummy word line DWL. Ground select lines GSL0 to GSL2 and serial select lines SSL1 and SSL2, located at approximately the same level as the common source line CSL, can be electrically isolated from each other.

[0048] Figure 3 This is a block diagram of a voltage generator 38 included in a semiconductor memory device 10 according to an embodiment. Figure 4A and Figure 4B This is a circuit diagram of a charge pump CP included in a voltage generator 38 according to some embodiments. Figure 4B yes Figure 4A The analog circuit diagram.

[0049] Reference Figure 1 , Figure 3 , Figure 4A and Figure 4B According to an embodiment, a voltage generator 38 included in a semiconductor memory device 10 may include a charge pump CP, a first regulator Reg, a first oscillator OSC, a second regulator Reg' and a second oscillator OSC', and may include a voltage source V that supplies power to the charge pump CP.

[0050] The charge pump CP can include multiple amplification stages, Stage 1 to Stage n (where n is an integer greater than 1). The charge pump CP can provide current through the row decoder 33 to apply the operating voltage to the word line WL of the memory cell array 20.

[0051] The first regulator Reg and the second regulator Reg' are separately connected to the charge pump CP, and respectively connected to the first oscillator OSC and the second oscillator OSC'. The oscillators OSC and OSC' provide constant clock signals to the regulators Reg and Reg', respectively. The clock signals provided by the first oscillator OSC and the second oscillator OSC' may be different or the same in frequency.

[0052] According to an embodiment, the first regulator Reg of the semiconductor memory device 10 can generate a clock signal received from the first oscillator OSC based on the feedback of the voltage applied to the nodes (not shown) between the amplification stages Stage 1 to Stage n in the charge pump CP and the control signal CTRL of the control logic 37, and provide the clock signal to the charge pump CP.

[0053] According to an embodiment, the second regulator Reg' of the semiconductor memory device 10 can generate a clock signal received from the second oscillator OSC' based on the feedback of the voltage applied to the word line WL by the row decoder 33 and the control signal CTRL of the control logic 37, and provide the clock signal to the charge pump CP.

[0054] In other words, the first regulator Reg can provide a first clock signal to the charge pump CP based on the signal of the first oscillator OSC, and the second regulator Reg' can provide a second clock signal to the charge pump CP based on the signal of the second oscillator OSC'.

[0055] According to an embodiment, the amplification stages Stage 1 to Stage n in the charge pump CP can be connected to different regulators. Figure 4A and Figure 4BThe first amplification stage 1 to the kth amplification stage k can be connected to the first regulator Reg, and the (k+1)th amplification stage k+1 to the nth amplification stage n can be connected to the second regulator Reg' (here, k is an integer greater than 1 and less than n). The connection relationship between the charge pump CP and the regulators Reg and Reg' according to the embodiment is not limited to... Figure 4A and Figure 4B The connection relationships are shown in the figure.

[0056] Each of the amplification stages 1 through n may include a diode and a capacitor. The following description will focus on the k-th amplification stage k and its differences from the corresponding amplification stages. Obviously, the description of the k-th amplification stage k applies to the other amplification stages.

[0057] The k-th amplification stage k may include the k-1 diode Dk-1, the k-2 diode Dk-2, the k-1 capacitor Ck-1, and the k-2 capacitor Ck-2.

[0058] The k_1 diode Dk_1 and the k_2 diode Dk_2 can each include the k_1 transistor Mk_1 and the k_2 transistor Mk_2, respectively. The gate of each of the k_1 transistor Mk_1 and the k_2 transistor Mk_2 can be connected to the source / drain of each other (e.g., the gate of the k_1 transistor Mk_1 can be connected to the source / drain between the k_1 transistor Mk_1 and the k_2 transistor Mk_2, and the gate of the k_2 transistor Mk_2 can be connected to the source / drain between the k_2 transistor Mk_2 and the (k+1)th transistor Mk+1_1 of the (k+1)th amplification stage). The kth amplification stage k can include, for example... Figure 4B The structure of the Dickson charge pump shown in the figure can be P-type transistors, where the k_1 transistor Mk_1 and the k_2 transistor Mk_2 can be P-type transistors, but the structure and configuration do not limit the technical spirit of this disclosure.

[0059] The k_1 diode Dk_1 can be connected between the (k-1)th amplification stage (not shown except for k=2) and the k_2nd diode Dk_2, and the k_2nd diode Dk_2 can be connected between the k_1 diode Dk_1 and the k+1th amplification stage (not shown except for k=n-1).

[0060] The k_1 capacitor Ck_1 has one end connected between the k_1 diode Dk_1 and the k_2 diode Dk_2, and the other end connected to the first regulator Reg. The k_2 capacitor Ck_2 may have one end connected between the k_2 diode Dk_2 and the (k+1)th amplification stage k+1, and the other end connected to an inverter that inverts the signal of the first regulator Reg. In an exemplary embodiment, the inverter may operate in an open-drain scheme. For example, as... Figure 4B As shown, the inverter may include a first inverter transistor INV_P and a second inverter transistor INV_N connected in series. One end of the first inverter transistor INV_P may be supplied with a power supply voltage VDD, and one end of the second inverter transistor INV_N may be grounded. The connection node between the first inverter transistor INV_P and the second inverter transistor INV_N may be connected to the other end of the k_2th capacitor Ck_2. The gates of the first inverter transistor INV_P and the second inverter transistor INV_N may be connected to each other and connected to a first regulator Reg to receive a first clock signal. However, the disclosed embodiments are not limited to this, and other suitable types of inverters may be used.

[0061] Except for the (k+1)th amplification stage to the nth amplification stage n, which are connected to the second regulator Reg', the first diode D1_1 connected between the voltage source V and the first diode D1_2, and the n_2 diode Dn_2 connected between the n_1 diode Dn_1 and the line decoder 33, the amplification stages excluding the kth amplification stage can have the same characteristics as... Figure 4A and Figure 4B The k-th amplification stage k shown in the diagram has the same connection relationship. However, the charge pump CP according to the embodiment is not limited to... Figure 4A and Figure 4B The configuration and connection relationships are shown in the diagram.

[0062] The charge pump CP may include multiple capacitors C1_1 to Cn_2 (where n is an integer greater than 1). Capacitors C1_1 to Cn_2 can accumulate charge, and the accumulated charge can be provided to the word line WL of the memory cell array 20 via the row decoder 33. Therefore, various voltages (such as programming voltages) can be applied to the word line WL.

[0063] Figure 5 This is a schematic perspective view of a semiconductor memory device 10 according to an embodiment. Figure 6 This is a planar block diagram of a semiconductor memory device 10 including a peripheral logic structure PS according to an embodiment. Figure 7 yes Figure 5A plan view of the cell array structure CS. Figure 8 It is along Figure 6 A sectional view taken by line A-A'. Figure 9 yes Figure 8 A magnified view of part P. Figure 10 It is along Figure 7 The sectional view taken by line B-B'.

[0064] Reference Figures 5 to 10 The semiconductor memory device 10 according to the embodiment may include a peripheral logic structure PS and a cell array structure CS.

[0065] According to the embodiment, the peripheral logic structure PS may include a first amplifier stage 1 to an nth amplifier stage Stage n, a first regulator Reg and a second regulator Reg', a first oscillator OSC and a second oscillator OSC', an analog circuit AC, a lower wiring structure 120, and an upper wiring structure 160. Furthermore, the peripheral logic structure PS may include... Figure 1 Page buffer 35 and Figure 1 Line decoder 33.

[0066] The peripheral logic structure PS may include a buried region BR that is superimposed on the cell array structure CS in a direction perpendicular to the substrate 100, a non-buried region NBR that is not superimposed on the cell array structure CS in a direction perpendicular to the substrate 100, and a portion of the upper wiring structure 160 that is not included in the non-buried region NBR but is disposed on the cell array structure CS.

[0067] The buried area BR may include a first regulator Reg, a first oscillator OSC, and so on. Figure 4A and Figure 4B The diagram shows the first amplification stages Stage 1 to Stage k connected to the first regulator Reg, and the analog circuit transistor AC_Tr included in the analog circuit AC.

[0068] Non-buried NBRs may include a second regulator Reg', a second oscillator OSC', etc. Figure 4A and Figure 4B The diagram shows the k+1th amplification stage (Stage k+1) to the nth amplification stage (Stage n) connected to the second regulator Reg', as well as the external voltage contact EVC or pad (or "soldering pad") GND.

[0069] According to an embodiment, the distance between the external voltage contact EVC or the ground mat GND and the amplification stages Stage 1 to Stage k provided in the buried area BR can be greater than the distance between the external voltage contact EVC or the ground mat GND and the amplification stages Stage k+1 to Stage n provided in the non-buried area NBR.

[0070] The cell array structure CS may include a horizontal semiconductor layer 150 disposed on the buried region BR and a stacked structure ST disposed on the horizontal semiconductor layer 150. The horizontal semiconductor layer 150 may be disposed on the buried region BR. The horizontal semiconductor layer 150 may extend along the upper surface of the buried region BR.

[0071] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be, but is not limited to, a silicon substrate or a substrate made of another material such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0072] A peripheral logic insulating layer 110 may be formed on the substrate 100. The peripheral logic insulating layer 110 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0073] The lower wiring structure 120 can be formed within the outer logic insulating layer 110. For example... Figure 8 As shown, a portion of the lower wiring structure 120 may be included in the k_2nd diode Dk_2 and the k_2nd capacitor Ck_2 disposed in the buried region BR, and in the (k+1)th diode Dk+1_1 and the (k+1)th capacitor Ck+1_1 disposed in the unburied region NBR. The above configuration and wiring will be described later.

[0074] The horizontal semiconductor layer 150 may include a lower support semiconductor layer (LSB) and a common source plate (CSP) disposed on the lower support semiconductor layer (LSB). The horizontal semiconductor layer 150 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The horizontal semiconductor layer 150 may have a crystal structure including at least one of single crystal, amorphous, and polycrystalline.

[0075] Common source plate CSP can be used as Figure 2 The common source pole line CSL.

[0076] Alternatively, unlike in the figures, the horizontal semiconductor layer 150 may be a common source plate (CSP) without a lower supporting semiconductor layer (LSB).

[0077] Alternatively, unlike in the figures, instead of a common source plate in the shape of a two-dimensional plane, a common source line in the shape of a line extending along the second direction D2 can be formed in the horizontal semiconductor layer 150.

[0078] exist Figure 7 and Figure 8 In the stacked structure ST, multiple electrode pads EP1 to EP8 may be stacked along the third direction D3. The stacked structure ST may include an inter-electrode insulating layer (also known as an interlayer insulating film) ILD disposed between the electrode pads EP1 to EP8. Although the stacked structure ST is shown as including eight electrode pads, this is only for ease of description, and the embodiment is not limited to this.

[0079] The electrode pads EP1 to EP8 stacked along the third direction D3 may include those referenced above. Figure 2 The described string select transistors SST1 and SST2 and the ground select transistor GST have gate electrodes. Furthermore, the electrode pads EP1 to EP8 stacked along the third direction D3 may include word lines WL connected to the memory cell MCT.

[0080] For example, the stacked structure ST may include a fourth electrode pad EP4 and a fifth electrode pad EP5 that are adjacent to each other on the third direction D3. The fifth electrode pad EP5 may be disposed on the fourth electrode pad EP4.

[0081] The fourth electrode pad EP4 can protrude further than the fifth electrode pad EP5 in the first direction D1, and the fourth electrode pad EP4 can protrude further than the fifth electrode pad EP5 in the second direction D2 (not shown). That is, the fourth electrode pad EP4 can protrude further than the fifth electrode pad EP5 in the first direction D1 and the second direction D2, so as to form a stepped structure not only in the first direction D1 but also in the second direction D2.

[0082] The stacked structure ST may include a cell region CR and a first cell extension region CER1 extending from the cell region CR along a first direction D1. Furthermore, the stacked structure ST may include a second cell extension region CER2 extending from the cell region CR along a second direction D2.

[0083] Multiple electrode separation regions (ESRs) can be set in the stacked structure ST. Each electrode separation region (ESR) can extend in the second direction D2.

[0084] The stacked structure ST can include multiple electrode separation trenches EST. Electrode separation regions ESR can each fill an electrode separation trench EST.

[0085] In the example, each electrode separation region ESR may include an insulating material filling the electrode separation trench EST. The electrode separation region ESR may include, for example, silicon oxide.

[0086] In another example, unlike in the accompanying drawings, each electrode separation region (ESR) may include a liner formed along the sidewall of the electrode separation trench (EST) and a filler layer disposed on the liner to fill the electrode separation trench (EST). For example, the liner may include an insulating material, and the filler layer may include a conductive material. In another example, the liner may include a conductive material, and the filler layer may include an insulating material.

[0087] At least some electrode separation regions (ESRs) can have a length in the second direction D2 that is smaller than the width of the stacked structure (ST) in the second direction D2, and in some cases, it can be equal to or greater than that width. Figure 7 In this embodiment, the length of the electrode separation region ESR in the second direction D2 is smaller than the width of the stacked structure ST in the second direction D2. However, the embodiments are not limited to this case.

[0088] The electrode separation region (ESR) may not be located in the first unit extension region (CER1). The electrode separation trench (EST) with the ESR is used in the replacement process to form word lines WL0 to WLn (see...). Figure 2 In other words, the electrode separation trench (EST) is used to remove a portion of the molding layer, and word lines are formed in the removed portion of the molding layer.

[0089] When the molding layer is removed using the electrode separation trench EST, not all of the molding layer in the first cell extension region CER1 is removed. Therefore, the unremoved portion of the molding layer can remain in the first cell extension region CER1. The first cell extension region CER1 includes a molding region EP_M extending in the second direction D2. That is, the stack structure ST includes molding regions EP_M disposed on both sides of the cell region CR in the first direction D1.

[0090] In the semiconductor memory device 10 according to an embodiment, each of the electrode pads EP1 to EP8 includes an electrode region EP_E and a molding region EP_M. The electrode region EP_E may include, for example, tungsten (W).

[0091] For example, in Figure 10 In this design, the electrode pad EP may include an electrode region EP_E and molding regions EP_M disposed on both sides of the electrode region EP_E in a first direction D1. The electrode region EP_E may be defined by an electrode separation region ESR extending in a second direction D2. The molding region EP_M may extend from the electrode region EP_E along the first direction D1.

[0092] The electrode separation region ESR may include a first electrode separation region and a second electrode separation region that are furthest apart from each other in the first direction D1. Here, the electrode region EP_E may be located between the first electrode separation region and the second electrode separation region. A portion of the electrode region EP_E may be located in a region other than the area between the first electrode separation region and the second electrode separation region.

[0093] The width of the molded region EP_M included in each of the electrode pads EP1 to EP8 in the first direction D1 can decrease as the distance from the peripheral logic structure PS increases. For example, the width of the molded region EP_M included in the fourth electrode pad EP4 in the first direction D1 is larger than the width of the molded region EP_M included in the fifth electrode pad EP5 in the first direction D1.

[0094] For example, the molded area EP_M included in the fourth electrode pad EP4 may protrude a first width W1 further in the first direction D1 than the molded area EP_M included in the fifth electrode pad EP5.

[0095] The sidewalls of the molded area EP_M back-to-stack structure ST included in the fourth electrode pad EP4 and the sidewalls of the molded area EP_M back-to-stack structure ST included in the fifth electrode pad EP5 can be spaced apart by a first width W1 in the first direction D1.

[0096] The sidewall profile of the stepped structure of the stacked structure ST, shown in the cross-sectional view taken along the first direction D1, can be defined by a molding region EP_M included in each of the electrode pads EP1 to EP8. The molding region EP_M can include, but is not limited to, silicon nitride.

[0097] Multiple vertical structures VS penetrating the stacked structure ST can be positioned between adjacent electrode separation regions ESR. Each vertical structure VS can be connected to a horizontal semiconductor layer 150.

[0098] For example, some vertical structure VSs that serve as channel regions for memory cells MCTs can be electrically connected to common source plates CSPs included in horizontal semiconductor layers 150.

[0099] The vertical structure VS can include, for example, semiconductor materials (such as silicon (Si), germanium (Ge), or mixtures thereof). Optionally, the vertical structure VS can include metal-oxide-semiconductor materials.

[0100] Barrier insulating layer (BIL), charge storage layer (CIL), and tunnel insulating layer (TIL) can be sequentially disposed between each vertical structure (VS) and the stacked structure (ST). However, the barrier insulating layer (BIL), charge storage layer (CIL), and tunnel insulating layer (TIL) disposed between each vertical structure (VS) and the stacked structure (ST) are merely examples, and the embodiments are not limited to this example.

[0101] A vertical insulating layer VI can be disposed on each vertical structure VS. The vertical insulating layer VI can fill the space defined by each vertical structure VS. In addition, a horizontal insulating pattern HP can be disposed between the electrode pad EP1 and the inter-electrode insulating layer ILD and between the electrode pad EP1 and the barrier insulating layer BIL. The horizontal insulating pattern HP can include, for example, silicon oxide or a high-k insulating layer, and can be included in a charge storage element capable of storing data between the vertical structure VS and the electrode pad EP1.

[0102] The barrier insulating layer (BIL), charge storage layer (CIL), and tunnel insulating layer (TIL) can be separated at the bottom of each vertical structure (VS). A contact support layer (CSB) can be disposed between portions of the separated barrier insulating layers (BIL), portions of the separated charge storage layers (CIL), and portions of the separated tunnel insulating layers (TIL). The contact support layer (CSB) can electrically connect the common source plate (CSP) and each vertical structure (VS). The contact support layer (CSB) can include, for example, a semiconductor material (such as silicon (Si), germanium (Ge), or mixtures thereof).

[0103] Furthermore, the sacrificial insulating layer 156 may be disposed between the stacked structure ST and the horizontal semiconductor layer 150, and between the stacked structure ST and the filling insulating layer 155. The sacrificial insulating layer 156 may contact the contact support layer CSB. The sacrificial insulating layer 156 may serve as a molding for forming the contact support layer CSB. The sacrificial insulating layer 156 may be a molded portion retained and not removed during the process of fabricating the space for forming the contact support layer CSB. The sacrificial insulating layer 156 may include, for example, silicon nitride.

[0104] The first interlayer insulating film 151 may be formed on the horizontal semiconductor layer 150. The first interlayer insulating film 151 may cover the stacked structure ST. The first interlayer insulating film 151 may include, for example, silicon oxide.

[0105] The second interlayer insulating film 152, the third interlayer insulating film 153, and the fourth interlayer insulating film 154 may be formed sequentially on the first interlayer insulating film 151. A portion of each electrode separation region ESR may extend to the second interlayer insulating film 152.

[0106] Bit line BL can be disposed on stacked structure ST. Bit line BL can extend in a first direction D1. Bit line BL can be electrically connected to at least one vertical structure VS in the first direction D1.

[0107] Bit lines BL can be formed on the third interlayer insulating film 153 and covered by a fourth interlayer insulating film 154. Bit lines BL can be electrically connected to the vertical structure VS via bit line pads BL_PAD and bit line plugs BL_PG.

[0108] The upper wiring structure 160 can be disposed on the bit line BL and / or the third interlayer insulating film 153, and can be surrounded by the fourth interlayer insulating film 154. For example... Figure 8 As shown, a portion of the upper wiring structure 160 can be included in the k+1_1 capacitor Ck+1_1.

[0109] Figure 11A It shows Figure 8 Wiring and capacitors. Figure 11B It is used to describe Figure 11A A magnified view of the k-th transistor capacitor. Figure 12 This is a circuit diagram of the capacitor of the charge pump CP according to an embodiment.

[0110] Reference Figure 11A , Figure 11B and Figure 12 The k-2nd diode Dk-2 and the k-2nd capacitor Ck-2 may be included in the buried region BR of the semiconductor memory device 10 according to the embodiment. The lower wiring structure 120 may include a first lower wiring 121 to a seventh lower wiring 127, and the upper wiring structure 160 may include a first upper wiring 161 to a third upper wiring 163.

[0111] Diode k_2 and Figure 4A and Figure 4B The k_2 diode Dk_2 shown is a transistor-based diode, and the wiring electrically connected to the gate electrode and the wiring electrically connected to the source / drain electrode can be electrically connected to each other. Although the k_2 diode Dk_2 according to the current embodiment is shown as a transistor-based diode, the embodiment is not limited to this and may include other types of diodes (such as diodes using PN junctions) in some cases.

[0112] The k_2 capacitor Ck_2 may include the fourth to sixth lower wirings 124 to 126 of the lower wiring structure 120 and transistors connected to the fourth to sixth lower wirings 124 to 126. Although not shown, the same voltage can be applied to the fourth lower wiring 124 and the sixth lower wiring 126, which are connected to the source / drain of the transistors in the k_2 capacitor Ck_2. Here, the same voltage can be applied to the fourth lower wiring 124 and the sixth lower wiring 126 by different power supplies, or the fourth lower wiring 124 and the sixth lower wiring 126 can be electrically connected so that the same voltage can be applied to them.

[0113] Therefore, since the voltage of the fifth lower wiring 125 of the gate electrode of the transistor connected to the k_2 capacitor Ck_2 is different from the voltage of the fourth lower wiring 124 and the sixth lower wiring 126 connected to the source / drain, the k-th transistor capacitor Ck_MOS can be formed to include the gate electrode portion.

[0114] Reference Figure 11B The transistor in the k_2nd capacitor Ck_2 includes a gate MOS_G, a source / drain MOS_SD, a spacer MOS_spacer, and a high-k film MOS_HK. The same voltage is applied to the source / drain MOS_SD on both sides of the gate MOS_G, such that the kth transistor capacitor Ck_MOS includes a first gate-source / drain capacitor Ck_g / sd_1 and a second gate-source / drain capacitor Ck_g / sd_2. According to some embodiments, the kth transistor capacitor Ck_MOS may include a capacitor in which the first gate-source / drain capacitor Ck_g / sd_1 and the second gate-source / drain capacitor Ck_g / sd_2 are connected in parallel.

[0115] Each of the first gate-source / drain capacitor Ck_g / sd_1 and the second gate-source / drain capacitor Ck_g / sd_2 may include a portion of the gate MOS_G and a portion of the source / drain MOS_SD. The first gate-source / drain capacitor Ck_g / sd_1 and the second gate-source / drain capacitor Ck_g / sd_2 may also include a spacer MOS_spacer and a high-k film MOS_HK as a dielectric disposed between the gate MOS_G and the source / drain MOS_SD.

[0116] Figure 11B The structure shown can be referred to as a transistor / dielectric structure. A transistor / dielectric structure can be used in a peripheral logic structure (PS). The transistor / dielectric structure can be used in either or both of the buried region (BR) and the unburied region (NBR) of the peripheral logic structure (PS).

[0117] Therefore, a transistor / dielectric structure may include a gate region, source / drain regions on either side of the gate region, spacers, and a dielectric film. The relative permittivity k of the dielectric film can range from 6 to 14. A dielectric constant with a value greater than 10 is considered a high dielectric constant.

[0118] In some embodiments, the transistor / dielectric structure is configured to provide a third capacitor (“capacitor 1”) and a fourth capacitor (“capacitor 2”) connected in parallel, capacitor 1 and capacitor 2 being associated with opposite sides of the gate region, respectively. Figure 11B In the diagram, capacitor 1 is indicated as Ck_g / sd_1, and capacitor 2 is indicated as Ck_g / sd_2.

[0119] Furthermore, the k-th metal-insulator-metal (MIM) capacitors Ck_MIM1 and Ck_MIM2, having a peripheral logic insulating layer 110 as the dielectric, can be formed as a portion including a fourth lower wiring 124 and a sixth lower wiring 126 connected to the source / drain, and a fifth lower wiring 125 connected to the gate electrode. The k_2 capacitor Ck_2 may include a capacitor in which the k-th transistor capacitor Ck_MOS and the k-th MIM capacitors Ck_MIM1 and Ck_MIM2 are connected in parallel.

[0120] The (k+1)th diode Dk+1_1 and the (k+1)th capacitor Ck+1_1 can be included in the unburied region NBR of the semiconductor memory device 10 according to the embodiment.

[0121] The (k+1)th diode Dk+1_1 is a diode that uses a transistor and may include the same structure and materials as the (k_2)th diode Dk_2. The (k+1)th diode Dk+1_1 may be electrically connected to the sixth lower wiring 126 connected to the source / drain of the (k_2)th capacitor Ck_2.

[0122] The k+1_1 capacitor Ck+1_1 may include the first lower wiring 121 to the third lower wiring 123 of the lower wiring structure 120, the first through via THV_PB1 to the third through via THV_PB3, and the first upper wiring 161 to the third upper wiring 163 of the upper wiring structure 160.

[0123] The first lower wiring 121 and the third lower wiring 123, which are connected to the source / drain of the transistor included in the (k+1_1)th capacitor Ck+1_1, can be electrically connected to the first upper wiring 161 and the third upper wiring 163, respectively. Furthermore, the second lower wiring 122, which is connected to the gate electrode of the transistor, can be electrically connected to the second upper wiring 162.

[0124] Therefore, the first lower wiring 121 and the third lower wiring 123, which are electrically connected to the source / drain of the transistor included in the (k+1_1)th capacitor Ck+1_1, can be electrically connected to the first through-via THV_PB1 and the third through-via THV_PB3, respectively. The first through-via THV_PB1 and the third through-via THV_PB3 can be electrically connected to the first upper wiring 161 and the third upper wiring 163, respectively, through the first through-via connection wiring THV_PL1 and the third through-via connection wiring THV_PL3. The second lower wiring 122, the second through-via THV_PB2, the second through-via connection wiring THV_PL2, and the second upper wiring 162 are also electrically connected to each other.

[0125] Although not shown, the same voltage can be applied to the first lower wiring 121 and the third lower wiring 123 connected to the source / drain of the transistor included in the (k+1_1)th capacitor Ck+1_1. Here, the same voltage can be applied to the first lower wiring 121 and the third lower wiring 123 by different power supplies, or the first lower wiring 121 and the third lower wiring 123 can be electrically connected so that the same voltage can be applied to them.

[0126] Therefore, because the voltage of the second lower wiring 122 connected to the gate electrode of the transistor in the (k+1)th capacitor Ck+1_1 is different from the voltages of the first lower wiring 121 and the third lower wiring 123 connected to the source / drain, the (k+1)th transistor capacitor Ck+1_MOS can be formed to include a portion of the gate electrode. The configuration of the (k+1)th transistor capacitor Ck+1_MOS can correspond to the configuration of the kth transistor capacitor Ck_MOS.

[0127] Furthermore, the (k+1)th lower MIM capacitors Ck+1_MIM1 and Ck+1_MIM2, having a peripheral logic insulating layer 110 as the dielectric, can be formed to include a portion comprising a first lower wiring 121 and a third lower wiring 123 connected to the source / drain, and a second lower wiring 122 connected to the gate electrode. The (k+1)th through-hole capacitors Ck+1_THV1 and Ck+1_THV2, having a first interlayer insulating film 151 as the dielectric, can be formed to include a first through-hole THV_PB1, a third through-hole THV_PB3, and a second through-hole THV_PB2. The (k+1)th upper MIM capacitors Ck+1_MIM3 and Ck+1_MIM4, having a fourth interlayer insulating film 154 as the dielectric, can be formed to include a first upper wiring 161, a third upper wiring 163, and a second upper wiring 162. The (k+1)th capacitor Ck+1_1 may include the (k+1)th transistor capacitor Ck+1_MOS, the (k+1)th through-hole capacitors Ck+1_THV1 and Ck+1_THV2, the (k+1)th lower MIM capacitors Ck+1_MIM1 and Ck+1_MIM2, and the (k+1)th upper MIM capacitors Ck+1_MIM3 and Ck+1_MIM4 connected in parallel.

[0128] Therefore, compared with the k-th capacitor Ck_2 set in the buried area BR, the (k+1)-th capacitor Ck+1_1 set in the non-buried area NBR additionally includes the (k+1)-th through-hole capacitors Ck+1_THV1 and Ck+1_THV2 connected in parallel, as well as the (k+1)-th upper MIM capacitors Ck+1_MIM3 and Ck+1_MIM4, so it can have a larger capacitance for the same area.

[0129] Furthermore, compared to the lower wiring structure 120, the upper wiring structure 160 is less affected by the process of the cell array structure CS, which includes the stacked structure ST. Therefore, compared to the upper wiring structure 160, the lower wiring structure 120, except for the seventh lower wiring 127 connecting the (k+1)th diode Dk+1_1 and the (k+1)th capacitor Ck+1_1, can include a metal with good thermal durability but low electrical conductivity. Examples of such metals include tungsten. The through-vias THV_PB1 to THV_PB3 can also include a metallic material with good thermal durability.

[0130] Compared to the lower wiring structure 120, the upper wiring structure 160, which includes the first upper wiring 161 to the third upper wiring 163, may include a metal with lower thermal durability but higher electrical conductivity. Examples of metals may include copper and aluminum.

[0131] Reference Figure 12The two ends of the (k+1)th upper MIM capacitors Ck+1_MIM3 and Ck+1_MIM4 are connected to wires with high conductivity (i.e., low resistance) including the first upper wiring 161 to the third upper wiring 163. Therefore, the conductivity of the (k+1)th capacitor Ck+1_1 can be higher than the conductivity of the (k_2)th capacitor Ck_2.

[0132] The higher the conductivity of a wire, the higher the frequency that can be applied through the wire. Therefore, the frequency applied to the (k+1)th capacitor Ck+1 can be higher than the frequency applied to the (k_2)th capacitor Ck_2.

[0133] Therefore, refer to Figure 4A and Figure 4B The frequency of the second clock signal of the second regulator Reg' connected to the k+1_1 capacitor Ck+1_1 can be higher than the frequency of the first clock signal of the first regulator Reg.

[0134] As the frequency applied to the capacitor increases, the capacitor's impedance decreases. Therefore, the impedance supplied through the capacitor... Figure 1 The charge amount of the line decoder 33 is increased. Therefore, for the same area, the (k+1)th capacitor Ck+1_1 can provide a larger amount of charge to the word line than the (k_2)th capacitor Ck_2.

[0135] Figure 13 This is a block diagram of a semiconductor memory device 10 according to an embodiment. Figure 1 Compared with the embodiments, Figure 13 The semiconductor memory device 10 may include multiple memory cell arrays 20_a and 20_b, multiple row decoders 33_a and 33_b corresponding to the memory cell arrays 20_a and 20_b, and multiple page buffers 35_a and 35_b. Peripheral circuitry 30 may refer to elements included in the semiconductor memory device 10 containing the row decoders 33_a and 33_b and the page buffers 35_a and 35_b. See also... Figure 13 The semiconductor memory device 10 may include multiple independently controlled planar memory cell arrays PLA and PLb (i.e., 20_a and 20_b). The word lines WL_a and WL_b of the planar memory cell arrays 20_a and 20_b can be independently activated by row decoders 33_a and 33_b and multiple voltage generators 38_a and 38_b, respectively. The operation of the planar memory cell arrays 20_a and 20_b (e.g., write operations and read operations) can be independently controlled by page buffers 35_a and 35_b, respectively.

[0136] As described above, in the semiconductor memory device 10, the cells of the memory cell array that are independently controlled to perform specific operations in parallel or to perform different operations can be referred to as a plane. Figure 13 In the example, memory cell array 20_a and memory cell array 20_b can be described as being included in different planes respectively.

[0137] Reference Figure 13 The peripheral circuit 30 can receive commands CMD and control signals CTRL from outside the semiconductor memory device 10 via common control logic 37, and separately provide address signals ADDR_a and ADDR_b corresponding to plane aPLa and plane bPLb, respectively, to the line decoders 33_a and 33_b. The page buffers 35_a and 35_b corresponding to plane aPLa and plane bPLb, respectively, can perform operations on the corresponding data Data_a and Data_b.

[0138] Although planes c PLc and d PLd are not shown, it is obvious that the descriptions of planes aPLa and b PLb, and the elements corresponding to planes a PLa and b PLb respectively, will apply to planes c PLc and d PLd, and the elements corresponding to planes c PLc and d PLd respectively.

[0139] Figure 14 This is a schematic perspective view of a semiconductor memory device 10 according to an embodiment. Figure 15 It is a planar block diagram of the peripheral logic structure PS included in the semiconductor memory device 10 according to an embodiment.

[0140] Reference Figure 14 and Figure 15 Compared with the previous embodiments, the cell array structure CS may include multiple planes PLA to PLd.

[0141] The focus now will be on describing the buried region BR of the peripheral logic structure PS using elements positioned below plane a PLa. Clearly, the description of elements positioned below plane a PLa applies to elements corresponding to those in other planes b PLb, c PLc, and d PLd.

[0142] and Figure 6 Compared to the previous embodiment, the peripheral logic structure PS may include an oscillator aOSC_a, a regulator aReg_a, a (k+2)th amplifier stage aStage_a, and amplifier stages aStage_a_n from k+2 to nth, and an analog circuit aACa, all located under the plane aPLA. These components can be respectively connected to... Figure 4A and Figure 4BThe first oscillator OSC, the first regulator Reg, the first amplifier stages Stage 1 to Stage k, and the analog circuit AC correspond to each other. However, with Figure 4A and Figure 4B Unlike other stages, the (k+2)th amplifier stage aStage_a can receive the output current of the non-buried NBR, while the nth amplifier stage aStage_a can provide the current to the line decoder 33_a of the plane aPLA.

[0143] In the unburied NBR of the peripheral logic structure PS, the common oscillator OSC', the common regulator Reg', the first common amplifier stages Stage 1 to Stage k+1, and the common external voltage contact EVC or common ground GND correspond to the elements of the unburied NBR of the previous embodiment. However, the unburied NBR of the peripheral logic structure PS differs from the unburied NBR of the previous embodiment in that the output of the (k+1)th common amplifier stage Stage k+1 is input to the corresponding (k+2)th amplifier stages Stage_a k+2, Stage_b k+2, Stage_c k+2, and Stage_dk+2 of the planes PLA, PLb, PLc, and PLd.

[0144] exist Figure 15 In the embodiments, with Figure 6 Compared to the previous embodiment, the (k+2)th amplification stages Stage_a k+2, Stage_b k+2, Stage_c k+2 and Stage_d k+2, which are respectively set under planes PLA, PLb, PLc and PLd, can be connected in series to the (k+1)th common amplification stage Stage k+1.

[0145] The number and connection relationships of planes PLA to PLd are not limited to Figure 15 The number and connection relationships of planes PLA to PLd are shown in the figure.

[0146] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those skilled in the art to which this disclosure pertains by referring to the claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes a first region and a second region; The first wiring is set in the first region of the substrate; The second wiring is located in the second region of the substrate; A stacked structure, wherein the stacked structure is disposed on a first lower wiring, and the stacked structure includes interlayer insulating films and electrode pads alternately stacked in a direction perpendicular to the substrate; Vertical structure, penetrating stacked structure; The tunnel insulation layer extends along the sidewalls of the vertical structure; A charge storage layer extends along the sidewall of the tunnel insulation layer; Multiple through-holes are disposed on the second lower wiring, wherein the multiple through-holes are configured to electrically connect the second lower wiring and the upper wiring disposed in the second region; A first amplification stage, including a first lower wiring, is stacked perpendicularly to the stacked structure and configured to generate a first operating voltage applied to the electrode pads; and The second amplification stage, including a second lower wiring and the plurality of through vias, is not stacked perpendicularly to the stack structure, is electrically connected to the first amplification stage, and is configured to generate a second operating voltage applied to the electrode pads. The first and second amplification stages are included in the charge pump.

2. The semiconductor memory device according to claim 1, in, The first region includes a first transistor, a first transistor capacitor, and a first metal-insulator-metal capacitor. The first transistor is electrically connected to a first lower wiring. The first transistor capacitor is implemented by the gate, source / drain, spacer, and dielectric film included in the first transistor. The first metal-insulator-metal capacitor includes a first portion of the first lower wiring. The second region includes a second transistor, a second transistor capacitor, a second metal-insulator-metal capacitor, and a through-via capacitor. The second transistor is electrically connected to a second lower wiring. The second transistor capacitor is implemented by a gate, source / drain, spacer, and dielectric film included in the second transistor. The second metal-insulator-metal capacitor includes a second portion of the second lower wiring, and the through-via capacitor includes a third portion of the plurality of through-vias.

3. The semiconductor memory device according to claim 2, wherein, The second region also includes a third metal-insulator-metal capacitor implemented by the fourth part of the upper wiring.

4. The semiconductor memory device of claim 3, wherein the semiconductor memory device comprises: The first capacitor includes a first transistor capacitor and a first metal-insulator-metal capacitor connected in parallel. as well as The second capacitor includes a second transistor capacitor, a second metal-insulator-metal capacitor, a through-hole capacitor, and a third metal-insulator-metal capacitor connected in parallel.

5. The semiconductor memory device according to claim 1, wherein, The first bottom and top wiring are made of different materials.

6. The semiconductor memory device according to any one of claims 1 to 5, wherein, The first region also includes a first regulator, wherein the first regulator is configured as follows: Drive the first amplification stage; and Generate the first clock signal, and The second region also includes a second regulator, wherein the second regulator is configured as follows: Drive the second amplification stage; and A second clock signal with a second frequency different from the first clock signal is generated.

7. The semiconductor memory device according to claim 6, wherein, The second frequency of the second clock signal is higher than the first frequency of the first clock signal.

8. The semiconductor memory device according to claim 6, wherein, The first bottom wiring includes tungsten, and the top wiring includes copper or aluminum.

9. The semiconductor memory device according to any one of claims 1 to 5, wherein the semiconductor memory device further comprises analog circuitry in the first region, wherein, The analog circuit is electrically connected to the stacked structure.

10. The semiconductor memory device according to any one of claims 1 to 5, in, The second area also includes external voltage contacts, and The first distance between the external voltage contact and the first amplification stage is greater than the second distance between the external voltage contact and the second amplification stage.

11. The semiconductor memory device according to any one of claims 1 to 5, in, The second area also includes floor mats, and The third distance between the floor mat and the first enlargement stage is greater than the fourth distance between the floor mat and the second enlargement stage.

12. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array, electrically connected to multiple word lines and electrically connected to multiple bit lines, wherein the memory cell array comprises multiple memory cells stacked perpendicularly to a substrate; and A charge pump is configured to generate an operating voltage applied to the plurality of word lines to operate the plurality of memory cells. The charge pump includes a first amplification stage and a second amplification stage, which are configured to generate an operating voltage. The first amplification stage is driven by the first regulator. The first regulator is configured to generate a first clock signal. The second amplification stage is driven by the second regulator. The second regulator is configured to generate a second clock signal having a second frequency that is higher than a first frequency of the first clock signal. The first amplification stage is positioned below the memory cell array and stacked perpendicularly to it. The second amplification stage is positioned below the memory cell array, but not stacked perpendicularly to it.

13. The semiconductor memory device according to claim 12, in, The first amplification stage includes a first lower wiring configured below the memory cell array and a first transistor electrically connected to the first lower wiring. The second amplification stage includes a second lower wiring configured below the memory cell array, a second transistor electrically connected to the second lower wiring, an upper wiring configured above the memory cell array, and a plurality of through-vias electrically connecting the second lower wiring and the upper wiring.

14. The semiconductor memory device according to claim 13, in, The first amplification stage includes a first capacitor, a first metal-insulator-metal capacitor, and a first transistor capacitor connected in parallel within the first capacitor. The first metal-insulator-metal capacitor includes a first portion of a first lower wiring. The first transistor capacitor is implemented by a gate, source / drain, spacer, and dielectric film included in the first transistor. The second amplification stage includes a second capacitor, a second metal-insulator-metal capacitor, a second transistor capacitor, a through-hole capacitor, and a third metal-insulator-metal capacitor connected in parallel within the second capacitor. The second metal-insulator-metal capacitor includes a second portion of a second lower wiring. The second transistor capacitor is implemented by a gate, source / drain, spacer, and dielectric film included in the second transistor. The through-hole capacitor includes a third portion of the plurality of through-holes. The third metal-insulator-metal capacitor includes a fourth portion of an upper wiring.

15. The semiconductor memory device according to claim 12, in, The first amplification stage includes a first bottom wiring configured to be lower than the memory cell array, and The second amplification stage includes a second lower wiring configured below the memory cell array, an upper wiring configured above the memory cell array, and a plurality of through vias electrically connecting the second lower wiring and the upper wiring, wherein the first lower wiring and the upper wiring are made of different materials.

16. The semiconductor memory device according to claim 15, wherein, The first bottom wiring includes tungsten, and the top wiring includes copper or aluminum.

17. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array electrically connected to multiple word lines and electrically connected to multiple bit lines, the memory cell array comprising multiple memory cells vertically stacked from a substrate, wherein the multiple memory cells include a first planar memory cell and a second planar memory cell arranged side by side on the substrate; A first amplification stage is disposed below and stacked perpendicularly to a first planar memory cell, wherein the first amplification stage is configured to generate a first operating voltage applied to the plurality of word lines to operate the first planar memory cell. A second amplification stage is disposed below and stacked perpendicularly to the second planar memory cell, wherein the second amplification stage is configured to generate a second operating voltage applied to the plurality of word lines to operate the second planar memory cell; and A common amplification stage, disposed below but not perpendicular to the memory cell array, and disposed on a substrate, wherein the common amplification stage is configured to generate a third operating voltage applied to the plurality of word lines to operate the first planar memory cell and the second planar memory cell. The first amplification stage includes a first lower wiring electrically connected to the memory cell array. The second amplification stage includes a second lower wiring electrically connected to the memory cell array. The common amplifier stage includes a common bottom wiring electrically connected to the memory cell array, and multiple through vias electrically connecting the common bottom wiring and the top wiring configured to be higher than the memory cell array. A common amplification stage is connected in series with each of the first and second amplification stages, and The first amplification stage, the second amplification stage, and the common amplification stage are included in the charge pump.

18. The semiconductor memory device according to claim 17, in, The first amplification stage also includes a first transistor electrically connected to the first lower wiring, a first transistor capacitor realized by the gate, source / drain, spacer and dielectric film included in the first transistor, and a first lower metal-insulator-metal capacitor including a first portion of the first lower wiring. The second amplification stage also includes a second transistor electrically connected to the second lower wiring, a second transistor capacitor implemented by the gate, source / drain, spacer, and dielectric film included in the second transistor, and a second lower metal-insulator-metal capacitor including a second portion of the second lower wiring. The common amplification stage also includes a third transistor electrically connected to a common bottom wiring, a third transistor capacitor comprised of a gate, source / drain, spacer, and dielectric film included in the third transistor, a third lower metal-insulator-metal capacitor including a third portion of the common bottom wiring, a through-via capacitor formed between the plurality of through vias, and an upper metal-insulator-metal capacitor including a fourth portion of the upper wiring.

19. The semiconductor memory device of claim 18, wherein the semiconductor memory device comprises: The first capacitor includes a first transistor capacitor and a first lower metal-insulator-metal capacitor connected in parallel. The second capacitor includes a second transistor capacitor and a second lower metal-insulator-metal capacitor connected in parallel. as well as A common capacitor, a third transistor capacitor, a third lower metal-insulator-metal capacitor, a through-hole capacitor, and an upper metal-insulator-metal capacitor are connected in parallel within the common capacitor.

20. The semiconductor memory device according to any one of claims 17 to 19, in, The first amplification stage is driven by a first regulator, wherein the first regulator is configured to generate a first clock signal. The second amplification stage is driven by a second regulator, which is configured to generate a second clock signal, and The common amplification stage is driven by a common regulator, which is configured to generate a common clock signal having a third frequency that is higher than the frequency of each of the first and second clock signals.

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