Read-write reliability detection method and device, electronic equipment and readable storage medium

Abstract

This application provides a read / write reliability detection method, apparatus, electronic device, and readable storage medium, comprising: determining a first pseudo-random counter function based on the data bus width of Synchronous Dynamic Random Access Memory (SDRAM); determining a first initial address value of the address bus and a first initial value of the data bus; iteratively calculating N times using the first pseudo-random counter function starting from the first initial value of the data bus to obtain N calculation results; and determining the read / write reliability of the SDRAM using N+1 pseudo-random values ​​composed of the N calculation results and the first initial value of the data bus, along with the first initial address value. Since the above implementation uses calculation results obtained from a pseudo-random counter function to verify the read / write reliability of the SDRAM, rather than natural numbers, it is less prone to numerical clustering issues, making the detection of SDRAM more accurate.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to a read / write reliability detection method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] When communication equipment uses a Field Programmable Gate Array (FPGA) to forward packets, it often requires an external Synchronous Dynamic Random-Access Memory (SDRAM) to buffer the packet data. Before use, these SDRAMs need to undergo a thorough self-test by the FPGA on their data and address buses. The testing method typically involves writing a natural number into the SDRAM, then reading back the cached natural number from the SDRAM, comparing it to the original natural number, and thus verifying the address and data buses.

[0003] However, using natural numbers for verification is not comprehensive and accurate because the values ​​of natural numbers are relatively concentrated and it is impossible to check the higher bits of the data bus. Summary of the Invention

[0004] The purpose of this application is to provide a read / write reliability detection method, apparatus, electronic device, and readable storage medium to improve the problem that the prior art cannot perform comprehensive and accurate detection.

[0005] In a first aspect, embodiments of this application provide a read / write reliability detection method, which determines a first pseudo-random calculator function based on the data bus width of Synchronous Dynamic Random Access Memory (SDRAM); determines a first initial address value of the address bus and a first initial value of the data bus; iterates N times using the first pseudo-random calculator function starting from the first initial value of the data bus to obtain N calculation results; and determines the read / write reliability of the SDRAM using N+1 pseudo-random values ​​composed of the N calculation results and the first initial value of the data bus, along with the first initial address value.

[0006] In the above implementation, since the calculation results calculated by the pseudo-random counter function are used to verify the read and write reliability of SDRAM instead of natural numbers, the problem of numerical concentration is less likely to occur, making the detection of SDRAM more accurate.

[0007] In one possible design, determining the read / write reliability of the SDRAM using the N calculation results, the first initial value of the data bus, and the first initial address value comprises: sequentially writing the N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, into N+1 consecutive memory cells starting from the memory cell corresponding to the first initial address value; reading N+1 pseudo-random values ​​cached in the SDRAM from the N+1 consecutive memory cells, while simultaneously using the first pseudo-random calculator to iteratively obtain N+1 pseudo-random values ​​starting from the first initial value of the data bus; and determining the read / write reliability of the SDRAM based on whether the N+1 pseudo-random values ​​obtained by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached in the SDRAM.

[0008] In the above implementation, for N+1 pseudo-random values, they can be sequentially written into N+1 consecutive memory cells of the SDRAM, starting from the memory cell corresponding to the first initial address. After writing the N+1 pseudo-random values ​​into the N+1 consecutive memory cells, N+1 pseudo-random values ​​cached in the SDRAM are read from the N+1 consecutive memory cells. Simultaneously, the first pseudo-random calculator iteratively obtains N+1 pseudo-random values ​​starting from the first initial value, and the two are compared. If there is a value among the N+1 pseudo-random values ​​cached in the SDRAM that is different from the corresponding N+1 pseudo-random values ​​calculated by the first pseudo-random calculator, it indicates that the read / write reliability of the SDRAM is poor.

[0009] In one possible design, determining the SDRAM read / write reliability based on whether the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached by the SDRAM includes: if the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached by the SDRAM, calculating the address calculation result using the first pseudo-random calculator function on the first address initial value; using the address calculation result as the new first address initial value, and setting the N+1th pseudo-random value among the N+1 pseudo-random values ​​as the new address initial value. The random value is used as the first initial value of the new data bus. The following steps are performed: the first pseudo-random calculator function is used to iterate and calculate N times from the first initial value of the data bus to obtain N calculation results. Then, N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, are sequentially written into N+1 consecutive memory cells starting from the memory cell corresponding to the first address initial value, until there is a pseudo-random value among the N+1 pseudo-random values ​​obtained by the first pseudo-random calculator that is not equal to the N+1 pseudo-random values ​​cached by SDRAM, or the above method runs for more than a preset time.

[0010] In the above implementation, if the N+1 pseudo-random values ​​cached in SDRAM are all equal to the N+1 pseudo-random values ​​calculated by the corresponding first pseudo-random calculator, a new initial value for the first address can be obtained. The N+1th pseudo-random value among the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator is used as the first initial value for the new data bus. The above operation is repeated until the running time exceeds the preset duration, or a pseudo-random value cached in SDRAM is not equal to the pseudo-random value calculated by the corresponding first pseudo-random calculator.

[0011] In one possible design, determining the first pseudo-random counter function based on the data bus width of the synchronous dynamic random access memory (SDRAM) includes: determining a first target N value for the pseudo-random counter function based on the SDRAM data bus width; determining a first target feedback coefficient corresponding to the first target N value based on the correspondence between the N value and the feedback coefficient; and determining the first pseudo-random counter function based on the first target feedback coefficient.

[0012] In the above embodiments, the first pseudo-random calculator function can be determined in the above manner. Of course, the first pseudo-random calculator function can also be determined in other ways. The specific process of determining the first pseudo-random calculator function should not be construed as a limitation of this application.

[0013] In one possible design, the method further includes: determining a second pseudo-randomization calculator function based on the number of address buses; determining a second initial address value for the address buses and a second initial value for the data buses; writing the second initial value of the data buses into the memory cell corresponding to the second initial address value; iteratively calculating from the second initial value of the data buses using the second pseudo-randomization calculator function to obtain a pseudo-randomization calculation result for each iteration; writing the same pseudo-randomization calculation result into the memory cell corresponding to the pseudo-randomization calculation result until the pseudo-randomization calculation result covers all addresses of the SDRAM; starting from the memory cell corresponding to the second initial address value, reading the pseudo-randomization value cached in the SDRAM, and iteratively calculating from the second initial value using the second pseudo-randomization calculator function to obtain the address of the next memory cell and the corresponding pseudo-randomization value cached in the SDRAM, while simultaneously iteratively obtaining a pseudo-randomization value from the second initial value using the second pseudo-randomization calculator function;

[0014] The pseudo-random value cached in SDRAM is compared with the pseudo-random value calculated by the corresponding second pseudo-random calculator until there is a pseudo-random value in the pseudo-random value calculated by the second pseudo-random calculator that is not equal to the pseudo-random value cached in SDRAM, or until all addresses of SDRAM have been read.

[0015] In the above implementation, each time a pseudo-random calculation result is obtained, the same pseudo-random calculation result is written into the memory cell corresponding to the data with the address value of the pseudo-random calculation result, until all addresses of the SDRAM are filled. The above implementation fills all addresses of the SDRAM, thus making the reliability detection of the SDRAM more comprehensive.

[0016] In one possible design, determining the second pseudo-random counter function based on the number of address buses includes: determining a second target N value for the pseudo-random counter function based on the number of address buses; determining a second target feedback coefficient corresponding to the second target N value based on the correspondence between the N value and the feedback coefficient; and determining the second pseudo-random counter function based on the second target feedback coefficient.

[0017] In the above embodiments, the second pseudo-random calculator function can be determined in the above manner. Of course, the second pseudo-random calculator function can also be determined in other ways. The specific process of determining the second pseudo-random calculator function should not be construed as a limitation of this application.

[0018] Secondly, embodiments of this application provide a read / write reliability detection device, the device comprising: a first function determination module, configured to determine a first pseudo-random calculator function based on the data bus width of a synchronous dynamic random access memory (SDRAM); a first initial determination module, configured to determine a first initial address value of the address bus and a first initial value of the data bus; a function calculation module, configured to iteratively calculate N times using the first pseudo-random calculator function starting from the first initial value of the data bus to obtain N calculation results; and a reliability determination module, configured to determine the read / write reliability of the SDRAM using N+1 pseudo-random values ​​composed of the N calculation results and the first initial value of the data bus, and the first initial address value.

[0019] In one possible design, the reliability determination module is used to: sequentially write N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, from the storage cell corresponding to the first address initial value into N+1 consecutive storage cells; read N+1 pseudo-random values ​​cached in SDRAM from the N+1 consecutive storage cells, and simultaneously use the first pseudo-random calculator to iteratively obtain N+1 pseudo-random values ​​starting from the first initial value of the data bus; and determine the read / write reliability of the SDRAM based on whether the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached in SDRAM.

[0020] In one possible design, the reliability determination module is used to: if the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator are all equal to the N+1 pseudo-random values ​​cached in SDRAM, calculate the address calculation result using the first pseudo-random calculator function on the first address initial value; use the address calculation result as the new first address initial value, and use the N+1th pseudo-random value among the N+1 pseudo-random values ​​as the new first initial value of the data bus, and execute the following steps: use the first pseudo-random calculator function to iteratively calculate N times starting from the first initial value of the data bus to obtain N calculation results, and write the N+1 pseudo-random values ​​including the N calculation results and the first initial value of the data bus into N+1 consecutive memory cells starting from the memory cell corresponding to the first address initial value, until there is a pseudo-random value among the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator that is not equal to the N+1 pseudo-random values ​​cached in SDRAM, or the above method runs for more than a preset time.

[0021] In one possible design, the first function determination module is used to determine a first target N value of the pseudo-random counter function based on the SDRAM data bus width; determine a first target feedback coefficient corresponding to the first target N value based on the correspondence between the N value and the feedback coefficient; and determine a first pseudo-random counter function based on the first target feedback coefficient.

[0022] In one possible design, the device further includes: a second function determination module, used to determine a second pseudo-randomization calculator function based on the number of address buses; a second initial determination module, used to determine a second initial address value for the address buses and a second initial value for the data buses; an initial write module, used to write the second initial value of the data buses into the memory cell corresponding to the second initial address value; a pseudo-randomization calculation module, used to iteratively calculate from the second initial value of the data buses using the second pseudo-randomization calculator function to obtain a pseudo-randomization calculation result for each iteration; and an address overwrite module, used to write the same pseudo-randomization calculation result into the memory cell corresponding to the pseudo-randomization calculation result until the pseudo-randomization calculation result covers all addresses of the SDRAM. Then, starting from the second initial address value of the address buses, previously stored data is read from the SDRAM and compared with the result calculated by the second pseudo-randomization calculator function until a calculated pseudo-random value is found that is not equal to the pseudo-random value cached by the SDRAM, or all addresses of the SDRAM have been read, thus detecting the validity of each SDRAM memory cell.

[0023] In one possible design, the second function determination module is used to determine a second target N value for the pseudo-random counter function based on the number of address buses; determine a second target feedback coefficient corresponding to the second target N value based on the correspondence between the N value and the feedback coefficient; and determine a second pseudo-random counter function based on the second target feedback coefficient.

[0024] Thirdly, embodiments of this application provide an electronic device including a processor of the first aspect or any optional implementation thereof.

[0025] Fourthly, this application provides a readable storage medium storing an executable program, which, when run by a processor, performs the method described in the first aspect or any optional implementation thereof.

[0026] Fifthly, this application provides an executable program product that, when run on a computer, causes the computer to perform the method of the first aspect or any possible implementation thereof.

[0027] To make the above-mentioned objectives, features and advantages to be achieved by the embodiments of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A flowchart illustrating the read / write reliability detection method provided in this application embodiment;

[0030] Figure 2 for Figure 1 A flowchart illustrating the specific steps of step S140;

[0031] Figure 3 A flowchart illustrating a specific implementation of the read / write reliability detection method provided in this application embodiment;

[0032] Figure 4 A schematic structural block diagram of the read / write reliability detection device provided in the embodiments of this application;

[0033] Figure 5 A table showing the correspondence between N values ​​and feedback coefficients;

[0034] Figure 6 A schematic block diagram of the FPGA used in the read / write reliability detection method provided in the embodiments of this application is shown. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0036] Please see Figure 1 , Figure 1 This application illustrates a read / write reliability detection method provided in an embodiment, which can be executed by an FPGA. The method specifically includes the following steps S110 to S140:

[0037] Step S110: Determine the first pseudo-random number generator function based on the data bus width of the synchronous dynamic random access memory (SDRAM).

[0038] The pseudo-random counter function can be a linear feedback shift register (LFSR) counter.

[0039] Optionally, in one specific embodiment, step S110 includes the following steps: determining a first target N value for the pseudo-random counter function based on the SDRAM data bus width; determining a first target feedback coefficient corresponding to the first target N value based on the correspondence between the N value and the feedback coefficient; and determining a first pseudo-random counter function based on the first target feedback coefficient.

[0040] The target value N for the pseudo-random counter function can be determined based on the data bus width. N is the maximum counting width of the LFSR counter function. Optionally, the target N value can be a random value smaller than the SDRAM data bus width. For example, if the SDRAM data bus width is 64 bits, the target N value can be a random value, such as 23.

[0041] Please refer to the table showing the correspondence between N-values ​​and feedback coefficients. Figure 5 , Figure 5 This shows multiple N values ​​(N values ​​from 3 to 168), and the corresponding XOR NOT feedback coefficient for each N value. The first target feedback coefficient corresponding to the first target N value can be obtained by looking up a table. For example, by looking up... Figure 5 The table shown shows that the feedback coefficients corresponding to the N value of 23 are 23 and 18.

[0042] After obtaining the first target feedback coefficient, the coefficients of the pseudo-random counter function can be determined, thereby obtaining the first pseudo-random counter function F1(x).

[0043] Step S120: Determine the first initial address value of the address bus and the first initial value of the data bus.

[0044] The first initial address value is the specific address of the first memory cell in the SDRAM where the data storage operation is performed. The first initial value of the data bus refers to the specific value of the data to be stored in the aforementioned memory cell. Both the first initial address value and the first initial value of the data bus can be randomly selected. For example, let's assume both the first initial address value and the first initial value of the data bus are 0. This means that the specific value 0 can be stored in the memory cell at address 0 in the SDRAM.

[0045] Step S130: Using the first pseudo-random calculator function, iterate N times starting from the first initial value of the data bus to obtain N calculation results.

[0046] Substituting the initial value 0 into the first pseudo-random calculator function F1(x), we obtain the corresponding calculation result f1 = F1(0); then substituting the calculation result f1 into the first pseudo-random calculator function F1(x), we obtain the calculation result f2 = F1(f1)... This iterative calculation is performed in the above manner until N calculation results f1, f2, f3...fn are obtained. The number of iterations can be any positive integer; for example, it can be iterated 15 times. The specific number of iterations should not be construed as a limitation of this application.

[0047] Step S140: Using the N calculation results and the first initial value of the data bus to form N+1 pseudo-random values ​​and the first address initial value, determine the read / write reliability of the SDRAM.

[0048] The N calculation results f1, f2, f3...fn obtained above are combined with the first initial value of the data bus to form N+1 pseudo-random values. Then, starting from the first address initial value, the read and write reliability of SDRAM is determined.

[0049] In the above implementation, a first pseudo-random counter function can be determined, along with a first initial address value and a first initial value for the data bus. Then, the pseudo-random counter function is used to iteratively calculate from the first initial value. The calculation results obtained from the iterative calculation, along with the first initial value and the first initial address value, are used to verify the read / write reliability of the SDRAM. Because the above implementation uses the calculation results obtained from the pseudo-random counter function to verify the read / write reliability of the SDRAM, rather than natural numbers, the problem of value clustering is less likely to occur, making the detection of SDRAM more accurate.

[0050] Please see Figure 2 , Figure 2 A flowchart illustrating the specific steps of step S140 is shown, which specifically includes the following steps S141 to S143:

[0051] Step S141: Starting from the storage unit corresponding to the first address initial value, write N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, into N+1 consecutive storage units.

[0052] Take the storage unit corresponding to the initial value of the first address as the first storage unit. Starting from the first storage unit, obtain N+1 consecutive storage units. For each of these N+1 storage units, store one of the N+1 pseudo-random values ​​in sequence.

[0053] For example, for N+1 memory cells with address values ​​from 0 to N, N+1 pseudo-random values ​​from 0 to fn are stored sequentially: the first initial value 0 is stored in the memory cell with address value 0, the pseudo-random value f1 is stored in the memory cell with address value 1, the pseudo-random value f2 is stored in the memory cell with address value 2, and so on, and the pseudo-random value fn is stored in the memory cell with address value N.

[0054] Step S142: Read N+1 pseudo-random values ​​cached in SDRAM from the N+1 consecutive memory cells, and simultaneously use the first pseudo-random calculator to iterate from the first initial value of the data bus to obtain N+1 pseudo-random values.

[0055] N+1 pseudo-random values ​​cached in SDRAM are read from N+1 consecutive memory cells, and N+1 pseudo-random values ​​are obtained again by iterating from the first initial value of the data bus using the first pseudo-random calculator.

[0056] Performing the above two steps simultaneously can shorten the acquisition time for both, so that step S143 can be executed more quickly.

[0057] Step S143: Determine the read / write reliability of SDRAM based on whether the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached by SDRAM.

[0058] Since data transmission between the FPGA and SDRAM storage cells requires a data bus, an anomaly in the data bus could cause N+1 pseudo-random values ​​cached in the SDRAM to be inconsistent with the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator. Therefore, by comparing whether the corresponding pseudo-random values ​​cached in the SDRAM are consistent with the pseudo-random values ​​calculated by the first pseudo-random calculator, it can be determined whether the read / write reliability provided by the SDRAM data lines and address lines is reliable.

[0059] For N+1 pseudo-random values, starting from the memory cell corresponding to the first initial address, they can be sequentially written into N+1 consecutive memory cells of the SDRAM. After writing the N+1 pseudo-random values ​​into the N+1 consecutive memory cells, N+1 pseudo-random values ​​cached in the SDRAM are read from the N+1 consecutive memory cells. Simultaneously, the first pseudo-random calculator iteratively obtains N+1 pseudo-random values ​​starting from the first initial value. The two are compared. If any of the N+1 pseudo-random values ​​cached in the SDRAM differs from the corresponding N+1 pseudo-random values ​​calculated by the first pseudo-random calculator, it indicates that the SDRAM has a read / write reliability problem.

[0060] Optionally, step S143 may further include the following steps:

[0061] If the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator are all equal to the N+1 pseudo-random values ​​cached in SDRAM, the first pseudo-random calculator function is used to calculate the address calculation result for the first address initial value; the address calculation result is used as the new first address initial value, and the N+1th pseudo-random value among the N+1 pseudo-random values ​​is used as the new first initial value of the data bus. Then, the following steps are executed: Step S130: The first pseudo-random calculator function iterates N times from the first initial value of the data bus to obtain N calculation results; Step S141: The N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, are sequentially written into N+1 consecutive memory cells starting from the memory cell corresponding to the first address initial value; until there is a pseudo-random value among the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator that is not equal to the N+1 pseudo-random values ​​cached in SDRAM, or the above method runs for more than a preset time.

[0062] If all N+1 pseudo-random values ​​cached in SDRAM are equal to the corresponding N+1 pseudo-random values ​​calculated by the first pseudo-random calculator, a new initial address value can be obtained. The N+1th pseudo-random value from the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator is then used as the new initial value for the data bus. This process is repeated until the running time exceeds a preset duration, or until a pseudo-random value cached in SDRAM is not equal to the corresponding pseudo-random value calculated by the first pseudo-random calculator. If the running time exceeds the preset duration and the corresponding pseudo-random value cached in SDRAM is still consistent with the pseudo-random value calculated by the first pseudo-random calculator, it means that the SDRAM has good read / write reliability. If a pseudo-random value cached in SDRAM is not equal to the corresponding pseudo-random value calculated by the first pseudo-random calculator, it means that the SDRAM has read / write reliability issues.

[0063] Optionally, please see Figure 3 In one specific embodiment, the read / write reliability detection method provided in this application may further include the following steps S210 to S250:

[0064] Step S210: Determine the second pseudo-random number calculator function based on the number of address buses.

[0065] Optionally, step S210 may specifically include the following steps: determining a second target N value for the pseudo-random counter function based on the number of address buses; determining a second target feedback coefficient corresponding to the second target N value based on the correspondence between the N value and the feedback coefficient; and determining a second pseudo-random counter function based on the second target feedback coefficient.

[0066] The number of address buses can be used as the second target value N. For example, let's assume the number of address buses is 28, then the value of N is 28.

[0067] from Figure 5 The table showing the correspondence between N values ​​and feedback coefficients reveals that the target feedback coefficients corresponding to an N value of 28 are 28 and 25. Based on these second target feedback coefficients, the second pseudo-random calculator function F2(x) is determined.

[0068] Step S220: Determine the second initial address value of the address bus and the second initial value of the data bus.

[0069] The second initial address value is the specific address of the first memory cell in the SDRAM where the data storage operation is performed. The second initial value of the data bus refers to the specific value of the data to be stored in the aforementioned memory cell. Both the second initial address value and the second initial value of the data bus can be randomly selected. For example, let's assume both the second initial address value and the second initial value of the data bus are 'a'. This means that the specific value 'a' can be stored in the memory cell at address 'a' in the SDRAM.

[0070] Step S230: Write the second initial value of the data bus into the storage cell corresponding to the second address initial value.

[0071] Step S240: The second pseudo-random calculator function is used to iteratively calculate from the second initial value of the data bus to obtain the pseudo-random calculation result of each iteration.

[0072] After storing the specific value 'a' in the memory cell at address 'a' in the SDRAM, iterative calculation is performed using the second pseudo-random number calculator function: substituting the second initial value 'a' into the second pseudo-random number calculator function F2(x) yields the corresponding calculation result f'1 = F2(a); then substituting the calculation result f'1 into the first pseudo-random number calculator function F2(x) yields the calculation result f'2 = F2(f'1)... iterative calculation is performed in the above manner.

[0073] Step S250: Write the same pseudo-random calculation result into the storage cell corresponding to the pseudo-random calculation result until the pseudo-random calculation result covers all addresses of the SDRAM.

[0074] Step S260: Starting from the storage cell corresponding to the second initial address value, read the pseudo-random value cached in SDRAM, and use the second pseudo-random calculator function to iteratively calculate from the second initial value to obtain the address of the next storage cell and the corresponding pseudo-random value cached in SDRAM. At the same time, use the second pseudo-random calculator to iteratively obtain the pseudo-random value from the second initial value.

[0075] Step S270: Compare the pseudo-random value cached in SDRAM with the pseudo-random value calculated by the corresponding second pseudo-random calculator until there is a pseudo-random value in the pseudo-random value calculated by the second pseudo-random calculator that is not equal to the pseudo-random value cached in SDRAM, or until all addresses of SDRAM have been read.

[0076] In the above implementation, the second pseudo-random number generator function can be determined based on the number of address buses, and the second initial value of the address and the second initial value of the data bus can be determined. Then, the second initial value is written into the SDRAM memory cell corresponding to the second initial value. Subsequently, the second pseudo-random number generator function is used to iterate from the second initial value. Each time a pseudo-random calculation result is obtained, the same pseudo-random calculation result is written into the memory cell corresponding to the data with the address value of the pseudo-random calculation result, until all addresses of the SDRAM are filled. For example, after storing a specific value 'a' in the memory cell at address 'a' in the SDRAM, f'1 = F2(a) is obtained; then the specific value f'1 is stored in the memory cell at address f'1 in the SDRAM. Subsequently, f'2 = F2(f'1) is obtained, then the specific value f'2 is stored in the memory cell at address f'2 in the SDRAM, and so on, until the calculation result fills all addresses of the SDRAM.

[0077] Then, starting from the memory cell corresponding to the second initial address, pseudo-random values ​​cached in SDRAM are read. For each pseudo-random value read, the address of the next memory cell is calculated using a second pseudo-random calculator, facilitating the reading of the SDRAM-cached pseudo-random value stored in that cell. Simultaneously, the second pseudo-random calculator iteratively calculates from the second initial value. Whenever a SDRAM-cached pseudo-random value is obtained and the corresponding pseudo-random value calculated by the second pseudo-random calculator is obtained, the two are compared. If they are confirmed to be the same, the above steps continue until the SDRAM-cached pseudo-random value is different from the corresponding pseudo-random value calculated by the second pseudo-random calculator, or all SDRAM addresses have been read.

[0078] Optionally, if the calculated pseudo-random value exceeds the address width range, the high-order bits of the bits exceeding the address width range can be removed.

[0079] The above implementation method fills all the addresses of the SDRAM, thus making the reliability testing of the SDRAM more comprehensive.

[0080] Please see Figure 4 , Figure 4 This application illustrates a read / write reliability detection device 300, which includes:

[0081] The first function determination module 310 is used to determine the first pseudo-random calculator function based on the data bus width of the synchronous dynamic random access memory (SDRAM).

[0082] The first initial determination module 320 is used to determine the first initial address value of the address bus and the first initial value of the data bus.

[0083] The function calculation module 330 is used to iteratively calculate N times from the first initial value of the data bus using the first pseudo-random calculator function to obtain N calculation results.

[0084] The reliability determination module 340 is used to determine the read / write reliability of the SDRAM by using the N calculation results, the N+1 pseudo-random values ​​composed of the first initial value of the data bus, and the first address initial value.

[0085] The reliability determination module 340 is used to: sequentially write N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, from the storage unit corresponding to the first address initial value into N+1 consecutive storage units; read N+1 pseudo-random values ​​cached in SDRAM from the N+1 consecutive storage units, and simultaneously use the first pseudo-random calculator to iteratively obtain N+1 pseudo-random values ​​starting from the first initial value of the data bus; and determine the read / write reliability of SDRAM based on whether the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached in SDRAM.

[0086] The reliability determination module 340 is configured to: if the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator are all equal to the N+1 pseudo-random values ​​cached in SDRAM, calculate the address calculation result using the first pseudo-random calculator function on the first address initial value; use the address calculation result as the new first address initial value, and use the N+1th pseudo-random value among the N+1 pseudo-random values ​​as the new first initial value of the data bus, and execute the following steps: use the first pseudo-random calculator function to iteratively calculate N times starting from the first initial value of the data bus to obtain N calculation results, and write the N+1 pseudo-random values ​​including the N calculation results and the first initial value of the data bus into N+1 consecutive memory cells starting from the memory cell corresponding to the first address initial value, until there is a pseudo-random value among the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator that is not equal to the N+1 pseudo-random values ​​cached in SDRAM, or the above method runs for more than a preset time.

[0087] The first function determination module 310 is used to determine the first target N value of the pseudo-random counter function based on the data bus width of the SDRAM; determine the first target feedback coefficient corresponding to the first target N value based on the correspondence between the N value and the feedback coefficient; and determine the first pseudo-random counter function based on the first target feedback coefficient.

[0088] The device further includes: a second function determination module, configured to determine a second pseudo-random calculator function based on the number of address buses; a second initial determination module, configured to determine a second initial address value of the address bus and a second initial value of the data bus; an initial writing module, configured to write the second initial value of the data bus into the storage unit corresponding to the second initial address value; a pseudo-random calculation module, configured to iteratively calculate from the second initial value of the data bus using the second pseudo-random calculator function to obtain a pseudo-random calculation result for each iteration; and an address overwriting module, configured to write the same pseudo-random calculation result into the storage unit corresponding to the pseudo-random calculation result until the pseudo-random calculation result overwrites the address. The entire address of the SDRAM is read; starting from the memory cell corresponding to the second initial address, the pseudo-random value cached in the SDRAM is read, and the second pseudo-random calculator function is used to iteratively calculate from the second initial value to obtain the address of the next memory cell and the corresponding pseudo-random value cached in the SDRAM. At the same time, the second pseudo-random calculator is used to iteratively obtain pseudo-random values ​​from the second initial value. The pseudo-random value cached in the SDRAM is compared with the pseudo-random value obtained by the corresponding second pseudo-random calculator until there is a pseudo-random value in the pseudo-random value obtained by the second pseudo-random calculator that is not equal to the pseudo-random value cached in the SDRAM, or the entire address of the SDRAM is read.

[0089] The second function determination module is used to determine the second target N value of the pseudo-random counter function based on the number of address buses; determine the second target feedback coefficient corresponding to the second target N value based on the correspondence between the N value and the feedback coefficient; and determine the second pseudo-random counter function based on the second target feedback coefficient.

[0090] Figure 4 The read / write reliability testing device shown is... Figure 1 The corresponding read / write reliability testing methods are shown, so they will not be elaborated here.

[0091] Please see Figure 6 , Figure 6 A schematic block diagram of the FPGA used in the read / write reliability detection method provided in this application embodiment is shown. The FPGA includes an SDRAM controller IP 410, a multi-port SDRAM operation management unit 420, an SDRAM self-test unit 430, and multiple service data read / write request units.

[0092] The main functions of each unit are described below:

[0093] SDRAM Controller IP 410: Provided by the FPGA manufacturer, this IP enables direct control of the SDRAM. The SDRAM Controller IP 410 can be a Xilinx MIG controller, which can perform operations such as initialization, data reading and writing, and automatic refresh of DDR2 / 3 / 4 SDRAM.

[0094] Multi-port SDRAM operation management unit 420: provides N operation ports for reading and writing SDRAM, of which ports 0 to N-2 (N-1) are connected to service data read and write units 0 to (N-1) respectively. Multi-port SDRAM operation management unit 420 is also connected to SDRAM controller IP 410.

[0095] Each of the multiple service data read / write units is connected to a port corresponding to the multi-port SDRAM operation management unit 420, and is used to send service data to or read service data from SDRAM during normal operation.

[0096] SDRAM self-test unit 430: Used to test SDRAM during device initialization by interacting with one port (i.e., port N-1) of the multi-port SDRAM operation management unit 420.

[0097] The read / write reliability detection method provided in this embodiment can be executed by the SDRAM self-test unit 430. The SDRAM self-test unit 430 can be used to test the read / write reliability of the SDRAM by continuously and intensively reading and writing the address of the SDRAM memory cell and the data to be stored in the memory cell using a pseudo-random function. Due to the nature of pseudo-random numbers, the address or read / write data will change significantly, thus allowing for a more comprehensive detection of the low and high bits of the data lines.

[0098] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0099] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0100] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0101] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0102] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for detecting read / write reliability, characterized in that, The method includes: The first pseudo-random number generator function is determined based on the data bus width of the synchronous dynamic random access memory (SDRAM). Determine the first initial address value for the address bus and the first initial value for the data bus; The first pseudo-random calculator function is used to iterate and calculate N times starting from the first initial value of the data bus to obtain N calculation results; The read / write reliability of the SDRAM is determined by using the N calculation results, the N+1 pseudo-random values ​​composed of the first initial value of the data bus, and the first initial address value. The step of determining the read / write reliability of the SDRAM using the N calculation results, the first initial value of the data bus, N+1 pseudo-random values, and the first address initial value includes: Starting from the storage unit corresponding to the first address initial value, N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, are sequentially written into N+1 consecutive storage units. N+1 pseudo-random values ​​cached in SDRAM are read from the N+1 consecutive memory cells, and N+1 pseudo-random values ​​are obtained iteratively from the first initial value of the data bus using the first pseudo-random calculator. The read / write reliability of SDRAM is determined by whether the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached in SDRAM.

2. The method according to claim 1, characterized in that, The step of determining the read / write reliability of SDRAM by comparing the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator with the N+1 pseudo-random values ​​cached in SDRAM includes: If the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator are all equal to the N+1 pseudo-random values ​​cached by SDRAM, the first pseudo-random calculator function is used to calculate the address initial value to obtain the address calculation result. The address calculation result is used as the new first address initial value, and the (N+1)th pseudo-random value among the N+1 pseudo-random values ​​is used as the new first initial value of the data bus. The following steps are performed: the first pseudo-random calculator function is used to iterate and calculate N times from the first initial value of the data bus to obtain N calculation results; the N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, are sequentially written into N+1 consecutive memory cells starting from the memory cell corresponding to the first address initial value; until there is a pseudo-random value among the N+1 pseudo-random values ​​obtained by the first pseudo-random calculator that is not equal to the N+1 pseudo-random values ​​cached by SDRAM, or the above method runs for more than a preset time.

3. The method according to claim 1, characterized in that, The step of determining the first pseudo-random number calculator function based on the data bus width of the synchronous dynamic random access memory (SDRAM) includes: The first target N value of the pseudo-random counter function is determined based on the SDRAM data bus width. Based on the correspondence between the N value and the feedback coefficient, determine the first target feedback coefficient corresponding to the first target N value; The first pseudo-random calculator function is determined based on the first target feedback coefficient.

4. The method according to claim 1, characterized in that, The method further includes: The second pseudo-random number calculator function is determined based on the number of address buses; Determine the second initial address value of the address bus and the second initial value of the data bus; Write the second initial value of the data bus into the storage unit corresponding to the second address initial value; The second pseudo-random calculator function is used to iteratively calculate from the second initial value of the data bus to obtain the pseudo-random calculation result of each iteration. Write the same pseudo-random calculation result into the storage cell corresponding to the pseudo-random calculation result until the pseudo-random calculation result covers all addresses of the SDRAM. Starting from the memory cell corresponding to the second initial address, read the pseudo-random value cached in SDRAM, and use the second pseudo-random calculator function to iteratively calculate from the second initial value to obtain the address of the next memory cell and the corresponding pseudo-random value cached in SDRAM. At the same time, use the second pseudo-random calculator to iteratively obtain the pseudo-random value from the second initial value. The pseudo-random value cached in SDRAM is compared with the pseudo-random value calculated by the corresponding second pseudo-random calculator until there is a pseudo-random value in the pseudo-random value calculated by the second pseudo-random calculator that is not equal to the pseudo-random value cached in SDRAM, or until all addresses of SDRAM have been read.

5. The method according to claim 4, characterized in that, The function for determining the second pseudo-random number generator based on the number of address buses includes: The second target N value of the pseudo-random counter function is determined based on the number of address buses; Based on the correspondence between N value and feedback coefficient, determine the second target feedback coefficient corresponding to the second target N value; The second pseudo-random calculator function is determined based on the second objective feedback coefficient.

6. A read / write reliability detection device, characterized in that, The device includes: The first function determination module is used to determine the first pseudo-random calculator function based on the data bus width of the synchronous dynamic random access memory (SDRAM). The first initial determination module is used to determine the first initial address value of the address bus and the first initial value of the data bus. The function calculation module is used to iteratively calculate N times from the first initial value of the data bus using the first pseudo-random calculator function to obtain N calculation results; The reliability determination module is used to determine the read / write reliability of the SDRAM by using the N calculation results, the N+1 pseudo-random values ​​composed of the first initial value of the data bus, and the first address initial value. The reliability determination module is used for: Starting from the storage unit corresponding to the first address initial value, N+1 pseudo-random values, including the N calculation results and the first initial value of the data bus, are sequentially written into N+1 consecutive storage units. N+1 pseudo-random values ​​cached in SDRAM are read from the N+1 consecutive memory cells, and N+1 pseudo-random values ​​are obtained iteratively from the first initial value of the data bus using the first pseudo-random calculator. The read / write reliability of SDRAM is determined by whether the N+1 pseudo-random values ​​calculated by the first pseudo-random calculator correspond to and are equal to the N+1 pseudo-random values ​​cached in SDRAM.

7. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the method as described in any one of claims 1-5.

8. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, performs the method as described in any one of claims 1-5.

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