Semiconductor memory device and memory system

Abstract

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, an error correction circuit, an input / output (I / O) gating circuit, and a control logic circuit. The memory cell array is coupled to a word line and a bit line, and is divided into subarray blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I / O gating circuit based on a command and an address. The control logic circuit stores the main data and the parity data in (k+1) target subarray blocks in a second direction among the subarray blocks, and controls the I / O gating circuit such that a portion of the (k+1) target subarray blocks stores both a portion of the main data and a portion of the parity data.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0170024, filed on December 18, 2019, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Example embodiments of the present disclosure relate to a memory device, and more particularly, to a semiconductor memory device and a memory system including the same. BACKGROUND

[0003] Semiconductor memory devices can be classified into nonvolatile memory devices, such as a flash memory device, and volatile memory devices, such as a dynamic random access memory (DRAM) device. Due to high-speed operation and high cost efficiency of the DRAM device, the DRAM device is frequently used for a system memory. As a design rule of the DRAM device is continuously reduced, bit errors of memory cells in the DRAM device can increase and cause deterioration of DRAM functionality, reliability, and yield. SUMMARY

[0004] Example embodiments of the present disclosure provide a semiconductor memory device and a memory system that allow enhanced performance and greater reliability.

[0005] According to some example embodiments, a semiconductor memory device includes a memory cell array, an error correction circuit, a control logic circuit, and an input / output (I / O) gating circuit connected between the memory cell array and the error correction circuit. The memory cell array includes a plurality of volatile memory cells coupled to a word line and a bit line. The memory cell array is divided into a plurality of subarray blocks arranged in a first direction and a second direction crossing the first direction. The error correction circuit generates parity data based on main data using an error correction code (ECC) represented by a generator matrix. The control logic circuit controls the error correction circuit and the I / O gating circuit based on a command and an address from an external memory controller. The control logic circuit stores the main data and the parity data in (k+1) target subarray blocks in the second direction among the plurality of subarray blocks. The control logic circuit controls the I / O gating circuit such that a portion of the (k+1) target subarray blocks stores a portion of the main data and a portion of the parity data. Here, k is an even number greater than two (2).

[0006] According to some example embodiments, a semiconductor memory device includes a memory cell array, an error correction circuit, a control logic circuit, and an input / output (I / O) gating circuit connected between the memory cell array and the error correction circuit. The memory cell array includes a plurality of memory bank arrays, each of the plurality of memory bank arrays including a plurality of volatile memory cells connected to a plurality of word lines and a plurality of bit lines. The error correction circuit is configured to generate parity data based on main data using an error correction code (ECC) represented by a generator matrix. The control logic circuit controls the error correction circuit based on a command and an address from an external memory controller. The error correction circuit: (i) stores the main data and the parity data in a target region within a target page in the memory cell array specified by the address, (ii) interleaves the main data and the parity data such that parity bits of the parity data are stored symmetrically with respect to a virtual center line in the target region, and (iii) changes a sub data pattern based on least significant bits (LSBs) of the address specifying the target page. The main data and the parity data stored in the target region constitute the sub data pattern.

[0007] According to additional embodiments, a memory system includes a semiconductor memory device and a memory controller controlling the semiconductor memory device. The semiconductor memory device includes a memory cell array, a first error correction circuit, a control logic circuit, and an input / output (I / O) gating circuit connected between the memory cell array and the error correction circuit. The memory cell array including a plurality of volatile memory cells coupled to word lines and bit lines is divided into a plurality of subarray blocks arranged in a first direction and a second direction crossing the first direction. The first error correction circuit generates parity data based on main data using a first error correction code (ECC) represented by a generator matrix. The control logic circuit controls the error correction circuit and the I / O gating circuit based on a command and an address from the memory controller. The control logic circuit stores the main data and the parity data in (k+1) target subarray blocks in the second direction among the plurality of subarray blocks, and controls the I / O gating circuit such that a portion of the main data and a portion of the parity data are stored in the (k+1) target subarray blocks. Here, k is an even number greater than 2.

[0008] According to further embodiments, a first error correction circuit included in a semiconductor memory device includes a first ECC including a column vector having elements that limit a position of a miss-corrected bit of a sub data unit to a certain symbol, the miss-corrected bit being generated from a plurality of error bits. A memory controller includes a second error correction circuit including a second ECC. The second ECC can correct error bits in the certain symbol and can correct the plurality of error bits and the miss-corrected bit. Accordingly, the memory controller can prevent a system failure caused by the plurality of error bits and the miss-corrected bit. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other features of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0010] Figure 1 is a block diagram illustrating a memory system according to an example embodiment of the present disclosure.

[0011] Figure 2 illustrates main data corresponding to a plurality of burst lengths in the memory system of Figure 1 according to an example embodiment.

[0012] Figure 3 is a block diagram illustrating an example of a memory controller in Figure 1 according to an example embodiment of the present disclosure.

[0013] Figure 4 is a block diagram illustrating an example of an ECC decoder in Figure 3 according to an example embodiment of the present disclosure.

[0014] Figure 5 is a block diagram illustrating a semiconductor memory device in Figure 1 according to an example embodiment of the present disclosure.

[0015] Figure 6 illustrates an example of a first memory bank array in the semiconductor memory device of Figure 5 according to an example embodiment of the present disclosure.

[0016] Figure 7 illustrates an example of a first memory bank array in the semiconductor memory device of Figure 5 according to an example embodiment of the present disclosure.

[0017] Figure 8 illustrates a portion of the first memory bank array in Figure 7 according to an example embodiment of the present disclosure.

[0018] Figure 9 is a block diagram illustrating an example of an error correction circuit in the semiconductor memory device of Figure 5 according to an example embodiment of the present disclosure.

[0019] Figure 10 is a block diagram illustrating an ECC decoder in the error correction circuit of Figure 9 according to an example embodiment of the present disclosure.

[0020] Figure 11 illustrates a relationship of first ECC and parity bits used in the error correction circuit of Figure 9 according to an example embodiment of the present disclosure.

[0021] Figure 12 An example of a first ECC according to example embodiments of the present disclosure is shown.

[0022] Figure 13 An example of how main data and parity data can be stored in subarray blocks in Figure 7 is shown.

[0023] Figures 14A-14C An example of first to eighth code groups in Figure 11 is shown.

[0024] Figure 15A and Figure 15B An example of how main data and parity data can be stored according to example embodiments of the present disclosure is shown.

[0025] Figure 16 is a block diagram showing another example of an error correction circuit in a semiconductor memory device according to example embodiments of the present disclosure. Figure 5

[0026] Figure 17 An example operation of an ECC encoder in the error correction circuit of Figure 16 according to example embodiments of the present disclosure is shown.

[0027] Figure 18 An example of a first ECC in the error correction circuit of Figure 16 according to example embodiments of the present disclosure is shown.

[0028] Figure 19 An example operation of the error correction circuit of Figure 16 is shown.

[0029] Figure 20 An example operation of the error correction circuit of Figure 16 is shown.

[0030] Figure 21 is a flowchart showing a method of operating a semiconductor memory device according to example embodiments of the present disclosure.

[0031] Figure 22 is a flowchart showing a method of operating a memory system according to example embodiments of the present disclosure.

[0032] Figure 23 is a block diagram of a semiconductor memory device according to example embodiments of the present disclosure.

[0033] Figure 24 is a cross-sectional view of a 3D chip structure of a semiconductor memory device employing Figure 23 according to example embodiments of the present disclosure.

[0034] ​Figure 25 is a diagram illustrating a semiconductor package including a stacked memory device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the drawings.

[0036] Figure 1 is a block diagram illustrating a memory system according to an example embodiment of the present disclosure. Referring to Figure 1 , the memory system 20 can include a memory controller 100 (e.g., an external memory controller) and a semiconductor memory device 200. The memory controller 100 can control overall operations of the memory system 20. The memory controller 100 can control overall data exchange between an external host and the semiconductor memory device 200. For example, the memory controller 100 can write data into or read data from the semiconductor memory device 200 in response to a request from the host. In addition, the memory controller 100 can issue an operation command for controlling the semiconductor memory device 200 to the semiconductor memory device 200.

[0037] In an example embodiment, the semiconductor memory device 200 is a memory device (such as a dynamic random access memory (DRAM), a double data rate 5 (DDR5) synchronous DRAM (SDRAM), a DDR6 SDRAM) including a plurality of dynamic (volatile) memory cells or a stacked memory device (such as a high bandwidth memory (HBM)). In addition, the memory controller 100 can transmit a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device 200 and exchange main data MD with the semiconductor memory device 200.

[0038] As shown in Figure 1 , the memory controller 100 can include an error correction circuit 130. The error correction circuit 130 can generate parity data based on the main data MD to be transmitted to the semiconductor memory device 200, can store the parity data, can generate check bits based on the main data MD received from the semiconductor memory device 200, and can correct an error bit in the main data MD based on a comparison of the system parity data and the check bits on a symbol basis.

[0039] The semiconductor memory device 200 includes a memory cell array (MCA) 300 storing main data MD, an error correction circuit 400, and a control logic circuit 210. The error correction circuit 400 can be referred to as a first error correction circuit. The memory cell array 300 can be divided into a plurality of subarray blocks arranged in a first direction and a second direction crossing the first direction.

[0040] The error correction circuit 400 may generate parity data by performing ECC encoding on the main data MD using an error correction code (ECC) represented by a generator matrix, and may use the parity data to detect and / or correct at least one error bit in the main data MD read from the memory cell array 300 by performing ECC decoding on the main data MD.

[0041] The control logic circuit 210 may control the error correction circuit 400 to store the main data MD and the parity data in the (k+1) target sub-array blocks in the second direction among the sub-array blocks, so that some of the (k+1) target sub-array blocks store both the main data and the parity data. Here, k is an even number greater than 2.

[0042] The main data MD includes a plurality of data bits, and the plurality of data bits may be divided into a plurality of sub-data units. The ECC may include a plurality of column vectors divided into a plurality of code groups corresponding to the sub-data units and parity data. The column vectors may have elements that limit the locations of the sub-data units where error correction bits occur. The error correction bits are generated by a plurality of error bits in the main data MD, and the error correction circuit 400 cannot correct these error bits by using the ECC. If the data read from the memory cell array 300 includes a plurality of error bits that are undetectable and / or uncorrectable by the error correction circuit 400, the error correction circuit 130 may correct the error bits in the sub-data unit including the plurality of error bits.

[0043] The semiconductor memory device 200 may perform a burst operation. Here, a burst operation refers to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller 100. The basic unit of a burst operation may be referred to as a burst length BL. In an example embodiment, the burst length BL refers to the number of operations of continuously reading or writing data by sequentially increasing or decreasing an initial address.

[0044] Figure 2 FIG. 1 shows a method for Figure 1 The main data corresponding to multiple burst lengths in the memory system. Figure 2 , main data MD corresponding to a plurality of burst lengths is input to / output from the semiconductor memory device 200. The main data MD includes data segments MD_SG1 to MD_SGt (t is a natural number equal to or greater than 8), and the data segments MD_SG1 to MD_SGt respectively correspond to a plurality of burst lengths. Figure 2 It is assumed that the burst length is 8. However, example embodiments of the present disclosure are not limited thereto. Main data MD corresponding to a plurality of burst lengths may be stored in the memory cell array 300 of the semiconductor memory device 200 .

[0045] Figure 3 is a block diagram illustrating an example of a memory controller in a memory system according to an example embodiment of the present disclosure. Figure 1 Figure 3 Referring to FIG. 1, the memory controller 100 can include a central processing unit (CPU) 110, a data buffer 120, an error correction circuit 130, a command buffer 180, and an address buffer 190. The error correction circuit 130 can include a parity generator 140, a buffer 145, a memory 150 storing a second ECC (ECC2) 155, and an ECC decoder 160. The CPU 110 receives a request REQ and data DTA from a host, and provides the data DTA to the data buffer 120 and the parity generator 140. The data buffer 120 buffers the data DTA to provide first main data MD1 to the semiconductor memory device 200. The parity generator 140 is connected to the memory 150, performs ECC encoding on the data DTA using the second ECC 155 to generate parity data PRTc, and stores the parity data PRTc in the buffer 145.

[0046] In a read operation of the semiconductor memory device 200, the ECC decoder 160 receives second main data MD2 from the semiconductor memory device 200, performs ECC decoding on the second main data MD2 using the second ECC 155 and the system parity data PRTc on a symbol basis, and can provide corrected main data C_MD2 to the CPU 110. The CPU 110 provides the corrected main data C_MD2 to the host.

[0047] The command buffer 180 stores a command CMD corresponding to the request REQ, and transmits the command CMD to the semiconductor memory device 200 under control of the CPU 110. The address buffer 190 stores an address ADDR, and transmits the address ADDR to the semiconductor memory device 200 under control of the CPU 110.

[0048] Figure 4 is a block diagram illustrating an example of an ECC decoder in a memory system according to an example embodiment of the present disclosure. Figure 3 Figure 4 ​​The ECC decoder 160 can include a check bit generator 161, a syndrome generator 163, and a data corrector 165. The check bit generator 161 receives the second main data MD2 and generates check bits CHBc corresponding to the second main data MD2 using the second ECC 155. The syndrome generator 163 compares the system parity data PRTc and the check bits CHBc on a symbol basis to generate syndrome data SDRc indicating whether the second main data MD2 includes at least one error bit and indicating a location of the at least one error bit. The data corrector 165 receives the second main data MD2 and corrects error bits in the second main data MD2 on a symbol basis based on the syndrome data SDRc to output corrected main data C_MD2.

[0049] A plurality of error bits in the second main data MD2 provided from the semiconductor memory device 200 and mis-corrected bits generated due to the plurality of error bits are gathered in one symbol or some symbols, and the data corrector 165 can correct error bits in the second main data MD2 on a symbol basis.

[0050] Figure 5 is a block diagram of a semiconductor memory device in Figure 1 according to an example embodiment of the present disclosure. Referring to Figure 5 The semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, a data input / output (I / O) buffer 295, a refresh counter 245, and an error correction circuit 400.

[0051] The memory cell array 300 includes a first memory bank array 310 to an eighth memory bank array 380. The row decoders 260 include a first memory bank row decoder 260a to an eighth memory bank row decoder 260h coupled to the first memory bank array 310 to the eighth memory bank array 380, respectively. The column decoders 270 include a first memory bank column decoder 270a to an eighth memory bank column decoder 270h coupled to the first memory bank array 310 to the eighth memory bank array 380, respectively. The sense amplifier units 285 include a first memory bank sense amplifier 285a to an eighth memory bank sense amplifier 285h coupled to the first memory bank array 310 to the eighth memory bank array 380, respectively. The first memory bank array 310 to the eighth memory bank array 380, the first memory bank row decoder 260a to the eighth memory bank row decoder 260h, the first memory bank column decoder 270a to the eighth memory bank column decoder 270h, and the first memory bank sense amplifier 285a to the eighth memory bank sense amplifier 285h can form first to eighth memory banks. In addition, each of the first memory bank array 310 to the eighth memory bank array 380 can be divided into a plurality of subarray blocks arranged in a first direction and a second direction. Each of the first memory bank array 310 to the eighth memory bank array 380 includes a plurality of memory cells MC coupled to a word line WL and a bit line BTL.

[0052] Although the semiconductor memory device 200 is shown as including eight memory banks in Figure 5 FIG. 1, example embodiments of the present disclosure are not limited thereto, and the semiconductor memory device 200 can include any number of memory banks.

[0053] The address register 220 receives an address ADDR including a memory bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100.

[0054] The address register 220 can provide the received memory bank address BANK_ADDR to the memory bank control logic 230, the received row address ROW_ADDR to the row address multiplexer 240, and the received column address COL_ADDR to the column address latch 250. The memory bank control logic 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first memory bank row decoder 260a to the eighth memory bank row decoder 260h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and one of the first memory bank column decoder 270a to the eighth memory bank column decoder 270h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0055] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and can receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 can selectively output one of the row address ROW_ADDR and the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 240 can be applied to the first to eighth memory bank row decoders 260a to 260h.

[0056] An activated one of the first to eighth memory bank row decoders 260a to 260h can decode the row address RA output from the row address multiplexer 240 and can activate a word line corresponding to the row address RA. For example, the activated one of the first to eighth memory bank row decoders 260a to 260h can apply a word line driving voltage to the word line corresponding to the row address RA.

[0057] The column address latch 250 can receive the column address COL_ADDR from the address register 220 and can temporarily store the received column address COL_ADDR. In an example embodiment, in a burst mode, the column address latch 250 can generate a column address that is incremented from the received column address COL_ADDR. The column address latch 250 can apply the temporarily stored or generated column address to the first to eighth memory bank column decoders 270a to 270h.

[0058] An activated one of the first to eighth memory bank column decoders 270a to 270h can decode the column address COL_ADDR output from the column address latch 250 and can control the input / output gate circuit 290 to output data corresponding to the column address COL_ADDR or a mapped column address. The I / O gate circuit 290 includes a circuit for gating input / output data. The I / O gate circuit 290 also includes a read data latch for storing data output from the first to eighth memory bank arrays 310 to 380 and a write driver for writing data to the first to eighth memory bank arrays 310 to 380.

[0059] A codeword CW to be read from one of the first memory bank array 310 to the eighth memory bank array 380 can be sensed by a sense amplifier coupled to the one memory bank array from which the codeword is to be read, and can be stored in a read data latch. The codeword CW stored in the read data latch is ECC-decoded by the error correction circuit 400, and can be provided to the memory controller 100 via the data I / O buffer 295. Data (or main data) MD to be written into one of the first memory bank array 310 to the eighth memory bank array 380 can be provided from the memory controller 100 to the data I / O buffer 295. The main data MD is provided to the error correction circuit 400.

[0060] The error correction circuit 400 performs ECC encoding on the main data MD to generate parity data, and provides a codeword CW including the main data MD and the parity data to the I / O gating circuit 290. The I / O gating circuit 290 can store the main data MD and the parity data in (k+1) target subarray blocks in a second direction among the subarray blocks based on a first control signal CTL from the control logic circuit 210, such that a portion of the (k+1) target subarray blocks stores both a portion of the main data and a portion of the parity data. Here, k is an even number greater than 2.

[0061] When the error correction circuit 400 performs the ECC encoding and the ECC decoding, the error correction circuit 400 can use a first ECC represented by a generator matrix. For example, a data structure / data format of the first ECC can be a generator matrix. The first ECC can include a plurality of column vectors corresponding to data bits of the data (or main data) MD and parity bits of the parity data, the column vectors can be divided into a plurality of code groups corresponding to a plurality of sub-data units and the parity data. The data bits can be divided into the plurality of sub-data units.

[0062] In addition, the column vectors can have elements that limit a position of an error correction bit of a sub-data unit, the error correction bit being generated from a plurality of error bits of the main data MD, the plurality of error bits being uncorrectable by the ECC. That is, the column vectors can have elements that place the error correction bit and the plurality of error bits in one symbol or a plurality of symbols. The symbol can include one sub-data unit or two adjacent sub-data units.

[0063] Accordingly, when the main data MD includes the plurality of error bits that the error correction circuit 400 is unable to correct / detect, because the plurality of error bits and the error correction bit are gathered in one sub-data unit or two adjacent sub-data units, the memory controller 100 can correct the plurality of error bits in the main data MD on a symbol basis at a system level.

[0064] The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200.

[0065] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 may generate a first control signal CTL1 for controlling the I / O gating circuit 290 and a second control signal CTL2 for controlling the error correction circuit 400.

[0066] Figure 6 The exemplary embodiment according to the present disclosure is shown Figure 5 An example of a first memory bank array in a semiconductor memory device. Figure 6 The first memory bank array 310 includes a plurality of word lines WL1 to WLm (where m is a natural number greater than 2), a plurality of bit lines BTL1 to BTLn (where n is a natural number greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLn. Each memory cell MC includes an access (cell) transistor coupled to a corresponding word line among the word lines WL1 to WLm and a corresponding bit line among the bit lines BTL1 to BTLn, and a storage (cell) capacitor coupled to the cell transistor. In other words, each memory cell MC has a DRAM cell structure.

[0067] Figure 7 The exemplary embodiment according to the present disclosure is shown Figure 5 An example of a first memory bank array in a semiconductor memory device. Figure 7 In the first memory bank array 310, I sub-array blocks SCB as row blocks may be arranged in a second direction D2, and J sub-array blocks SCB as column blocks may be arranged in a first direction D1 substantially perpendicular to the second direction D2. I and J represent the number of sub-array blocks SCB in the second direction and the first direction, respectively, and are natural numbers greater than 2. Multiple bit lines, multiple word lines, and multiple memory cells connected to the bit lines and word lines are arranged in each sub-array block SCB.

[0068] I+1 sub word line driver regions SWB can be disposed between the sub array blocks SCB in the second direction D2. Sub word line drivers can be disposed in the sub word line driver regions SWB. J+1 bit line sense amplifier regions BLSAB can be disposed between, for example, the sub array blocks SCB in the first direction Dl. Bit line sense amplifiers for sensing data stored in the memory cells can be disposed in the bit line sense amplifier regions BLSAB.

[0069] A plurality of conjunction regions CONJ can be disposed adjacent to the sub word line driver regions SWB and the bit line sense amplifier regions BLSAB. A voltage generator is disposed in each conjunction region CONJ. Reference is made to Figure 8 A portion 390 of the first memory array 310 is described.

[0070] Figure 8 A portion of a first memory array in accordance with example embodiments of the present disclosure is shown. Figure 7 Reference is made to Figure 8 In the portion 390 of the first memory array 310, sub array blocks SCB, bit line sense amplifier regions BLSAB, sub word line driver regions SWB, and conjunction regions CONJ are arranged.

[0071] The sub array block SCB includes a plurality of word lines WL1 to WL4 extending in a row direction (second direction D2) and a plurality of bit line pairs BTL1 and BTLB1 to BTL2 and BTLB2 extending in a column direction (first direction Dl). The sub array block SCB includes a plurality of memory cells MC disposed at intersections between the word lines WL1 to WL4 and the bit line pairs BTL1 and BTLB1 to BTL2 and BTLB2.

[0072] Reference is made to Figure 8 The sub word line driver region SWB includes a plurality of sub word line drivers (SWD) 551, 552, 553, and 554 that drive the word lines WL1 to WL4, respectively. The sub word line drivers 551 and 552 can be disposed in the sub word line driver region SWB on a left side (in this example) relative to the sub array block SCB. Additionally, the sub word line drivers 553 and 554 can be disposed in the sub word line driver region SWB on a right side (in this example) relative to the sub array block SCB.

[0073] The bit line sense amplifier region BLSAB includes bit line sense amplifiers BLSA 560 and 570 coupled to the bit line pairs BTL1 and BTLB1 to BTL2 and BTLB2 and local sense amplifier (LSA) circuits 580 and 590. The bit line sense amplifier 560 can sense and amplify a voltage difference between the bit line pairs BTL and BTLB to provide the amplified voltage difference to a local I / O line pair LIO1 and LIOB1.

[0074] Local sense amplifier circuit 580 controls the connection between local I / O line pair LIO1 and LIOB1 and global I / O line pair GIO1 and GIOB1, and local sense amplifier circuit 590 controls the connection between local I / O line pair LIO2 and LIOB2 and global I / O line pair GIO2 and GIOB2.

[0075] like Figure 8 As shown in FIG, bit line sense amplifiers 560 and 570 may be alternately arranged at the upper and lower portions of the sub-array block SCB. A junction region CONJ is provided adjacent to the bit line sense amplifier region BLSAB, the sub-word line driver region SWB, and the sub-array block SCB. A plurality of voltage generators (VG) 510, 520, 530, and 540 may be provided in the junction region CONJ.

[0076] Figure 9 is a diagram showing an example embodiment according to the present disclosure Figure 5 A block diagram of an example of an error correction circuit in a semiconductor memory device. Figure 9 , the error correction circuit 400a includes an (ECC) memory 410, an ECC encoder 430, and an ECC decoder 450. The ECC encoder 430 and the ECC decoder 450 may implement the ECC engine 420. The ECC memory 410 stores a first ECC 415. The first ECC 415 may be represented by a generator matrix (e.g., the data format / structure of the first ECC 415 may be a generator matrix) and may include a plurality of column vectors corresponding to data bits in the main data (e.g., MD) and the parity data.

[0077] The ECC encoder 430 is connected to the ECC memory 410 and may perform ECC encoding on the main data MD using the first ECC 415 stored in the ECC memory 410 to generate parity data PRT during a write operation of the semiconductor memory device 200. The ECC encoder 430 may provide a codeword CW including the main data MD and the parity data PRT to the I / O gating circuit 290.

[0078] ECC decoder 450 is connected to ECC memory 410 and can receive a codeword CW including main data MD and parity data PRT. It can perform ECC decoding on the main data MD based on the parity data PRT using a first ECC 415 to correct and / or detect error bits in the main data MD, and can output corrected main data C_MD. The first ECC 415 can be a single error correction and double error detection (SECDED) code capable of correcting one error bit and detecting two error bits in the main data MD. ECC 415 can be implemented using one of various codes.

[0079] Although the reference Figure 9The ECC memory 410 is described as being incorporated into the ECC encoder 430 and the ECC decoder 450, but in example embodiments, the ECC memory 410 can be implemented with exclusive OR gates within the ECC encoder 430 and the ECC decoder 450.

[0080] Figure 10 is a block diagram of an ECC decoder in an error correction circuit according to an example embodiment of the present disclosure. Figure 9 Referring to Figure 10 , the ECC decoder 450 includes a check bit generator 451, a syndrome generator 453, and a data corrector 455. The check bit generator 451 generates check bits CHB based on data bits in the main data MD using the first ECC 415. The syndrome generator 453 generates syndrome data SDR indicating whether an error bit occurs and a location of the error bit based on a comparison of the check bits CHB and parity bits of the parity data PRT. The data corrector 455 receives the main data MD and the syndrome data SDR, corrects the error bit in the main data MD, and outputs corrected main data C_MD.

[0081] In Figure 9 and Figure 10 , the main data MD includes 2 p bits (where p is an integer equal to or greater than 7) data bits, and the parity data PRT includes (p+1) bits parity bits. However, in other example embodiments, the main data MD includes 3×2 q bits (where q is an integer equal to or greater than 6) data bits, and the parity data PRT includes (q+2) bits parity bits.

[0082] Figure 11 shows a relationship of the first ECC and the parity bits used in the error correction circuit of Figure 9 according to an example embodiment of the present disclosure. In Figure 11 , it is assumed that the main data MD includes a plurality of sub data units SDU1 to SDUx, and the parity data PRT includes 8 bits parity bits PB1 to PB8. In Figure 11 , it is assumed that x is a natural number equal to or greater than 8.

[0083] Referring to Figure 11 , the first ECC 415 can be divided into a plurality of code groups CG1 to CGx and PCG corresponding to the plurality of sub data units SDU1 to SDUx and the parity data PRT, respectively. The code group PCG can include a plurality of column vectors PV1 to PV8 corresponding to the parity bits PB1 to PB8 of the parity data PRT.

[0084] Figure 12An example of a first ECC according to an example embodiment of the present disclosure is shown. In Figure 12 In the example shown in FIG. 3, it is assumed that the main data MD includes 128-bit data bits d0 to d127. That is, it is assumed that x is 8 in Figure 11 Figure 12 The data bits d0 to d127 of the main data MD can be divided into first to eighth sub-data units SDU11 to SDU18. Each of the first to eighth sub-data units SDU11 to SDU18 includes 16-bit data bits. The first ECC ECC1a includes first to eighth code groups CG11 to CG18 corresponding to the first to eighth sub-data units SDU11 to SDU18, respectively.

[0085] Figure 13 The main data and the parity data stored in the sub-array blocks in Figure 7 In Figure 13 In order to facilitate explanation, an I / O gating circuit 290 is also shown in FIG. 3, which can include a plurality of switches 291 to 29s that are closed / opened in response to a first control signal CTL1. Here, s is an integer greater than 2. Referring to Figure 13 The main data MD and the parity data PRT are stored in (k+1) target sub-array blocks among row blocks arranged in the second direction D2 in the sub-array blocks SCB in Figure 7 Here, k is an even number greater than 3.

[0086] If the target sub-array blocks include the first to (k+1)th sub-array blocks identified by the index SINX, some of the main data MD and the parity data PRT are stored in the k / 2th, (k / 2+1)th, and (k / 2+3)th sub-array blocks, and the remaining part of the main data MD is stored in the other sub-array blocks except for the k / 2th, (k / 2+1)th, and (k / 2+3)th sub-array blocks. The sub-array blocks among the first to (k+1)th sub-array blocks that include the data bits of some of the main data MD are referred to as a first group of sub-array blocks (for example, the sub-array blocks among the first to (k+1)th sub-array blocks that do not include the parity bits of the parity data PRT are referred to as a first group of sub-array blocks), and the sub-array blocks among the first to (k+1)th sub-array blocks that include both the data bits of the remaining part of the main data MD and the parity bits of the parity data PRT are referred to as a second group of sub-array blocks. In Figure 13 In FIG. 3, solid arrows indicate a path in which the main data MD is stored, and dotted arrows indicate a path in which the parity data PRT is stored. ​

[0087] The switches 291 to 29 s in the I / O gating circuit 290 may respectively provide the main data MD and the parity data PRT to the corresponding sub-array blocks in response to the first control signal CTL1 .

[0088] Figures 14A-14C Show Figure 11 The first to eighth code groups in . Figures 14A-14C In the example, we assume that k is 8. Figures 14A-14C The first code group CG11 includes column vectors CV11 to CV116 corresponding to data bits d0 to d15 of the first sub-data unit SDU11. The column vectors CV11 to CV116 have the same elements as one another, and data bits d0 to d15 are stored in sub-array block SCB1. The second code group CG12 includes column vectors CV21 to CV216 corresponding to data bits d16 to d31 of the second sub-data unit SDU12. The column vectors CV21 to CV216 have the same elements as one another, and data bits d16 to d31 are stored in sub-array block SCB2. The third code group CG13 includes column vectors CV31 to CV316 corresponding to data bits d32 to d47 of the third sub-data unit SDU13. The column vectors CV31 to CV316 have the same elements as one another, and data bits d32 to d47 are stored in sub-array block SCB3.

[0089] In addition, the fourth code group CG14' includes column vectors CV41 to CV415 corresponding to data bits d48 to d62 of the fourth sub-data unit SDU14, and a column vector PV7 corresponding to parity bit PB7. Column vectors CV41 to CV415 have the same elements as one another, and each of column vectors CV41 to CV415 is different from column vector PV7. Data bits d48 to d62 and parity bit PB7 are stored in subarray block SCB4. Parity bits PB1 to PB6 and data bits d63 and d95 are stored in subarray block SCB5. Code group PCG' includes column vectors PV1 to PV6 corresponding to parity bits PB1 to PB6, and column vectors CV416 and CV616 corresponding to data bits d63 and d95. The fifth code group CG15 includes column vectors CV51 to CV516 corresponding to data bits d64 to d79 of the fifth sub-data unit SDU15, the column vectors CV51 to CV516 having the same elements as one another, and the data bits d64 to d79 are stored in the sub-array block SCB6.

[0090] In addition, the sixth code group CG16' includes column vectors CV61 to CV615 corresponding to the data bits d80 to d94 of the sixth sub-data unit SDU16 and a column vector PV8 corresponding to the parity bit PB8. The column vectors CV61 to CV615 have the same elements as each other, each of the column vectors CV61 to CV615 is different from the column vector PV8, and the data bits d80 to d94 and the parity bit PB8 are stored in the sub-array block SCB7. The seventh code group CG17 includes column vectors CV71 to CV716 corresponding to the data bits d96 to d111 of the seventh sub-data unit SDU17, the column vectors CV71 to CV716 have the same elements as each other, and the data bits d96 to d111 are stored in the sub-array block SCB8. The eighth code group CG18 includes column vectors CV81 to CV816 corresponding to the data bits d112 to d127 of the eighth sub-data unit SDU18, the column vectors CV81 to CV816 have the same elements as each other, and the data bits d112 to d127 are stored in the sub-array block SCB9.

[0091] In Figures 14A-14C the code groups CG11, CG12, CG13, CG15, CG17, and CG18 including the column vectors corresponding to the data bits are referred to as a first group of code groups, and the code groups CG14', PCG', and CG16' including the column vectors corresponding to the data bits and the parity bit are referred to as a second group of code groups. The column vectors in each of the code groups of the first group of code groups have the same elements. Therefore, because the result of an OR operation on the two column vectors in one of the code groups of the first group of code groups is the same as the column vector in one of the code groups of the first group of code groups, when a plurality of error bits occur in a first sub-data unit among a plurality of sub-data units corresponding to the first group of code groups, the error correction bit generated by the plurality of error bits also occurs in the first sub-data unit.

[0092] In addition, the seventh element of each of the column vectors in the code groups CG14' and PCG' of the second group of code groups has "0", and the seventh element of each of the column vectors in the code group CG16' of the second group of code groups has "1". Therefore, the column vector corresponding to the result of an XOR operation on the two column vectors in one of the code groups of the second group of code groups includes the seventh element having "0", and the column vector indicating the error correction bit is similar to one of the column vectors in the code groups CG14' and PCG'. Therefore, the memory controller 100 can correct the error correction bit.

[0093] That is, the column vectors in the first ECC 415 have elements that limit the position of the occurrence of the error correction bit of the sub-data unit, the error correction bit being generated by a plurality of error bits of the main data MD, the plurality of error bits being uncorrectable by the first ECC 415.

[0094] Figure 15A and15B The storage of main data and parity data according to example embodiments of the present disclosure is shown. Referring to Figure 15A and Figure 15B , Figure 5 The control logic circuit 210 in the control logic circuit 210 controls the error correction circuit 400 to store the main data MD and the parity data PRT in a target region of a target page of an array of memory cells specified by the row address ROW_ADDR to interleave the main data MD and the parity data PRT such that parity bits PB of the parity data PRT are stored symmetrically with respect to a virtual center line CL in the target region and the sub data patterns EP11, EP12 and EP13 and EP21, EP22 and EP23 are changed based on the least significant bits (LSBs) of the row address ROW_ADDR specifying the target page. The main data MD and the parity data PRT stored in the target region can constitute the sub data patterns EP11, EP12 and EP13 and EP21, EP22 and EP23.

[0095] Referring to Figure 15A When the LSBs of the row address ROW_ADDR specify an even target page (e.g., when the LSBs of the row address ROW_ADDR specify the starget page and s is even), the sub data pattern EP11 includes data bits DB and parity bits PB stored in memory cells identified by cell indices 0 to 3, the sub data pattern EP12 includes data bits DB and parity bits PB stored in memory cells identified by cell indices 4 to 7, and the sub data pattern EP13 includes data bits DB and parity bits PB stored in memory cells identified by cell indices 8 and 9. Referring to Figure 15B When the LSBs of the row address ROW_ADDR specify an odd target page (e.g., when the LSBs of the row address ROW_ADDR specify the starget page and s is odd), the sub data pattern EP21 includes data bits DB and parity bits PB stored in memory cells identified by cell indices 0 and 1, the sub data pattern EP22 includes data bits DB and parity bits PB stored in memory cells identified by cell indices 2 to 5, and the sub data pattern EP23 includes data bits DB and parity bits PB stored in memory cells identified by cell indices 6 to 9.

[0096] Figure 16 is a block diagram showing another example of an error correction circuit in a semiconductor memory device according to example embodiments of the present disclosure. Referring to Figure 5 Figure 16 ​The error correction circuit 400b includes an (ECC) memory 410a, an ECC encoder 430a, an ECC decoder 450a, a data interleaver 460, a parity interleaver 465, a data deinterleaver 470, a parity deinterleaver 475, and a data deinterleaver 480.

[0097] The ECC memory 410a stores a first ECC (ECC1) 415a, the ECC encoder 430a is connected to the ECC memory 410a, and the ECC decoder 450a is connected to the ECC memory 410a. The ECC encoder 430a and the ECC decoder 450a can implement an ECC engine (e.g., 420) of the memory device 400. Figure 9 The data interleaver 460 can selectively interleave the main data MD based on the LSB of the row address, LSB_RA, to provide intermediate main data IRMD to the ECC encoder 430a. The ECC encoder 430a performs ECC encoding on the intermediate main data IRMD using the first ECC 415a to generate parity data PRT2 and provides the parity data PRT2 to the parity interleaver 465.

[0098] The parity interleaver 465 can selectively interleave the parity data PRT2 based on the LSB of the row address, LSB_RA, to output intermediate parity data IRPRT2. The main data MD and the intermediate parity data IRPRT2 as a codeword CW1 are stored in a target region of a target page by the I / O gating circuit 290 in the memory device 400. Figure 5 The parity bits of the intermediate parity data IRPRT2 are symmetrically stored with respect to a virtual center line in the target region.

[0099] The data deinterleaver 470 can deinterleave the main data MD read from the target region to provide intermediate data DRMD to the ECC decoder 450a. The parity deinterleaver 475 can selectively interleave the parity data IRPRT2 read from the target region based on the LSB of the row address, LSB_RA, to output data DRPRT2. The ECC decoder 450a performs ECC decoding on the intermediate data DRMD using the parity data DRPRT2 to correct error bits and provides corrected intermediate data C_DRMD to the data deinterleaver 480. The data deinterleaver 480 can selectively interleave the corrected intermediate data C_DRMD based on the LSB of the row address, LSB_RA, to output corrected data C_MD.

[0100] In an example embodiment, when the LSB of the row address, LSB_RA, specifies an even target page, the order of the bits of the main data MD and the parity data PRT2 can be maintained. In an example embodiment, when the LSB of the row address, LSB_RA, specifies an odd target page, the order of the bits of the main data MD can be maintained, and the order of the bits of the parity data PRT2 can be reversed.

[0101] Figure 17 An example operation of an ECC encoder in an error correction circuit of Figure 16 according to an example embodiment of the disclosure is shown. Referring to Figure 17 When the main data includes the data bits d0 to d5, the ECC encoder 430a performs ECC encoding on the data bits d0 to d5 using the first ECC 415a to generate the parity data PRT2 including the parity bits P0 to P3.

[0102] Figure 18 An example of a first ECC in an error correction circuit of Figure 16 according to an example embodiment of the disclosure is shown. Referring to Figure 18 The first ECC ECC11a can include column vectors CV0 to CV9 corresponding to the data bits d0 to d5 and the parity bits P0 to P3. Each of the column vectors CV0 to CV9 can correspond to a respective one of the bits d0, p0, d1, d2, p1, p2, d3, d4, p3, and d5. Referring back to Figure 15A The sub data pattern EP11 corresponds to the column vectors CV0 to CV3, the sub data pattern EP12 corresponds to the column vectors CV4 to CV7, and the sub data pattern EP13 corresponds to the column vectors CV8 and CV9.

[0103] Thus, if multiple error bits occur in the sub data pattern EP11, the error correction bits generated by the multiple error bits occur in the sub data pattern EP11 or the sub data pattern EP12. If multiple error bits occur in the sub data pattern EP12, the error correction bits generated by the multiple error bits occur in the sub data pattern EP11 or the sub data pattern EP12. If multiple error bits occur in the sub data pattern EP13, the error correction bits generated by the multiple error bits occur in the sub data pattern EP12 or the sub data pattern EP13.

[0104] That is, when a plurality of error bits occur in one of the sub data patterns EP11, EP12, and EP13, the column vector in the first ECC ECC11a has elements that limit the positions of the occurrence of the error correction bits to at most two sub data patterns, the error correction bits being generated by the plurality of error bits. The second error correction circuit 130 in the memory controller 100 has an error correction capability for correcting error bits in two sub data patterns, and thus the second error correction circuit 130 can correct the plurality of error bits and the error correction bits.

[0105] The above description with reference to Figure 18 is applicable to Figure 15B the example. The column vector in the first ECC ECC11a has elements that limit the positions of the occurrence of the error correction bits to at most two sub data patterns, the error correction bits being generated by the plurality of error bits, such that the error correction bits occur in the sub data pattern in which the plurality of error bits occur or in another sub data pattern.

[0106] Figure 19 An example operation of the error correction circuit of Figure 16 when the LSB of the row address specifies an even target page according to an example embodiment of the present disclosure is shown. Referring to Figure 19 , when the LSB LSB_RA of the row address specifies an even target page, the data interleaver 460 maintains the order of the data bits ed0 to ed5 of the main data MD to output the intermediate data IRMD1, the ECC encoder 430a performs ECC encoding on the intermediate data IRMD1 to generate the parity data PRT2, the parity interleaver 465 maintains the order of the parity bits p0 to p3 of the parity data PRT2 based on the LSB LSB_RA of the row address to output the parity data IPRT21, and the data bits ed0 to ed5 and the parity bits P0 to P3 of the parity data IPRT21 are stored in the target area 395.

[0107] Figure 20 An example operation of the error correction circuit of Figure 16 when the LSB of the row address specifies an odd target page according to an example embodiment of the present disclosure is shown.

[0108] Referring to Figure 20When the LSB of the row address, LSB_RA, specifies an odd target page, the data interleaver 460 reverses the order of the data bits od0 to od5 of the main data MD to output intermediate data IRMD2, the ECC encoder 430a performs ECC encoding on the intermediate data IRMD2 to generate parity data PRT2, the parity interleaver 465 reverses the order of the parity bits p0 to p3 of the parity data PRT2 based on the LSB of the row address, LSB_RA, to output parity data IPRT22, the data bits od0 to od5 and the parity bits P3 to P0 of the parity data IPRT22 are stored in the target area 395.

[0109] The error correction circuit 400b interleaves the parity data PRT2 in response to the LSB of the row address, LSB_RA, specifying an even target page such that the order of the parity bits of the parity data PRT2 is maintained, and interleaves the parity data PRT2 in response to the LSB of the row address, LSB_RA, specifying an odd target page such that the order of the parity bits of the parity data PRT2 is reversed.

[0110] Figure 21 is a flowchart illustrating a method of operating a semiconductor memory device according to an example embodiment of the present disclosure. Referring to Figures 5-21 In a method of operating the semiconductor memory device 200 including the memory cell array 300, the error correction circuit 400 generates parity data PRT based on main data MD by using a first ECC 415 (S110).

[0111] The first ECC 415 can be represented by a generator matrix, can include a plurality of column vectors, and the column vectors can be divided into a plurality of code groups corresponding to sub-data units of the main data and the parity data. The column vectors can have elements that limit positions of error correction bits that occur in the sub-data units, the error correction bits being generated from a plurality of error bits of the main data. The plurality of error bits are uncorrectable by the first ECC 415.

[0112] The error correction circuit 400 stores the main data MD and the parity data PRT in the memory cell array 300 via the I / O gating circuit 290 (S120). The error correction circuit 400 reads the main data MD and the parity data PRT from the memory cell array 300 via the I / O gating circuit 290 (S130). The error correction circuit 400 generates check bits CHB based on the main data MD by using the first ECC 415 (S140). The error correction circuit 400 corrects error bits in the main data MD based on a comparison of the parity data PRT and the check bits CHB (S150).

[0113] Although the main data MD includes a plurality of error bits that are uncorrectable and / or undetectable by the error correction circuit 400, the first ECC 415 has a column vector for placing uncorrectable bits in one symbol, and the memory controller 100 can correct the plurality of error bits and the uncorrectable bits on a symbol basis. One symbol can include a data unit or two adjacent data units.

[0114] Figure 22 is a flowchart illustrating a method of operating a memory system according to an example embodiment of the present disclosure. Referring to Figures 1-20 and Figure 22 In a method of operating a memory system 20 including a semiconductor memory device 200 and a memory controller 100 that controls the semiconductor memory device 200, an error correction circuit 130 in the memory controller 100 generates parity data PRTc based on write data to be transmitted to the semiconductor memory device 200 by using a second ECC 155 (S210), and stores the parity data PRTc in a buffer 145. The memory controller 100 transmits the write data to the semiconductor memory device 200 (S220).

[0115] The error correction circuit 400 in the semiconductor memory device 200 performs ECC encoding on the write data using the first ECC 415 to generate parity data, and stores the write data and the parity data in the memory cell array 300. The error correction circuit 400 in the semiconductor memory device 200 reads data and parity data from the memory cell array 300 in response to a read command, performs ECC decoding on the read data using the first ECC 415, and transmits the read data to the memory controller 100.

[0116] The memory controller 100 receives read data from the semiconductor memory device 200 in response to the write data (S230). An ECC decoder 160 in the memory controller 100 generates check bits CHBc based on the read data by using the second ECC 155 (S240). The ECC decoder 160 corrects a plurality of error bits in the read data based on a comparison of the system parity data PRTc and the check bits CHBc (S250).

[0117] Figure 23 is a block diagram illustrating a semiconductor memory device according to an example embodiment of the present disclosure. Referring to Figure 23 The semiconductor memory device 600 can include a first group of dies 610 and a second group of dies 620 that provide soft error analysis and correction functions in a stacked chip structure. The second group of dies 620 can be a high bandwidth memory (HBM).

[0118] The first group of dies 610 can include at least one buffer die 611. The second group of dies 620 can include a plurality of memory dies 620-1 to 620-u (u is a natural number greater than two) stacked on the buffer die 611 and transmitting data through a plurality of through silicon via (TSV, also called, through hole via) lines. Each of the memory dies 620-1 to 620-u can include a cell core 622 which can include a memory cell array including a plurality of subarray blocks arranged in a first direction and a second direction, and an error correction circuit 624. The error correction circuit 624 can be referred to as an ECC circuit, and can employ an error correction circuit 400a of Figure 9 or an error correction circuit 400b of Figure 16 Thus, the error correction circuit 624 can include a first ECC which can include a plurality of column vectors having elements that limit the positions of error correction bits of a sub-data unit generated from a plurality of error bits.

[0119] The buffer die 611 can include an error correction circuit 612 which corrects a transmission error using a transmission parity bit when a transmission error is detected from transmission data received through the TSV lines, and generates error-corrected data. The error correction circuit 612 can be referred to as a via error correction circuit.

[0120] The semiconductor memory device 600 can be a stacked chip type memory device or a stacked memory device transmitting data and control signals through TSV lines. The TSV lines can also be referred to as through electrodes. A transmission error in which transmission data occurs can be due to noise occurring in the TSV lines. Since a data failure due to noise occurring in the TSV lines can be distinguished from a data failure due to an error operation of a memory die, the data failure due to noise occurring in the TSV lines can be considered as a soft data failure (or a soft error). The soft data failure can be generated due to a transmission failure on a transmission path, and can be detected and corrected by an ECC operation. For example, when the transmission data is 128-bit data, the transmission parity bit can be set to 8 bits. However, the scope and spirit of the disclosure are not limited thereto. The number of transmission parity bits can be increased or decreased.

[0121] Through the above description, a TSV line group 632 formed in one memory die 620-u can include 128 TSV lines L1 to Lu, and a parity TSV line group 634 can include 8 TSV lines L10 to Lv. The TSV lines L1 to Lu of the data TSV line group 632 and the parity TSV lines L10 to Lv of the parity TSV line group 634 can be connected to micro bumps MCB formed in the memory dies 620-1 to 620-u, respectively.

[0122] Each of the memory dies 620-1 to 620-u can include DRAM cells, each of which includes at least one access transistor and one storage capacitor. The semiconductor memory device 600 can have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a memory controller through a data bus B10. The first group of dies 610 can be connected with the memory controller through the data bus B10.

[0123] The error correction circuit 612 can determine whether a transmission error occurs on the transmission data received through the data TSV line group 632 based on the transmission parity bits received through the parity TSV line group 634. When a transmission error is detected, the error correction circuit 612 can correct the transmission error on the transmission data using the transmission parity bits. When the transmission error is not correctable, the error correction circuit 612 can output information indicating the occurrence of the uncorrectable data error.

[0124] Figure 24 is a cross-sectional view of a 3D chip structure of a semiconductor memory device according to an example embodiment of the present disclosure. Figure 23 Figure 24 A 3D chip structure 700 in which a host and an HBM are directly connected without an interposer is shown. Referring to Figure 24 , a host die 710 such as a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU) can be disposed on a printed circuit board (PCB) 720 using flip chip bumps FB. Memory dies D11 to D14 can be stacked on the host die 720 to implement an HBM structure 620 as in Figure 23 . In Figure 24 , Figure 23 a buffer die 611 or a logic die is omitted. However, the buffer die 611 or the logic die can be disposed between the memory dies D11 and the host die 720.

[0125] To implement the HBM (620) structure, TSV lines can be formed in the memory dies D11 and D14. The TSV lines can be electrically connected with micro bumps MCB placed between the memory dies. In addition, each of the memory dies D11 to D14 can include an error correction circuit such as an error correction circuit 400a of Figure 9 or an error correction circuit 400b of Figure 16 .

[0126] Figure 25 is a diagram illustrating a semiconductor package including a stacked memory device according to an example embodiment of the present disclosure. Referring to Figure 25 ​semiconductor package 900 can include one or more stacked memory devices 910 and a graphics processor (GPU) 920, the GPU 920 including a memory controller (CONT) 925. The stacked memory devices 910 and the GPU 920 can be mounted on an interposer 930, the interposer 930 on which the stacked memory devices 910 and the GPU 920 are mounted can be mounted on a package substrate 940. Conductive devices (e.g., solder balls 950) can be mounted under the package substrate 940. The memory controller 925 can employ the memory controller 100 in Figure 1

[0127] Each of the stacked memory devices 910 can be implemented in various forms and can be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. Accordingly, each of the stacked memory devices 910 can include a buffer die and a plurality of memory dies, each of the plurality of memory dies can include an array of memory cells and an error correction circuit.

[0128] The plurality of stacked memory devices 910 can be mounted on the interposer 930, the GPU 920 can communicate with the plurality of stacked memory devices 910. For example, each of the stacked memory devices 910 and the GPU 920 can include a physical region, and communication can be performed between the stacked memory devices 910 and the GPU 920 through the physical region.

[0129] As described above, according to an example embodiment, the ECC includes a plurality of column vectors corresponding to data bits and parity data, the column vectors are divided into a plurality of code groups, the column vectors have elements that limit positions of error correction bits that occur in a sub-data unit, the error correction bits are generated from a plurality of error bits. Accordingly, although the main data includes a plurality of error bits that the error correction circuit cannot correct and / or detect, the error correction circuit in the memory controller can correct the plurality of error bits and the error correction bits in the sub-data unit. Accordingly, the semiconductor memory device and the memory system can enhance performance and reliability of error correction.

[0130] Example embodiments of the present disclosure can be applied to a semiconductor memory device and a memory system employing the ECC described herein. Although the present disclosure has been particularly shown and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.​

Claims

1. A semiconductor memory device comprising: a memory cell array having a plurality of volatile memory cells in the memory cell array, the plurality of volatile memory cells being connected to word lines and bit lines and being divided into a plurality of sub-array blocks; an error correction circuit configured to generate parity data from main data using an error correction code represented by a generator matrix; an input / output gating circuit connected between the memory cell array and the error correction circuit; and A control logic circuit is configured to control the error correction circuit and the input / output gating circuit in response to a command and an address received from an external memory controller, the control logic circuit being configured to: (i) store the main data and the parity data in k+1 target sub-array blocks among the plurality of sub-array blocks, and (ii) control the input / output gating circuit so that each of the portions in the k+1 target sub-array blocks stores both a portion of the main data and a portion of the parity data, where k is an even number greater than 2.

2. The semiconductor memory device according to claim 1, wherein The main data includes a plurality of data bits arranged into a plurality of sub-data units; wherein the error correction code includes a plurality of column vectors divided into a plurality of code groups corresponding to the plurality of sub-data units and parity data; and wherein the plurality of column vectors have elements that limit positions of miscorrected bits of the sub-data units in response to generation of a plurality of error bits of the main data, the plurality of error bits being uncorrectable by the error correction code.

3. The semiconductor memory device according to claim 2, in, The k+1 target sub-array blocks include a first group of sub-array blocks configured to store some of the plurality of data bits of main data and a second group of sub-array blocks configured to store both the remaining portion of the plurality of data bits of main data and parity data; and The multiple code groups include a first code group and a second code group, the first code group corresponds to a first group of sub-array blocks, and the second code group corresponds to a second group of sub-array blocks.

4. The semiconductor memory device according to claim 3, wherein Each code-group in the first set of code-groups includes a plurality of first column vectors; and wherein each column vector in the plurality of first column vectors includes identical elements relative to one another.

5. The semiconductor memory device according to claim 3, in, The plurality of error bits include a first error bit and a second error bit; wherein, when a first sub-data unit among the plurality of sub-data units is stored in a first sub-array block among the first group of sub-array blocks and a first error bit and a second error bit are included in the first sub-data unit, a column vector of a code group corresponding to the first sub-array block among the first group of code groups is configured to place the error correction bit in the first sub-data unit; and The external memory controller is configured to correct a first error bit, a second error bit, and an error-corrected bit in the first sub-data unit.

6. The semiconductor memory device according to claim 3, wherein The plurality of error bits include a first error bit and a second error bit; wherein, when a sub-data unit among the plurality of sub-data units is stored in a sub-array block among the second group of sub-array blocks and the first error bit and the second error bit are included in the sub-data unit, the plurality of column vectors have elements for limiting positions where error-correction bits of the sub-data unit occur, so that the error-correction bits can be corrected by an external memory controller, and the error-correction bits are generated by the first error bit and the second error bit.

7. The semiconductor memory device according to any one of claims 1 to 6, wherein: The control logic circuit is configured to control the input / output gating circuit so that the input / output gating circuit stores the parity bits of the parity data in the k / 2th sub-array block, the k / 2+1th sub-array block, and the k / 2+3th sub-array block among the k+1 sub-array blocks.

8. The semiconductor memory device according to any one of claims 1 to 6, wherein: The error correction circuit includes: a memory configured to store an error correction code; an error correction code encoder connected to the memory, the error correction code encoder configured to perform an error correction code encoding operation on main data using an error correction code in a write operation of the semiconductor memory device to generate parity data; and An error correction code decoder is connected to the memory, the error correction code decoder being configured to perform an error correction code decoding operation on the main data based on the parity data using the error correction code in a read operation of the semiconductor memory device.

9. The semiconductor memory device according to any one of claims 1 to 6, further comprising: at least one buffer die; and a plurality of memory dies stacked on the at least one buffer die and transmitting data through a plurality of through-silicon via lines; At least one memory die among the plurality of memory dies includes a memory cell array and an error correction circuit.

10. The semiconductor memory device according to claim 9, wherein The at least one buffer die includes via error correction circuitry configured to correct transmission errors included in data transmitted through the plurality of through-silicon via lines.

11. A semiconductor memory device comprising: a memory cell array having a plurality of volatile memory bank arrays in the memory cell array, the plurality of volatile memory bank arrays being connected to a plurality of word lines and a plurality of bit lines; an error correction circuit configured to generate parity data based on main data using an error correction code represented by a generator matrix, the error correction circuit configured to: (i) store the main data and the parity data in a target area of ​​a target page in a memory cell array specified by an address, (ii) interleave the main data and the parity data so that parity bits of the parity data are stored symmetrically with respect to a virtual center line in the target area, and (iii) change a plurality of sub-data patterns based on the least significant bit of the address specifying the target page, the main data and the parity data stored in the target area constituting the plurality of sub-data patterns; an input / output gating circuit connected between the memory cell array and the error correction circuit; and The control logic circuit is configured to control the error correction circuit based on commands and addresses received from the external memory controller.

12. The semiconductor memory device according to claim 11, wherein The main data includes multiple data bits, and the parity data includes multiple parity bits; wherein the error correction code includes multiple column vectors corresponding to the multiple data bits and the multiple parity bits; and wherein the multiple column vectors have elements that limit the positions of the sub-data pattern where erroneous correction bits appear, the erroneous correction bits are generated by erroneous bits of the main data, and the erroneous bits are uncorrectable by the error correction code.

13. The semiconductor memory device according to claim 12, wherein When a first sub-data pattern among the multiple sub-data patterns includes the erroneous bit, the multiple column vectors have elements that place the error correction bit in the first sub-data pattern or one of the other sub-data patterns among the multiple sub-data patterns except the first sub-data pattern.

14. The semiconductor memory device according to claim 12, wherein The multiple data bits are divided into multiple sub-data units, and when the first sub-data pattern among the multiple sub-data patterns includes the error bit, the multiple column vectors have elements that limit the positions of the sub-data units where the error correction bits appear, so that the error correction bits can be corrected by an external memory controller, and the error correction bits are generated by the error bits.

15. The semiconductor memory device according to any one of claims 11 to 14, wherein When the least significant bit of the address indicates that the target page corresponds to an even page, the error correction circuit is configured to interleave the parity data such that an order of parity bits of the parity data is maintained.

16. The semiconductor memory device according to any one of claims 11 to 14, wherein: When the least significant bit of the address indicates that the target page corresponds to an odd page, the error correction circuit is configured to interleave the parity data such that an order of parity bits of the parity data is reversed.

17. A memory system comprising: semiconductor memory devices; and a memory controller configured to control the semiconductor memory device; The semiconductor memory device includes: a memory cell array including a plurality of volatile memory cells connected to word lines and bit lines and divided into a plurality of sub-array blocks arranged in a first direction and a second direction crossing the first direction; a first error correction circuit configured to generate parity data based on the main data using a first error correction code represented by a first generator matrix; an input / output gating circuit connected between the memory cell array and the first error correction circuit; and a control logic circuit configured to control the first error correction circuit and the input / output gating circuit based on a command and an address from the memory controller; and wherein the control logic circuit is configured to: (i) store the main data and the parity data in k+1 target sub-array blocks in a second direction among the plurality of sub-array blocks, and (ii) control the input / output gating circuit so that each of the portions in the k+1 target sub-array blocks stores both a portion of the main data and a portion of the parity data, and wherein k is an even number greater than 2.

18. The memory system according to claim 17, in, The main data includes a plurality of data bits divided into a plurality of sub-data units; wherein the first error correction code includes a plurality of column vectors divided into a plurality of code groups corresponding to the plurality of sub-data units and the parity check data, and The plurality of column vectors have elements that limit positions of sub-data units where error correction bits occur, the error correction bits are generated by a plurality of error bits of the main data, and the plurality of error bits are uncorrectable by the first error correction code.

19. The memory system according to claim 18, in, The memory controller includes: a second error correction circuit configured to correct error bits in main data received from the semiconductor memory device using a second error correction code represented by a second generator matrix; The k+1 sub-array blocks include: a first group of sub-array blocks configured to store some of the plurality of data bits of main data; a second group of sub-array blocks configured to store both a remaining portion of the plurality of data bits of the main data and parity data; The plurality of code groups include a first code group and a second code group, the first code group corresponds to the first group of sub-array blocks, and the second code group corresponds to the second group of sub-array blocks; wherein the plurality of error bits include a first error bit and a second error bit; wherein, when a first sub-data unit among the plurality of sub-data units is stored in a first sub-array block among the first group of sub-array blocks and a first error bit and a second error bit are included in the first sub-data unit, a column vector of a code group corresponding to the first sub-array block among the first group of code groups has an element configured to place the error correction bit in the first sub-data unit; and The second error correction circuit is configured to correct the plurality of error bits and miscorrected bits using a second error correction code.

20. The memory system according to claim 18, in, The memory controller includes: a second error correction circuit configured to correct error bits in main data received from the semiconductor memory device using a second error correction code represented by a second generator matrix; The k+1 sub-array blocks include: a first group of sub-array blocks configured to store some of the plurality of data bits of main data; a second group of sub-array blocks configured to store both a remaining portion of the plurality of data bits of the main data and parity data; The multiple code groups include: A first code group corresponding to a first group of sub-array blocks; and a second code group corresponding to a second group of subarray blocks; wherein the plurality of error bits include a first error bit and a second error bit; wherein, when a sub-data unit among the plurality of sub-data units is stored in a sub-array block among the second group of sub-array blocks and a first error bit and a second error bit are included in the sub-data unit, the plurality of column vectors have elements that limit positions where error correction bits of the sub-data unit occur, so that the error correction bits can be corrected by the memory controller, the error correction bits being generated by the first error bit and the second error bit; and The second error correction circuit is configured to correct the plurality of error bits and miscorrected bits using a second error correction code.

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