Solderless Interconnects for Semiconductor Device Assemblies

Abstract

This application relates to solderless interconnects for semiconductor device assemblies. Semiconductor device assemblies with solderless interconnects and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediate conductive structure formed between the first and second conductive pillars using an electroless plating solution injected between the first and second conductive pillars. The first and second conductive pillars and the intermediate conductive structure may include copper as a common major component other than intermetallic compound (IMC) of the soldering process. A first sidewall surface of the first conductive pillar may be misaligned relative to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve the electrical and metallurgical characteristics of the interconnects of the semiconductor device assembly.

Description

Technical Field

[0001] The present invention generally relates to semiconductor device assemblies, and more particularly, to solderless interconnects for semiconductor device assemblies. Background Art

[0002] Semiconductor packages typically include semiconductor dies (such as memory chips, microprocessor chips, imager chips) mounted on a substrate and encapsulated in a protective coating. The semiconductor die may include functional features such as memory cells, processor circuitry, or imager devices and bond pads electrically connected to the functional features. The bond pads may be electrically connected to corresponding conductive structures of the substrate, and the corresponding conductive structures may be coupled to terminals outside the protective coating such that the semiconductor die can be connected to a higher-level circuit system.

[0003] In some semiconductor packages, direct chip attachment methods (such as flip-chip bonding between a semiconductor die and a substrate) can be used to reduce the footprint of the semiconductor package. Such direct chip attachment methods may include interfaces between different metal materials in contact that can form an intermetallic compound (IMC). The IMC degrades the electrical properties (such as increasing resistance) at the interface or causes reliability problems due to its metallurgical properties (such as brittleness). In addition, an annealing step may be required to promote bonding between different metal materials, which introduces thermal stress into the semiconductor package. Such thermal stress can cause additional problems such as cracks spreading in the passivation layer of the semiconductor die, warping of the semiconductor die, the substrate, or both, resulting in high resistance at the interface, or the like. Summary of the Invention

[0004] One aspect of the present invention relates to a method that includes: forming a first metal structure on a semiconductor die, the first metal structure including a first top surface remote from the semiconductor die; forming a second metal structure on a substrate, the second metal structure including a second top surface remote from the substrate; aligning the first metal structure with the second metal structure such that the first top surface faces the second top surface; and bonding the first top surface and the second top surface by simultaneously plating a conductive material on both the first top surface and the second top surface with an electroless plating solution.

[0005] Another aspect of the present invention relates to a method, which includes: forming a first plurality of copper pillars on a first semiconductor die and forming a second plurality of copper pillars on a second semiconductor die, wherein a semiconductor wafer includes the first and second semiconductor dies; forming a first group of conductive bumps and a second group of conductive bumps on a package support substrate; aligning individual copper pillars in the first and second pluralities with individual conductive bumps in the first and second groups, wherein the first and second pluralities of copper pillars face the first and second groups of conductive bumps; and connecting individual copper pillars in the first and second pluralities to individual conductive bumps in the first and second groups via a conductive material formed in an electroless solution injected between the first and second pluralities of copper pillars and the first and second groups of conductive bumps.

[0006] Yet another aspect of the present invention relates to a semiconductor device assembly, which includes: a first metal structure extending from a first side of a semiconductor die; a second metal structure extending from a first side of a substrate facing the first side of the semiconductor die; and a third metal structure coupling the first metal structure and the second metal structure, wherein the third metal structure is formed by an electroless solution injected between the first metal structure and the second metal structure, wherein: the first, second, and third metal structures include a common major metal component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Many aspects of the present invention can be better understood with reference to the accompanying drawings. The components in the figures are not necessarily drawn to scale. Instead, emphasis is placed on clearly illustrating the principles of the present invention.

[0008] Figure 1 A cross-sectional view illustrating an exemplary semiconductor device assembly.

[0009] Figures 2A to 2E A process for forming a solderless interconnect of a semiconductor device assembly according to an embodiment of the present invention is illustrated.

[0010] Figure 3A AND 3B A process for forming a solderless interconnect of a semiconductor device assembly according to an embodiment of the present invention is illustrated.

[0011] Figure 4 is a block diagram schematically illustrating a system including a semiconductor device assembly configured according to an embodiment of the present invention.

[0012] Figure 5 AND 6 is a flowchart illustrating a method for forming a solderless interconnect of a semiconductor device assembly according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following describes specific details of several embodiments of a semiconductor device assembly (“assembly”) having solderless interconnects and associated systems and methods. The solderless interconnects can provide improved electrical characteristics and reduced thermal budget during an assembly process, which in turn improves the reliability performance of the interconnects. The term “semiconductor device or die” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices particularly include logic devices, memory devices, microprocessors, or diodes. Such semiconductor devices can include integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. Additionally, the term “semiconductor device or die” can refer to a finished device or an assembly or other structure in various processing stages before becoming a finished device. Depending on the context in which it is used, the term “substrate” can refer to a wafer-level substrate or a singulated die-level substrate. Moreover, the substrate can include a semiconductor wafer, a package support substrate, an interposer, a semiconductor device or die, or the like. Those of ordinary skill in the relevant art should recognize that the appropriate steps of the methods described herein can be performed at the wafer level or the die level.

[0014] In addition, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques, some of which can be combined with a lithography step. Those skilled in the relevant art should also understand that the present invention can have additional embodiments and that the present invention can be practiced without some of the details of the embodiments described with reference to FIGS. 2-5 herein.

[0015] As used herein, the terms “vertical,” “lateral,” “downward,” “upward,” “upper,” and “lower” can refer to the relative direction or position of features in a semiconductor device assembly in view of the orientation shown in the figures. For example, “upper” or “uppermost” can refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations.

[0016] Figure 1 Cross-sectional views 101a and 101b illustrate an exemplary semiconductor device assembly. FIG. 101a includes a semiconductor die 105 and a substrate 160 before the semiconductor die 105 and the substrate 160 are attached together to form a semiconductor device assembly. The semiconductor die 105 includes conductive posts 115 formed on bond pads 110 of the semiconductor die 105. The bond pads 110 can be connected to various functional features of the semiconductor die 105. Additionally, solder 120 is formed on the conductive posts 115. The conductive die 105 is Figure 1"After flipping", the active surface of the semiconductor die 105 faces the substrate 160, where functional features are formed on the active surface. The conductive pillars 115 may comprise copper (Cu), and the solder 120 may comprise a tin-based alloy. The substrate 160 includes a conductive structure 165, which may be further connected to terminals (not shown) outside the protective coating of the semiconductor device assembly. The conductive structure 165 may comprise copper.

[0017] FIG. 101b depicts a semiconductor device assembly of a semiconductor die 105 and a substrate 160 after being attached to each other via an interconnect 170 (e.g., the semiconductor die 105 is flip-chip bonded to the substrate 160). The interconnect 170 includes conductive pillars 115 connected to the conductive structure 165 via an IMC 175. The IMC 175 may be formed during an annealing step (e.g., a soldering process) performed after bringing the solder 120 into contact with the conductive structure 165 to facilitate bonding between the solder 120 and the conductive structure 165. In some instances, the soldering process may reach about 230 degrees Celsius to melt the solder 120. The IMC 175 may comprise a metal compound including Cu (e.g., Cu of the conductive pillar 115 or the conductive structure 165 or both) and Sn (e.g., tin of the solder 120).

[0018] Disadvantages associated with the IMC 175 stem from the electrical and metallurgical properties of the IMC 175. In some instances, the IMC 175 may degrade the conductivity of the interconnect 170 due to Sn mixing with Cu during the annealing step (this may be referred to as Sn consuming Cu). Additionally, the IMC 175 cannot stretch as well as Cu (e.g., is more brittle than Cu), resulting in weaknesses in the interconnect 170 (e.g., the interface between the IMC 175 and the Cu of the conductive pillar 115 or the conductive structure 165 or both), which are prone to catastrophic failures (e.g., the interconnect 170 disconnecting) during reliability testing or the lifetime of the semiconductor device assembly. Furthermore, the heating and cooling associated with the annealing step exacerbate additional reliability issues (e.g., cracks form and spread in the passivation layer of the semiconductor die 105) or cause warping of the semiconductor die 105, the substrate 160, or both. Such warping increases the resistance of the interconnect 170 or even causes an electrical discontinuity that renders the interconnect 170 non-functional.

[0019] Figures 2A to 2EDescribe a process for forming a solderless interconnect for a semiconductor device assembly according to an embodiment of the present invention. As described herein, the solderless interconnect can be fabricated by using a low thermal budget electroless process. The solderless interconnect can improve the electrical and metallurgical characteristics of the interconnect by eliminating intermetallic compounds (such as IMC 175) and associated interfaces (such as the interface between Cu and IMC). In addition, forming the solderless interconnect using a low thermal budget electroless process reduces additional reliability issues or warpage issues compared to a soldering process due to the lower thermal budget associated with the electroless process.

[0020] Figure 2A Describe a cross-sectional view 201a of a semiconductor die 205. The semiconductor die 205 includes bond pads 210 that are connected to various functional features of the semiconductor die 205. The semiconductor die 205 can be covered with a first passivation layer 215 that includes an opening located above the bond pads 210. In some embodiments, the first passivation layer 215 can include a dielectric material (such as a nitrogen oxide) formed on the semiconductor die 205, on which an opening exposing the bond pads 210 is formed above the bond pads 210 (e.g., using a lithography process and an etching process). Additionally or alternatively, in some embodiments, the first passivation layer 215 can include a solder mask that includes a dielectric material, on which an opening above the bond pads 210 is formed. Further, the semiconductor die 205 includes a first conductive pillar 220 that is formed to contact the bond pads 210. In some embodiments, the first conductive pillar 220 includes copper (Cu) as a main component (or main ingredient). Thus, the first conductive pillar 220 can be referred to as a Cu pillar.

[0021] Figure 2B Describe a cross-sectional view 201b of a semiconductor die 205 having an adhesive member 225 attached to the semiconductor die 205. In some embodiments, the adhesive member 225 includes a die attach film (DAF). Figure 2B Also describe a plan view 201c depicting the position of the adhesive member 225 relative to the semiconductor die 205. The adhesive member 225 is arranged to include a space that facilitates the inflow or outflow of a solution, as indicated in FIG. 201c. In some embodiments, the adhesive member 225 can be attached to a substrate (e.g., refer to Figure 2Ca substrate 260 as described) rather than the semiconductor die 205. Although FIG. 201c depicts four bonding members (e.g., bonding members 225a to 225d) (where each bonding member 225 is respectively located at four corners of the semiconductor die 205), the present invention is not limited thereto. For example, additional bonding members 225 may be disposed along any side of the semiconductor die 205. In another example, the four bonding members 225 may be located on four sides of the semiconductor die 205, i.e., one bonding member 225 on each side of the semiconductor die 205. In addition, the shape of the bonding member 225 may include shapes other than the square shape depicted in FIG. 201, such as a rectangular or oblong shape, a circular or elliptical shape, or the like.

[0022] Figure 2C FIG. 201d is a cross-sectional view illustrating a semiconductor assembly after the semiconductor die 205 is attached to the substrate 260 by the bonding member 225. The substrate 260 includes a second conductive pillar 270. In some embodiments, the second conductive pillar 270 may include copper (Cu) as a main component (or main ingredient). Thus, the second conductive pillar 270 may be referred to as a second Cu pillar. In some embodiments, the second conductive pillar 270 may be referred to as a conductive bump. In some embodiments, an organic solderability preservative (OSP) may cover the second conductive pillar 270 and / or other conductive features (such as Cu traces) of the substrate 260. In such embodiments, the OSP may be removed before attaching the semiconductor die 205 to the substrate 260. In some embodiments, the second conductive pillar 270 may be connected to a terminal outside a protective coating (such as a housing of a semiconductor assembly including the semiconductor die 205 and the substrate 260). In some embodiments, the substrate 260 may be another semiconductor die configured similarly to the semiconductor die 205. In such embodiments, the second conductive pillar 270 may be connected to a second bonding pad (not shown), and the second bonding pad is then connected to a functional feature of the substrate 260. In addition, the substrate 260 includes a second passivation layer 265 that covers metal features of the substrate 260 other than the second conductive pillar 270. In some embodiments, the second passivation layer 265 may be an instance of the first passivation layer 215 or include aspects of the first passivation layer 215.

[0023] As Figure 2C shown, the individual first conductive pillars 220 may be aligned with the corresponding individual second conductive pillars 270. In addition, the cross-sectional dimensions (such as diameter, cross-sectional area) of the first conductive pillar 220 and the second conductive pillar 270 are illustrated as being substantially the same, but the present invention is not limited thereto. For example, the cross-sectional dimensions of the first conductive pillar 220 may be different from the cross-sectional dimensions of the second conductive pillar 270. The height of the bonding member 225 ( Figure 2C labeled as H in ) may be configured to leave a distance or gap (Figure 2C is labeled as D). For example, a first surface 221 of the first conductive pillar 220 is spaced apart from a second surface 271 of the second conductive pillar 270 by a distance D. In some embodiments, the height H can be about 15 μm, and the distance D can be about 10 μm. Additionally, the distance D can be based on the spacing ( Figure 2C labeled as S) between two adjacent first conductive pillars 220 (or second conductive pillars 270). In some embodiments, the minimum spacing between two adjacent first (or second) conductive pillars can be greater than the distance D. In some embodiments, the minimum spacing between two conductive pillars can be about 25 μm.

[0024] Figure 2D illustrates placing (e.g., immersing) a semiconductor assembly including a semiconductor die 205 attached to a substrate 260 in a solution 280. In some embodiments, the solution 280 can include an electroless plating solution that forms a Cu layer on a metal surface exposed to the solution 280. In some embodiments, the solution 280 can be injected into the gap between the first conductive pillar 220 and the second conductive pillar 270 to form a Cu layer therebetween. In some embodiments, the solution 280 can be heated to facilitate the electroless plating process, such as to a temperature less than about 100 degrees Celsius.

[0025] Figure 2E illustrates a cross-sectional view 201e of a semiconductor assembly including a semiconductor die 205 attached to a substrate 260 and interconnects 275 formed between the semiconductor die 205 and the substrate 260. Figure 2E also illustrates various configurations of the interconnects (such as interconnects 275a to 275d).

[0026] Interconnect 275a illustrates that the first conductive pillar 220 and the second conductive pillar 270 are perfectly aligned when the diameters of the first conductive pillar 220 and the second conductive pillar 270 are substantially the same. Interconnect 275a depicts that a first sidewall surface of the first conductive pillar 220 is aligned with a corresponding second sidewall surface of the second conductive pillar 270 and no steps or protrusions are formed in the interconnect 275a. Additionally, interconnect 275a depicts the first conductive pillar 220, the second conductive pillar 270, and a third conductive structure 285 depicted as a gray feature.

[0027] The third conductive structure 285 may comprise a conductive material (such as copper) that has been formed from the solution 280 during a low thermal budget electroless plating process. That is, the third conductive structure 285 comprises a conductive material (such as copper) that is simultaneously plated on the first surface 221 and the second surface 271 with the solution 280, which joins the first top surface 221 and the second surface 271, that is, the third conductive structure 285 connects the first surface 221 of the first conductive pillar 220 to the second surface 271 of the second conductive pillar 270. The dashed line between the first conductive pillar 220 and the second conductive pillar 270 depicts the median position within the gap (labeled D) where two advancing Cu surfaces may join during the low thermal budget electroless plating process, that is, the first Cu surface advances from the first surface of the first conductive pillar 220, and the second Cu surface advances from the second surface 271 of the second conductive pillar 270. In addition, the third conductive structure 285 comprises an intermediate portion positioned between the first conductive pillar 220 and the second conductive pillar 270 (i.e., the intermediate portion of the conductive material corresponding to the diameters of the first conductive pillar 220 and the second conductive pillar 270) and a peripheral portion surrounding the sidewall surfaces of the first conductive pillar 220 and the second conductive pillar 270 (i.e., the peripheral portion of the conductive material formed on the sidewall surfaces of the first and second conductive pillars).

[0028] The interconnect 275b illustrates a misalignment of the first conductive pillar 220 relative to the second conductive pillar 270 when the diameters of the first conductive pillar 220 and the second conductive pillar 270 are substantially the same. The interconnect 275b depicts a misalignment of the first sidewall surface of the first conductive pillar 220 relative to the corresponding second sidewall surface of the second conductive pillar 270, thereby forming a protrusion or step 290. The width of the protruding portion of the step 290 may be substantially uniform around the interconnect 275b.

[0029] The interconnect 275c illustrates a perfect alignment of the first conductive pillar 220 and the second conductive pillar 270 when the diameters of the first conductive pillar 220 and the second conductive pillar 270 are different. The interconnect 275c depicts a misalignment of the first sidewall surface of the first conductive pillar 220 relative to the corresponding second sidewall surface of the second conductive pillar 270, thereby forming a protrusion or step 291. The width of the protruding portion of the step 291 may be substantially uniform around the interconnect 275c.

[0030] The interconnect 275d illustrates a misalignment of the first conductive pillar 220 relative to the second conductive pillar 270 when the diameters of the first conductive pillar 220 and the second conductive pillar 270 are different. The interconnect 275d depicts a misalignment of the first sidewall surface of the first conductive pillar 220 relative to the corresponding second sidewall surface of the second conductive pillar 270, thereby forming a protrusion or step 292. The width of the protruding portion of the step 292 may vary around the interconnect 275d.

[0031] In some embodiments, a semiconductor device assembly may include: a first metal structure extending from a first side of a semiconductor die; a second metal structure extending from a first side of a substrate facing the first side of the semiconductor die; and a third metal structure coupling the first metal structure and the second metal structure, wherein the third metal structure is formed by an electroless plating solution injected between the first metal structure and the second metal structure. Further, the first, second, and third metal structures may include a common major metal component (or composition). In some embodiments, the common major metal component includes copper. In some embodiments, a first sidewall surface of the first metal structure is misaligned relative to a corresponding second sidewall surface of the second metal structure. The semiconductor device assembly may further include one or more bonding members configured to attach the semiconductor die to the substrate and facilitate inflow or outflow of the electroless plating solution. In some embodiments, a thickness of the one or more bonding members is related to a sum of a first height of the first metal structure, a second height of the second metal structure, and a thickness of the third metal structure in a vertical direction relative to the first side of the semiconductor die or the substrate, respectively.

[0032] Figure 3A Describes a cross-sectional view 301a including a semiconductor die 205 and a substrate 260, where the semiconductor die 205 is brought close to the substrate 260. Individual first conductive pillars 220 are aligned relative to individual second conductive pillars 270, where a first surface 221 of the first conductive pillar 220 faces a second surface 271 of the second conductive pillar 270. Further, the first surface 221 of the first conductive pillar 220 is spaced apart from the second surface 271 of the second conductive pillar 270 by a distance D. In this regard, except for adding a support assembly 295 to replace the bonding member 225 that has been omitted, FIG. 301a corresponds to FIG. 201d described in the reference Figure 2C That is, the semiconductor die 205 may be supported by a first support assembly 295a, and the substrate 260 may be supported by a second support assembly 295b.

[0033] Such support components can be configured to hold an object (e.g., semiconductor die 205, substrate 260) via vacuum suction or electrostatic suction (or other suitable support mechanisms). In this manner, the semiconductor die 205 and the substrate 260 can be arranged by manipulating the first and second support components 295 rather than the bonding member 225 as shown in FIG. 301a. Additionally, the semiconductor die 205 and the substrate 260 can be immersed in a solution 280 (e.g., electroless plating solution) while being supported by the first and second support components 295 respectively to bond the first surface 221 and the second surface 271 by simultaneously plating a conductive material (e.g., copper) on both the first surface 221 and the second surface 271 with the electroless plating solution, i.e., connecting the first conductive pillar 220 to the corresponding second conductive pillar 270. In some cases, the solution 280 can be injected into the gap between the first conductive pillar 220 and the second conductive pillar 270 to form a Cu layer therebetween, as referenced Figure 2D described. The absence of the bonding member 225 can facilitate the electroless plating solution to flow into and / or out of between the first surface 221 and the second surface 271 relatively more easily than in embodiments using the bonding member 225.

[0034] Figure 3B FIG. 301b illustrates a cross-sectional view of a semiconductor assembly including a semiconductor die 205 attached to a substrate 260 and interconnects 275 formed between the semiconductor die 205 and the substrate 260. After the semiconductor die 205 is attached to the substrate 260 via the interconnects 275, the support components 295 can be removed from the semiconductor die 205 and the substrate 260. In this regard, FIG. 301b corresponds to FIG. 201e as referenced Figure 2E described, except for the bonding member 225 which has been omitted. Additionally, the interconnects 275 of FIG. 301 can include various configurations of interconnects (e.g., Figure 2E the interconnects 275a to 275d depicted in Figure 2E ), as referenced

[0035] Although the process of forming solderless interconnects is illustrated with reference to Figures 2A to 2E , 3A, and 3B for die-level process steps (e.g., a singulated semiconductor die (e.g., semiconductor die 205) attached to a singulated substrate (e.g., substrate 260)), the process can be applied to wafer-level process steps. In some embodiments, a semiconductor wafer can include a first semiconductor die including a first plurality of copper pillars and a second semiconductor die including a second plurality of copper pillars. The semiconductor wafer can be brought close to a package support substrate including a first group of conductive bumps and a second group of conductive bumps such that individual copper pillars in the first and second pluralities are aligned with individual conductive bumps in the first and second groups. In some embodiments, the conductive bumps in the first and second groups can include copper as a main component.

[0036] In addition, the first and second pluralities of copper pillars face the first and second groups of conductive bumps, and the first and second pluralities of copper pillars are spaced apart from the first and second groups of conductive bumps by a distance (e.g., the distance D described with reference to Figure 2C or Figure 3A ). Subsequently, individual copper pillars in the first and second pluralities can be connected to individual conductive bumps in the first and second groups via a conductive material (e.g., copper) formed in an electroless plating solution injected between the first and second pluralities of copper pillars and the first and second groups of conductive bumps.

[0037] In some embodiments, bringing the semiconductor wafer close to the package support substrate may further include bonding the semiconductor wafer to the package support substrate using one or more bonding members before connecting individual copper pillars in the first and second pluralities to individual conductive bumps in the first and second groups. In such embodiments, the thickness of the one or more bonding members can be configured to maintain the distance (e.g., the distance D described with reference to Figure 2C ) between the first top surfaces of the copper pillars in the first and second pluralities and the second top surfaces of the conductive bumps in the first and second groups. In some embodiments, the distance can be less than the lateral distance between the copper pillars in the first or second plurality.

[0038] In some embodiments, bringing the semiconductor wafer close to the package support substrate may further include using a support assembly (e.g., the support assembly 295 described with reference to Figure 3A and 3B ) to support the semiconductor wafer and the package support substrate respectively before connecting individual copper pillars in the first and second pluralities to individual conductive bumps in the first and second groups. In such embodiments, the support assembly can be manipulated to maintain the distance (e.g., the distance D described with reference to Figure 3A ) between the first top surfaces of the copper pillars in the first and second pluralities and the second top surfaces of the conductive bumps in the first and second groups. In some embodiments, the distance can be less than the lateral distance between the copper pillars in the first or second plurality.

[0039] In addition, after connecting individual copper pillars in the first and second pluralities to individual conductive bumps in the first and second groups, the semiconductor wafer can be singulated along a scribe line between the first and second semiconductor dies. Moreover, the package support substrate can be singulated along the scribe line simultaneously when the semiconductor wafer is singulated, where the scribe line is between the first and second groups of conductive bumps.

[0040] Any of the semiconductor device assemblies described above with reference to FIG. 2 can be incorporated into any of a variety of larger and / or more complex systems, representative examples of which are Figure 4The system 470 schematically shown in. The system 470 may include a semiconductor device assembly 400, a power supply 472, a driver 474, a processor 476, and / or other subsystems or components 478. The semiconductor device assembly 400 may include features generally similar to those of the solderless interconnects described herein and may thus include various features that enhance the electrical and metallurgical properties of the interconnects. The resulting system 470 may perform any of a variety of functions such as memory storage, data processing, and / or other suitable functions. Accordingly, a representative system 470 may include (but is not limited to) handheld devices (such as mobile phones, tablet computers, digital readers, and digital audio players), computers, and appliances. The components of the system 470 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of the system 470 may also include remote devices and any of a variety of computer-readable media.

[0041] Figure 5 is a flowchart 500 illustrating a method of forming a solderless interconnect of a semiconductor device assembly in accordance with an embodiment of the present invention. The flowchart 500 may include aspects of the methods described with reference to Figures 2A to 2E , 3A, and 3B.

[0042] The method includes forming a first metal structure on a semiconductor die, the first metal structure including a first top surface remote from the semiconductor die (block 510). The method further includes forming a second metal structure on a substrate, the second metal structure including a second top surface remote from the substrate (block 515). The method further includes aligning the first metal structure with the second metal structure such that the first top surface faces the second top surface (block 520). The method further includes bonding the first top surface and the second top surface by simultaneously plating a conductive material on both the first top surface and the second top surface with an electroless plating solution (block 525).

[0043] In some embodiments, the method may further include injecting an electroless plating solution between the first top surface and the second top surface, wherein plating the conductive material is at least partially based on the injected electroless plating solution. In some embodiments, the method may further include heating the electroless plating solution injected between the first top surface and the second top surface, wherein plating the conductive material is at least partially based on heating the electroless plating solution. In some embodiments, the method may further include attaching one or more bonding members to the semiconductor die before aligning the first metal structure with the second metal structure. In some embodiments, the one or more bonding members are configured to facilitate the inflow or outflow of the electroless plating solution.

[0044] In some embodiments, the method may further include bonding a semiconductor die to a substrate using one or more bonding members before forming the conductive material. In some embodiments, the thickness of the one or more bonding members may be configured to provide a spacing between a first top surface and a second top surface after bonding the semiconductor die to the substrate, the spacing being less than the lateral distance between a first metal structure and a third metal structure adjacent to the first metal structure on the semiconductor die. In some embodiments, the first metal structure, the second metal structure, and the conductive material each include copper as a main component (or ingredient).

[0045] In some embodiments, the substrate includes a package support substrate or a second semiconductor die. In some embodiments, the method may further include bringing the semiconductor die to the substrate such that a first metal structure that has been aligned with a second metal structure is spaced apart by a gap between a first top surface and a second top surface, the gap being less than the lateral distance between the first metal structure and a third metal structure adjacent to the first metal structure on the semiconductor die.

[0046] Figure 6 is a flowchart 600 illustrating a method of forming solderless interconnects for a semiconductor device assembly in accordance with an embodiment of the present invention. Flowchart 600 may include aspects of the method described with reference Figures 2A to 2E to FIGS. 3A and 3B.

[0047] The method includes forming a first plurality of copper pillars on a first semiconductor die and forming a second plurality of copper pillars on a second semiconductor die, wherein the semiconductor wafer includes the first and second semiconductor dies (block 610). The method further includes forming a first group of conductive bumps and a second group of conductive bumps on a package support substrate (block 615). The method further includes aligning individual copper pillars of the first and second pluralities with individual conductive bumps of the first and second groups, wherein the first and second pluralities of copper pillars face the first and second groups of conductive bumps (block 620). The method further includes connecting individual copper pillars of the first and second pluralities to individual conductive bumps of the first and second groups via a conductive material formed in an electroless plating solution injected between the first and second pluralities of copper pillars and the first and second groups of conductive bumps (block 625).

[0048] In some embodiments, the method may further include bonding the semiconductor wafer to the package support substrate using one or more bonding members before connecting individual copper pillars of the first and second pluralities to individual conductive bumps of the first and second groups. In some embodiments, the thickness of the one or more bonding members may be configured to provide a spacing between a first top surface of the copper pillars in the first and second pluralities and a second top surface of the conductive bumps in the first and second groups after bonding the semiconductor wafer to the package support substrate, the spacing being less than the lateral distance between the copper pillars in the first or second plurality.

[0049] In some embodiments, the method may further include singulating the semiconductor wafer along a saw street between the first and second semiconductor dies after connecting the individual copper pillars in the first and second pluralities to the individual conductive bumps in the first and second groups. In some embodiments, the method may further include, when singulating the semiconductor wafer, simultaneously singulating the package support substrate along the saw street, wherein the saw street is between the conductive bumps in the first and second groups.

[0050] It should be noted that the above method descriptions may represent embodiments, and the operations and steps may be rearranged or otherwise modified and other embodiments are possible. Additionally, embodiments from two or more than two methods may be combined.

[0051] It will be appreciated from the foregoing that specific embodiments of the invention have been described herein for purposes of illustration, but various modifications may be made without departing from the invention. For example, although embodiments of semiconductor device assemblies have been described with respect to a single semiconductor die attached to a substrate, other embodiments of semiconductor device assemblies may be configured to include, for example, more than one semiconductor die, such as stacked semiconductor dies, hybrid memory cubes (HMCs), or the like. Additionally, while specific features or components have been shown in the illustrated embodiments as having a particular arrangement or configuration, other arrangements and configurations are possible. For example, the first conductive pillar 220 and the second conductive pillar 270 may include a greater or lesser number of conductive pillars than shown in the illustrated embodiments. Additionally, certain aspects of the invention described in the context of a particular embodiment may also be combined or eliminated in other embodiments.

[0052] The devices discussed herein, including semiconductor devices, may be formed on a semiconductor substrate or die such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. The doping may be performed by ion implantation or any other doping method during the initial formation or growth of the substrate.

[0053] As used herein (including in the claims), the "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on..." should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present invention, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same manner as the phrase "at least partially based on...".

[0054] It should be understood from the foregoing that specific embodiments of the invention have been described herein for purposes of illustration, but various modifications may be made without departing from the scope of the invention. Specifically, in the foregoing description, numerous specific details are set forth in order to provide a thorough and advantageous description of embodiments of the invention. However, one of ordinary skill in the relevant art will recognize that the invention may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail so as not to obscure other aspects of the invention. In general, it should be understood that various other devices, systems, and methods, in addition to those specific embodiments disclosed herein, may be within the scope of the invention.

Claims

1. A method for a semiconductor device assembly, the method comprising: forming a first metal structure on a first side of a semiconductor die, the first metal structure including a first top surface remote from the semiconductor die; forming a second metal structure on a first side of a substrate, the second metal structure including a second top surface remote from the substrate; attaching a first support assembly to a second side of the semiconductor die opposite the first side of the semiconductor die; attaching a second support assembly to a second side of the substrate opposite the first side of the substrate; manipulating the first support assembly and the second support assembly such that the first metal structure is aligned with the second metal structure and such that the first top surface faces the second top surface; and bonding the first top surface and the second top surface by electroless plating a conductive material simultaneously on both the first top surface and the second top surface.

2. The method according to claim 1, further comprising: injecting the electroless plating solution between the first top surface and the second top surface, wherein plating the conductive material is at least partially based on injecting the electroless plating solution.

3. The method according to claim 1, further comprising: heating the electroless plating solution injected between the first top surface and the second top surface, wherein plating the conductive material is at least partially based on heating the electroless plating solution.

4. The method according to claim 1, wherein the first metal structure, the second metal structure, and the conductive material each include copper as a main component.

5. The method according to claim 1, wherein the substrate includes a package support substrate or a second semiconductor die.

6. The method according to claim 1, wherein operating the first support assembly and the second support assembly further comprises: bringing the semiconductor die to the substrate such that the first metal structure is spaced apart by a gap between the first top surface and the second top surface, wherein the gap is less than a lateral distance between the first metal structure and another first metal structure adjacent to the first metal structure on the semiconductor die.

7. The method according to claim 1, further comprising: immersing the semiconductor die and the substrate into the electroless plating solution while being supported by the first support assembly and the second support assembly, wherein bonding the first top surface and the second top surface is at least partially based on immersing the semiconductor die and the substrate into the electroless plating solution.

8. The method according to claim 1, wherein the first support assembly and the second support assembly are configured to provide vacuum suction or electrostatic suction to hold the semiconductor die and the substrate, respectively.

9. A method for a semiconductor device assembly, the method comprising: forming a first plurality of copper pillars on a first semiconductor die and forming a second plurality of copper pillars on a second semiconductor die, wherein a semiconductor wafer includes the first and second semiconductor dies, and wherein the semiconductor wafer has a first side and the first plurality of copper pillars and the second plurality of copper pillars are disposed on the first side of the semiconductor wafer; Form a first group of conductive bumps and a second group of conductive bumps on a package support substrate, wherein the package support substrate has a first side, and the first group of conductive bumps and the second group of conductive bumps are disposed on the first side of the package support substrate; Attach a first support component to a second side of the semiconductor wafer opposite the first side of the semiconductor wafer; Attach a second support component to a second side of the package support substrate opposite the first side of the package support substrate; Manipulate the first support component and the second support component such that individual copper pillars among the first and second pluralities of copper pillars are aligned with individual conductive bumps among the first and second groups of conductive bumps, wherein the first and second pluralities of copper pillars face the first and second groups of conductive bumps; and Connect individual copper pillars among the first and second pluralities of copper pillars to individual conductive bumps among the first and second groups of conductive bumps via a conductive material formed in an electroless plating solution injected between the first and second pluralities of copper pillars and the first and second groups of conductive bumps.

10. The method according to claim 9, wherein the copper pillars among the first and second pluralities of copper pillars include a first top surface remote from the respective first and second semiconductor dies and the conductive bumps among the first and second groups of conductive bumps include a second top surface remote from the package support substrate, and wherein manipulating the first support component and the second support component provides a spacing between the first top surface of the copper pillars among the first and second pluralities of copper pillars and the second top surface of the conductive bumps among the first and second groups of conductive bumps, the spacing being less than a lateral distance between adjacent ones of the first plurality of copper pillars or the second plurality of copper pillars.

11. The method according to claim 9, further comprising: After connecting individual copper pillars among the first and second pluralities of copper pillars to individual conductive bumps among the first and second groups of conductive bumps, singulate the semiconductor wafer along a scribe line between the first and second semiconductor dies.

12. The method according to claim 11, further comprising: When singulating the semiconductor wafer, simultaneously singulate the package support substrate along the scribe line, wherein the scribe line is between the first and second groups of conductive bumps.

13. The method according to claim 9, further comprising: Immerse the semiconductor wafer and the package support substrate in the electroless plating solution while being supported by the first support component and the second support component, wherein connecting the individual copper pillars among the first and second pluralities of copper pillars to the individual conductive bumps among the first and second groups of conductive bumps is at least partially based on immersing the semiconductor wafer and the package support substrate in the electroless plating solution.

14. The method according to claim 9, wherein the first support component and the second support component are configured to provide vacuum suction or electrostatic suction to respectively hold the semiconductor wafer and the package support substrate.

15. The method according to claim 9, further comprising: heating the electroless plating solution, wherein the conductive material is formed at least in part based on heating the electroless plating solution.

16. A semiconductor device assembly, comprising: a first plurality of metal structures extending from a first side of a semiconductor die; a second plurality of metal structures extending from a first side of a substrate facing the first side of the semiconductor die; and a third plurality of metal structures coupling respective first metal structures to corresponding second metal structures, wherein the third metal structures are formed of an electroless plating solution injected between the first metal structures and the second metal structures, wherein: the first, second, and third metal structures include copper as a common major metal component; the third metal structures include an intermediate portion positioned between the first metal structures and the second metal structures and a peripheral portion surrounding sidewall surfaces of the first metal structures and the second metal structures; and the first, second, and third metal structures form a plurality of interconnects, wherein there are no other structures between the semiconductor die and the substrate other than the plurality of interconnects.

17. The semiconductor device assembly according to claim 16, wherein a first sidewall surface of the first metal structure is misaligned with respect to a corresponding second sidewall surface of the second metal structure.

18. The semiconductor device assembly according to claim 16, wherein: the first metal structure has a first diameter; and the second metal structure has a second diameter different from the first diameter.

Images