Semiconductor structure and manufacturing method

Abstract

This disclosure relates to a semiconductor structure and a method for manufacturing the same. In the case of layer offset between a substrate and a redistribution layer, the offset of the redistribution layer relative to the substrate is first determined, and then the energy distribution of the laser is adjusted according to the offset. The reflection of the light forms a via with an oblique hole structure to achieve electrical connection between the substrate and the redistribution layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology

[0002] In a current semiconductor structure, the redistribution layer and the substrate are bonded together by an adhesive layer, and the electrical channels between the redistribution layer and the substrate are connected by vias.

[0003] In the thermal process of fixing the redistribution layer to the substrate via an adhesive layer, material mismatch between the substrate and the redistribution layer, as well as issues related to the precision of the bonding equipment, can lead to layer misalignment between the substrate and the redistribution layer, resulting in via fabrication failure. Even with prior consideration of compensating for material expansion and contraction and bonding precision errors between the redistribution layer and the substrate to avoid this misalignment, the degree of misalignment can only be controlled to around 20 micrometers. This still results in via fabrication failure, preventing accurate connection between the redistribution layer and the substrate, ultimately causing semiconductor structure failure. Summary of the Invention

[0004] This disclosure provides semiconductor structures and methods for manufacturing them.

[0005] In a first aspect, this disclosure provides a semiconductor structure comprising: a substrate; an adhesive layer disposed on the substrate; a redistribution layer disposed on the adhesive layer; and a via penetrating the adhesive layer and the redistribution layer, wherein the via is an oblique via structure, and the redistribution layer is electrically connected to the substrate through the via.

[0006] In some alternative implementations, the substrate has a first alignment mark and the redistribution layer has a second alignment mark.

[0007] In some alternative embodiments, the via has a first sidewall angle and a second sidewall angle, the first sidewall angle being between 90 degrees and 156 degrees, and the second sidewall angle being between 34 degrees and 90 degrees.

[0008] In some alternative implementations, the via includes a top opening that penetrates the upper surface of the redistribution layer, and the length ratio of the diameter of the top opening to the height of the via is between 0.2 and 1.1.

[0009] In some alternative embodiments, the substrate is provided with conductive connectors, and the vias are electrically connected to the conductive connectors.

[0010] In some alternative implementations, the first alignment mark and the second alignment mark are cross-shaped alignment marks.

[0011] In some alternative implementations, the offset of the first alignment mark relative to the second alignment mark in a first preset direction or a second preset direction is less than or equal to the diameter of the upper opening of the through hole.

[0012] In a second aspect, this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate having conductive connectors; providing an adhesive layer on the substrate; providing a redistribution layer on the adhesive layer, the redistribution layer having a predetermined removal area, the predetermined removal area being offset from the conductive connectors; providing a laser to remove the predetermined removal area to expose the conductive connectors, forming a via penetrating the adhesive layer and the redistribution layer, the via being an oblique hole structure, the energy center axis of the laser being offset by a predetermined distance according to the offset.

[0013] In some alternative implementations, the substrate has a first alignment mark and the redistribution layer has a second alignment mark.

[0014] In some alternative implementations, after the redistribution layer is provided on the adhesive layer, the method further includes: determining the offset distance of the first alignment mark relative to the second alignment mark in a first preset direction or a second preset direction as an offset amount.

[0015] In some alternative embodiments, the via has a first sidewall angle and a second sidewall angle, the first sidewall angle being between 90 degrees and 156 degrees, and the second sidewall angle being between 34 degrees and 90 degrees.

[0016] In some alternative implementations, the via includes a top opening that extends through the upper surface of the redistribution layer, and the length ratio of the diameter of the top opening to the height of the via is between 0.2 and 1.1.

[0017] In some alternative implementations, the first alignment mark and the second alignment mark are cross-shaped alignment marks.

[0018] In some alternative implementations, the offset of the first alignment mark relative to the second alignment mark in a first preset direction or a second preset direction is less than or equal to the diameter of the upper opening of the through hole.

[0019] To address the technical problem of layer mismatch between the substrate and the redistribution layer, and subsequent failure of via fabrication, caused by material mismatch and bonding equipment precision issues, the semiconductor structure and manufacturing method disclosed herein first determine the offset of the redistribution layer relative to the substrate when layer mismatch occurs between the substrate and the redistribution layer. Then, the energy distribution of the laser is adjusted according to the offset, and the via with oblique hole structure is formed by light reflection to achieve electrical connection between the substrate and the redistribution layer. Attached Figure Description

[0020] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0021] Figure 1This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0023] Figure 3 This is a schematic diagram of a structure based on an embodiment of a via in the prior art;

[0024] Figure 4 This is a schematic diagram of a structure based on an embodiment of the via in this disclosure;

[0025] Figures 5A to 5C A schematic diagram of the manufacturing process of the semiconductor structure disclosed herein.

[0026] Symbol explanation:

[0027] 1-Substrate, 11-Conductive connector, 12-First alignment mark, 2-Adhesive layer, 3-Rewiring layer, 31-Second alignment mark, 4-Through hole, 5-Predetermined removal area, 6-Energy distribution of laser, D1-First aperture, H1-First height, α1-Third sidewall angle, β1-Fourth sidewall angle, D2-Aperture, H2-Height, α2-Second sidewall angle, β2-First sidewall angle. Detailed Implementation

[0028] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0029] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0030] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure may include: a substrate 1, an adhesive layer 2, and a redistribution layer 3. The adhesive layer 2 is disposed on the substrate 1, the redistribution layer 3 is disposed on the adhesive layer 2, and a via 4 penetrates both the adhesive layer 2 and the redistribution layer 3. The via 4 has an angled hole structure, and the redistribution layer 3 is electrically connected to the substrate 1 through the via 4.

[0032] Substrate 1 can be a coreless substrate or a cored substrate. Substrate 1 can be made of rigid substrate material or flexible substrate material. Rigid substrate material can be, for example, copper clad laminate material, and flexible substrate material can be, for example, PI (Polyimide) material. Substrate 1 can be a BGA (Ball Grid Array) substrate, and can be provided with multiple metal bumps and multiple solder balls.

[0033] The adhesive layer 2 can be made of, for example, epoxy resin conductive adhesive, phenolic resin conductive adhesive, polyurethane conductive adhesive, thermoplastic resin conductive adhesive, and polyimide conductive adhesive.

[0034] Various conductors, vias, buried vias, or blind vias can be provided in redistribution layer 3 to achieve circuit connections. It should be noted that there are no specific limitations on the size or orientation of vias, buried vias, or blind vias. If vias, buried vias, or blind vias are provided, they can be filled with conductive materials such as metals or metal alloys, or contain conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0035] The via 4 can be an angled hole structure, meaning the angle between the central axis and the horizontal plane is not 90 degrees, i.e., the central axis is an inclined line. The via 4 serves to electrically connect the substrate 1 and the redistribution layer 3. Compared to the via 4 of the existing structure, the angled hole structure of the via 4 has a larger area and better electrical connection effect.

[0036] In some alternative implementations, Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure according to the present disclosure. Figure 2 As shown, the substrate 1 has a first alignment mark 12, and the redistribution layer 3 has a second alignment mark 31.

[0037] Here, the first alignment mark 12 and the second alignment mark 31 can be used to determine the offset of the redistribution layer 3 relative to the substrate 1. The first alignment mark 12 and the second alignment mark 31 can be, for example, optical alignment elements. The shape of the first alignment mark 12 and the second alignment mark 31 can be, for example, rectangular or other shapes.

[0038] In some alternative implementations, the first alignment mark 12 and the second alignment mark 31 are cross-shaped alignment marks.

[0039] Here, the four corners and the center of the cross-shaped alignment mark can all be used as reference points for alignment, which improves the accuracy of alignment.

[0040] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of a structure based on an embodiment of a via in the prior art. Figure 4 This is a schematic diagram of a structure of a via 4 according to an embodiment of the present disclosure.

[0041] In some alternative implementations, such as Figure 4 As shown, the through hole 4 has a first sidewall angle β2 and a second sidewall angle α2. The first sidewall angle β2 is between 90 degrees and 156 degrees, and the second sidewall angle α2 is between 34 degrees and 90 degrees.

[0042] In practice, the specific angles of the first sidewall angle β2 and the second sidewall angle α2 can be defined by the height H2 of the via 4 and the offset distance between the first alignment mark 12 and the second alignment mark 31 (i.e., the offset of the redistribution layer 3 relative to the substrate 1).

[0043] Generally, the larger the height H2 of the via 4, the closer the first sidewall angle β2 and the second sidewall angle α2 are to 90 degrees. Conversely, the larger the height H2 of the via 4, the closer the first sidewall angle β2 is to 156 degrees, and the closer the second sidewall angle α2 is to 90 degrees. The smaller the offset distance between the first alignment mark 12 and the second alignment mark 31, the closer the first sidewall angle β2 and the second sidewall angle α2 are to 90 degrees. Conversely, the larger the offset distance between the first alignment mark 12 and the second alignment mark 31, the closer the first sidewall angle β2 is to 156 degrees, and the closer the second sidewall angle α2 is to 90 degrees.

[0044] like Figure 3 As shown, the third sidewall angle α1 and the fourth sidewall angle β1 of the via structure in the prior art can be between 90 degrees and 100 degrees.

[0045] In some alternative implementations, such as Figure 4As shown, the via 4 includes an upper opening that penetrates the upper surface of the redistribution layer 3. The ratio of the diameter D2 of the upper opening to the length H2 of the height H2 of the via 4 is between 0.2 and 1.1.

[0046] like Figure 3 As shown, in the prior art, the length ratio of the first aperture D1 of the upper opening of the through hole structure to the first height H1 of the through hole 4 can be greater than or equal to 1.2.

[0047] Therefore, relative to Figure 3 The via structure in the prior art is shown. Figure 4 The vias with the oblique hole structure shown in this disclosure can be applied to scenarios where there is layer misalignment between the substrate 1 and the redistribution layer 3. The vias with the oblique hole structure can realize the electrical connection between the substrate 1 and the redistribution layer 3.

[0048] In some alternative embodiments, the substrate 1 is provided with a conductive connector 11, and the through hole 4 is electrically connected to the conductive connector 11.

[0049] Here, the conductive connector 11 can be, for example, a pad.

[0050] In some alternative implementations, such as Figure 4 As shown, the offset of the first alignment mark 12 relative to the second alignment mark 31 in the first preset direction or the second preset direction is less than or equal to the aperture D2 of the upper opening of the through hole 4.

[0051] Here, the first preset direction can be, for example, a horizontal direction, and the second preset direction can be, for example, a vertical direction. When the offset of the first alignment mark 12 relative to the second alignment mark 31 is less than the aperture D2 of the upper opening, that is, when the offset of the redistribution layer 3 relative to the substrate 1 is smaller and the layer offset is smaller, the positional offset between the upper and lower openings of the via 4 is smaller, and the position of the via 4 can be controlled more accurately to achieve electrical connection between the redistribution layer 3 and the substrate 1.

[0052] The semiconductor structure disclosed herein can achieve electrical connection between the substrate 1 and the redistribution layer 3 under layer bias conditions by providing vias 4 with an oblique aperture structure. Furthermore, the vias 4 with the oblique aperture structure have a larger area and better electrical connection performance compared to existing via structures.

[0053] Figures 5A to 5B A schematic diagram of the manufacturing process of the semiconductor structure according to this disclosure. The figures have been simplified for better understanding of various aspects of this disclosure.

[0054] Please refer to Figure 5AA substrate 1 is provided, wherein the substrate 1 is provided with a conductive connector 11. Then, an adhesive layer 2 is provided on the substrate 1. Next, a redistribution layer 3 is provided on the adhesive layer 2, the redistribution layer 3 having a predetermined removal area 5, the predetermined removal area 5 being offset from the conductive connector 11.

[0055] Here, the pre-removal area 5 can be used to define the diameter of the upper opening of the through hole 4.

[0056] In practice, due to the layer offset between the substrate 1 and the redistribution layer 3, there is an offset between the predetermined removal area 5 and the conductive connector 11.

[0057] In some alternative embodiments, the substrate 1 has a first alignment mark 12 and the redistribution layer 3 has a second alignment mark 31.

[0058] In some alternative embodiments, after the redistribution layer 3 is disposed on the adhesive layer 2, the method further includes: determining the offset distance of the first alignment mark 12 relative to the second alignment mark 31 in a first preset direction or a second preset direction as an offset amount.

[0059] Specifically, the offset distance between the determined first alignment mark 12 and the second alignment mark 31 can be used as the offset between the predetermined removal area 5 and the conductive connector 11, that is, the offset between the substrate 1 and the redistribution layer 3.

[0060] Please refer to Figure 5B and Figure 5C A laser is used to remove a predetermined removal area 5 to expose the conductive connector 11. A through-hole 4 is then formed through the adhesive layer 2 and the redistribution layer 3. The through-hole 4 is an oblique hole structure, and the energy center axis of the laser is offset by a predetermined distance according to the offset.

[0061] Here, the laser can have an energy central axis; moving the position of the laser's energy central axis allows for adjustment of the laser's energy distribution. For example,... Figure 5B As shown, after the position of the laser energy center axis is moved to the left, the laser energy distribution 6 moves to the left as a whole. As a result, more tilted light enters from the right side of the laser energy distribution 6, which ultimately leads to the creation of the through hole 4 with the tilted hole structure.

[0062] The method for manufacturing a semiconductor structure provided in this disclosure, in the case of layer misalignment between substrate 1 and redistribution layer 3, firstly determines the offset of redistribution layer 3 relative to substrate 1 based on the offset of first alignment mark 12 relative to second alignment mark 31, then moves the position of the energy center axis of the laser according to the offset to adjust the energy distribution 6 of the laser, and then forms a through hole 4 with a slanted hole structure by light reflection to achieve electrical connection between substrate 1 and redistribution layer 3. In addition, the semiconductor structure provided in this disclosure can be completed in existing process equipment without the need to develop new equipment.

[0063] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor structure, comprising: A substrate having a first alignment mark; An adhesive layer is disposed on the substrate; A redistributable layer is disposed on the adhesive layer, the redistributable layer having a second alignment mark; A via hole penetrates the adhesive layer and the redistribution layer. The via hole has an angled structure, and the redistribution layer is electrically connected to the substrate through the via hole. Wherein, the first alignment mark and the second alignment mark are cross-shaped alignment marks, and the offset of the first alignment mark relative to the second alignment mark in a first preset direction or a second preset direction is less than or equal to the diameter of the upper opening of the through hole.

2. The semiconductor structure according to claim 1, wherein, The via includes an upper opening that penetrates the upper surface of the redistribution layer, and the ratio of the diameter of the upper opening to the height of the via is between 0.2 and 1.

1.

3. The semiconductor structure according to claim 1, wherein, The substrate is provided with a conductive connector, and the through hole is electrically connected to the conductive connector.

4. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, the substrate being provided with conductive connectors; An adhesive layer is disposed on the substrate; A redistribution layer is provided on the adhesive layer, the redistribution layer having a predetermined removal area, and the predetermined removal area having an offset from the conductive connector; A laser is provided to remove the predetermined removal area to expose the conductive connector, forming a via through the adhesive layer and the redistribution layer. The via is an angled hole structure, and the energy center axis of the laser is offset by a predetermined distance according to the offset.

5. The method according to claim 4, wherein, The substrate has a first alignment mark, and the redistribution layer has a second alignment mark; as well as After the redistribution layer is formed on the adhesive layer, the method further includes: The offset distance between the first alignment mark and the second alignment mark in a first preset direction or a second preset direction is determined as the offset amount.

6. The method according to claim 5, wherein, The first alignment mark and the second alignment mark are cross-shaped alignment marks.

7. The method according to claim 5 or 6, wherein, The offset of the first alignment mark relative to the second alignment mark in the first preset direction or the second preset direction is less than or equal to the diameter of the upper opening of the through hole.

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