Semiconductor package

Abstract

A semiconductor package includes: a frame having a through opening; a first semiconductor chip and a second semiconductor chip, the first semiconductor chip being disposed in the through opening and having a first active surface on which a first connection pad is disposed and a first passive surface opposite to the first active surface, the second semiconductor chip being disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second passive surface opposite to the second active surface; first and second bumps electrically connected to the first connection pad and the second connection pad respectively; first and second dummy bumps disposed at a same horizontal height as that of the first bump and a same horizontal height as that of the second bump respectively; first and second pillars electrically connected to the first bump and the second bump respectively; a connection member including a redistribution layer electrically connected to each of the first pillar and the second pillar; and a dummy pillar disposed between the frame and the connection member.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0166308, filed with the Korean Intellectual Property Office on December 13, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Exemplary embodiments of the inventive concept relate to semiconductor packages. Background art

[0004] As the demand for electronic products with high capacity, reduced thickness, and size has increased, various forms of semiconductor packages have been developed. Among various types of semiconductor packaging technologies, packaging technologies have been developed in which a single package is configured to include multiple semiconductor chips. Summary of the invention

[0005] Exemplary embodiments of the inventive concept will provide a semiconductor package that can implement high - density wiring on a substrate using a low - cost process.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a frame having a through - opening; a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor chip being disposed in the through - opening and having a first active surface on which a first connection pad is disposed and a first passive surface opposite to the first active surface, the second semiconductor chip being disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second passive surface opposite to the second active surface. The semiconductor package further includes: a first bump and a second bump electrically connected to the first connection pad and the second connection pad, respectively; a first dummy bump and a second dummy bump disposed at the same horizontal height as the first bump and the second bump, respectively; a first pillar and a second pillar electrically connected to the first bump and the second bump, respectively; a connection member including a redistribution layer electrically connected to each of the first pillar and the second pillar; and a dummy pillar disposed between the frame and the connection member.

[0007] According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a frame having a through opening; a first semiconductor chip disposed in the through opening of the frame and having a first active surface on which a first connection pad is disposed and a first passive surface opposite to the first active surface; a first bump pattern including first bumps connected to the first connection pads on the first active surface of the first semiconductor chip and at least one first dummy bump not connected to the first connection pads; and a first filling layer filling an area between the frame and the first semiconductor chip, covering the first passive surface of the first semiconductor chip and a lower surface of the frame, and covering a part of the first active surface of the first semiconductor chip.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a frame having a through opening; a plurality of semiconductor chips; a plurality of filling layers respectively surrounding side surfaces of the plurality of semiconductor chips; a connection member disposed on the plurality of filling layers; a plurality of pillars disposed in the plurality of filling layers; and a plurality of bumps respectively electrically connected to the plurality of semiconductor chips. The plurality of semiconductor chips include a first semiconductor chip disposed in the through opening and a second semiconductor chip partially overlapping the first semiconductor chip and the frame. The plurality of filling layers include a first filling layer surrounding a side surface of the first semiconductor chip in the through opening and a second filling layer surrounding a side surface of the second semiconductor chip. The plurality of bumps include first bumps electrically connected to first connection pads of the first semiconductor chip and second bumps electrically connected to second connection pads of the second semiconductor chip. The plurality of pillars include first pillars penetrating the second filling layer on the first filling layer and electrically connected to the first bumps and a plurality of dummy pillars penetrating the second filling layer on the frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0011] Figure 2 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0012] Figure 3It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0013] Figure 4 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0014] Figure 5 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0015] Figure 6 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0016] Figure 7 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0017] Figure 8 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0018] Figures 9 to 16 It is a cross-sectional view showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. Detailed Description

[0019] Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout the drawings, like reference numerals may refer to like elements.

[0020] Figure 1 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment.

[0021] Referring to Figure 1 , the semiconductor package 100A may include a frame 101, a plurality of semiconductor chips 20 including a first semiconductor chip 120, a plurality of bump patterns 40, a plurality of pillars 10, and a connection member 550 including a redistribution layer 552.

[0022] The frame 101 may have an upper surface 101U and a lower surface 101L. The upper surface 101U may face the connection member 550.

[0023] The frame 101 may have a through opening 101H. The first semiconductor chip 120 may be disposed in the through opening 101H. In an exemplary embodiment, passive components (such as inductors or capacitors) may be disposed in the through opening 101H.

[0024] The frame 101 may have a first side surface 101S1 and a second side surface 101S2. The first side surface 101S1 may be exposed by the through-opening 101H and may face the first semiconductor chip 120. The second side surface 101S2 may be opposite to the first side surface 101S1. The second side surface 101S2 may form a part of the outer side surface of the semiconductor package 100A.

[0025] The frame 101 may include an insulating material. The insulating material may include at least one of, for example, a thermosetting resin (e.g., an epoxy resin) and a thermoplastic resin (e.g., a polyimide resin). The insulating material may include an insulating material in which a core material such as an inorganic filler and / or glass fiber (or glass cloth or glass fabric) is impregnated in a thermosetting resin or a thermoplastic resin, for example, prepreg, Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), etc.

[0026] In an exemplary embodiment, the frame 101 may include a plurality of insulating layers, a plurality of wiring layers buried in the insulating layers, and a plurality of wiring via layers that electrically connect the plurality of wiring layers to each other.

[0027] The frame 101 may be used as a support member that provides a flat surface on which a plurality of semiconductor chips 20 may be stacked. The frame 101 may increase the stiffness of the semiconductor package 100A and may maintain the flatness of the semiconductor package 100A.

[0028] In addition to the first semiconductor chip 120, the plurality of semiconductor chips 20 may further include a second semiconductor chip 220 disposed on the first semiconductor chip 120, a third semiconductor chip 320 disposed on the second semiconductor chip 220, and a fourth semiconductor chip 420 disposed on the third semiconductor chip 320.

[0029] The plurality of semiconductor chips 20 may have a structure in which the first to fourth semiconductor chips 120, 220, 320, and 420 are stacked. However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, the plurality of semiconductor chips 20 may have a structure in which fewer than four or more than four semiconductor chips are stacked.

[0030] The first to fourth semiconductor chips 120, 220, 320, and 420 may each include an integrated circuit (IC). The first to fourth semiconductor chips 120, 220, 320, and 420 may each have an active surface on which an integrated circuit is provided and a passive surface opposite to the active surface. Connection pads to which electrical signals can be applied may be provided on the active surface of each of the first to fourth semiconductor chips 120, 220, 320, and 420. For example, the first semiconductor chip 120 may have a first active surface 120S1 on which a first connection pad 120P is provided and a first passive surface 120S2 opposite to the first active surface 120S1. Similarly, the second semiconductor chip 220 may include a second active surface 220S1 on which a second connection pad 220P is provided and a second passive surface 220S2 opposite to the second active surface 220S1, the third semiconductor chip 320 may include a third active surface 320S1 on which a third connection pad 320P is provided and a third passive surface 320S2 opposite to the third active surface 320S1, and the fourth semiconductor chip 420 may include a fourth active surface 420S1 on which a fourth connection pad 420P is provided and a fourth passive surface 420S2 opposite to the fourth active surface 420S1.

[0031] The first semiconductor chip 120 may be disposed in the through-opening 101H such that the first active surface 120S1 may face the connection member 550. The second semiconductor chip 220 may be disposed such that the second active surface 220S1 may face the connection member 550 on the upper surface 101U of the frame 101. The third semiconductor chip 320 may be disposed such that the third active surface 320S1 may face the connection member 550 on the upper surface 101U. The fourth semiconductor chip 420 may be disposed such that the fourth active surface 420S1 may face the connection member 550 on the upper surface 101U.

[0032] The first to fourth semiconductor chips 120, 220, 320, and 420 may be sequentially offset such that the first to fourth connection pads 120P, 220P, 320P, and 420P may be exposed. For example, the first to fourth semiconductor chips 120, 220, 320, and 420 may be sequentially offset and stacked toward a corner of the connection member 550.

[0033] In an exemplary embodiment, a portion of the first to fourth semiconductor chips 120, 220, 320, and 420 may overlap each other vertically. For example, at least a portion of the second semiconductor chip 220 may be disposed on the first semiconductor chip 120 such that at least a portion of the second semiconductor chip 220 may overlap at least a portion of the first semiconductor chip 120. The second semiconductor chip 220 may overlap the first semiconductor chip 120 and the frame 101 partially.

[0034] In semiconductor package 100A, the first semiconductor chip 120 may be disposed in the through opening 101H of the frame 101, and the second to fourth semiconductor chips 220, 320, and 420 may be stacked on the upper surface 101U of the frame 101. However, the exemplary embodiments are not limited thereto. For example, in an exemplary embodiment, another frame may be further disposed on the frame 101, and the second semiconductor chip 220 may be disposed in the through opening of the other frame. This configuration may also be applied to the third semiconductor chip 320 and the fourth semiconductor chip 420. By providing the frame, a semiconductor package with improved flatness can be provided.

[0035] The first to fourth semiconductor chips 120, 220, 320, and 420 may all be implemented as memory chips. The memory chips may include, for example, DRAM, SRAM, flash memory, PRAM, ReRAM, FeRAM, or MRAM.

[0036] In an exemplary embodiment, the first to fourth semiconductor chips 120, 220, 320, and 420 may be the same type of semiconductor chips or different types of semiconductor chips.

[0037] In an exemplary embodiment, the first to fourth semiconductor chips 120, 220, 320, and 420 may be included in a high bandwidth memory (HBM).

[0038] The plurality of bump patterns 40 may include a first bump pattern 140 disposed on the first active surface 120S1 of the first semiconductor chip 120, a second bump pattern 240 disposed on the second active surface 220S1 of the second semiconductor chip 220, a third bump pattern 340 disposed on the third active surface 320S1 of the third semiconductor chip 320, and a fourth bump pattern 440 disposed on the fourth active surface 420S1 of the fourth semiconductor chip 420.

[0039] The first bump pattern 140 may include a first bump 141 disposed on the first connection pad 120P and a first dummy bump 141D disposed at the same horizontal height as the horizontal height of the first bump 141. For example, the first bump 141 and the first dummy bump 141D may be substantially aligned with each other in a cross-sectional view. In an exemplary embodiment, the first bump 141 is electrically connected to the first connection pad 120P, while the first dummy bump 141D is not electrically connected to the first connection pad 120P.

[0040] In this document, the term "dummy" may refer to an element that is manufactured together with other elements for achieving electrical connection, but does not itself achieve electrical connection. For example, according to an exemplary embodiment, a dummy bump may be manufactured together with a bump, and although the bump can be electrically connected to another element, the dummy bump is not electrically connected to another element. Similarly, according to an exemplary embodiment, a dummy post may be manufactured together with a post, and although the post can be electrically connected to another element, the dummy post is not electrically connected to another element.

[0041] The second bump pattern 240 may include a second bump 241 disposed on the second connection pad 220P and a second dummy bump 241D disposed at the same horizontal height as the horizontal height of the second bump 241. For example, the second bump 241 and the second dummy bump 241D may be substantially aligned with each other in a cross-sectional view. In an exemplary embodiment, the second bump 241 is electrically connected to the second connection pad 220P, while the second dummy bump 241D is not electrically connected to the second connection pad 220P.

[0042] The third bump pattern 340 may include a third bump 341 disposed on the third connection pad 320P and a third dummy bump 341D disposed at the same horizontal height as the horizontal height of the third bump 341. In an exemplary embodiment, the third bump 341 is electrically connected to the third connection pad 320P, while the third dummy bump 341D is not electrically connected to the third connection pad 320P.

[0043] The fourth bump pattern 440 may include a fourth bump 441 disposed on the fourth connection pad 420P and a fourth dummy bump 441D disposed at the same horizontal height as the horizontal height of the fourth bump 441. In an exemplary embodiment, the fourth bump 441 is electrically connected to the fourth connection pad 420P, while the fourth dummy bump 441D is not electrically connected to the fourth connection pad 420P.

[0044] In an exemplary embodiment, the first to fourth bumps 141, 241, 341, and 441 may all have a columnar shape.

[0045] In an exemplary embodiment, the width of each of the first to fourth bumps 141, 241, 341, and 441 may be similar to or substantially the same as the width of each of the first to fourth connection pads 120P, 220P, 320P, and 420P. For example, the width of the first connection pad 120P may be in the range of about 40 μm to about 60 μm, and the first bump 141 may have a similar width.

[0046] In an exemplary embodiment, the number of the first bumps 141, the gaps between the first bumps 141, and the arrangement form of the first bumps 141 may be the same as the number of the first connection pads 120P, the gaps between the first connection pads 120P, and the arrangement form of the first connection pads 120P, respectively. The first bumps 141 may be aligned with the first connection pads 120P.

[0047] In an exemplary embodiment, the number of the second bumps 241, the gaps between the second bumps 241, and the arrangement form of the second bumps 241 may be the same as the number of the second connection pads 220P, the gaps between the second connection pads 220P, and the arrangement form of the second connection pads 220P, respectively. The second bumps 241 may be aligned with the second connection pads 220P.

[0048] In an exemplary embodiment, the number of the third bumps 341, the gaps between the third bumps 341, and the arrangement form of the third bumps 341 may be the same as the number of the third connection pads 320P, the gaps between the third connection pads 320P, and the arrangement form of the third connection pads 320P, respectively. The third bumps 341 may be aligned with the third connection pads 320P.

[0049] In an exemplary embodiment, the number of the fourth bumps 441, the gaps between the fourth bumps 441, and the arrangement form of the fourth bumps 441 may be the same as the number of the fourth connection pads 420P, the gaps between the fourth connection pads 420P, and the arrangement form of the fourth connection pads 420P, respectively. The fourth bumps 441 may be aligned with the fourth connection pads 420P.

[0050] In an exemplary embodiment, the first to fourth dummy bumps 141D, 241D, 341D, and 441D may each have a plate shape. The heights of the first to fourth dummy bumps 141D, 241D, 341D, and 441D may be the same as the heights of the first to fourth bumps 141, 241, 341, and 441, respectively.

[0051] In an exemplary embodiment, the first to fourth bump patterns 140, 240, 340, and 440 may each have a height greater than about 0 μm and equal to or less than about 40 μm.

[0052] In an exemplary embodiment, the first to fourth bump patterns 140, 240, 340, and 440 may each have a height greater than about 0 μm and equal to or less than about 30 μm. Thus, in an exemplary embodiment, the first bump 141 and the second bump 241 may each have a height greater than about 0 μm and equal to or less than about 30 μm.

[0053] In an exemplary embodiment, the first to fourth bump patterns 140, 240, 340, and 440 may include a metal such as copper (Cu). The first to fourth bump patterns 140, 240, 340, and 440 may be formed of the same material.

[0054] The first to fourth dummy bumps 141D, 241D, 341D, and 441D may improve the warpage of the semiconductor package 100A and may maintain the flatness of the semiconductor package 100A. The first to fourth dummy bumps 141D, 241D, 341D, and 441D may dissipate heat generated from the plurality of semiconductor chips 20.

[0055] The plurality of posts 10 may include a first post 110 disposed on the first connection pad 120P, a second post 210 disposed on the second connection pad 220P, a third post 310 disposed on the third connection pad 320P, and a dummy post 110D disposed on the frame 101.

[0056] The first post 110 may be disposed on the first bump 141. The first post 110 may vertically overlap the first bump 141. For example, in a cross-sectional view, the first post 110 may overlap the first bump 141. The first post 110 may extend in a direction substantially perpendicular to the first active surface 120S1 of the first semiconductor chip 120. The first post 110 may be electrically connected to the first connection pad 120P. The width of the lower portion of the first post 110 may be greater than the width of the first bump 141.

[0057] The first post 110 may include a first lower post 111, a first intermediate post 112, and a first upper post 113 stacked in sequence. The first lower post 111, the first intermediate post 112, and the first upper post 113 may vertically overlap each other. The first lower post 111, the first intermediate post 112, and the first upper post 113 may have different widths. The first intermediate post 112 may be disposed on the first lower post 111, and the first upper post 113 may be disposed on the first intermediate post 112.

[0058] The first width w1 of the first lower post 111 may be greater than the width of the first bump 141. The second width w2 of the first intermediate post 112 may be less than the first width w1. The third width w3 of the first upper post 113 may be greater than the second width w2. Accordingly, the first post 110 may be understood as having a plurality of regions with different widths. Accordingly, the alignment margin of the first lower post 111, the first intermediate post 112, and the first upper post 113 may be improved.

[0059] In an exemplary embodiment, the cross-sectional shape of each of the first lower column 111, the first intermediate column 112, and the first upper column 113 may vary. For example, the first lower column 111, the first intermediate column 112, and the first upper column 113 may each have a circular shape or an oval shape.

[0060] In an exemplary embodiment, the first lower column 111, the first intermediate column 112, and the first upper column 113 may each have a conical shape or a cylindrical shape.

[0061] The second column 210 may be disposed on the second bump 241. The second column 210 may vertically overlap with the second bump 241. The second column 210 may extend in a direction substantially perpendicular to the second active surface 220S1 of the second semiconductor chip 220. The second column 210 may be electrically connected to the second connection pad 220P. The width of the lower portion of the second column 210 may be greater than the width of the second bump 241.

[0062] The second column 210 may include a second lower column 211 and a second upper column 212 that vertically overlap each other and have different widths. The second upper column 212 may be disposed on the second lower column 211.

[0063] The width of the second lower column 211 may be greater than the width of the second bump 241 and be substantially the same as the second width w2 of the first intermediate column 112. The width of the second upper column 212 may be greater than the second width w2 and be substantially the same as the third width w3 of the first upper column 113. The second column 210 may be understood as having a plurality of regions with different widths. In this case, the alignment margin of the second lower column 211 and the second upper column 212 may be improved.

[0064] In an exemplary embodiment, the cross-sectional shape of each of the second lower column 211 and the second upper column 212 may vary. For example, the cross-section may have a circular or oval shape.

[0065] In an exemplary embodiment, the second lower column 211 and the second upper column 212 may each have a conical shape or a cylindrical shape.

[0066] The third column 310 may be disposed on the third bump 341. The third column 310 may vertically overlap with the third bump 341. The third column 310 may extend in a direction substantially perpendicular to the third active surface 320S1 of the third semiconductor chip 320. The third column 310 may be electrically connected to the third connection pad 320P. The width of the lower portion of the third column 310 may be greater than the width of the third bump 341.

[0067] The width of the third column 310 may be greater than the width of the third bump and be substantially the same as the third width w3 of the first upper column 113 or the width of the second upper column 212.

[0068] In an exemplary embodiment, the distance between the upper end and the lower end of the first pillar 110 may be greater than the distance between the upper end and the lower end of the second pillar 210.

[0069] In an exemplary embodiment, the distance between the upper end and the lower end of the second pillar 210 may be greater than the distance between the upper end and the lower end of the third pillar 310.

[0070] In an exemplary embodiment, the cross-sectional shape of the third pillar 310 may vary. For example, the cross-section may have a circular shape or an oval shape.

[0071] In an exemplary embodiment, the third pillar 310 may have a conical shape or a cylindrical shape.

[0072] In an exemplary embodiment, the plurality of pillars 10 may have a structure in which the first to third pillars 110, 210, and 310 are provided. However, the exemplary embodiment is not limited thereto. For example, the number of the plurality of pillars 10, the gap between the plurality of pillars 10, and the arrangement form of the plurality of pillars 10 may be changed according to the number of semiconductor chips included in the plurality of semiconductor chips 20 and / or the number of exposed connection pads.

[0073] In an exemplary embodiment, the first to third pillars 110, 210, and 310 may include a metal material including copper. The first to third pillars 110, 210, and 310 may each have a columnar shape.

[0074] The first to third pillars 110, 210, and 310 may respectively form a circuit path between the first to third semiconductor chips 120, 220, and 320 and the redistribution layer 552 of the connection member 550 through the first to third connection pads 120P, 220P, and 320P. The connection member 550 for redistribution may have a relatively high wiring density without increasing the thickness of the semiconductor package, thereby reducing the size of the semiconductor package. Since columns are used instead of using wire bonding using gold (Au) for the circuit path of the redistribution layer 552, the process cost can be reduced, and a reduced connection distance can be achieved, thereby improving the operating speed of the semiconductor chip. According to the exemplary embodiment, by forming the plurality of pillars using electroplating and forming a redistribution layer for redistributing the pillars, a packaging technology that can reduce the manufacturing cost and can implement a plurality of input and output (I / O) paths can be provided.

[0075] Dummy post 110D may be disposed on the upper surface 101U of the frame 101 and may overlap with the frame 101. Dummy post 110D may be disposed between the frame 101 and the connection member 550. Dummy post 110D may extend in a direction substantially perpendicular to the first active surface 120S1 of the first semiconductor chip 120. Dummy post 110D may be electrically insulated from the plurality of semiconductor chips 20. Dummy post 110D may be electrically insulated from the signal pattern of the redistribution layer 552. In an exemplary embodiment, dummy post 110D is not electrically connected to the connection member 550.

[0076] Dummy post 110D may include a first dummy post 111D, a second dummy post 112D, and a third dummy post 113D that vertically overlap each other and have different widths. The third dummy post 113D may be disposed on the second dummy post 112D, and the second dummy post 112D may be disposed on the first dummy post 111D.

[0077] The width of the first dummy post 111D may be substantially the same as the first width w1 of the first lower post 111. The width of the second dummy post 112D may be substantially the same as the second width w2 of the first intermediate post 112. The width of the third dummy post 113D may be substantially the same as the third width w3 of the first upper post 113. Thus, dummy post 110D may be understood as having a plurality of regions with different widths.

[0078] In an exemplary embodiment, the cross-sectional shape of each of the first dummy post 111D, the second dummy post 112D, and the third dummy post 113D may vary. For example, the cross-section may have a circular shape or an elliptical shape.

[0079] In an exemplary embodiment, each of the first dummy post 111D, the second dummy post 112D, and the third dummy post 113D may have a tapered shape or a cylindrical shape.

[0080] In an exemplary embodiment, the height and / or thickness of at least one dummy post 110D may be substantially the same as the height and / or thickness of the first post 110.

[0081] In an exemplary embodiment, at least a portion of the dummy post 110D may be disposed between the frame 101 and the third semiconductor chip 320 or between the frame 101 and the fourth semiconductor chip 420.

[0082] In an exemplary embodiment, at least one dummy post 110D may overlap with at least one of the plurality of semiconductor chips 20. For example, the first dummy post 111D may be disposed between the frame 101 and the third semiconductor chip 320 and may overlap with the third semiconductor chip 320. As Figure 1As shown, the first dummy post 111D and the second dummy post 112D may be disposed between the frame 101 and the fourth semiconductor chip 420 and may overlap the fourth semiconductor chip 420.

[0083] In an exemplary embodiment, the dummy post 110D may include a metallic material including copper. The dummy post 110D may have a columnar shape.

[0084] In an exemplary embodiment, the number of dummy posts 110D, the gaps between the dummy posts 110D, and the arrangement form of the dummy posts 110D may be changed. For example, a greater number of dummy posts 110D may be disposed between the frame 101 and the connection member 550. The number of stacked semiconductor chips may be increased or decreased according to the number of dummy posts 110D.

[0085] Since the dummy posts 110D are disposed on the frame 101, the semiconductor package 100A may include a greater number of metal layers, thereby reducing warping of the semiconductor package 100A.

[0086] The dummy posts 110D may improve the heat dissipation performance of the semiconductor package 100A. For example, since the dummy posts 110D are disposed between the frame 101 and the connection member 550, heat generated from the plurality of semiconductor chips 20 may be efficiently dissipated.

[0087] In an exemplary embodiment, the height of the dummy post 110D may be substantially the same as the height of the first post 110. The distance between the upper end and the lower end of the dummy post 110D may be substantially the same as the distance between the upper end and the lower end of the first post 110.

[0088] In an exemplary embodiment, the upper surfaces of the first to third posts 110, 210, and 310 may be substantially coplanar with the upper surface of the dummy post 110D. For example, the upper surfaces of the first to third posts 110, 210, and 310 may be substantially aligned with the upper surface of the dummy post 110D.

[0089] In an exemplary embodiment, the upper surface of the first lower post 111 may be substantially coplanar with the upper surface of the first dummy post 111D. For example, the upper surface of the first lower post 111 may be substantially aligned with the upper surface of the first dummy post 111D.

[0090] In an exemplary embodiment, the upper surfaces of the first intermediate post 112, the second lower post 211, and the second dummy post 112D may be substantially coplanar with each other. For example, the upper surfaces of the first intermediate post 112, the second lower post 211, and the second dummy post 112D may be substantially aligned with each other.

[0091] In an exemplary embodiment, the upper surfaces of the first upper pillar 113, the second upper pillar 212, the third pillar 310, and the third dummy pillar 113D may be substantially coplanar with each other. For example, the upper surfaces of the first upper pillar 113, the second upper pillar 212, the third pillar 310, and the third dummy pillar 113D may be substantially aligned with each other.

[0092] In an exemplary embodiment, the first to third pillars 110, 210, and 310 and the first to third dummy pillars 111D, 112D, and 113D may include first to third metal seed layers 107, 207, and 307 respectively disposed below the first to third pillars 110, 210, and 310 and the first to third dummy pillars 111D, 112D, and 113D. For example, the first pillar 110 may include a first metal seed layer 107 disposed below the first pillar 110 and connected to the first connection pad 120P. The first metal seed layer 107 may be disposed below the first dummy pillar 111D and may also be disposed on the frame 101. The first to third metal seed layers 107, 207, and 307 may be formed by an electroless plating method. In an exemplary embodiment, the first to third metal seed layers 107, 207, and 307 are not provided.

[0093] In addition to the redistribution layer 552, the connection member 550 may further include an insulating layer 551 that buries the redistribution layer 552 and redistribution vias 553 that penetrate the insulating layer 551 and are connected to the redistribution layer 552.

[0094] The connection member 550 may redistribute the first to fourth connection pads 120P, 220P, 320P, and 420P of the first to fourth semiconductor chips 120, 220, 320, and 420. The first to fourth connection pads 120P, 220P, 320P, and 420P may be physically and / or electrically connected to an external entity through the connection member 550.

[0095] The insulating layer 551 may include the above-mentioned insulating material. The insulating material may include a photosensitive insulating material such as a PID resin.

[0096] In an exemplary embodiment, when the insulating layer 551 includes a photosensitive insulating material, the thickness of the insulating layer 551 may be reduced, and a fine pitch of the redistribution vias 553 may be efficiently achieved.

[0097] The redistribution layer 552 can perform redistribution on the first to fourth connection pads 120P, 220P, 320P, and 420P. The redistribution layer 552 can include a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layer 552 can perform various functions according to the design of each individual layer. For example, the redistribution layer 552 can include a ground pattern, a power pattern, a signal pattern, etc. The signal pattern can transmit various signals other than ground signals, power signals, etc., such as data signals. The pattern can include wirings and pads.

[0098] The redistribution vias 553 can electrically connect the redistribution layer 552 to the first to fourth connection pads 120P, 220P, 320P, and 420P to each other, such that a circuit path can be formed in the connection member 550. The redistribution vias 553 can include a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution vias 553 can be filled vias completely filled with a metallic material, or can be conformal vias in which a metallic material is formed along the walls of the through-holes. The redistribution vias 553 can have a cross-section with a tapered shape. For example, the redistribution vias 553 can have a tapered shape in which the width of the upper part is larger than the width of the lower part.

[0099] The number of each of the insulating layer 551, the redistribution layer 552, and the redistribution vias 553 of the connection member 550 can be greater than or less than the example shown in the figure.

[0100] Referring Figure 1 , the semiconductor package 100A can further include a plurality of filling layers 30.

[0101] The plurality of filling layers 30 can include a first filling layer 130, a second filling layer 230, a third filling layer 330, and a fourth filling layer 430. The second filling layer 230 can be disposed on the first filling layer 130, the third filling layer 330 can be disposed on the second filling layer 230, and the fourth filling layer 430 can be disposed on the third filling layer 330.

[0102] In an exemplary embodiment, the connection member 550 can be disposed on the plurality of filling layers 30. The plurality of pillars 10 can be disposed in the plurality of filling layers 30.

[0103] The first filling layer 130 may be disposed in the through-opening 101H of the frame 101 and may cover the first active surface 120S1 and the first passive surface 120S2 of the first semiconductor chip 120. In an exemplary embodiment, the first filling layer 130 may cover the entire first passive surface 120S2 of the first semiconductor chip 120 and may partially cover the first active surface 120S1 of the first semiconductor chip 120. The first filling layer 130 may surround the side surface of the first semiconductor chip 120. The first filling layer 130 may cover the side surface of the first bump pattern 140. The first filling layer 130 may extend to cover the first passive surface 120S2 of the first semiconductor chip 120 and cover the lower surface 101L of the frame 101. The first filling layer 130 may fill the area between the frame 101 and the first semiconductor chip 120, may extend to and cover the first passive surface 120S2 of the first semiconductor chip 120 and the lower surface 101L of the frame 101, and may also extend to and cover a part of the first active surface 120S1 of the first semiconductor chip 120.

[0104] The second filling layer 230 may be disposed on the first active surface 120S1 of the first semiconductor chip 120 and may cover the second active surface 220S1 of the second semiconductor chip 220. The second filling layer 230 may surround the side surface of the second semiconductor chip 220. The second filling layer 230 may cover the side surface of the second bump pattern 240. The second filling layer 230 may cover the side surface of the first lower post 111 and the side surface of the first dummy post 111D. The second filling layer 230 may surround at least a part of the first post 110 and at least a part of the dummy post 110D. The first lower post 111 and the first dummy post 111D may penetrate through the second filling layer 230. At least a part of the second filling layer 230 may be in direct contact with at least a part of the first filling layer 130.

[0105] The third filling layer 330 may be disposed on the second active surface 220S1 of the second semiconductor chip 220 and may cover the third active surface 320S1 of the third semiconductor chip 320. The third filling layer 330 may surround the side surface of the third semiconductor chip 320. The third filling layer 330 may cover the side surface of the third bump pattern 340. The third filling layer 330 may cover the side surface of the first intermediate post 112, the side surface of the second lower post 211, and the side surface of the second dummy post 112D. The first intermediate post 112, the second lower post 211, and the second dummy post 112D may penetrate through the third filling layer 330. At least a part of the third filling layer 330 may be in direct contact with at least a part of the second filling layer 230.

[0106] The fourth filling layer 430 may be disposed on the third active surface 320S1 of the third semiconductor chip 320 and may cover the fourth active surface 420S1 of the fourth semiconductor chip 420. The fourth filling layer 430 may surround the side surface of the fourth semiconductor chip 420. The fourth filling layer 430 may cover the side surface of the fourth bump pattern 440. The fourth filling layer 430 may cover the side surfaces of the first upper post 113, the second upper post 212, the third post 310, and the third dummy post 113D. The first upper post 113, the second upper post 212, the third post 310, and the third dummy post 113D may penetrate through the fourth filling layer 430. At least a part of the fourth filling layer 430 may be in direct contact with at least a part of the third filling layer 330.

[0107] The first to fourth filling layers 130, 230, 330, and 430 may include an insulating material. The insulating material may include a non-photosensitive insulating material, which includes, for example, inorganic fillers and / or insulating resins. The non-photosensitive insulating material may include at least one of, for example, thermosetting resins (such as epoxy resins) and thermoplastic resins (such as polyimide resins). The non-photosensitive insulating material may be ABF or EMC, or may be a photoimageable sealant (PIE).

[0108] As further described below, the semiconductor package 100A may undergo a grinding process, and in this case, the surface of the first bump pattern 140 connected to the first post 110 may be disposed at the same level as the upper surface of the first filling layer 130, the surface of the second bump pattern 240 connected to the second post 210 may be disposed at the same level as the upper surface of the second filling layer 230, and the surface of the third bump pattern 340 connected to the third post 310 may be disposed at the same level as the upper surface of the third filling layer 330. For example, the surface of the second bump 241 connected to the second post 210 may be disposed at the same level as the upper surface (the part in contact with the third filling layer 330) of the second filling layer 230. The term "the same level" may include slight differences caused by process errors.

[0109] Referring to Figure 1 , the semiconductor package 100A may further include adhesion layers 220A, 320A, and 420A for fixing the plurality of semiconductor chips 20.

[0110] A die attach film (DAF) can be used to implement the adhesion layers 220A, 320A, and 420A. The adhesion layers 220A, 320A, and 420A can be, for example, tapes that fix a plurality of semiconductor chips 20. The tape used to implement the adhesion layers 220A, 320A, and 420A can be, for example, an epoxy composition. The plurality of semiconductor chips 20 can be stably fixed through the adhesion layers 220A, 320A, and 420A, and thus the reliability can be improved.

[0111] The adhesion layers 220A, 320A, and 420A can include a first adhesion layer 220A, a second adhesion layer 320A, and a third adhesion layer 420A.

[0112] In an exemplary embodiment, the first adhesion layer 220A can be disposed under the second passive surface 220S2 of the second semiconductor chip 220. The first adhesion layer 220A can be in contact with the frame 101, the first filling layer 130, and the first dummy bump 141D.

[0113] In an exemplary embodiment, the second adhesion layer 320A can be disposed under the third passive surface 320S2 of the third semiconductor chip 320. The second adhesion layer 320A can be in contact with the second filling layer 230 and the second dummy bump 241D.

[0114] In an exemplary embodiment, the third adhesion layer 420A can be disposed under the fourth passive surface 420S2 of the fourth semiconductor chip 420. The third adhesion layer 420A can be in contact with the third filling layer 330 and the third dummy bump 341D.

[0115] Referring to Figure 1 , the semiconductor package 100A can further include an under-bump metal layer 560 disposed on the connection member 550, a conductive pattern 570 disposed on the under-bump metal layer 560, and a metal layer 105.

[0116] The conductive pattern 570 can physically connect and / or electrically connect the semiconductor package 100A to an external entity. For example, the semiconductor package 100A can be mounted on a main board of an electronic device through the conductive pattern 570. The conductive pattern 570 can be electrically connected to the redistribution layer 552 exposed through the under-bump metal layer 560. The conductive pattern 570 can include tin (Sn) or a tin (Sn)-containing alloy. The conductive pattern 570 can be formed of, for example, solder, but the exemplary embodiment is not limited thereto.

[0117] The conductive pattern 570 can be configured as, for example, a land, a ball, a pin, etc. A plurality of conductive patterns 570 or a single conductive pattern 570 can be provided. When a plurality of conductive patterns 570 are provided, the conductive patterns 570 can include, for example, copper pillars or solder. When a single conductive pattern 570 is provided, the conductive pattern 570 can include, for example, tin-silver solder or copper, but the exemplary embodiments are not limited thereto.

[0118] In the exemplary embodiments, the number of the conductive patterns 570, the gap between the conductive patterns 570, and the arrangement form of the conductive patterns 570 can be changed.

[0119] Figure 2 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment.

[0120] For ease of explanation, further descriptions of the previously described elements and technical aspects can be omitted.

[0121] Referring to Figure 2 and different from the semiconductor package 100A described with reference to Figure 1 in the semiconductor package 100B, the first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da can all have a columnar shape instead of a plate shape.

[0122] In the exemplary embodiments, the number of the first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da, the gap between the first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da, and the arrangement form of the first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da can vary. The thickness and / or height of each of the first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da can be substantially the same as the thickness and / or height of each of the first to fourth bumps 141, 241, 341, and 441.

[0123] The first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da can be included in the first to fourth bump patterns 140a, 240a, 340a, and 440a together with the first to fourth bumps 141, 241, 341, and 441. The first bump pattern 140a can be disposed on the first active surface of the first semiconductor chip 120 at a consistent horizontal height, can maintain the flatness of the semiconductor package 100B, and can improve the heat dissipation performance. The second to fourth bump patterns 240a, 340a, and 440a can all have a structure similar to the above structure and can provide the above effects.

[0124] Figure 3It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment.

[0125] For ease of explanation, further descriptions of the previously described elements and technical aspects may be omitted.

[0126] Referring to Figure 3 , in the semiconductor package 100C, the widths of the upper portions of each of the first to third pillars 110a, 210a, and 310a and the width of the upper portion of the dummy pillar 110Da may be different from the widths of the corresponding pillars of the first semiconductor package 100A described above. For example, the first pillar 110a may include a first lower pillar 111 having a first width w1, a first intermediate pillar 112 having a second width w2 smaller than the first width w1, and a first upper pillar 113a having a third width w3a smaller than the second width w2. The above exemplary embodiment may also be applied to the second upper pillar 212a of the second pillar 210a and the third pillar 310a.

[0127] The dummy pillar 110Da may include a first dummy pillar 111D having a first width w1, a second dummy pillar 112D having a second width w2 smaller than the first width w1, and a third dummy pillar 113Da having a third width w3a smaller than the second width w2. By differently configuring the widths of each of the first to third pillars 110a, 210a, and 310a and the width of the dummy pillar 110Da, the alignment margin between the pillars can be improved.

[0128] Figure 4 It is a cross-sectional view showing a semiconductor package according to an exemplary embodiment.

[0129] For ease of explanation, further descriptions of the previously described elements and technical aspects may be omitted.

[0130] Referring to Figure 4 , different from the semiconductor package 100B described with reference to Figure 2 , the semiconductor package 100D may further include first to fourth insulating layers 125, 225, 325, and 425 respectively provided on the first to fourth active surfaces of the first to fourth semiconductor chips 120, 220, 320, and 420.

[0131] The first insulating layer 125 may cover the side surfaces of the first bump pattern 140a on the first active surface. Thus, in the exemplary embodiment, the first insulating layer 125 may cover the side surfaces of the first bump 141 and the first dummy bump 141Da on the first active surface 120S1 of the first semiconductor chip 120. The first bump pattern 140a may penetrate the first insulating layer 125. The side surfaces of the first insulating layer 125 may be covered by the first filling layer 130.

[0132] The descriptions of the second to fourth insulating layers 225, 325, and 425 may be similar to the description of the first insulating layer 125 above. Therefore, the repeated detailed descriptions thereof will be omitted.

[0133] The first to fourth insulating layers 125, 225, 325, and 425 may include an insulating material. For example, the insulating material may be a photosensitive insulating material such as a PID resin.

[0134] The first to fourth insulating layers 125, 225, 325, and 425 may improve the stiffness of the semiconductor package 100D to improve its flatness. In addition, the first to fourth insulating layers 125, 225, 325, and 425 may be used as support members such that the first to fourth bump patterns 140a, 240a, 340a, and 440a can maintain their shapes.

[0135] Figure 5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0136] For ease of illustration, further descriptions of the previously described elements and technical aspects may be omitted.

[0137] Referring to Figure 5 , different from the semiconductor package 100A described with reference to Figure 1 , the semiconductor package 100E may further include a first connection member 150 disposed between the first filling layer 130 and the second filling layer 230, a second connection member 250 disposed between the second filling layer 230 and the third filling layer 330, and a third connection member 350 disposed between the third filling layer 330 and the fourth filling layer 430.

[0138] The first connection member 150 may include a first interlayer insulating layer 151, a first wiring layer 152 disposed on the first interlayer insulating layer 151, and a first connection via 153 penetrating the first interlayer insulating layer 151 and electrically connected to the first wiring layer 152. A part of the first wiring layer 152 may be electrically connected to the first bump 141 through the first connection via 153. The first lower post 111 may be disposed on the first wiring layer 152 and may be electrically connected to the first connection pad 120P through the first wiring layer 152. The first dummy post 111D may also be disposed on the first wiring layer 152.

[0139] The second connection member 250 may include a second interlayer insulating layer 251, a second wiring layer 252 disposed on the second interlayer insulating layer 251, and a second connection via 253 that penetrates the second interlayer insulating layer 251 and is electrically connected to the second wiring layer 252. A part of the second wiring layer 252 may be electrically connected to the second bump 241 through the second connection via 253. The second lower post 211 may be disposed on the second wiring layer 252 and may be electrically connected to the second connection pad 220P through the second wiring layer 252. The first intermediate post 112 may be disposed on the second wiring layer 252 and may be electrically connected to the first lower post 111 through the second wiring layer 252. The second dummy post 112D may also be disposed on the second wiring layer 252.

[0140] The third connection member 350 may include a third interlayer insulating layer 351, a third wiring layer 352 disposed on the third interlayer insulating layer 351, and a third connection via 353 that penetrates the third interlayer insulating layer 351 and is electrically connected to the third wiring layer 352. A part of the third wiring layer 352 may be electrically connected to the third bump 341 through the third connection via 353. The third post 310 may be disposed on the third wiring layer 352 and may be electrically connected to the third connection pad 320P through the third wiring layer 352. The second upper post 212 may be disposed on the third wiring layer 352 and may be electrically connected to the second lower post 211 through the third wiring layer 352. The first upper post 113 may be disposed on the third wiring layer 352 and may be electrically connected to the first intermediate post 112 through the third wiring layer 352. The third dummy post 113D may also be disposed on the third wiring layer 352.

[0141] Since the semiconductor package 100E further includes a first connection member 150 having a first wiring layer 152, a second connection member 250 having a second wiring layer 252, and a third connection member 350 having a third wiring layer 352, the process margin of the posts disposed on each layer can be improved, and the first to third interlayer insulating layers 151, 251, and 351 can be set to be flat, thereby improving the flatness of the semiconductor package 100E.

[0142] Figure 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0143] For ease of explanation, further descriptions of the previously described elements and technical aspects may be omitted.

[0144] Referring to Figure 6 and, in reference to Figure 5Unlike the described semiconductor package 100E, in the semiconductor package 100F, the first to fourth dummy bumps 141Da, 241Da, 341Da, and 441Da can all have a columnar shape instead of a plate shape. The description of this configuration is substantially the same as the description of the semiconductor package 100E, and thus, the repeated description thereof is omitted.

[0145] Figure 7 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment.

[0146] For ease of explanation, further description of the previously described elements and technical aspects may be omitted.

[0147] Referring to Figure 7 , in an exemplary embodiment, unlike the semiconductor package 100A described with reference to Figure 1 , the semiconductor package 100G does not include the fourth bump pattern 440. Accordingly, the second connection pad 420P of the fourth semiconductor chip 420 can be in direct contact with the redistribution path 553 of the connection member 550 and can be electrically connected to the redistribution layer 552. Since the process for forming the fourth bump pattern 440 is not performed, the process cost can be reduced, and the electrical connection path between the fourth connection pad 420P of the fourth semiconductor chip 420 and the redistribution layer 552 can be reduced.

[0148] Figure 8 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment.

[0149] Referring to Figure 8 , the semiconductor package 100H may further include a substrate 701, a lower semiconductor chip 620 disposed on the substrate 701, an interposer substrate 601 disposed on the lower semiconductor chip 620, and passive components 720.

[0150] In an exemplary embodiment, the semiconductor package 100A may be arranged such that the conductive pattern 570 of the semiconductor package 100A can be in contact with the first surface of the interposer substrate 601. The conductive pattern 570 can be electrically connected to the interposer substrate 601 on the interposer substrate 601. For example, four semiconductor packages 100A can be arranged at the same horizontal height as the first surface of the interposer substrate 601. The first to fourth connection pads 120P, 220P, 320P, and 420P that can be used as input and output (I / O) terminals can be redistributed again through the interposer substrate 601. The conductive pattern 570 can be fixed by, for example, underfill resin.

[0151] The lower semiconductor chip 620 may be disposed on a second surface of the interposer substrate 601 opposite to the first surface of the interposer substrate 601. The lower semiconductor chip 620 may include an integrated circuit (IC). The integrated circuit may include a processor chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.

[0152] The lower semiconductor chip 620 may be implemented as an application processor (AP), but the exemplary embodiments are not limited thereto. The lower semiconductor chip 620 may be implemented as: a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc., a logic chip such as an analog-to-digital converter, an application specific IC (ASIC), or a different type of chip such as a power management IC (PMIC), or may be implemented by a combination thereof.

[0153] The lower semiconductor chip 620 may be in contact with the substrate 701 through a first conductive pattern 670a, and the interposer substrate 601 may be in contact with the substrate 701 through a second conductive pattern 670b.

[0154] The passive components 720 may be disposed on a lower surface of the substrate 701 and may be disposed between third conductive patterns 770. The passive components 720 may be configured as chip-type capacitors such as MLCCs or LICCs or chip-type inductors such as power inductors. The number of the passive components 720 is not limited to any specific example, and in the exemplary embodiments, the number of the passive components 720 may be greater than Figure 8 the number shown.

[0155] Figures 9 to 16 is a cross-sectional view showing a method of manufacturing a semiconductor package (e.g., a semiconductor package according to an exemplary embodiment). Figures 9 to 16 shows a cross-section corresponding to Figure 1 the corresponding cross-section.

[0156] Referring to Figure 9 , a frame 101 having a through opening 101H may be disposed on an adhesive film 103. A first semiconductor chip 120 having a first active surface 120S1 on which a first connection pad 120P is disposed may be disposed in the through opening 101H.

[0157] The adhesive film 103 may be a tape for fixing the frame 101. For example, the adhesive film 103 may include a heat-treatable curable adhesive tape whose adhesive force may be weakened by heat treatment, or the adhesive film 103 may include an infrared curable adhesive tape whose adhesive force may be weakened by irradiating infrared rays.

[0158] The frame 101 may have a first side surface 101S1 exposed through the through-opening 101H. The first side surface 101S1 may face the first semiconductor chip 120. The frame 101 may include an insulating material as described above with reference to Figure 1 as described.

[0159] The first semiconductor chip 120 may be arranged such that the first active surface 120S1 may face the adhesive film 103 in the through-opening 101H of the frame 101. The first bump pattern 140 may be provided on the first active surface 120S1 of the first semiconductor chip 120. The first bump pattern 140 may include a first bump 141 connected to the first connection pad 120P on the first connection pad 120P and a first dummy bump 141D not connected to the first connection pad 120P.

[0160] Referring to Figure 10 , a first filling layer 130 may be provided to fill the space between the through-opening 101H of the frame 101 and the first semiconductor chip 120.

[0161] In the through-opening 101H of the frame 101, the first filling layer 130 may fill the space between the first side surface 101S1 of the frame 101 and the side surface of the first semiconductor chip 120. The first filling layer 130 may cover the first active surface 120S1 and the first passive surface 120S2 of the first semiconductor chip 120. The first filling layer 130 may extend to cover one surface (e.g., the lower surface 101L) of the frame 101.

[0162] In an exemplary embodiment, forming the first filling layer 130 may include laminating and curing a precursor for forming the first filling layer 130. In an exemplary embodiment, the first filling layer 130 may be formed by applying the precursor to seal the first semiconductor chip 120 and curing the precursor. By performing the curing process, the first semiconductor chip 120 may be fixed.

[0163] A metal layer 105 may be formed. The metal layer 105 may be provided on the first filling layer 130. In an exemplary embodiment, the thickness of the metal layer 105 may vary (e.g., the thickness may be greater than Figures 10 to 16 the thickness shown), or the metal layer 105 may not be provided. The metal layer 105 controls warping. The metal layer 105 may dissipate heat generated from the plurality of semiconductor chips 20 (see Figure 1 ).

[0164] The adhesive film 103 may be removed (see Figure 9) By removing the adhesion film 103, the upper surface 101U of the frame 101 can be exposed. In an exemplary embodiment, the adhesion film 103 may be removed after forming the metal layer 105, but the exemplary embodiment is not limited thereto. For example, in an exemplary embodiment, the adhesion film 103 may be removed before forming the metal layer 105.

[0165] In an exemplary embodiment, when the adhesion film 103 includes a heat-treatable curable adhesive tape whose adhesion can be weakened by heat treatment, the removal of the adhesion film 103 may be performed after weakening the adhesion of the adhesion film 103 by performing heat treatment.

[0166] In an exemplary embodiment, when the adhesion film 103 includes an infrared-curable adhesive tape whose adhesion can be weakened by irradiating infrared rays, the removal of the adhesion film 103 may be performed after weakening the adhesion of the adhesion film 103 by irradiating infrared rays to the adhesion film 103.

[0167] Referring to Figure 11 , a metal seed layer 107 covering the upper surface 101U of the frame 101 may be provided.

[0168] The metal seed layer 107 may extend to cover the upper surface 101U of the frame 101, a part of the first filling layer 130, the upper surface of the first bump 141, and the upper surface of the first dummy bump 141D. The metal seed layer 107 may be formed by an electrolytic plating method or an electroless plating method.

[0169] In an exemplary embodiment, the formation of the metal seed layer 107 is not performed.

[0170] Referring to Figure 12 , a mask layer 108 covering the metal seed layer 107 may be formed, and a via hole may be formed by partially removing the mask layer 108 to expose a part of the upper surface of the metal seed layer 107.

[0171] The mask layer 108 may be formed by a method of laminating and curing a precursor or a method of applying and curing a precursor material. A via hole may be formed in the mask layer 108 using, for example, photolithography, mechanical drilling, and / or laser drilling. The mask layer 108 may include an insulating material, for example, a photoimageable dielectric (PID). As a result of forming the via hole, a part of the upper surface of the metal seed layer 107 may be exposed.

[0172] Referring to Figure 13 , a first lower pillar 111 and a first dummy pillar 111D filling the via hole may be formed, and the mask layer 108 and the portion of the upper surface of the metal seed layer 107 that is not exposed may be removed together.

[0173] In an exemplary embodiment, the first lower post 111 and the first dummy post 111D may be formed by a plating process. The plating process may be, for example, an electrolytic plating process or an electroless plating process.

[0174] In an exemplary embodiment, the first lower post 111 and the first dummy post 111D may be formed using, for example, a subtractive method, an additive method, a semi-additive method, and a modified semi-additive method (MSAP).

[0175] In an exemplary embodiment, the first lower post 111 and the first dummy post 111D may be formed using, for example, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0176] After partially removing the metal seed layer 107, the metal seed layer 107 may remain at the lower portion of each of the first lower post 111 and the first dummy post 111D.

[0177] In an exemplary embodiment, the metal seed layer 107 is not provided. In this case, both the first lower post 111 and the first dummy post 111D may be in direct contact with the upper surface 101U of the frame 101.

[0178] Referring Figure 14 , a second semiconductor chip 220 may be disposed on the first semiconductor chip 120. The second semiconductor chip 220 may have a second passive surface 220S2 to which an adhesion layer 220A is attached and a second active surface 220S1 on which a second connection pad 220P is disposed.

[0179] The second semiconductor chip 220 may be offset from the first semiconductor chip 120.

[0180] Disposing the second semiconductor chip 220 may include: disposing the second semiconductor chip 220 on the first semiconductor chip 120 while forming a second bump pattern 240 on the second active surface 220Sl of the second semiconductor chip 220. The second bump pattern 240 may include a second bump 241 connected to the second connection pad 220P on the second connection pad 220P and a second dummy bump 241D not connected to the second connection pad 220P.

[0181] Referring Figure 15 , a second filling layer 230 covering the second semiconductor chip 220 may be disposed.

[0182] The second filling layer 230 may cover the second active surface 220S1 of the second semiconductor chip 220. The second filling layer 230 may cover the side surfaces of the second bump pattern 240. The second filling layer 230 may cover the side surfaces of each of the first lower post 111, the first dummy post 111D, and the second bump pattern 240.

[0183] In an exemplary embodiment, forming the second filling layer 230 may include laminating and curing a precursor for forming the second filling layer 230. In an exemplary embodiment, the second filling layer 230 may be applied and cured to seal the second semiconductor chip 220. By performing a curing process, the second semiconductor chip 220 may be fixed.

[0184] The second filling layer 230 may be planarized until the second bump pattern 240, the first lower post 111, and the first dummy post 111D are exposed.

[0185] Planarizing the second filling layer 230 may include performing a grinding process. In this process, the upper surfaces of the second bump pattern 240, the first lower post 111, and the first dummy post 111D may be substantially coplanar with each other. For example, the upper surfaces of the second bump pattern 240, the first lower post 111, and the first dummy post 111D may be substantially aligned with each other.

[0186] Referring to Figure 16 and Figures 11 to 15 described above, the methods described with reference to

[0187] may be repeatedly performed to form the third semiconductor chip 320, the fourth semiconductor chip 420, the third bump pattern 340, the fourth bump pattern 440, the first post 110, the second post 210, the third post 310, the dummy post 110D, the third filling layer 330, and the fourth filling layer 430.

[0188] Returning to referring to Figure 1 and

[0189] In an exemplary embodiment, the connection member 550 may be formed by the following method: forming an insulating layer 551 using a lamination process or a coating process; forming a through hole in the insulating layer 551; and forming a redistribution layer 552 and a redistribution path 553 by an electrolytic plating process or an electroless plating process. When using PID as the insulating layer, a photolithography method may be used to form through holes with a fine pitch. An opening may be formed in the insulating layer 551, a under-bump metal layer 560 may be disposed in the opening, and a conductive pattern 570 may be formed on the under-bump metal layer 560 and the conductive pattern 570 may be electrically connected to the under-bump metal layer 560. The under-bump metal layer 560 may be electrically connected to the redistribution layer 552. Thus, it is possible to manufacture Figure 1 the semiconductor package 100A shown.

[0190] In an exemplary embodiment, the connection member 550 may be disposed on the uppermost part of a plurality of stacked semiconductor chips 20. Different from the exemplary embodiment shown in the figure, when the plurality of semiconductor chips 20 include only the first semiconductor chip 120 and the second semiconductor chip 220, the connection member 550 may be disposed on the second fill layer 230, and redistribution may be performed on the first connection pads 120P of the first semiconductor chip 120 and the second connection pads 220P of the second semiconductor chip 220.

[0191] According to the foregoing exemplary embodiments, a semiconductor package having improved packaging performance and an appropriate package size may be provided.

[0192] In an exemplary embodiment, for ease of description, the lower part, the lower surface, etc. may indicate the downward direction of the cross section in the reference drawings, and the upper part, the upper surface, etc. may indicate the opposite direction, unless otherwise specified.

[0193] In an exemplary embodiment, the term "connection" may include "direct connection", and may also include "indirect connection" through an adhesion layer. In addition, the term "electrical connection" may include "physical connection" and "non-physical connection". Terms including ordinal numbers such as "first", "second", etc. may be used in the specification and claims to distinguish elements from each other. These terms are only used for the purpose of distinguishing one component from another component, and are not used to define them. For example, the "first" member in an exemplary embodiment may be described as the "second" member in another exemplary embodiment.

[0194] It should be understood that the description of the features or aspects in each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments, unless the context clearly indicates otherwise.

[0195] As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0196] It will be understood that when an element such as a film, region, layer or component is referred to as being "on", "connected to", "coupled to" or "adjacent to" another component, the element can be directly on, directly connected to, directly coupled to or directly adjacent to the other component, or intervening components may be present. It should also be understood that when an element is referred to as being between two components, the element can be the only element between the two components, or one or more intervening components may also be present. It should also be understood that when an element is referred to as "covering" another element, the element can be the only element covering the other element, or one or more intervening components may also cover the other element. Other words used to describe the relationship between elements should be interpreted in a similar manner.

[0197] In this document, when elements are described as being substantially coplanar with each other, it should be understood that the elements are precisely coplanar with each other, or nearly coplanar with each other (e.g., within measurement error), as would be understood by a person of ordinary skill in the art. In addition, when a value is described as being approximately the same as or approximately equal to another value, it should be understood that the values are equal to each other within measurement error, or if measurably unequal, the values are close enough in value to be functionally equal to each other, as would be understood by a person of ordinary skill in the art. It will also be understood that when two components or directions are described as extending substantially parallel or perpendicular to each other, the two components or directions extend precisely parallel or perpendicular to each other, or extend generally parallel or perpendicular to each other, as would be understood by a person of ordinary skill in the art (e.g., within the range of measurement error). Other uses of the terms "substantially" and "about" should be interpreted in a similar manner.

[0198] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, the semiconductor package comprising: A frame having a through opening; A plurality of semiconductor chips, the plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor chip being disposed in the through opening and having a first active surface on which a first connection pad is disposed and a first passive surface opposite to the first active surface, the second semiconductor chip being disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second passive surface opposite to the second active surface; A first bump and a second bump, the first bump and the second bump being electrically connected to the first connection pad and the second connection pad respectively; A first dummy bump and a second dummy bump, the first dummy bump and the second dummy bump being disposed at a same level as the horizontal height of the first bump and at a same level as the horizontal height of the second bump respectively; A first post and a second post, the first post and the second post being electrically connected to the first bump and the second bump respectively; A first connection member, the first connection member including a first redistribution layer electrically connected to each of the first post and the second post; And A dummy post disposed between the frame and the first connection member.

2. The semiconductor package according to claim 1, wherein, The upper surfaces of the first post and the second post are substantially coplanar with the upper surface of the dummy post.

3. The semiconductor package according to claim 1, the semiconductor package further comprising: A first filling layer covering the first active surface and the first passive surface of the first semiconductor chip.

4. The semiconductor package according to claim 3, the semiconductor package further comprising: A second filling layer covering the second active surface of the second semiconductor chip, wherein the second filling layer surrounds at least a part of the first post and at least a part of the dummy post.

5. The semiconductor package according to claim 4, wherein, At least a part of the second filling layer is in direct contact with at least a part of the first filling layer.

6. The semiconductor package according to claim 4, the semiconductor package further comprising: A second connection member disposed between the first filling layer and the second filling layer and including a first interlayer insulating layer, a second redistribution layer, and a first redistribution via.

7. The semiconductor package according to claim 1, Among them, The width of the lower part of the first post is greater than the width of the first bump, wherein the width of the lower part of the second post is greater than the width of the second bump.

8. The semiconductor package according to claim 1, wherein, Both the first bump and the second bump have a height equal to or less than 30 μm.

9. The semiconductor package according to claim 1, the semiconductor package further comprising: A first insulating layer covering the side surfaces of the first bump and the first dummy bump on the first active surface of the first semiconductor chip.

10. The semiconductor package according to claim 1, the semiconductor package further comprising: Under-bump metal layer, the under-bump metal layer being electrically connected to the first redistribution layer; And Conductive pattern, the conductive pattern being electrically connected to the under-bump metal layer.

11. The semiconductor package according to claim 10, the semiconductor package further comprising: Lower semiconductor chip; And Interposer substrate, the interposer substrate being disposed on the lower semiconductor chip, wherein the conductive pattern is electrically connected to the interposer substrate.

12. A semiconductor package, the semiconductor package comprising: Frame, the frame having a through opening; A plurality of semiconductor chips, the plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor chip being disposed in the through opening of the frame and having a first active surface on which a first connection pad is disposed and a first passive surface opposite to the first active surface, the second semiconductor chip being disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second passive surface opposite to the second active surface; First bump pattern and second bump pattern, the first bump pattern including a first bump connected to the first connection pad on the first active surface of the first semiconductor chip and at least one first dummy bump not connected to the first connection pad, the second bump pattern including a second bump connected to the second connection pad on the second active surface of the second semiconductor chip and at least one second dummy bump not connected to the second connection pad; First pillar and second pillar, the first pillar and the second pillar being electrically connected to the first bump and the second bump respectively; Connection member, the connection member being disposed on the first pillar and the second pillar and including a redistribution layer electrically connected to the first pillar and the second pillar and redistribution paths connecting the redistribution layer to the first connection pad and the second connection pad; Dummy pillar, the dummy pillar overlapping with the frame and being disposed between the frame and the connection member; And First filling layer, the first filling layer filling the region between the frame and the first semiconductor chip, covering the first passive surface of the first semiconductor chip and the lower surface of the frame, and covering a part of the first active surface of the first semiconductor chip.

13. The semiconductor package according to claim 12, Among them, The first pillar vertically overlaps with the first bump and extends in a direction substantially perpendicular to the first active surface of the first semiconductor chip.

14. The semiconductor package according to claim 13, Among them, The first pillar includes a first lower pillar, a first middle pillar and a first upper pillar sequentially stacked with each other, wherein the first lower pillar and the first middle pillar have different widths.

15. A semiconductor package, the semiconductor package comprising: Frame, the frame having a through opening; A plurality of semiconductor chips; A plurality of filling layers, the plurality of filling layers respectively surrounding side surfaces of the plurality of semiconductor chips; A connection member, the connection member being disposed on the plurality of filling layers; A plurality of columns, the plurality of columns being disposed in the plurality of filling layers; And A plurality of bumps, the plurality of bumps being electrically connected to the plurality of semiconductor chips respectively, Wherein, the plurality of semiconductor chips include a first semiconductor chip disposed in the through-opening and a second semiconductor chip that partially overlaps with the first semiconductor chip and the frame, Wherein, the plurality of filling layers include a first filling layer around a side surface of the first semiconductor chip in the through-opening and a second filling layer around a side surface of the second semiconductor chip; Wherein, the plurality of bumps include a first bump electrically connected to a first connection pad of the first semiconductor chip and a second bump electrically connected to a second connection pad of the second semiconductor chip, Wherein, the plurality of columns include a first column that penetrates the second filling layer on the first filling layer and is electrically connected to the first bump and a plurality of dummy columns that penetrate the second filling layer on the frame.

16. The semiconductor package according to claim 15, wherein, At least one of the plurality of dummy columns overlaps with at least one of the plurality of semiconductor chips.

17. The semiconductor package according to claim 15, Among them, The plurality of semiconductor chips further include a third semiconductor chip disposed on the second semiconductor chip and a fourth semiconductor chip disposed on the third semiconductor chip, Wherein, the plurality of filling layers further include a third filling layer around a side surface of the third semiconductor chip and a fourth filling layer around a side surface of the fourth semiconductor chip, Wherein, the plurality of bumps further include a third bump electrically connected to a third connection pad of the third semiconductor chip and a fourth bump electrically connected to a fourth connection pad of the fourth semiconductor chip, Wherein, the plurality of columns further include a second column that penetrates the third filling layer on the second filling layer and is electrically connected to the second bump and a third column that penetrates the fourth filling layer on the third filling layer and is electrically connected to the third bump.

18. The semiconductor package according to claim 15, wherein, The connection member includes a redistribution layer electrically connected to the plurality of columns and redistribution paths that connect the redistribution layer to the first connection pad and the second connection pad.

19. The semiconductor package according to claim 18, the semiconductor package further includes: A under-bump metal layer, the under-bump metal layer being electrically connected to the redistribution layer; And A conductive pattern, the conductive pattern being electrically connected to the under-bump metal layer.

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