Substrate with embedded electronic components

Abstract

The present disclosure provides a substrate embedded with electronic components, the substrate embedded with electronic components comprising: a first electronic component; a first insulating material covering at least a portion of the first electronic component; a first wiring layer arranged on one surface of the first insulating material; a second electronic component arranged on the first wiring layer and connected to the first electronic component through the first wiring layer; and a second insulating material covering at least a portion of the second electronic component, wherein at least a portion of the first electronic component is exposed from another surface of the first insulating material opposite to the one surface of the first insulating material.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0167951 filed on December 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a substrate with embedded electronic components. Background Art

[0003] Recently, electronic devices are required to have relatively high performance and relatively high functionality while being slim and miniaturized. Therefore, the number of electronic components to be mounted on a printed circuit board is increasing, but the number of electronic components that can be mounted on the surface of the printed circuit board is limited. This is because the size of the printed circuit board is also required to be reduced according to the miniaturization and slimming of the electronic devices. Therefore, a technology for embedding electronic components (such as passive components and active components) in a substrate with electronic components embedded in a printed circuit board has been developed. Summary of the invention

[0004] An aspect of the present disclosure is to provide an electronic component-embedded substrate having a shortened electrical connection path.

[0005] Another aspect of the present disclosure is to provide an electronic component-embedded substrate having improved power integrity (PI) characteristics due to an increase in capacitance of the electronic component and / or a decrease in equivalent series inductance (ESL) of the electronic component.

[0006] Another aspect of the present disclosure is to provide an electronic component-embedded substrate having improved warpage characteristics.

[0007] According to one aspect of the present disclosure, a substrate embedded with electronic components includes: a first electronic component; a first insulating material covering at least a portion of the first electronic component; a first wiring layer disposed on one surface of the first insulating material; a second electronic component disposed on the first wiring layer and connected to the first electronic component through the first wiring layer; and a second insulating material covering at least a portion of the second electronic component, wherein at least a portion of the first electronic component is exposed from another surface of the first insulating material opposite to the one surface of the first insulating material.

[0008] According to another aspect of the present disclosure, a substrate embedded with electronic components includes: a base substrate, including an insulating body; a first electronic component and a second electronic component, both embedded in the insulating body; a first wiring layer, arranged between the first electronic component and the second electronic component, and connected to an electrode of the first electronic component; and a connecting conductor, containing a material different from that of the first wiring layer, and contacting the electrode of the second electronic component and the first wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is an example of a block diagram schematically illustrating an electronic device system according to an example.

[0011] Figure 2 is a perspective view schematically illustrating an electronic device according to an example.

[0012] Figure 3 is a cross-sectional view schematically illustrating an electronic component-embedded substrate 100A according to an example.

[0013] FIG. 4A to FIG. 8 A manufacturing process of an electronic component embedded substrate 100A according to an example is schematically illustrated.

[0014] Fig. 9 is a cross-sectional view schematically showing an electronic component-embedded substrate 100B according to another example.

[0015] FIG. 10A to FIG. 14 A manufacturing process of a substrate 100B embedded with electronic components according to another example is schematically shown.

[0016] Fig.15 is a cross-sectional view schematically showing an example in which a semiconductor package is mounted on an electronic component-embedded substrate 100A according to an example.

[0017] Fig.16 A circuit diagram between electronic components included in the electronic component-embedded substrate 100A according to an example is schematically shown. DETAILED DESCRIPTION

[0018] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0019] Electronic Devices

[0020] Figure 1is an example of a block diagram schematically illustrating an electronic device system according to an example.

[0021] Referring to the drawings, the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically and / or electrically connected thereto. These components may be connected to other components to be described below through various signal lines 1090.

[0022] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0023] The network-related components 1030 may include components operating according to protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution Data Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 .

[0024] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0025] The electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010, depending on the type of the electronic device 1000. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. These other components may also include other components for various purposes according to the type of the electronic device 1000, etc.

[0026] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0027] Figure 2 is a perspective view schematically illustrating an electronic device according to an example.

[0028] Referring to the accompanying drawings, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component (e.g., a semiconductor package 1121), but is not limited thereto. The semiconductor package 1121 may be a surface-mounted package in which a semiconductor chip or a passive component is mounted on a packaging substrate in the form of a packaging substrate, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0029] Substrate with embedded electronic components

[0030] Figure 3 is a cross-sectional view schematically illustrating an electronic component-embedded substrate 100A according to an example.

[0031] Reference Figure 3 According to the example, the substrate 100A embedded with electronic components may include: a base substrate 110; an electronic component 120, embedded in the base substrate 110; a first accumulation structure 130 and a second accumulation structure 140, respectively disposed on both sides of the base substrate 110; a first passivation layer 150, disposed on the first accumulation structure 130; and a second passivation layer 160, disposed on the second accumulation structure 140. As required, an electrical connection metal member (not shown) disposed in each of the openings of the first passivation layer 150 and the second passivation layer 160 may be further included. In addition, as required, the first accumulation structure 130 and the second accumulation structure 140 and the first passivation layer 150 and the second passivation layer 160 may also be omitted.

[0032] In this specification, "disposed on" a component may refer to being disposed on the upper side or upper surface of the component, but is not limited to its direction. In some cases, it may refer to being disposed on the lower side or lower surface of the component.

[0033] The base substrate 110 may include a region in which the electronic component 120 is embedded, and may include an insulating material 111, a wiring layer 112, a via 113, and a through-hole 114. Specifically, the base substrate 110 may include: a first insulating material 111A; a first wiring layer 112A disposed on the first insulating material 111A; a first via 113A penetrating the first insulating material 111A and connecting the first wiring layer 112A and the first electronic component 120A; a first through-hole 114A penetrating the first insulating material 111A and connecting the first wiring layer 112A and the first electronic component 120A; The invention includes a first wiring layer 142A connected in the second accumulation structure 140; a second insulating material 111B, which is arranged on the first insulating material 111A and covers the first wiring layer 112A; a second wiring layer 112B, which is arranged on the second insulating material 111B; a second via 113B, which penetrates the second insulating material 111B and connects the second wiring layer 112B and the second electronic component 120B; and a second through via 114B, which penetrates the second insulating material 111B and connects the first wiring layer 112A and the second wiring layer 112B.

[0034] At least a portion of the first electronic component 120A may be covered by the first insulating material 111A, and at least a portion of the first electronic component 120A may be exposed from another surface of the first insulating material 111A opposite to one surface on which the second insulating material 111B is disposed. In this case, the exposed portion of the first electronic component 120A may be an electrode 120Ap. Therefore, the surface of the electrode 120Ap of the first electronic component 120A exposed from another surface of the first insulating material 111A may be substantially coplanar with another surface of the first insulating material 111A. The body 120Ab of the first electronic component may be embedded in the first insulating material 111A. Therefore, the first electronic component 120A may be connected to the first wiring layer 142A through the first via 143A of the second accumulation structure 140. Furthermore, the first via 143A and the first and second vias 113A and 113B may each have a tapered shape, and the tapered shape of the first via 143A may taper in a direction opposite to the tapering direction of the tapered shape of each of the first and second vias 113A and 113B.

[0035] The second electronic component 120B may be mounted on the first wiring layer 112A by surface mounting technology (SMT) and at least a portion of the second electronic component 120B may be covered by the second insulating material 111 B. In this case, the second electronic component 120B may be mounted on the first wiring layer 112A by the connecting conductor 121, and the first electronic component 120A may be spaced apart from the connecting conductor 121.

[0036] The first electronic component 120A and the second electronic component 120B may be connected to each other through the first via 113A and the first wiring layer 112A. In this case, as described below, the first electronic component 120A and the second electronic component 120B may be connected in parallel. The first via 113A and the first wiring layer 112A may be arranged at a height between the first electronic component 120A and the second electronic component 120B, so that the first electronic component 120A and the second electronic component 120B may be directly connected to each other without any other wiring layer.

[0037] The first and second electronic components 120A and 120B may be arranged along a thickness direction of each of the first and second electronic components 120A and 120B. On a plane, the first and second electronic components 120A and 120B may be arranged to overlap each other in a thickness direction of each of the first and second electronic components 120A and 120B.

[0038] As shown in the drawings, each of the first electronic component 120A and the second electronic component 120B may be provided as a plurality of electronic components. In this case, adjacent first electronic components 120A may be spaced apart from each other by a predetermined distance. In addition, the spaces between adjacent first electronic components 120A may be filled with a first insulating material 111A, and adjacent first electronic components 120A may be spaced apart from each other by the first insulating material 111A. In addition, the plurality of second electronic components 120B may also be provided in the same or similar manner as the plurality of first electronic components 120A described above.

[0039] The first electronic component 120A and the second electronic component 120B can be connected to a semiconductor package (not shown) mounted on a substrate embedded with electronic components, etc. through the wiring layers 132A and 132B included in the first accumulation structure 130. Therefore, the electrical connection path between the first electronic component 120A and / or the second electronic component 120B and the semiconductor package (not shown) can be shortened. In addition, electrical signal loss, etc. can be minimized.

[0040] Typically, in order to shorten the signal path with a semiconductor package (not shown) mounted on a substrate embedded with electronic components, the electronic component embedded in the substrate may be buried adjacent to a side on which the semiconductor package (not shown) is mounted to face the semiconductor package (not shown). In this case, since the substrate may have an asymmetric structure due to an area in which the electronic component is disposed and an area in which the electronic component is not disposed, bending or warping may occur. In the case of a substrate 100A embedded with electronic components according to the example, the first electronic component 120A and the second electronic component 120B may not be buried adjacent to a side on which the semiconductor package (not shown) is mounted, and may be buried symmetrically in the base substrate 110 in the thickness direction. Therefore, the bending or warping of the substrate may be improved.

[0041] As described below, the first electronic component 120A and the second electronic component 120B may be capacitors having electrodes 120Ap and 120Bp, respectively. In this case, the electrode 120Ap of the first electronic component 120A and the electrode 120Bp of the second electronic component 120B may be connected to each other through the first via 113A and the first wiring layer 112A of the base substrate 110. In addition, the first electronic component 120A and the second electronic component 120B may be connected in parallel. In one example, the body 120Ab of the first electronic component 120A and the body 120Bb of the second electronic component 120B may be embedded in the first insulating material 111A and the second insulating material 111B, respectively. Therefore, it is possible to have the effect of increasing the capacitance of the electronic component and / or reducing the equivalent series inductance (ESL) of the electronic component, and it is possible to improve the power integrity (PI) characteristics.

[0042] Fig.16 A circuit diagram of a first electronic component 120A and a second electronic component 120B included in the electronic component 120 is schematically shown. In this case, the capacitance values ​​of the first electronic component 120A and the second electronic component 120B may be represented by C1 and C2, respectively. As shown in the accompanying drawings, since the first electronic component 120A and the second electronic component 120B are connected in parallel to each other, the total capacitance value may increase to C1+C2. In this case, as shown in the accompanying drawings, it is shown that each of the first electronic component 120A and the second electronic component 120B is provided as a plurality of electronic components.

[0043] The first accumulation structure 130 may be disposed on the second insulating material 111B and include an insulating layer 131, a wiring layer 132 and a via 133. Specifically, it may include: a first insulating layer 131A; a first wiring layer 132A, disposed on the first insulating layer 131A; a first via 133A, penetrating the first insulating layer 131A and connecting the first wiring layer 132A and the second wiring layer 112B of the base substrate 110; a second insulating layer 131B, disposed on the first insulating layer 131A; a second wiring layer 132B, disposed on the second insulating layer 131B; and a second via 133B, penetrating the second insulating layer 131B and connecting the second wiring layer 132B and the first wiring layer 132A.

[0044] The second accumulation structure 140 may be disposed on the first insulating material 111A and include an insulating layer 141, a wiring layer 142 and a via 143. Specifically, it may include: a first insulating layer 141A; a first wiring layer 142A, disposed on the first insulating layer 141A; a first via 143A, penetrating the first insulating layer 141A and connecting the first wiring layer 142A and the first electronic component 120A; a second insulating layer 141B, disposed on the first insulating layer 141A; a second wiring layer 142B, disposed on the second insulating layer 141B; and a second via 143B, penetrating the second insulating layer 141B and connecting the second wiring layer 142B and the first wiring layer 142A.

[0045] Hereinafter, each configuration of the electronic component-embedded substrate 100A according to an example will be described in more detail.

[0046] As described above, the base substrate 110 may include: a first insulating material 111A; a first wiring layer 112A, which is arranged on the first insulating material 111A; a first via 113A, which penetrates the first insulating material 111A and connects the first wiring layer 112A and the first electronic component 120A; a first through-hole 114A, which penetrates the first insulating material 111A and connects the first wiring layer 112A and the first wiring layer 142A included in the second accumulation structure 140; a second insulating material 111B, which is arranged on the first insulating material 111A and covers the first wiring layer 112A; a second wiring layer 112B, which is arranged on the second insulating material 111B; a second via 113B, which penetrates the second insulating material 111B and connects the second wiring layer 112B and the second electronic component 120B; and a second through-hole 114B, which penetrates the second insulating material 111B and connects the first wiring layer 112A and the second wiring layer 112B.

[0047] The structure of the base substrate 110 is not limited thereto, and those skilled in the art may make changes within the scope of design. For example, the number of insulating layers, wiring layers, and / or vias included in the base substrate 110 may be greater or less than the number of insulating layers, wiring layers, and / or vias shown in the drawings.

[0048] The material used to form each of the first insulating material 111A and the second insulating material 111B is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including a reinforcing material such as an inorganic filler and / or glass cloth, glass fabric, etc. together with a thermosetting resin or a thermoplastic resin, such as a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc. can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0049] The material used to form each of the first insulating material 111A and the second insulating material 111B may include the same kind of material and may have substantially the same thickness as each other. However, the present disclosure is not limited thereto, and the first insulating material 111A and the second insulating material 111B may include different kinds of materials and may have different thicknesses.

[0050] Depending on the materials and processes of the first insulating material 111A and the second insulating material 111B, the boundary between the first insulating material 111A and the second insulating material 111B may not be recognizable. For example, during the stacking process, the first insulating material 111A and the second insulating material 111B may be integrated with each other, or the boundary therebetween may not be clear. Therefore, it may be difficult to visually determine the boundary of the substrate embedded with electronic components that is finally produced.

[0051] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming each of the first wiring layer 112A and the second wiring layer 112B. Each of the first wiring layer 112A and the second wiring layer 112B may perform various functions according to their design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern. In addition, a via pad, etc. may be included.

[0052] As a material for forming each of the first via hole 113A and the second via hole 113B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used. Each of the first via hole 113A and the second via hole 113B may be completely filled with a conductive material, or the conductive material may be formed along the wall of the via hole. When the via hole is a via hole in which a conductive material is formed along the wall of the via hole, an insulating material may fill the rest of the via hole. In addition, the shape of each of the first via hole 113A and the second via hole 113B may be any shape known in the art, such as a conical shape, a cylindrical shape, etc.

[0053] The first via 113A may have a structure integrated with the first wiring layer 112A connected to the first via 113 A. The second via 113B may have a structure integrated with the second wiring layer 112B connected to the second via 113B.

[0054] As a material for forming each of the first through-via 114A and the second through-via 114B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used. Each of the first through-via 114A and the second through-via 114B may be completely filled with the conductive material, or the conductive material may be formed along the wall of the through-via. When each of the first through-via 114A and the second through-via 114B is a through-via in which the conductive material is formed along the wall of the through-via, an insulating material may fill the rest of the through-via. In addition, the shape of each of the first through-via 114A and the second through-via 114B may apply all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0055] The first through via 114A may have a structure integrated with the first wiring layer 112A connected to the first through via 114 A. The second through via 114B may have a structure integrated with the second wiring layer 112B connected to the second through via 114B.

[0056] The first through-hole 114A may be connected to and in contact with the first via 143A of the second accumulation structure 140. In this case, the first through-hole 114A and the first via 143A may contact each other at a boundary where the first insulating material 111A and the first insulating layer 141A contact each other. At the boundary where the first through-hole 114A and the first via 143A contact each other, the width and / or cross-sectional area of ​​each of the first through-hole 114A and the first via 143A may be different from each other. For example, although Figure 3 Although it is not obvious in the figure, at the boundary where the first through-hole 114A and the first via hole 143A contact each other, the width of the first through-hole 114A may be wider than the width of the first via hole 143A. Alternatively, at the boundary where the first through-hole 114A and the first via hole 143A contact each other, the width of the first via hole 143A may be wider than the width of the first through-hole 114A. Since the width of the first through-hole 114A or the first via hole 143A may be widened, the first through-hole 114A and the first via hole 143A may be effectively aligned.

[0057] Each of the first electronic component 120A and the second electronic component 120B may be a chip capacitor having an electrode. For example, the first electronic component 120A and the second electronic component 120B may be a multilayer ceramic capacitor (MLCC), but is not limited thereto. In addition, as described above, the first electronic component 120A and the second electronic component 120B may be connected in parallel. For example, each of the first electronic component 120A and the second electronic component 120B may include a first electrode and a second electrode. The first electrodes of the first electronic component 120A and the second electronic component 120B may be connected to each other, and the second electrodes of the first electronic component 120A and the second electronic component 120B may be connected to each other.

[0058] However, the present disclosure is not limited thereto, and each of the first electronic component 120A and the second electronic component 120B may be a passive component such as an inductor, may be an active component such as an integrated circuit (IC), a semiconductor chip, or the like.

[0059] The connection conductor 121 may include solder or conductive paste. The connection conductor 121 may include a material different from that of the first wiring layer 112A (eg, may be made of a material different from that of the first wiring layer 112A), and the material of the connection conductor 121 may be a conductive material that satisfies the above conditions.

[0060] As described above, the first accumulation structure 130 may include: a first insulating layer 131A; a first wiring layer 132A, which is arranged on the first insulating layer 131A; a first via 133A, which penetrates the first insulating layer 131A and connects the first wiring layer 132A and the second wiring layer 112B of the base substrate 110; a second insulating layer 131B, which is arranged on the first insulating layer 131A; a second wiring layer 132B, which is arranged on the second insulating layer 131B; and a second via 133B, which penetrates the second insulating layer 131B and connects the second wiring layer 132B and the first wiring layer 132A.

[0061] The structure of the first accumulation structure 130 is not limited thereto, and those skilled in the art may make changes within the scope of design. For example, the number of insulating layers, wiring layers, and / or vias included in the first accumulation structure 130 may be greater or less than the number of insulating layers, wiring layers, and / or vias shown in the drawings.

[0062] The material used to form each of the first insulating layer 131A and the second insulating layer 131B is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including a reinforcing material such as an inorganic filler and / or glass cloth, glass fabric, etc. together with a thermosetting resin or a thermoplastic resin, such as a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc. can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0063] Depending on the materials and processes of the first insulating layer 131A and the second insulating layer 131B, the boundary between the first insulating layer 131A and the second insulating layer 131B may not be recognizable. For example, during the stacking process, the first insulating layer 131A and the second insulating layer 131B may be integrated with each other, or the boundary therebetween may not be clear. Therefore, it may be difficult to visually determine the boundary of the finally produced electronic component-embedded substrate.

[0064] In addition, depending on the materials and processes of the first insulating layer 131A and the second insulating material 111B, the boundary between the first insulating layer 131A and the second insulating material 111B contacting it may not be recognizable. For example, during the stacking process, the first insulating layer 131A and the second insulating material 111B may be integrated with each other, or the boundary between them may not be clear. Therefore, it may be difficult to visually determine the boundary of the substrate embedded with electronic components that is finally produced.

[0065] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming each of the first wiring layer 132A and the second wiring layer 132B. Each of the first wiring layer 132A and the second wiring layer 132B may perform various functions according to their design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern. In addition, a via pad, etc. may be included.

[0066] As a material for forming each of the first via hole 133A and the second via hole 133B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used. Each of the first via hole 133A and the second via hole 133B may be completely filled with a conductive material, or the conductive material may be formed along the wall of the via hole. When the via hole is a via hole in which a conductive material is formed along the wall of the via hole, an insulating material may fill the rest of the via hole. In addition, the shape of each of the first via hole 133A and the second via hole 133B may be any shape known in the art, such as a conical shape, a cylindrical shape, etc.

[0067] The first via 133A may have a structure integrated with the first wiring layer 132A connected to the first via 133 A. The second via 133B may have a structure integrated with the second wiring layer 132B connected to the second via 133B.

[0068] As described above, the second accumulation structure 140 may include: a first insulating layer 141A; a first wiring layer 142A, which is arranged on the first insulating layer 141A; a first via 143A, which penetrates the first insulating layer 141A and connects the first wiring layer 142A and the first electronic component 120A; a second insulating layer 141B, which is arranged on the first insulating layer 141A; a second wiring layer 142B, which is arranged on the second insulating layer 141B; and a second via 143B, which penetrates the second insulating layer 141B and connects the second wiring layer 142B and the first wiring layer 142A.

[0069] The structure of the second accumulation structure 140 is not limited thereto, and those skilled in the art may make changes within the scope of design. For example, the number of insulating layers, wiring layers, and / or vias included in the second accumulation structure 140 may be greater or less than the number of insulating layers, wiring layers, and / or vias shown in the drawings.

[0070] The material used to form each of the first insulating layer 141A and the second insulating layer 141B is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including a reinforcing material such as an inorganic filler and / or glass cloth, glass fabric, etc. together with a thermosetting resin or a thermoplastic resin, such as a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc. can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0071] Depending on the materials and processes of the first insulating layer 141A and the second insulating layer 141B, the boundary between the first insulating layer 141A and the second insulating layer 141B may not be recognizable. For example, during the stacking process, the first insulating layer 141A and the second insulating layer 141B may be integrated with each other, or the boundary therebetween may not be clear. Therefore, it may be difficult to visually determine the boundary of the substrate embedded with electronic components that is finally produced.

[0072] In addition, depending on the materials and processes of the first insulating layer 141A and the first insulating material 111A, the boundary between the first insulating layer 141A and the first insulating material 111A contacting it may not be recognizable. For example, during the stacking process, the first insulating layer 141A and the first insulating material 111A may be integrated with each other, or the boundary between them may not be clear. Therefore, it may be difficult to visually determine the boundary of the substrate embedded with electronic components that is finally produced.

[0073] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming each of the first wiring layer 142A and the second wiring layer 142B. Each of the first wiring layer 142A and the second wiring layer 142B may perform various functions according to their design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern. In addition, a via pad, etc. may be included.

[0074] As a material for forming each of the first via hole 143A and the second via hole 143B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used. Each of the first via hole 143A and the second via hole 143B may be completely filled with a conductive material, or the conductive material may be formed along the wall of the via hole. When the via hole is a via hole in which a conductive material is formed along the wall of the via hole, an insulating material may fill the rest of the via hole. In addition, the shape of each of the first via hole 143A and the second via hole 143B may be any shape known in the art, such as a conical shape, a cylindrical shape, etc.

[0075] The first via 143A may have a structure integrated with the first wiring layer 142A connected to the first via 143 A. The second via 143B may have a structure integrated with the second wiring layer 142B connected to the second via 143B.

[0076] The first passivation layer 150 and the second passivation layer 160 may protect the internal structure of the substrate 100A embedded with electronic components according to the example from external physical damage or chemical damage, etc. Each of the first passivation layer 150 and the second passivation layer 160 may include a thermosetting resin and an inorganic filler. For example, each of the first passivation layer 150 and the second passivation layer 160 may be ABF. The present disclosure is not limited thereto, and the first passivation layer 150 and the second passivation layer 160 may be a known photosensitive insulating layer, such as a solder resist (SR) layer. The first passivation layer 150 and the second passivation layer 160 may include the same type of material and may have substantially the same thickness as each other. However, the present disclosure is not limited thereto, and the first passivation layer 150 and the second passivation layer 160 may include different types of materials and may have different thicknesses from each other.

[0077] The first passivation layer 150 may have one or more openings (not shown) that expose at least a portion of the second wiring layer 132B of the first accumulation structure 130. In addition, the second passivation layer 160 may have one or more openings (not shown) that expose at least a portion of the second wiring layer 142B of the second accumulation structure 140. In these cases, a surface treatment layer may be formed on each of the exposed wiring layers 132B and 142B. The surface treatment layer may be formed by, for example, a gold plating process, a tin plating process, a silver plating process, a nickel plating process, etc. As needed, the openings of each of the first passivation layer 150 and the second passivation layer 160 may be formed using a plurality of via holes.

[0078] FIG. 4A to FIG. 8 A manufacturing process of an electronic component embedded substrate 100A according to an example is schematically illustrated.

[0079] Reference FIG. 4A to FIG. 4C, an adhesive member 230 may be attached to the metal layer 220 (such as copper foil, etc.) to which the carrier film 210 is attached, a first electronic component 120A may be disposed on the adhesive member 230, and the first electronic component 120A may be sealed using a first insulating material 111A.

[0080] The adhesive member 230 is not particularly limited as long as it can fix the first electronic component 120A. For example, a well-known tape or the like can be used.

[0081] The first insulating material 111A may be formed by a known method. For example, the first insulating material 111A may be formed by a process including laminating its precursor by a known lamination process and then curing the laminated precursor, may be formed by a process including applying its precursor and then curing the applied precursor, or may be formed by other processes.

[0082] Reference FIG. 5A to FIG. 5C , the first via 113A, the first through via 114A, and the first wiring layer 112A may be formed. In addition, the second electronic component 120B may be disposed on the first wiring layer 112A through a connection conductor 121 such as solder, and the second electronic component 120B may be sealed with a second insulating material 111B.

[0083] The first via hole 113A, the first through via hole 114A, and the first wiring layer 112A may be formed by known methods. For example, the through via hole or the via via hole may be formed using photolithography, mechanical drilling, laser drilling, etc., a patterned space may be formed using a dry film, etc., and the through via hole or the via via hole and the patterned space may be filled by a plating process, etc. to form the first via hole 113A, the first through via hole 114A, and the first wiring layer 112A.

[0084] The connection conductor 121 may be formed by a known method. For example, the connection conductor 121 may be formed by applying solder or the like by a screen printing process, a dispenser process, or the like, or may be formed by other processes.

[0085] Reference FIG. 6A to FIG. 6C , the second via hole 113B, the second through via hole 114B, and the second wiring layer 112B may be formed. In addition, the carrier film 210, the metal layer 220, and the adhesive member 230 may be peeled off.

[0086] Reference FIG. 7A to FIG. 7B, the first insulating layer 131A, the first via 133A, and the first wiring layer 132A of the first accumulation structure 130 and the first insulating layer 141A, the first via 143A, and the first wiring layer 142A of the second accumulation structure 140 may be formed respectively. In addition, the second insulating layer 131B, the second via 133B, and the second wiring layer 132B of the first accumulation structure 130 and the second insulating layer 141B, the second via 143B, and the second wiring layer 142B of the second accumulation structure 140 may be formed. The accumulation structure may also be formed according to the above method.

[0087] Reference Figure 8 , a first passivation layer 150 and a second passivation layer 160 may be formed.

[0088] Each of the first passivation layer 150 and the second passivation layer 160 may also be formed by a known method, for example, may be formed by a process including laminating precursors of each of the first passivation layer 150 and the second passivation layer 160 and then curing the laminated precursors, may be formed by a process including applying a material for forming each of the first passivation layer 150 and the second passivation layer 160 and then curing the applied precursors, or may be formed by other processes.

[0089] Fig. 9 is a cross-sectional view schematically showing an electronic component-embedded substrate 100B according to another example.

[0090] Compared with the electronic component embedded substrate 100A according to the example, the electronic component embedded substrate 100B according to another example may further include an adhesive member 171 and a wiring layer 172 .

[0091] Therefore, the first through vias 114A may penetrate the first insulating material 111A, may further penetrate the adhesive member 171, and may connect the wiring layer 172 and the first wiring layer 112A. In addition, some of the first vias 143A of the second accumulation structure 140 may penetrate the first insulating layer 141A, and may further penetrate the adhesive member 171. Others of the first vias 143A of the second accumulation structure 140 may penetrate the first insulating layer 141A, and may be connected to the wiring layer 172.

[0092] The adhesive member 171 may be disposed between the base substrate 110 and the second accumulation structure 140, and the wiring layer 172 may be embedded in the adhesive member 171. In this case, one surface of the wiring layer 172 may be coplanar with a surface of the adhesive member 171 on which the second accumulation structure 140 is disposed. Therefore, the one surface of the wiring layer 172 may be exposed from the adhesive member 171.

[0093] The material for forming the adhesive member 171 may be used without limitation as long as the material has insulating properties and adhesive properties. For example, the adhesive member 171 may include a thermosetting resin and / or a thermoplastic resin.

[0094] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming the wiring layer 172. The wiring layer 172 may perform various functions according to its design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern. In addition, a via pad, etc. may be included.

[0095] Since other structures may be substantially the same as those described in the electronic component-embedded substrate 100A according to an example, a detailed description thereof will be omitted.

[0096] FIG. 10A to FIG. 14 A manufacturing process of a substrate 100B embedded with electronic components according to another example is schematically shown.

[0097] Reference FIG. 10A to FIG. 10D , the metal layer 172c to which the carrier film 210 is attached may be patterned to form the wiring layer 172. In this case, only the seed layer 172s may remain in a portion where the wiring layer 172 is not required. In addition, the adhesive member 171 may be formed on the wiring layer 172.

[0098] The wiring layer 172 may be formed by a known method. For example, a sputtering process, a subtractive process, an additive process, a semi-additive process (SAP), a modified semi-additive process (MSAP), etc. may be used.

[0099] Reference FIG. 12A to FIG. 12C , only the seed layer 172s may be peeled off through an etching process or the like by peeling off the carrier film 210. Therefore, the adhesive member 171 and the wiring layer 172 may not be removed.

[0100] because FIG. 13A to FIG. 14 Other methods shown in may be substantially the same as the methods described in the electronic component-embedded substrate 100A according to an example, and thus a detailed description thereof will be omitted.

[0101] Fig.15 is a cross-sectional view schematically showing an example in which a semiconductor package is mounted on an electronic component-embedded substrate 100A according to an example.

[0102] Referring to the drawings, when the above-described electronic component-embedded substrate 100A according to an example of the present disclosure is used, a semiconductor package 300 may be mounted on the electronic component-embedded substrate through an electrical connection metal member 310. In this case, the embedded electronic component 120 may be electrically connected to a semiconductor chip (not shown) included in the semiconductor package 300 through a relatively short electrical path.

[0103] In addition, the semiconductor package 300 may be a package in which a semiconductor chip (not shown) is mounted on a separate interposer, but is not limited thereto.

[0104] The semiconductor chip (not shown) may be an application specific integrated circuit (ASIC) and / or a high bandwidth memory (HBM), but is not limited thereto.

[0105] The electrical connection metal member 310 may include a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). More specifically, the electrical connection metal member 310 may be formed using solder or the like, but is merely illustrative and its material is not particularly limited thereto.

[0106] In addition, the electrical connection metal member 310 may be fixed by an underfill resin as required.

[0107] The substrate embedded with electronic components may be mounted on a substrate 400 (such as a main board) through a separate electrical connection metal member 410 .

[0108] The term "connecting..." or "connection" in this specification may be not only "direct connection" but also a concept including indirect connection through an adhesive layer or the like. In addition, the term "electrically connecting..." or "electrical connection" in this specification is a concept including both physical connection and physical non-connection. In addition, the expressions "first", "second", etc. in this specification are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, without departing from the spirit of the present disclosure, the "first" component may be referred to as the "second" component, and similarly, the "second" component may be referred to as the "first" component.

[0109] The expression "example" used in this specification does not refer to examples that are identical to each other, but may be provided to emphasize and illustrate different unique features. However, the above examples do not exclude that the above examples are implemented in combination with features of other examples. For example, although a description in a specific example is not described in another example, it can be understood as a description related to another example unless otherwise described or contradicted with another example.

[0110] The terms used in the present disclosure are only used to illustrate various examples and are not intended to limit the inventive concept. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0111] As one of several effects of the present disclosure, an electronic component-embedded substrate having a shortened electrical connection path can be provided.

[0112] As another effect among various effects of the present disclosure, an electronic component-embedded substrate having improved power integrity (PI) characteristics due to increase in capacitance of the electronic component and / or reduction in equivalent series inductance (ESL) of the electronic component may be provided.

[0113] As another effect among various effects of the present disclosure, an electronic component-embedded substrate having improved warpage characteristics may be provided.

[0114] While examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A substrate with embedded electronic components, include: a first electronic component; a first insulating material covering at least a portion of the first electronic component; A first wiring layer is provided on a surface of the first insulating material; a second electronic component disposed on the first wiring layer and connected to the first electronic component through the first wiring layer; as well as a second insulating material covering at least a portion of the second electronic component, wherein at least a portion of the first electronic component is exposed from another surface of the first insulating material opposite to the one surface of the first insulating material, and Part of the second insulating material overlaps with the first wiring layer in a direction perpendicular to a direction in which the first electronic component and the second electronic component overlap with each other.

2. The substrate with embedded electronic components according to claim 1, in, The second electronic component is mounted on the first wiring layer via a connecting conductor.

3. The substrate with embedded electronic components according to claim 2, in, The connecting conductor includes solder.

4. The substrate with embedded electronic components according to claim 1, in, On a plane, the second electronic component is arranged to overlap with the first electronic component.

5. The substrate with embedded electronic components according to claim 1, in, The first wiring layer is provided at a height between the first electronic component and the second electronic component. 6 . The electronic component embedded substrate according to claim 1 , further comprising a first via hole penetrating through the first insulating material and connecting the first electronic component and the first wiring layer.

7. The electronic component-embedded substrate according to claim 1, in, Each of the first electronic component and the second electronic component is a capacitor having electrodes, Wherein, the first electronic component and the second electronic component are connected in parallel.

8. The electronic component embedded substrate according to claim 7, in, The electrodes of each of the first electronic component and the second electronic component include a first electrode and a second electrode, respectively, wherein the first electrode of the first electronic component is connected to the first electrode of the second electronic component, and The second electrode of the first electronic component is connected to the second electrode of the second electronic component.

9. The electronic component-embedded substrate according to claim 7, in, A surface of the electrode of the first electronic component exposed from the other surface of the first insulating material is coplanar with the other surface of the first insulating material. 10 . The electronic component embedded substrate according to claim 1 , further comprising a second wiring layer provided on the second insulating material and connected to the second electronic component.

11. The substrate with embedded electronic components according to claim 1, wherein the substrate with embedded electronic components further comprises: include: a first build-up structure disposed on the first insulating material and comprising a first insulating layer and a second wiring layer connected to the first electronic component; as well as A second build-up structure is disposed on the second insulating material and includes a second insulating layer and a third wiring layer connected to the second electronic component.

12. The electronic component-embedded substrate according to claim 11, further comprising a first through-via penetrating through the first insulating material and connected to the first wiring layer, in, The first accumulation structure further includes a via hole penetrating the first insulating layer and connected to the second wiring layer, wherein the first through via and the via hole contact each other at a boundary between the first insulating material and the first insulating layer, and At the boundary where the first through via and the via contact, a width of the first through via is different from a width of the via.

13. The substrate with embedded electronic components according to claim 11, wherein the substrate with embedded electronic components further comprises: include: an adhesive member disposed between the first insulating material and the first insulating layer; as well as A fourth wiring layer is embedded in the bonding member. 14 . The electronic component embedded substrate according to claim 13 , further comprising a first through via penetrating the first insulating material and the adhesive member and connecting the first wiring layer and the fourth wiring layer.

15. The electronic component embedded substrate according to claim 1, in, The first electronic components are provided as a plurality of first electronic components spaced apart from each other, and The second electronic components are provided as a plurality of second electronic components spaced apart from each other.

16. A substrate having an electronic component embedded therein, include: A base substrate, including an insulating body; A first electronic component and a second electronic component, both embedded in the insulating body; a first wiring layer provided between the first electronic component and the second electronic component and connected to an electrode of the first electronic component; as well as a connecting conductor including a material different from that of the first wiring layer and in contact with an electrode of the second electronic component and the first wiring layer, and wherein a portion of a portion of the insulating body where the second electronic component is disposed overlaps the first wiring layer in a direction perpendicular to a direction in which the first electronic component and the second electronic component overlap each other.

17. The electronic component embedded substrate according to claim 16, in, The first electronic component is spaced apart from the connecting conductor.

18. The electronic component embedded substrate according to claim 17, in, The connecting conductor includes solder or conductive paste.

19. The electronic component-embedded substrate according to claim 16, further comprising a first accumulation structure and a second accumulation structure disposed on opposite sides of the base substrate, in, The electrode of the first electronic component is connected to the first wiring layer through a first via hole embedded in the insulating body, An electrode of the first electronic component is exposed from the insulating body and connected to a second wiring layer embedded in the first build-up structure through a second via hole, and An electrode of the second electronic component is connected to a third wiring layer embedded in the second build-up structure through a third via.

20. The electronic component embedded substrate according to claim 19, in, The second via hole has a tapered shape that tapers in a direction opposite to a taper direction of the tapered shape of each of the first via hole and the third via hole.

Images