Transistor array substrate and electronic device including the same

Abstract

A transistor array substrate and an electronic device are provided. A first active layer includes a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region. A gate insulating film is disposed on the first active layer. A gate electrode is disposed on the gate insulating film to overlap a portion of the channel region of the first active layer. The gate electrode overlaps a portion of at least one region of the first region and the second region of the first active layer. Deterioration of the channel region is prevented.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0168156, filed on December 16, 2019, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical field

[0003] Embodiments relate to a transistor array substrate and an electronic device including the transistor array substrate. Background art

[0004] With the development of the information society, the demand for various types of electronic devices such as display devices and lighting devices is increasing. Such an electronic device may include a panel in which data lines and gate lines are provided, a data driver for driving the data lines, and a gate driver for driving the gate lines.

[0005] In a panel serving as a key component of such an electronic device, a plurality of transistors having various functions may be provided to drive the panel.

[0006] Therefore, the manufacturing process of the panel inevitably becomes complex and difficult. When seeking process convenience to overcome such problems, the device performance of the transistors may be disadvantageously reduced.

[0007] In particular, it may be difficult to design a plurality of transistors to have structures corresponding to different requirements of transistors with different functions. Summary of the invention

[0008] Embodiments provide a transistor array substrate and an electronic device including the transistor array substrate, the transistor array substrate having a structure for preventing a short - circuit between an active layer and a gate electrode.

[0009] In addition, embodiments provide a transistor array substrate and an electronic device including the transistor array substrate, the transistor array substrate having a structure capable of preventing deterioration of a channel region of an active layer even when a high voltage is applied to an electrode connected to a power supply node.

[0010] In addition, embodiments provide a transistor array substrate having a structure for preventing a reduction in mobility and an electronic device including the transistor array substrate.

[0011] According to one aspect, an embodiment may provide a transistor array substrate and an electronic device including the transistor array substrate. The electronic device includes: a panel including at least one transistor; and a driving circuit for driving the panel. The panel includes: a substrate; a first active layer disposed on the substrate, the first active layer including a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region; a gate insulating film disposed on the first active layer; a gate electrode of at least one transistor, which is disposed on the gate insulating film and overlaps a part of the channel region of the first active layer; an interlayer insulating film disposed on the gate electrode; and a first electrode and a second electrode of at least one transistor, which are disposed on the interlayer insulating film and spaced apart from each other. The gate electrode overlaps a part of at least one of the first region and the second region of the first active layer.

[0012] According to one aspect, an embodiment may provide a transistor array substrate, which includes: a substrate; a first active layer disposed on the substrate, the first active layer including a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region; a gate insulating film disposed on the first active layer; a gate electrode, which is disposed on the gate insulating film and overlaps a part of the channel region of the first active layer; an interlayer insulating film disposed on the gate electrode; and a first electrode and a second electrode, which are disposed on the interlayer insulating film and spaced apart from each other. The gate electrode overlaps a part of at least one of the first region and the second region of the first active layer.

[0013] According to an exemplary embodiment, in the transistor array substrate and the electronic device, the gate insulating film may be disposed such that the gate electrode does not contact the conductive region of the active layer, thereby preventing a short circuit between the active layer and the gate electrode.

[0014] In addition, according to an exemplary embodiment, in the transistor array substrate and the electronic device, a part of the channel region is disposed in a region that does not overlap the gate electrode, so that even if a high voltage is applied to the electrode connected to the power supply node, the channel region of the active layer is not deteriorated.

[0015] In addition, according to an exemplary embodiment, in the transistor array substrate and the electronic device, the length of the channel region of the active layer is designed appropriately, thereby preventing a reduction in mobility. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a diagram showing a schematic system configuration of an electronic device according to an embodiment;

[0018] Figure 2 is a diagram showing the system structure of an electronic device according to an embodiment;

[0019] Figure 3 is a diagram showing the structure of sub-pixels in the case where the panel is an organic light-emitting diode (OLED) panel;

[0020] Figure 4 is a diagram showing a 3T1C structure including three transistors and a single capacitor, where a single sub-pixel further includes a second transistor electrically connected to a second node of a driving transistor and a reference voltage line;

[0021] Figure 5 is a diagram schematically showing each of the gate driving circuits provided in a panel according to an embodiment;

[0022] Figure 6 is a cross-sectional view of a transistor provided in an electronic device according to an embodiment;

[0023] Figures 7 to 10 is a schematic diagram showing the process of manufacturing Figure 6 the first active layer and the gate electrode of the transistor shown;

[0024] Figure 11 is a graph comparing the characteristics of a transistor having the Figure 6 structure according to an embodiment with the characteristics of a transistor according to a comparative example;

[0025] Figure 12 is a cross-sectional view of a transistor provided in an electronic device according to another embodiment;

[0026] Figure 13 is a cross-sectional view of a transistor provided in an electronic device according to another embodiment;

[0027] Figure 14 is a cross-sectional view of a transistor provided in an electronic device according to another embodiment; and

[0028] Figure 15 is a graph showing the characteristics of a transistor having the Figure 14 structure. DETAILED DESCRIPTION

[0029] In the following description of examples or embodiments of the present invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and where the same reference numerals may be used to denote the same or similar components, even if they are shown in different drawings from each other. Further, in the following description of examples or embodiments of the present invention, when it is determined that the description of well-known functions and components incorporated herein may obscure the subject matter in some embodiments of the present invention, the detailed description thereof will be omitted. Terms such as "comprising", "having", "including", "constituting", "composing", and "forming" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0030] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to define the nature, order, sequence, or number, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0031] When it is mentioned that a first element is "connected or coupled", "contacted or overlapped" with a second element, etc., it should be interpreted that not only can the first element be "directly connected or coupled" or "directly contacted or overlapped" with the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "contacted or overlapped", etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacted or overlapped", etc. with each other.

[0032] When using time-related terms (such as "after", "subsequently", "next", "before", etc.) to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless used together with the term "directly" or "immediately", the above terms can be used to describe a non-continuous or non-sequential process or operation.

[0033] In addition, when referring to any size, relative size, etc., the numerical value or corresponding information (such as level, range, etc.) of an element or feature should be considered to include a tolerance or error range that may be caused by various factors (such as process factors, internal or external influences, noise, etc.), even if there is no relevant description. Further, the term "may" fully encompasses all meanings of the term "can".

[0034] Figure 1 is a diagram showing a schematic system configuration of an electronic device according to an embodiment.

[0035] An electronic device according to an embodiment may include a display device, a lighting device, a light-emitting device, etc. For simplicity, the following description will mainly focus on the display device. However, the following description is not only applicable to the display device, but may also be applied to various other electronic devices, such as lighting devices or light-emitting devices, in substantially the same manner as long as they include transistors.

[0036] An electronic device according to an embodiment may include a panel PNL that displays an image or emits light and a driving circuit that drives the panel PNL.

[0037] In the panel PNL, a plurality of data lines DL and a plurality of gate lines GL may be provided, and a plurality of sub-pixels SP defined by the plurality of gate lines GL and the plurality of data lines DL may be arranged in a matrix form.

[0038] In the panel PNL, the plurality of data lines DL and the plurality of gate lines GL may be provided to intersect each other. For example, the plurality of data lines DL may be arranged in rows or columns, and the plurality of gate lines GL may be arranged in columns or rows. Hereinafter, for simplicity, the plurality of gate lines GL will be described as being provided in rows, and the plurality of data lines DL will be described as being provided in columns.

[0039] In the panel PNL, in addition to the plurality of data lines DL and the plurality of gate lines GL, depending on the sub-pixel structure, etc., other types of signal lines may be provided. Driving voltage lines, reference voltage lines, common voltage lines, etc. may also be provided in the panel PNL.

[0040] The panel PNL may be various types of panels, such as a liquid crystal display (LCD) panel and an organic light-emitting diode (OLED) display panel.

[0041] The type of signal lines provided in the panel PNL may vary according to the sub-pixel structure and the panel type (e.g., LCD panel or OLED panel). In addition, the term "signal line" used herein may be a concept including an electrode to which a signal is applied.

[0042] The panel PNL may include an active area A / A that displays an image (video) and a non-active area N / A provided at the periphery of the active area A / A that does not display an image. Herein, the non-active area N / A is also referred to as a border area.

[0043] In the active area A / A, a plurality of sub-pixels SP for displaying an image are provided.

[0044] In the non-active region N / A, pads can be provided to be electrically connected to the data driver DDR, and multiple data link lines that connect the pads to multiple data lines DL can be provided. The multiple data link lines can be portions of the multiple data lines DL that extend into the non-active region N / A, or separate patterned portions that are electrically connected to the multiple data lines DL.

[0045] In addition, in the non-active region N / A, wires related to gate driving can be provided to transmit the voltage (signal) required for gate driving to the gate driver GDR through pads electrically connected to the data driver DDR. For example, the wires related to gate driving can include a clock line that transmits a clock signal, gate voltage lines that transmit gate voltages VGH and VGL, gate driving control signal lines that transmit various control signals required to generate scan signals, etc. These wires related to gate driving are provided in the non-active region N / A in a different manner from the gate lines GL provided in the active region A / A.

[0046] The driving circuit can include a data driver DDR that drives multiple data lines DL, a gate driver GDR that drives multiple gate lines GL, a controller CTR that controls the data driver DDR and the gate driver GDR, etc.

[0047] The data driver DDR can drive multiple data lines DL by outputting data voltages to the multiple data lines DL.

[0048] The gate driver GDR can drive multiple gate lines GL by outputting scan signals to the multiple gate lines GL.

[0049] The controller CTR can control the operations of the data driver DDR and the gate driver GDR by providing various control signals DCS and GCS required for the driving operations of the data driver DDR and the gate driver GDR. Additionally, the controller CTR can provide image data DATA to the data driver DDR.

[0050] The controller CTR starts scanning at a time (or time point) defined by a frame, converts the image data received from an external source into a data signal format readable by the data driver DDR, outputs the converted image data DATA, and controls data driving at an appropriate time according to the scan.

[0051] The controller CTR receives various timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, and a clock signal CLK, from an external source (such as a host system), generates various control signals, and outputs the control signals to the data driver DDR and the gate driver GDR to control the data driver DDR and the gate driver GDR.

[0052] For example, the controller CTR outputs various gate control signals GCS including a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, etc., to control the gate driver GDR.

[0053] In addition, the display controller 140 outputs various data control signals DCS including a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, etc., to control the data driver DDR.

[0054] The controller CTR can be a timing controller used in typical display technologies, or can be a control device including a timing controller and capable of performing other control functions.

[0055] The controller CTR can be set as a component separate from the data driver DDR, or can be set as an integrated circuit (IC) together with the data driver DDR.

[0056] The data driver DDR drives a plurality of data lines DL by receiving image data DATA from the controller CTR and providing data voltages to the plurality of data lines DL. Herein, the data driver DDR will also be referred to as a source driver.

[0057] The data driver DDR can send various signals to and receive various signals from the controller CTR via various interfaces.

[0058] The gate driver GDR drives a plurality of gate lines GL in sequence by sequentially providing scan signals to the plurality of gate lines GL. Herein, the gate driver GDR will also be referred to as a scan driver.

[0059] The gate driver GDR sequentially provides scan signals having on or off voltages to the plurality of gate lines GL under the control of the controller CTR.

[0060] When a specific gate line is turned on by the gate driver GDR, the data driver DDR converts the image data DATA received from the controller CTR into an analog data voltage and provides the analog data voltage to the plurality of data lines DL.

[0061] Depending on the driving method, the design of the panel, etc., the data driver DDR can be located on one side (above or below) of the panel PNL, or in some cases, can be located on both sides (e.g., above and below) of the panel PNL.

[0062] Depending on the driving method, the design of the panel, etc., the gate driver GDR can be located on one side (e.g., left or right) of the panel PNL, or in some cases, can be located on both sides (e.g., left and right) of the panel PNL.

[0063] The data driver DDR may include one or more source driver integrated circuits (SDICs).

[0064] Each of the SDICs may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. In some cases, the data driver DDR may further include an analog-to-digital converter (ADC).

[0065] Each of the SDICs may be connected to a bonding pad of the panel PNL by a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed on the panel PNL. In some cases, the SDIC may be provided as an integrated part of the panel PNL. Additionally, a chip on film (COF) method may be used to implement each of the SDICs. In this case, each of the SDICs may be mounted on a circuit film to be electrically connected to a data line DL in the panel PNL via the circuit film.

[0066] The gate driver GDR may include a plurality of gate driving circuits (GDCs). The plurality of gate driving circuits may respectively correspond to a plurality of gate lines GL.

[0067] Each of the gate driving circuits may include a shift register, a level shifter, etc.

[0068] Each of the gate driving circuits may be connected to a bonding pad of the panel PNL by a TAB method or a COG method. Additionally, each of the gate driving circuits may be implemented using a COF method. In this case, each of the gate driving circuits may be mounted on a circuit film to be electrically connected to a gate line GL in the panel PNL via the circuit film. Additionally, an in-panel gate (GIP) method provided inside the panel PNL may be used to implement each of the gate driving circuits. That is, each of the gate driving circuits may be directly disposed in the panel PNL.

[0069] Figure 2 It is a diagram showing a system configuration of an electronic device according to an embodiment.

[0070] Refer to Figure 2 , in an electronic device according to an embodiment, the data driver DDR may be implemented using a COF method among various methods such as a TAB method, a COG method, and a COF method, while the gate driver GDR may be implemented using a GIP method among various methods such as a TAB method, a COG method, a COF method, and a GIP method.

[0071] The data driver DDR may be implemented as one or more source driver integrated circuits SDICs. Figure 2 The case where the data driver DDR is implemented as a plurality of source driver integrated circuits SDICs is shown.

[0072] When the data driver DDR is of the COF type, each of the source driver integrated circuits SDICs that make up the data driver DDR can be mounted on the source-side circuit film SF.

[0073] A part of the source-side circuit film SF can be electrically connected to a pad group (i.e., a group of pads) existing in the non-active area N / A of the panel PNL.

[0074] Wires for electrically connecting the source driver integrated circuit SDIC and the panel PNL can be provided on the source-side circuit film SF.

[0075] The electronic device can include at least one source printed circuit board SPCB and a control printed circuit board CPCB on which control components and various electronic devices are mounted, for circuit connection between multiple source driver integrated circuits SDICs and other devices.

[0076] Another part of the source-side circuit film SF on which the source driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB.

[0077] That is, a part of the source-side circuit film SF on which the source driver integrated circuit SDIC is mounted can be electrically connected to the non-active area N / A, while another part of the source-side circuit film SF can be electrically connected to the source printed circuit board SPCB.

[0078] A controller CTR for controlling the operations of the data driver DDR, the gate driver GDR, etc. can be provided in the control printed circuit board CPCB.

[0079] In addition, a power management integrated circuit (PMIC), etc. can also be provided on the control printed circuit board CPCB. The power management integrated circuit supplies various forms of voltage or current to the panel PNL, the data driver DDR, the gate driver GDR, etc., or controls the various forms of voltage or current to be supplied thereto.

[0080] The source printed circuit board SPCB and the control printed circuit board CPCB can be circuit-connected via at least one connection member CBL. The connection member CBL can be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

[0081] At least one source printed circuit board SPCB and the control printed circuit board CPCB can be integrated into a single PCB.

[0082] When the gate driver GDR is of the GIP type, multiple gate drive circuits GDCs included in the gate driver GDR can be directly provided on the non-active area N / A of the panel PNL.

[0083] Each of the gate driving circuits GDC can output a corresponding scan signal to a corresponding gate line GL provided in the active area A / A of the panel PNL.

[0084] Via wires related to gate driving provided in the non-active area N / A, a plurality of gate driving circuits GDC provided in the panel PNL can be supplied with various signals (e.g., a clock signal, a high-level gate voltage VGH, a low-level gate voltage VGL, a start signal VST, and a reset signal) required to generate a scan signal.

[0085] The wires related to gate driving provided in the non-active area N / A can be electrically connected to the source-side circuit film SF provided closest to the plurality of gate driving circuits GDC.

[0086] Figure 3 is a diagram showing the structure of each of the sub-pixels SP in the case where the panel PNL is an organic light-emitting diode (OLED) panel.

[0087] Refer to Figure 3 , each of the sub-pixels SP in the OLED panel PNL may further include: a first transistor T1 that transfers a data voltage Vdata to a first node N1 corresponding to the gate node of the driving transistor T3; and a storage capacitor Cst that holds the data voltage Vdata corresponding to the image signal voltage or a voltage corresponding to the data voltage Vdata during a period of one frame.

[0088] The organic light-emitting diode OLED may include a first electrode (i.e., an anode or a cathode), an organic layer including at least one light-emitting layer, a second electrode (i.e., a cathode or an anode), etc.

[0089] The driving transistor T3 drives the organic light-emitting diode OLED by supplying a driving current to the organic light-emitting diode OLED.

[0090] The driving transistor T3 includes a first node N1, a second node N2, a third node N3, etc.

[0091] The first node N1 of the driving transistor T3 is a node corresponding to the gate node and may be electrically connected to the source node or the drain node of the first transistor T1.

[0092] The second node N2 of the driving transistor T3 may be electrically connected to the first electrode 301 of the organic light-emitting diode OLED and may be a source node or a drain node.

[0093] The third node N3 of the driving transistor T3 is the node to which the driving voltage EVDD is applied. The third node N3 can be electrically connected to the driving voltage line DVL through which the driving voltage EVDD is provided, and can be a drain node or a source node.

[0094] Each of the driving transistor T3 and the first transistor T1 can be an N-type transistor or a P-type transistor.

[0095] The first transistor T1 can be electrically connected between the data line DL and the first node N1 of the driving transistor T3, and can be controlled by the first scan signal SCAN1 applied to the gate node through the gate line.

[0096] The first transistor T1 can be turned on by the first scan signal SCAN1 to transfer the data voltage Vdata provided through the data line DL to the first node N1 of the driving transistor T3.

[0097] The storage capacitor Cst can be electrically connected to the first node N1 and the second node N2 of the driving transistor T3.

[0098] The storage capacitor Cst is intentionally designed as an external capacitor disposed outside the driving transistor T3, rather than a parasitic capacitor (e.g., Cgs or Cgd), i.e., an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor T3.

[0099] Figure 3 The illustrated sub-pixel structure has a 2T1C structure including two transistors and a single capacitor, and is only an example provided for illustration. The sub-pixel structure can also include one or more transistors, or in some cases, one or more capacitors. Each of the plurality of sub-pixels can have the same structure, or some of the plurality of sub-pixels can have different structures.

[0100] Figure 4 is a diagram showing a 3T1C structure including three transistors and a single capacitor, where a single sub-pixel SP further includes a second transistor T2 electrically connected to the second node N2 of the driving transistor T3 and the reference voltage line RVL.

[0101] Refer to Figure 4 , the second transistor T2 can be electrically connected to the second node N2 of the driving transistor T3 and the reference voltage line RVL to be controlled for conduction and cutoff by the second scan signal SCAN2 applied to the gate node.

[0102] The drain node or source node of the second transistor T2 can be electrically connected to the reference voltage line RVL, and the source node or drain node of the second transistor T2 can be electrically connected to the second node N2 of the driving transistor T3.

[0103] For example, the second transistor T2 may be turned on during a display driving period, or may be turned on during a sense driving period in which the characteristics of the driving transistor T3 or the characteristics of the organic light-emitting diode OLED are sensed.

[0104] The second transistor T2 may be turned on by a second scan signal SCAN2 at a corresponding driving time (e.g., a display driving time or a voltage initialization time within the sense driving period) to transfer a reference voltage Vref provided through a reference voltage line RVL to a second node N2 of the driving transistor T3.

[0105] In addition, the second transistor T2 may be turned on by a second scan signal SCAN2 at a corresponding driving time (e.g., a sampling time within the sense driving period) to transfer the voltage of the second node N2 of the driving transistor T3 to the reference voltage line RVL.

[0106] That is, the second transistor T2 may control the voltage state of the second node N2 of the driving transistor T3, or transfer the voltage of the second node N2 of the driving transistor T3 to the reference voltage line RVL.

[0107] Here, the reference voltage line RVL may be electrically connected to an analog-to-digital converter (ADC) that senses the voltage of the reference voltage line RVL, converts the sensed voltage into a digital value, and outputs sensed data including the digital value.

[0108] The analog-to-digital converter may be included in each of the source driver integrated circuits SDICs that constitute the data driver DDR.

[0109] The sensed data output from the analog-to-digital converter may be used to sense the characteristics of the driving transistor T3 (e.g., threshold voltage or mobility) or the characteristics of the light-emitting diode OLED (e.g., threshold voltage).

[0110] In addition, the storage capacitor Cst may be an external capacitor intentionally designed to be disposed outside the driving transistor T3, rather than a parasitic capacitor (e.g., Cgs or Cgd), i.e., an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor T3.

[0111] Each of the driving transistor T3, the first transistor T1, and the second transistor T2 may be an N-type transistor or a P-type transistor.

[0112] In addition, the first scan signal SCAN1 and the second scan signal SCAN2 may be discrete gate signals. In this case, the first scan signal SCAN1 and the second scan signal SCAN2 may be respectively applied to the gate node of the first transistor T1 and the gate node of the second transistor T2 through different gate lines.

[0113] In some cases, the first scan signal SCAN1 and the second scan signal SCAN2 may be the same gate signal. In this case, the first scan signal SCAN1 and the second scan signal SCAN2 may be commonly applied to the gate node of the first transistor T1 and the gate node of the second transistor T2 through a single gate line (or a common gate line).

[0114] Figure 3 and Figure 4 The sub-pixel structure shown is merely an example provided for illustration. In some cases, each of the sub-pixels in the sub-pixel structure may further include one or more transistors or one or more capacitors.

[0115] In addition, each of the multiple sub-pixels may have the same structure, or some of the multiple sub-pixels may have different structures.

[0116] Figure 5 is a diagram schematically showing each of the gate driving circuits GDC provided in the panel PNL according to the embodiment.

[0117] Referring to Figure 5 , each of the gate driving circuits GDC may include a pull-up transistor Tup, a pull-down transistor Tdown, a control switch circuit CSC, etc.

[0118] The control switch circuit CSC may be a circuit that controls the voltage of a node Q corresponding to the gate node of the pull-up transistor Tup and the voltage of a node QB corresponding to the gate node of the pull-down transistor Tdown. The control switch circuit CSC may include a plurality of switches (transistors).

[0119] The pull-up transistor Tup is a transistor that provides a gate signal Vgate corresponding to a first-level voltage (e.g., a high-level voltage VGH) to the gate line GL through a gate signal output node Nout. The pull-down transistor Tdown is a transistor that provides a gate signal corresponding to a second-level voltage (e.g., a low-level voltage VGL) to the gate line GL through the gate signal output node Nout. The pull-up transistor Tup and the pull-down transistor Tdown may be turned on at different times.

[0120] The pull-up transistor Tup is electrically connected to a clock signal application node Nclk to which a clock signal CLK is applied and a gate signal output node Nout electrically connected to a gate line GL, and is turned on or off by the voltage at node Q.

[0121] The gate node of the pull-up transistor Tup is electrically connected to node Q. The drain node or source node of the pull-up transistor Tup is electrically connected to the clock signal application node Nclk. The source node or drain node of the pull-up transistor Tup is electrically connected to the gate signal output node Nout, and a gate signal Vgate is output from the gate signal output node Nout.

[0122] The pull-up transistor Tup is turned on by the voltage at node Q to output, through the gate signal output node Nout, a gate signal Vgate having a high-level voltage VGH in the high-level section of the clock signal CLK.

[0123] The gate signal Vgate having the high-level voltage VGH output through the gate signal output node Nout is provided to the corresponding gate line GL.

[0124] The pull-down transistor Tdown is electrically connected to the gate signal output node Nout and a base voltage node Nvss, and is turned on or off by the voltage at node QB.

[0125] The gate node of the pull-down transistor Tdown is electrically connected to node QB. The drain node or source node of the pull-down transistor Tdown is electrically connected to the base voltage node Nvss to receive a base voltage VSS corresponding to a constant voltage. The source node or drain node of the pull-down transistor Tdown is electrically connected to the gate signal output node Nout, and the gate signal Vgate is output through the gate signal output node Nout.

[0126] The pull-down transistor Tdown is turned on by the voltage at node QB to output, through the gate signal output node Nout, a gate signal Vgate having a low-level voltage VGL. Thus, the gate signal Vgate having the low-level voltage VGL can be provided to the corresponding gate line GL through the gate signal output node Nout. The gate signal Vgate having the low-level voltage VGL can be, for example, the base voltage VSS.

[0127] In addition, the control switch circuit CSC may include two or more transistors or the like, and includes main nodes such as node Q, node QB, a set node (also referred to as a start node) S, and a reset node R. In some cases, the control switch circuit CSC may also include, for example, an input node through which various voltages such as a drive voltage VDD are input.

[0128] In the control switch circuit CSC, node Q is electrically connected to the gate node of the pull-up transistor Tup and is repeatedly charged and discharged.

[0129] In the control switch circuit CSC, node QB is electrically connected to the gate node of the pull-down transistor Tdown and is repeatedly charged and discharged.

[0130] In the control switch circuit CSC, the set node S receives the set signal SET applied thereto, and the set signal SET indicates the start of the gate drive of the corresponding gate drive circuit GDC.

[0131] Here, the set signal SET applied to the set node S can be the start signal VST input from outside the gate driver GDR or the signal (e.g., carry signal) obtained by feeding back the gate signal Vgate output from the gate drive circuit GDC in the previous stage before the current gate drive circuit GDC.

[0132] In the control switch circuit CSC, the reset signal RST applied to the reset node R can be the reset signal for initializing the gate drive circuits GDC of all stages, or the carry signal input from another stage (e.g., the previous stage or the subsequent stage).

[0133] The control switch circuit CSC charges node Q in response to the set signal SET and discharges node Q in response to the reset signal RST. The control switch circuit CSC may include an inverter circuit to charge or discharge node Q and node QB at different times.

[0134] As Figure 3 shown, the driving transistor T3 and the switching transistor T1 (the first transistor) may be provided in each of the plurality of sub-pixels SP in the active region A / A of the panel PNL corresponding to the OLED panel. However, this embodiment is not limited thereto, and as Figure 4 shown, three or more transistors may be provided in the active region A / A of the OLED panel PNL.

[0135] In addition, as Figure 2 shown, when the gate drive circuit GDC is the INS1P circuit, that is, when the gate drive circuit GDC is provided within the panel PNL, the various transistors (e.g., the pull-up transistor Tup, the pull-down transistor Tdown, and the transistors within the control switch circuit CSC) constituting each of the gate drive circuits GDC as Figure 5 shown may be provided in the non-active region N / A surrounding the active region A / A of the panel PNL.

[0136] Figure 6 is a cross-sectional view showing the transistors provided in the electronic device according to the embodiment.

[0137] Reference Figure 6 According to an embodiment, the electronic device may include at least one transistor Tr.

[0138] The transistor Tr may include a first active layer 620, a gate electrode 640, a first electrode 671, and a second electrode 672.

[0139] As Figure 6 shown, the first active layer 620 including a first region 621, a second region 622, and a channel region 623 is disposed on a substrate 610, and a gate insulating film 630 may be disposed on the first active layer 620. The gate electrode 640 may be disposed on the gate insulating film 630, and an insulating film 650 may be disposed on the substrate 610 on which the gate electrode 640 is disposed. An interlayer insulating film 660 is disposed on the insulating film 650, and the first electrode 671 and the second electrode 672 spaced apart from each other may be disposed on the interlayer insulating film 660.

[0140] Here, one of the first electrode 671 and the second electrode 672 may be electrically connected to a power supply node of the electronic device.

[0141] For simplicity, the following description will mainly focus on the configuration in which the second electrode 672 is connected to the power supply node.

[0142] After manufacturing a module of an electronic device including a transistor Tr that needs to be driven at high speed, a high voltage (e.g., 35V or higher) may be applied to the transistor Tr, more specifically, to the second electrode 672 connected to the power supply node, in an aging step for testing defects in the transistor Tr. Here, the voltage applied to the gate electrode 640 may be 0V.

[0143] When the transistor Tr is driven under the above conditions, a strong electric field is applied to the transistor Tr, such that the channel region 623 adjacent to the second region 622 of the first active layer 620 may deteriorate. This may cause defects in the conduction band of the first active layer 620 and adjacent regions, thereby reducing the on-current of the transistor Tr and changing the threshold voltage Vth of the transistor Tr. Therefore, the reliability of the transistor Tr may be reduced.

[0144] This may be due to a reduction in the thickness of the gate insulating film 630 located between the gate electrode 640 and the channel region 623. According to a typical transistor structure, the gate insulating film may be disposed to overlap with the gate electrode and the channel region of the active layer. The cross-section of the gate insulating film may have a positive conical shape such that the thickness of the gate insulating film may decrease in a direction toward the edge of the gate insulating film.

[0145] As described above, the channel region of the region corresponding to the thinned region of the gate insulating film between the gate electrode and the channel region of the active layer may deteriorate, thereby reducing the reliability of the transistor, which is problematic.

[0146] The transistor Tr provided in the electronic device according to the embodiment may have a structure for preventing deterioration of the channel region of the active layer of each of the transistors Tr that require high-speed driving and the transistors Tr that are subjected to aging.

[0147] Specifically, the first active layer 620 of the transistor Tr may be provided on the substrate 610.

[0148] Although not shown in Figure 6 at least one buffer layer may be provided between the substrate 610 and the first active layer 620.

[0149] The buffer layer may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0150] In addition, in the case where the buffer layer has a multilayer structure, the buffer layer may have a structure in which layers each including at least two inorganic insulating materials selected from SiOx, SiNx, and SiON overlap each other, but the present disclosure is not limited thereto.

[0151] The first active layer 620 may be made of an oxide semiconductor. The material of the first active layer 620 may be a metal oxide semiconductor including one of oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), and combinations of metals such as Zn, In, Ga, Sn, and Ti and their oxides.

[0152] For example, the first active layer 620 may include at least one selected from zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO), but the present disclosure is not limited thereto.

[0153] Such an oxide semiconductor is advantageously applicable to large-area electronic devices as compared with a silicon (Si) semiconductor.

[0154] The first active layer 620 may include a first region 621, a second region 622 spaced apart from the first region 621, and a channel region 623 provided between the first region 621 and the second region 622.

[0155] The first region 621 and the second region 622 of the first active layer 620 can be conductive regions (i.e., regions processed to be conductive). Accordingly, the resistance of each of the first region 621 and the second region 622 of the first active layer 620 can be lower than the resistance of the channel region 623.

[0156] When the transistor Tr is in the on state, charges can move through the channel region 623 of the first active layer 620.

[0157] The width W1 of the first region 621 of the first active layer 620 can be different from the width W2 of the second region 622 of the first active layer 620. For example, as Figure 6 shown, the width W1 of the first region 621 of the first active layer 620 can be greater than the width W2 of the second region 622 of the first active layer 620.

[0158] The gate insulating film 630 can be disposed on the first active layer 620.

[0159] The gate insulating film 630 can include an inorganic insulating material such as SiOx, SiNx, or SiON, but the present disclosure is not limited thereto.

[0160] As Figure 6 shown, the gate insulating film 630 can be disposed to expose a part of the first active layer 620. For example, the gate insulating film 630 can be disposed to expose a part of the first region 621 of the first active layer 620.

[0161] The gate insulating film 630 can overlap the entire channel region 623 of the first active layer 620. In addition, the gate insulating film 630 can overlap all of one of the first region 621 and the second region 622 of the first active layer 620 and overlap a part of the other region.

[0162] For example, as Figure 6 shown, the gate insulating film 630 can overlap a part of the first region 621 of the first active layer 620 and can overlap the entire second region 622 of the first active layer 620.

[0163] In addition, the gate insulating film 630 can be disposed to surround the top surface and the side surface of the second region 622 of the first active layer 620. As Figure 6 shown, the gate insulating film 630 can extend in the direction in which the second region 622 extends from the channel region 623 while being disposed to cover the second region 622 of the first active layer 620. In the present disclosure, the gate insulating film 630 can have a structure for covering the second region 622 of the first active layer 620.

[0164] In the gate insulating film 630 as described above, the material of the gate insulating film 630 provided on the substrate 610 can be patterned by dry etching, so that finally a part of the first region 621 of the first active layer 620 is exposed.

[0165] In the process of dry etching the material of the gate insulating film 630, a partial region of the first active layer 620 can be made conductive. Specifically, the region of the first active layer 620 provided in a region that does not overlap with the gate insulating film 630 can be made conductive.

[0166] That is, the first region 621, which is one of the conductive regions of the first active layer 620, can include a region that does not overlap with the gate insulating film 630.

[0167] The gate electrode 640 of the transistor Tr can be provided on the gate insulating film 630.

[0168] The composition of the gate electrode 640 can include one selected from aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), and their alloys, but the present disclosure is not limited thereto.

[0169] In cross section, one end and the other end of the gate electrode 640 can be provided on the top surface of the gate insulating film 630.

[0170] The width W3 of the gate electrode 620 can be smaller than the width W4 of the gate insulating film 630. The width W3 of the gate electrode 620 and the width W4 of the gate insulating film 630 can be the minimum lengths in a direction perpendicular to the stacking direction of the gate insulating film 630 and the gate electrode 620.

[0171] The gate electrode 640 can overlap with the first active layer 620.

[0172] Specifically, the gate electrode 640 can overlap with a part of the channel region 623 of the first active layer 620, and can overlap with a part of one of the first region 621 and the second region 622 of the first active layer 620.

[0173] For example, as Figure 6 shown, the gate electrode 640 can overlap with a part of the channel region 623 of the first active layer 620, and can overlap with a part of the first region 621 of the first active layer 620. The gate electrode 640 can overlap with the boundary between the channel region 623 and the first region 621 of the first active layer 620. In addition, the gate electrode 640 can overlap with the second region 622 of the first active layer 620.

[0174] That is, the gate electrode 640 can overlap with a part of the channel region 623 of the first active layer 620.

[0175] Therefore, the channel region 623 of the first active layer 620 can be set to deviate from the center of the gate electrode 640 in the direction in which the second region 622 of the first active layer 620 extends from the channel region 623.

[0176] That is, the channel region 623 of the first active layer 620 can be set asymmetrically with respect to the center of the gate electrode 640.

[0177] In addition, the gate insulating film 630 can overlap with the entire channel region 623 of the first active layer 620 and can overlap with a part of the first region 621 of the first active layer 620. In this structure, one end of the gate insulating film 630 can be set to deviate more from the center of the gate electrode 640 than one end of the gate electrode 640 in the direction in which the first region 621 extends from the channel region 623.

[0178] That is, the width of the region where the gate insulating film 630 overlaps with the first region 621 of the first active layer 620 can be greater than the width of the region where the gate 640 overlaps with the first region 621 of the first active layer 620. Here, the width of the region where the gate insulating film 630 overlaps with the first region 621 of the first active layer 620 and the width of the region where the gate electrode 640 overlaps with the first region 621 of the first active layer 620 can have a minimum length in a direction perpendicular to the stacking direction of the first active layer 620 and the gate insulating film 630.

[0179] Since one end of the gate insulating film 630 is set to deviate more from the center of the gate electrode 640 than one end of the gate electrode 640 in the direction in which the first region 621 extends from the channel region 623 as described above, one end of the gate electrode 640 can be separated from the first region 621 of the first active layer 620 by the gate insulating film 630. Therefore, it is possible to prevent a short circuit from occurring due to contact between the gate electrode 640 and the first region 621, that is, the conductive region, due to process errors or the like.

[0180] The insulating film 650 can be provided on the substrate 610 on which the gate electrode 640 is provided.

[0181] Here, the insulating film 650 can include an inorganic insulating material such as SiOx, SiNx, or SiON. For example, the insulating film 650 can be SiNx.

[0182] Such an insulating film 650 can contain hydrogen.

[0183] The hydrogen contained in the insulating film 650 can be used to supply hydrogen to the first region 621 and the second region 622 of the first active layer 620 provided below the insulating film 650.

[0184] In addition, the amount of electric charge of a thin film transistor including an oxide semiconductor can be determined by the hydrogen content with respect to the metal components contained in the oxide semiconductor. Since hydrogen in the oxide semiconductor can act as a carrier, the mobility of the charge can be greater as the hydrogen content increases.

[0185] As described above, supplying hydrogen to the first region 621 and the second region 622 of the first active layer 620 through the insulating film 650 can increase the charge mobility in the first region 621 and the second region 622 of the first active layer 620. That is, the insulating film 650 can be used to make the first region 621 and the second region 622 of the first active layer 620 conductive.

[0186] Due to the insulating film 650, the first region 621 of the first active layer 620 that conducts electricity in the dry etching of the gate insulating film 630 can extend to the region under the gate electrode 640. That is, the area of the region 621 that is made conductive in the process of manufacturing the gate insulating film 630 can be increased by hydrogen diffused from the insulating film 650, so that the first region 621, i.e., the conductive region, can be provided not only in the region that does not overlap with the gate insulating film 630, but also in the regions under the gate insulating film 630 and the gate electrode 640.

[0187] In addition, the insulating film 650 can make other regions of the first active layer 620 that are not made conductive in the dry etching of the gate insulating film 630 conductive.

[0188] For example, due to the insulating film 650, the second region 622 that is spaced apart from the first region 621 of the first active layer 620 as an edge of the first active layer 620 can be made conductive by the diffusion of hydrogen through the gate insulating film 630.

[0189] However, since a part of the first region 621 of the first active layer 620 is in direct contact with the insulating film 650, and the gate insulating film 630 is disposed between the second region 622 of the first active layer 620 and the insulating film 650, the amount of hydrogen diffused into the first region 621 can be different from the amount of hydrogen diffused into the second region 622.

[0190] In addition, the channel region 623 integrated with the second region 622 can also be provided in the region that does not overlap with the gate electrode 640, where the hydrogen content in the channel region 623 is lower than the hydrogen content in each of the first region 621 and the second region 622.

[0191] In the portion of the first active layer 620 that overlaps with the gate electrode 640, the hydrogen diffused from the insulating film 650 can be blocked by the gate electrode 640 and not reach the first active layer 620.

[0192] Therefore, hydrogen as a carrier may not be provided to a part of the region of the first active layer 620 that overlaps with a part of the gate electrode 640, thereby forming a channel region 623 having a higher resistance than each of the first region 621 and the second region 622.

[0193] That is, a part of the channel region 623 of the first active layer 620 may overlap with a part of the gate electrode 640, and another part of the channel region 623 may be disposed between an edge of the gate electrode 640 and the second region 622 of the first active layer 620.

[0194] Therefore, the channel region 623 of the first active layer 620 may be disposed asymmetrically with respect to the center of the gate electrode 640.

[0195] Reference may be made later to Figures 7 to 10 Specifically describe the position of the channel region 623 of the first active layer 620 due to the conductivity effect caused by the insulating film 650.

[0196] The interlayer insulating film 660 may be disposed on the insulating film 650.

[0197] The interlayer insulating film 660 may include an inorganic insulating material such as SiOx, SiNx, or SiON. For example, the insulating film 650 may be SiNx.

[0198] The first electrode 671 and the second electrode 672 of the transistor Tr that are separated from each other may be disposed on the interlayer insulating film 660.

[0199] One of the first electrode 671 and the second electrode 672 may be the source electrode of the transistor Tr, and the other of the first electrode 671 and the second electrode 672 may be the drain electrode of the transistor Tr.

[0200] For example, the first electrode 671 may be the source electrode of the transistor Tr, and the second electrode 672 may be the drain electrode of the transistor Tr. However, the present disclosure is not limited thereto. The first electrode 671 may be the drain electrode of the transistor Tr, and the second electrode 672 may be the source electrode of the transistor Tr.

[0201] The first electrode 671 may be connected to the first region 621 of the first active layer 620 through a contact hole provided in the interlayer insulating film 660 and the insulating film 650. The second electrode 672 may be connected to the second region 622 of the first active layer 620 through a contact hole provided in the interlayer insulating film 660, the insulating film 650, and the gate insulating film 630.

[0202] As described above, the second electrode 672 of the transistor Tr may be electrically connected to the power supply node of the electronic device.

[0203] In driving the transistor Tr according to an embodiment, even when a high voltage is applied to the second electrode 672, the gate insulating film 630 can be arranged to overlap the entire channel region 623 and the second region 622 and surround the top surface and one side surface of the second region 622, so that the channel region 623 adjacent to the second region 622 of the first active layer 620 connected to the second electrode 672 does not deteriorate.

[0204] Therefore, this can overcome the problem that the reliability of the transistor Tr is reduced due to the deterioration of the channel region 623 caused by the reduction in the thickness of the gate insulating film 630 present between the gate electrode 640 and the channel region 623.

[0205] In addition, since one of the conductive regions of the first active layer 620, i.e., the first region 621, is arranged to overlap the gate electrode 640, the length of the channel region 623 can be reduced, such that the charge mobility may be affected. However, in the transistor Tr according to the embodiment, the channel region 623 can extend toward the region where the channel region 623 of the first active layer 620 does not overlap the gate electrode 640, i.e., the second region 622, so that a reduction in the mobility of the transistor Tr can be prevented.

[0206] The positions of the first region 621, the second region 622, and the channel region 623 of the first active layer 620 will be discussed in detail below with reference to the process flow diagram.

[0207] Figures 7 to 10 is a diagram schematically showing the process of manufacturing Figure 6 the first active layer and the gate electrode of the transistor shown.

[0208] Hereinafter, in cases where some features (e.g., components or effects) are the same as those of the above-described embodiment, their descriptions may be omitted.

[0209] Referring to Figure 7 , a first active layer material 620a can be provided on the substrate 610. After the first active layer material 620a is provided on the entire surface of the substrate 610, the first active layer material 620a can be patterned to be present in a specific region, as Figure 7 shown.

[0210] A gate insulating film material 630a can be provided on the first active layer material 620a.

[0211] The gate insulating film material 630a can be provided on the entire surface of the substrate 610.

[0212] A gate electrode material 640a can be provided on the gate insulating film material 630a.

[0213] A photoresist 710 can be disposed on the gate electrode material 640a.

[0214] The photoresist 710 can be disposed to expose a part of the top surface of the gate electrode material 640a.

[0215] In addition, the photoresist 710 can have different thicknesses according to its regions. For example, the photoresist 710 can include a region having a first thickness T1 and a region having a second thickness T2, where the first thickness T1 is thicker than the second thickness T2.

[0216] The region where the photoresist 710 is disposed to expose a part of the top surface of the gate electrode material 640a can be a region including the first region 621 of the first active layer 620 shown therein Figure 6 wherein the first active layer 620 is disposed.

[0217] The region where the photoresist 710 has the first thickness T1 can be a region corresponding to the region where the gate electrode 640 is disposed as shown Figure 6 therein.

[0218] The region where the photoresist 710 has the second thickness T2 can be a region including the second region 622 of the first active layer 620 and a part of the channel region 623 as shown Figure 6 therein.

[0219] Thereafter, a dry etching for patterning the gate electrode material 640a and the gate insulating film material 630a can be performed.

[0220] The dry etching using the photoresist 710 as a mask can produce a structure as shown Figure 8 therein.

[0221] Specifically, in the region where the photoresist 710 does not exist, the gate electrode material 640a and the gate insulating film material 630a can be removed by dry etching, thereby providing the gate electrode 640 and the gate insulating film 630 as shown Figure 7 therein. Figure 8 Therein.

[0222] As shown Figure 8 therein, the top surface and the side surfaces of the first active layer material 820 disposed in the region where the gate electrode material 640a and the gate insulating film material 630a are removed can be exposed.

[0223] In addition, the part of the first active layer material 820 whose top surface and side surfaces are exposed can be converted into a conductive region 621a by dry etching. That is, the conductive region can exist only in one edge part of the first active layer material 820.

[0224] Here, the gate insulating film 630 provided on the first active layer material 820 may be provided such that a part of the top surface of one edge of the gate insulating film 630 is exposed from the gate electrode 640. The other edge of the gate insulating film 630 may extend to a part of the top surface of the substrate 610 where there is no first active layer material 820 thereon, while surrounding the top surface and side surfaces of the first active layer material 820.

[0225] In addition, as Figure 8 shown, Figure 7 the region of the photoresist 710 having the first thickness T1 as shown may be reduced in thickness by dry etching.

[0226] The region of the photoresist 710 having the second thickness T2 as shown may be removed after the dry etching, thereby providing a photoresist pattern 810. Thus, as Figure 7 shown, the top surface and side surfaces of the region of the gate insulating film 630 where the photoresist 710 having the second thickness T2 has been provided may be exposed. Figure 8 After that, as

[0227] shown, the photoresist pattern 810 remaining on the gate electrode 640 may be removed, and the top surface and side surfaces of the gate electrode 640 may be exposed. Figure 9

[0228] Thereafter, as Figure 10 shown, an insulating film 650 may be provided on the substrate 610 on which the gate electrode 640 is provided.

[0229] The insulating film 650 may extend to contact a part of the top surface and the side surface of the region of the first active layer material that has been made conductive by dry etching ( Figure 8 621a in ), and may contact at least one side surface of the gate insulating film 630 and the top surface and side surfaces of the gate electrode 640. In addition, the insulating film 650 may contact the surface of the gate insulating film 630 provided in a region that does not overlap with the gate electrode 640.

[0230] Here, the insulating film 650 may contain hydrogen. The hydrogen contained in the insulating film 650 may reach the first active layer material provided below the insulating film 650.

[0231] Therefore, the size of the region ( Figure 8 621a in Figure 10 that is conductive during the formation of the gate insulating film 630) may be increased by the hydrogen diffusing from the insulating film 650, and finally the first region 621 of the first active layer 620 as shown in

[0232] The first region 621 of the first active layer 620 formed through the above process can be disposed not only in a region non-overlapping with the gate insulating film 630, but also in a region under the gate insulating film 630 and the gate electrode 640.

[0233] In addition, a second region 622 spaced apart from the first region 621 on one edge of the first active layer 620 can be made conductive by the diffusion of hydrogen from the insulating film 650.

[0234] Furthermore, since the gate insulating film 630 is disposed between the second region 622 of the first active layer 620 and the insulating film 650, the hydrogen provided from the insulating film 650 can reach the second region 622 of the first active layer 620 through the gate insulating film 630.

[0235] The length of the second region 622 of the first active layer 620 can be less than the length of the first region 621. The second region 622 can be disposed non-overlapping with the gate electrode 640. Here, the lengths of the first region 621 and the second region 622 of the first active layer 620 can be minimum lengths in a direction perpendicular to the stacking direction of the first active layer 620 and the gate insulating film 630.

[0236] In addition, in a region where the first active layer 620 overlaps with the gate electrode 640, the hydrogen diffused from the insulating film 650 can be blocked by the gate electrode 640 and thus does not reach the first active layer 620. Therefore, hydrogen as a carrier can be not provided from the insulating film 650 to a part of a region where the first active layer 620 partially overlaps with the gate electrode 640, thereby providing a higher resistance for the channel region 623 compared to each of the first region 621 and the second region 622.

[0237] In addition, the channel region 623 can extend to a part of the first active layer 620 that does not overlap with the gate electrode 640.

[0238] The part of the first active layer 620 that does not overlap with the gate electrode 640 can be a region with a resistance less than that of the second region 622 because the diffusion of hydrogen provided from the insulating film 650 is prevented by the gate electrode 640.

[0239] That is, the channel region 623 of the first active layer 620 can include a part overlapping with a part of the gate electrode 640 and a part not overlapping with the gate electrode 640.

[0240] The resistance of the channel region 623 of the first active layer 620 can be higher than the resistance of each of the first region 621 and the second region 622.

[0241] In addition, the resistance of the portion of the channel region 623 that overlaps with the gate electrode 640 may be different from the resistance of the portion of the channel region 623 that does not overlap with the gate electrode 640. However, the present disclosure is not limited thereto, and the resistance of the entire channel region 623 may be the same.

[0242] In the case where a part of the first region 621 of the first active layer 620 as shown Figure 10 overlaps with the gate electrode 640, the length of the channel region 623 can be reduced, thereby affecting the mobility of charges. However, according to the present disclosure, the first region 621 of the first active layer 620 can have a portion that does not overlap with the gate electrode 640, which is provided by the increased length of the first region 621 of the first active layer 620. Therefore, the length of the channel region 623 may be substantially sufficient to prevent a decrease in the mobility of charges.

[0243] Hereinafter, the characteristics of the transistor Tr having the above structure according to an embodiment will be compared with the characteristics of a transistor according to a comparative example.

[0244] Figure 11 is a graph comparing the characteristics of the transistor Tr having the Figure 6 structure according to an embodiment with the characteristics of a transistor according to a comparative example.

[0245] In this case, the transistor according to the comparative example may include an active layer, a gate electrode provided on the active layer, and a source electrode and a drain electrode provided on the gate electrode and electrically connected to the active layer. According to the structure of the transistor, a gate insulating film may be provided between the active layer and the gate electrode, and the entire region of the gate insulating film and the entire region of the gate electrode may overlap with the channel region of the active layer.

[0246] In Figure 11 , the x-axis represents the gate voltage, and the y-axis represents the drain current.

[0247] In Figure 11 , in order to measure the characteristics of the transistor according to the comparative example and the characteristics of the transistor according to the example, the drain current is measured by applying a gate voltage from -20V to +20V.

[0248] In an initial state where no voltage is applied to the electrodes (e.g., the second electrode) connected to the power supply node and the gate electrode in each of the transistors, a driving voltage VDD of 0.1V and a driving voltage of 10V are applied to both the transistor according to the comparative example and the transistor according to the example.

[0249] In addition, a voltage of 45 V is applied to the electrode connected to the power supply node of each of the transistor according to the comparative example and the transistor according to the example. After applying a voltage of 0 V to the gate electrode for 11 hours (after 11 hours of stress), a drive voltage VDD of 0.1 V and a drive voltage of 10 V are applied to the two transistors.

[0250] When driving the transistor according to the comparative example under the above conditions, it can be understood that the on-current has decreased and the threshold voltage Vth has changed from the initial value.

[0251] However, in the transistor according to the example, it can be understood that even after driving for 11 hours, the on-current has not decreased and the threshold voltage Vth has not changed from the initial value.

[0252] That is, it can be understood that even when a high voltage is applied to the electrode connected to the power supply node, the reliability of the transistor according to the example can be maintained.

[0253] The transistor Tr having Figure 6 the structure shown can be Figure 3 one of the transistors T1, T2, and T3 shown in Figure 4 and Figure 5 one of the pull-up transistor Tup and the pull-down transistor Tdown shown in

[0254] In particular, when the transistor Tr having Figure 6 the structure shown is the transistor T3, the transistor Tr can have the structure shown in Figure 12

[0255] Figure 12 is a cross-sectional view showing the structure of a transistor provided in an electronic device according to other embodiments.

[0256] Hereinafter, when some features (for example, components or effects) are the same as those of the above embodiments, the description thereof may be omitted.

[0257] Referring to Figure 12 , a light-shielding layer 1280 can also be provided below the transistor Tr including the first active layer 620, the gate electrode 640, the first electrode 671, and the second electrode 672.

[0258] The composition of the light-shielding layer 1280 may include one selected from aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), and their alloys, but the present disclosure is not limited thereto.

[0259] In addition, although in Figure 12 ​The light shielding layer 1280 is shown as having a single-layer structure, but the present disclosure is not limited thereto. The light shielding layer 1280 may have a multi-layer structure.

[0260] The light shielding layer 1280 may be disposed to overlap with the first active layer 620 of the transistor Tr. The light shielding layer 1280 may prevent the electrical characteristics of the first active layer 620 from being changed by light incident on the first active layer 620.

[0261] A buffer layer 1290 may be disposed on the light shielding layer 1280.

[0262] The buffer layer 1290 may include an inorganic insulating material such as SiOx, SiNx, or SiON, but the present disclosure is not limited thereto.

[0263] Although in Figure 12 the buffer layer 1290 is shown as having a single-layer structure, the buffer layer 1290 according to the present disclosure may have a multi-layer structure.

[0264] In the case where the buffer layer 1290 has a multi-layer structure, the buffer layer may have a structure in which layers each including at least two inorganic insulating materials selected from SiOx, SiNx, and SiON overlap each other, but the present disclosure is not limited thereto.

[0265] In addition, although not shown in the figure, in the case where the transistor Tr having the structure as shown in Figure 6 or Figure 12 is a driving transistor, one of the first electrode 671 and the second electrode 672 of the transistor Tr may be electrically connected to the pixel electrode of the electronic device.

[0266] In addition, the transistor provided in the electronic device according to the embodiment may have a different structure.

[0267] Figure 13 is a cross-sectional view showing the structure of the transistor provided in the electronic device according to other embodiments.

[0268] Hereinafter, in the case where some features (for example, components or effects) are the same as those of the above-described embodiment, the description thereof may be omitted.

[0269] Referring to Figure 13 , the transistor Tr provided in the electronic device according to other embodiments may further include a second active layer 1320 disposed below the first active layer 620 shown in Figure 6 .

[0270] The second active layer 1320 may be an oxide semiconductor.

[0271] The second active layer 1320 may include a third region 1321, a fourth region 1322 spaced apart from the third region 1321, and a channel region 1323 disposed between the third region 1321 and the fourth region 1322.

[0272] Here, the third region 1321 of the second active layer 1320 may overlap with the first region 621 of the first active layer 620, and the fourth region 1322 of the second active layer 1320 may overlap with the second region 622 of the first active layer 620. Additionally, the channel region 1323 of the second active layer 1320 may overlap with the channel region 623 of the first active layer 620.

[0273] The third region 1321 of the second active layer 1320 may be made conductive due to dry etching of the gate insulating film 630 and hydrogen diffused through the insulating film 650 provided on the gate electrode 640.

[0274] The fourth region 1322 of the second active layer 1320 may be made conductive by hydrogen diffused through the insulating film 650.

[0275] When viewed in cross-section, the length of the fourth region 1322 may be shorter than the length of the third region 1321. The lengths of the fourth region 1322 and the third region 1321 may be minimum lengths in a direction perpendicular to the stacking direction of the second active layer 1320 and the gate insulating film 630.

[0276] A part of the channel region 1323 of the second active layer 1320 may overlap with the gate electrode 640, and another part of the channel region 1323 of the second active layer 1320 may not overlap with the gate electrode 640 but may overlap with the gate insulating film 630 and the insulating film 650.

[0277] Furthermore, the thicknesses of the first active layer 620 and the gate insulating film 630 may be thin such that hydrogen diffused through the insulating film 650 can reach the fourth region 1322 of the second active layer 1320.

[0278] In this regard, the first active layer 620 and the second active layer 1320 may be manufactured by, for example, metalorganic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD).

[0279] Here, the MOCVD method is a subclass of chemical vapor deposition (CVD) and is used to fabricate thin films through a deposition reaction on the surface of a hot substrate onto which reactive gases are injected. The reactant gases contain organometallic complexes. The MOCVD method is a technique for growing semiconductor thin films by decomposing organometallic gases on a hot substrate through heating. Compared with other CVD methods such as plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD), the MOCVD method is performed at a lower temperature. Thin film processing can be controlled at the atomic level, and uniform thin films can be fabricated.

[0280] The ALD method is a subclass of CVD and is used to fabricate thin films on the surface of a substrate by separately providing reactants and deposition particles generated from the chemical reaction of reactant gases. After chemisorbing one reactant onto the substrate, a second gas or a third gas is provided to the substrate, resulting in subsequent chemisorption onto the substrate, thereby depositing a thin film on the substrate.

[0281] Compared with physical vapor deposition (PVD) methods or other CVD methods, the use of MOCVD or ALD methods can improve the productivity or growth rate of thin films. Additionally, due to high thin film coating performance, the thickness of the thin film can be precisely adjusted.

[0282] The first active layer 620 and the second active layer 1320 arranged in such a manner may contain at least one element such as In, Ga, Zn, Ti, or Sn and oxygen (O 2 ).

[0283] Here, the content of the composition of the first active layer 620 may be different from the content of the composition of the second active layer 1320. Thus, although the first active layer 620 and the second active layer 1320 may have different conductivities. However, the present disclosure is not limited thereto.

[0284] In the case where an oxide semiconductor is used as the active layer of a driving transistor, the threshold voltage significantly shifts with the change in the channel length. Therefore, in the case where an oxide semiconductor is used as the active layer of a driving transistor, it may be difficult to achieve a short channel while maintaining the threshold voltage value required for an electronic device.

[0285] As Figure 13 shown, an electronic device according to an embodiment can achieve a short channel while maintaining the threshold voltage value required for the electronic device by using a multilayer structure in which two active layers are stacked.

[0286] As described above, since the first active layer 620 and the second active layer 1320 are stacked on each other, the first active layer 620 and the second active layer 1320 may have a heterojunction structure.

[0287] In the junction between the first active layer 620 and the second active layer 1320, a depletion region can be formed by the built-in potential. The built-in potential Vbi causes band bending in the junction. Since the depletion region is provided in the junction between the first active layer 620 and the second active layer 1320, the total charge density can be controlled, thereby preventing the threshold voltage from being distorted according to the channel length.

[0288] Although the transistor Tr having the Figure 13 structure shown can be Figure 3 and Figure 4 the driving transistor T3 shown, the present disclosure is not limited thereto.

[0289] For example, the transistor Tr having the Figure 3 structure shown can be Figure 3 and Figure 4 one of the transistors T1 and T2 shown, or can be Figure 5 one of the pull-up transistor Tup and the pull-down transistor Tdown shown.

[0290] Figure 14 is a cross-sectional view showing the structure of a transistor provided in an electronic device according to other embodiments.

[0291] Hereinafter, in the case where some features (for example, components or effects) are the same as those of the above-described embodiments, descriptions thereof may be omitted.

[0292] Referring to Figure 14 , an electronic device according to other embodiments may include a transistor Tr.

[0293] The transistor Tr may include a second active layer 1420, a gate electrode 640, a first electrode 671, and a second electrode 672.

[0294] As Figure 14 shown, the second active layer 1420 may be provided on the substrate 610, and the gate insulating film 630 may be provided on the second active layer 1420. The gate electrode 640 may be provided on the gate insulating film 630, the interlayer insulating film 660 may be provided on the substrate 610 on which the gate electrode 640 is provided, and the first electrode 671 and the second electrode 672 spaced apart from each other may be provided on the interlayer insulating film 660.

[0295] The second active layer 1420 may be an oxide semiconductor.

[0296] The second active layer 1420 may include a first region 1421, a second region 1422, a third region 1424, and a channel region 1423.

[0297] The first region 1421 and the second region 1422 can be spaced apart from each other. One of the first region 1421 and the second region 1422 can be disposed between the channel region 1423 and a third region 1424 spaced apart from the channel region 1423.

[0298] For example, as Figure 14 shown, the channel region 1423 can be disposed between the first region 1421 and the second region 1422, and the second region 1422 can be disposed between the channel region 1423 and the third region 1424.

[0299] Here, the resistance between the first region 1421 and the second region 1422 can be lower than the resistance of each of the third region 1424 and the channel region 1423.

[0300] That is, the first region 1421 and the second region 1422 of the second active layer 1420 can be conductive regions, and the channel region 1423 and the third region 1424 can be non-conductive regions.

[0301] The first electrode 671 of the transistor Tr can be connected to the first region 1421 of the second active layer 1420, and the second electrode 672 of the transistor Tr can be connected to the second region 1422 of the second active layer 1420.

[0302] When viewed in cross section, the first region 1421 and the second region 1422, i.e., the conductive regions, of the second active layer 1420 can have different lengths. Here, the length of the first region 1421 and the length of the second region 1422 can be the minimum lengths in a direction perpendicular to the stacking direction of the second active layer 1420 and the gate insulating film 630.

[0303] The first region 1421 of the second active layer 1420 can be made conductive in a dry etching for patterning the gate insulating film 630.

[0304] The second region 1422 of the second active layer 1420 can be made conductive by laser processing or the like.

[0305] The gate insulating film 630 provided on the second active layer 1420 can overlap with the whole of one of the first region 1421 and the second region 1422, the whole of the channel region 1423, and the whole of the third region 1424. In addition, the region of the other of the first region 1421 and the second region 1422 of the second active layer 1420 can overlap with only a part of the gate insulating film 630.

[0306] For example, as Figure 14As shown, the gate insulating film 630 may overlap the entirety of each of the second region 1422, the channel region 1423, and the third region 1424 of the second active layer 1420. In addition, the gate insulating film 630 may overlap a part of the first region 1421 of the second active layer 1420.

[0307] A part of the first region 1421 of the second active layer 1420 may overlap the gate electrode 640.

[0308] The width of the region where the gate insulating film 630 overlaps the first region 1421 of the second active layer 1420 may be greater than the width of the region where the gate electrode 640 overlaps the first region 1421 of the second active layer 1420. The width of the region where the gate insulating film 1430 overlaps the first region 1421 of the second active layer 1420 and the width of the region where the gate electrode 1440 overlaps the first region 1421 of the second active layer 1420 may be the minimum length in the direction perpendicular to the stacking direction of the second active layer 1420 and the gate insulating film 630.

[0309] As described above, in the direction in which the first region 1421 extends from the channel region 1423, one end of the gate insulating film 630 is arranged to be more offset than one end of the gate electrode 640. One end of the gate electrode 640 may be separated from the first region 1421 of the second active layer 1420. Therefore, it is possible to prevent a short circuit from occurring due to contact between the gate electrode 640 and the first region 1421 (i.e., the conductive region) due to process errors or the like.

[0310] In addition, the channel region 1423 of the second active layer 1420 may include a part that overlaps the gate electrode 640 and another part that does not overlap the gate electrode 640.

[0311] In addition, the second region 1422 of the second active layer 1420 electrically connected to the second electrode 672 may be located between the non-conductive region, i.e., the channel region 1423 and the third region 1424.

[0312] As described above, the second region 1422 of the active layer 1420 may be provided between the channel region 1423 and the third region 1424 without overlapping the gate electrode 640, so that the length of the channel region 1423 is substantially sufficient.

[0313] That is, the second region 1422 of the second active layer 1420 may be positioned such that the length of the channel region 1423 is not too short.

[0314] Therefore, the mobility of the transistor Tr may not be reduced.

[0315] In addition, in the case where the second electrode 672 of the transistor Tr is connected to a power supply node, the gate insulating film 630 can be provided to entirely overlap both the channel region 1423 and the second region 1422, so that even when a high voltage is applied to the second electrode 672, the channel region 1423 adjacent to the second region 1422 connected to the second electrode 672 of the second active layer 1420 does not deteriorate. In addition, the gate insulating film 630 can be provided to entirely overlap the second region 622.

[0316] Therefore, this can overcome the following problem: the reliability of the transistor Tr is reduced due to the deterioration of the channel region 1423 caused by the reduction in the thickness of the gate insulating film 630 existing between the gate electrode 640 and the channel region 1423.

[0317] Figure 15 is a graph showing the characteristics of the transistor Tr having Figure 14 the structure.

[0318] In Figure 15 it, the x-axis indicates the gate voltage, and the y-axis indicates the drain current.

[0319] In Figure 15 it, in order to measure the characteristics of the transistor Tr having Figure 14 the structure, the drain current is measured by applying a gate voltage in the range of -20V to +20V.

[0320] In the initial state where no voltage is applied to the electrode (such as the second electrode) of the transistor Tr connected to the power supply node and the gate electrode, a driving voltage VDD of 0.1V and a driving voltage of 10V are applied to the transistor Tr having Figure 14 the structure.

[0321] In addition, a voltage of 45V is applied to the electrode connected to the power supply node of the transistor Tr. After applying a voltage of 0V to the gate electrode for 11 hours (after 11 hours of stress), a driving voltage VDD of 0.1V and a driving voltage of 10V are applied to the two transistors.

[0322] Referring to Figure 14 it, it can be understood that in the transistor Tr having Figure 14 the structure, even after driving for 11 hours, the on-current does not decrease and the threshold voltage Vth does not change from the initial value.

[0323] That is, it can be understood that even when a high voltage is applied to the electrode connected to the power supply node, the reliability of the transistor according to the embodiment can be maintained.

[0324] The transistor Tr having Figure 14 the structure shown can be, for example, as Figure 3 andFigure 4 One of the transistors T1, T2, and T3 shown, or may be one of the pull-up transistor Tup and the pull-down transistor Tdown arranged as shown in Figure 5 the control switch circuit CSC.

[0325] Specifically, the transistor Tr according to the embodiment may be the transistor T3 shown as in Figure 3 or Figure 4 among the transistors arranged in the active region. Here, a high voltage (e.g., a driving voltage) may be applied to the transistor Tr.

[0326] In addition, the transistor Tr according to the embodiment may be at least one of the pull-up transistor to which a high voltage (e.g., a clock signal) can be applied among the transistors arranged in the non-active region and the transistors arranged in the control switch circuit.

[0327] The above description has been given to enable any person skilled in the art to implement and use the technical concept of the present invention, and the above description has been provided in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present invention. For illustrative purposes only, the above description and drawings provide examples of the technical concept of the present invention. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present invention. Therefore, the scope of the present invention is not limited to the shown embodiments, but is consistent with the broadest scope consistent with the claims. The protection scope of the present invention should be interpreted based on the appended claims, and all technical concepts within the scope of their equivalents should be interpreted as being included within the scope of the present invention.

Claims

1. An electronic device, comprising: a panel including at least one transistor; as well as a driving circuit for driving the panel, Wherein, the panel comprises: substrate; a first active layer disposed on the substrate, the first active layer comprising a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region; a gate insulating film disposed on the first active layer; a gate electrode of the at least one transistor, which is disposed on the gate insulating film and overlaps a portion of the channel region of the first active layer; an interlayer insulating film disposed on the gate electrode; An insulating film provided between the gate electrode and the interlayer insulating film; and a first electrode and a second electrode of the at least one transistor, the first electrode and the second electrode being provided on the interlayer insulating film and spaced apart from each other, wherein the gate electrode overlaps a portion of at least one of the first region and the second region of the first active layer, and wherein the insulating film contacts a portion of a surface of the first region or the second region of the first active layer, and contacts a portion of a top surface of the gate insulating film overlapping the first region and the second region of the first active layer, wherein the gate insulating film overlaps only a portion of the first region of the first active layer, the entirety of the channel region, and the entirety of the second region, The width of the first region is greater than the width of the second region, The insulating film contains hydrogen, and the first region and the second region are formed by diffusion of hydrogen in the insulating film into the first active layer.

2. The electronic device according to claim 1, wherein: The first active layer is an oxide semiconductor, wherein each of the first region and the second region of the first active layer is a conductive region, and The resistance of each of the first region and the second region is lower than the resistance of the channel region.

3. The electronic device according to claim 1, wherein: The first region is connected to the first electrode, and the second region is connected to the second electrode.

4. The electronic device according to claim 1, wherein: A portion of the first region overlaps with the gate electrode, and The second region does not overlap with the gate electrode.

5. The electronic device according to claim 4, wherein: the first region is connected to the first electrode, wherein the second region is connected to the second electrode, and Wherein, the second electrode is electrically connected to a power supply node of the electronic device.

6. The electronic device according to claim 1, wherein: The channel region of the first active layer is disposed asymmetrically with respect to a center of the gate electrode.

7. The electronic device according to claim 1, wherein: A portion of a channel region of the first active layer overlaps a portion of the gate electrode.

8. The electronic device according to claim 1, wherein: One of the first region and the second region is disposed between the channel region and the first active layer further including a third region spaced apart from the channel region.

9. The electronic device according to claim 8, wherein: The resistance of each of the first region and the second region is lower than the resistance of each of the third region and the channel region.

10. The electronic device according to claim 9, wherein: The first region is connected to the first electrode, and the second region is connected to the second electrode.

11. The electronic device according to claim 8, wherein: The gate insulating film overlaps the entirety of the one of the first region and the second region, the entirety of the channel region, and the entirety of the third region.

12. The electronic device according to claim 11, wherein: A portion of the other of the first region and the second region overlaps with the gate insulating film.

13. The electronic device according to claim 1, further comprising a second active layer disposed below the first active layer, in, The second active layer comprises: a fourth region overlapping the first region of the first active layer; a fifth region overlapping the second region of the first active layer; and a channel region, arranged between the fourth region and the fifth region, Wherein, the channel region of the second active layer overlaps with the channel region of the first active layer.

14. The electronic device according to claim 13, wherein: The fourth region and the fifth region of the second active layer are conductive regions, and The gate electrode overlaps a portion of at least one of the fourth region and the fifth region of the second active layer.

15. The electronic device according to claim 13, wherein: A portion of another channel region of the second active layer overlaps with the gate electrode, and The entirety of another channel region of the second active layer overlaps with the gate insulating film.

16. The electronic device according to claim 1, wherein: The panel includes an active area and an inactive area surrounding the active area, and The transistor is at least one of a driving transistor disposed in the active region, a pull-up transistor disposed in the inactive region, or a transistor disposed in a control switch circuit.

17. A transistor array substrate, comprising: a substrate on which a transistor array consisting of a plurality of transistors is formed; a first active layer disposed on the substrate, the first active layer comprising a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region; a gate insulating film disposed on the first active layer; a gate electrode disposed on the gate insulating film and overlapping a portion of the channel region of the first active layer; an interlayer insulating film disposed on the gate electrode; an insulating film provided between the gate electrode and the interlayer insulating film; as well as a first electrode and a second electrode, the first electrode and the second electrode being provided on the interlayer insulating film and spaced apart from each other, wherein the gate electrode overlaps a portion of at least one of the first region and the second region of the first active layer, and wherein the insulating film contacts a portion of a surface of the first region or the second region of the first active layer, and contacts a portion of a top surface of the gate insulating film overlapping the first region and the second region of the first active layer, wherein the gate insulating film overlaps only a portion of the first region of the first active layer, the entirety of the channel region, and the entirety of the second region, The width of the first region is greater than the width of the second region, The insulating film contains hydrogen, and the first region and the second region are formed by diffusion of hydrogen in the insulating film into the first active layer.

18. A transistor comprising: substrate; a first active layer disposed on the substrate, the first active layer comprising a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region; a gate insulating film disposed on the first active layer; a gate electrode disposed on the gate insulating film and overlapping a portion of the channel region of the first active layer; an interlayer insulating film disposed on the gate electrode; an insulating film provided between the gate electrode and the interlayer insulating film; as well as a source electrode and a drain electrode, the source electrode and the drain electrode being provided on the interlayer insulating film and spaced apart from each other, wherein the gate electrode overlaps a portion of at least one of the first region and the second region of the first active layer, and wherein the source electrode or the drain electrode is connected to the second region of the first active layer, and wherein the insulating film contacts a portion of a surface of the first region or the second region of the first active layer, and contacts a portion of a top surface of the gate insulating film overlapping the first region and the second region of the first active layer, wherein the gate insulating film overlaps only a portion of the first region of the first active layer, the entirety of the channel region, and the entirety of the second region, The width of the first region is greater than the width of the second region, The insulating film contains hydrogen, and the first region and the second region are formed by diffusion of hydrogen in the insulating film into the first active layer.

19. A method of manufacturing a transistor, comprising: sequentially arranging a first active layer material, a gate insulating film material and a gate electrode material on a substrate; Disposing a photoresist including a region having a first thickness and a region having a second thickness on the gate electrode material, wherein the first thickness is thicker than the second thickness; performing dry etching for patterning the gate electrode material and the gate insulating film material using the photoresist as a mask to form a gate electrode and a gate insulating film, a region of the photoresist having a first thickness corresponding to the gate electrode; removing the photoresist; providing an insulating film containing hydrogen on the substrate; diffusing hydrogen contained in the insulating film into the first active layer material to form a first active layer, the first active layer including a first region, a second region spaced apart from the first region, and a channel region disposed between the first region and the second region, the gate electrode overlapping a portion of the channel region of the first active layer; providing an interlayer insulating film on the insulating film; forming a source electrode and a drain electrode on the interlayer insulating film; as well as connecting the source electrode to the first region of the first active layer and connecting the drain electrode to the second region of the first active layer, wherein the gate electrode overlaps a portion of at least one of the first region and the second region of the first active layer, and wherein the insulating film contacts a portion of a surface of the first region or the second region of the first active layer, and contacts a portion of a top surface of the gate insulating film overlapping the first region and the second region of the first active layer, wherein the gate insulating film overlaps only a portion of the first region of the first active layer, the entirety of the channel region, and the entirety of the second region, The width of the first region is greater than the width of the second region, The first region and the second region are formed by diffusing hydrogen in the insulating film into the first active layer material.

Images