Display device

Abstract

The present disclosure relates to a display device, which includes: a substrate, including an island-shaped portion, a first connector extending from the island-shaped portion in a first direction, and a second connector extending from the island-shaped portion in a second direction intersecting the first direction; a display unit, arranged on the island-shaped portion and including at least one thin film transistor and at least one display element connected to the at least one thin film transistor; and connecting wiring, arranged on the first connector and the second connector and connected to the display unit, wherein at least one of the connecting wirings is arranged on the same layer as the semiconductor layer of the at least one thin film transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0170204 filed on December 18, 2019, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments relate to a display device. Background Art

[0004] As display devices for visually displaying visual information have been developed, various thin, lightweight, and low-power display devices have been introduced. Recently, flexible display devices that can be folded or rolled have been developed, and further, stretchable display devices that can be transformed into various forms have been actively studied. Summary of the Invention

[0005] In order to increase the flexibility of a substrate of a deformable display device, the deformable display device includes an island portion on which a display unit is disposed, and a connector extending from the island portion and including a wiring disposed thereon.

[0006] One or more embodiments include a display device capable of minimizing the width of a connector including wiring disposed thereon.

[0007] According to one or more embodiments, a display device includes: a substrate including an island-shaped portion, a first connector extending from the island-shaped portion in a first direction, and a second connector extending from the island-shaped portion in a second direction intersecting the first direction; a display unit, arranged on the island-shaped portion and including at least one thin film transistor and at least one display element connected to the at least one thin film transistor; and connecting wiring, arranged on the first connector and the second connector and connected to the display unit, wherein at least one of the connecting wirings is arranged on the same layer as the semiconductor layer of the at least one thin film transistor.

[0008] In an embodiment, the connection wiring includes a first wiring and a second wiring. The first wiring of the first connector is provided on the same layer as the semiconductor layer, and the second wiring of the first connector is electrically connected to an opposing electrode of the display element.

[0009] In an embodiment, the first wiring and the second wiring overlap each other.

[0010] In an embodiment, a plurality of insulating layers are provided between the first wiring and the second wiring.

[0011] In an embodiment, a first data line, a second data line, and a third data line connected to the display unit are provided on the island portion. The connection wiring of the first connector includes: a middle conductive pattern connected to the first data line provided on the same layer as the middle conductive pattern; a lower conductive pattern provided below the middle conductive pattern and connected to the second data line; and an upper conductive pattern provided above the middle conductive pattern and connected to the third data line.

[0012] In an embodiment, at least one insulating layer is interposed between the upper conductive pattern and the middle conductive pattern.

[0013] In an embodiment, the lower conductive pattern and the first wiring are spaced apart from each other in a direction parallel to an upper surface of the substrate.

[0014] In an embodiment, the lower conductive pattern includes a first conductive pattern and a second conductive pattern, and at least one first insulating layer is interposed between the first conductive pattern and the second conductive pattern.

[0015] At least one second insulating layer is interposed between the second conductive pattern and the intermediate conductive pattern.

[0016] In an embodiment, the first conductive pattern and the second conductive pattern extend to the island portion and are connected to each other through a contact hole penetrating the at least one first insulating layer.

[0017] In an embodiment, the connection wiring is arranged on a third connector extending from the island portion in a direction parallel to the first direction, wherein the third connector includes: the lower conductive pattern, connected to the first data line; the upper conductive pattern, connected to the second data line; and the middle conductive pattern, connected to the third data line.

[0018] In an embodiment, the connecting wiring includes a first wiring and a second wiring. The second wiring of the second connector is electrically connected to the opposite electrode of the display element, and the first wiring of the second connector is provided on the second wiring, wherein the second wiring is provided on the same layer as the semiconductor layer.

[0019] In an embodiment, the first wiring and the second wiring may overlap each other.

[0020] In an embodiment, an insulating layer is interposed between the first wiring and the second wiring.

[0021] In an embodiment, the connection wiring further includes at least one scan line for transmitting a scan signal, and the at least one scan line is provided on the first insulating layer covering the second wiring.

[0022] In an embodiment, the at least one scan line and the second wiring are spaced apart from each other in a direction parallel to the upper surface of the substrate.

[0023] In an embodiment, the at least one scan line includes a first scan line and a second scan line, wherein the first scan line is provided on the first insulating layer covering the second wiring, and the second scan line is provided on the second insulating layer covering the first scan line.

[0024] According to one or more embodiments, a display device includes: a substrate including an island portion, a first connector extending from the island portion in a first direction, and a second connector extending from the island portion in a second direction intersecting the first direction; a display unit, arranged on the island portion and including at least one thin film transistor and at least one display element connected to the at least one thin film transistor; and a connecting wiring, arranged on the first connector and the second connector and connected to the display unit, wherein an inorganic insulating layer is provided on a portion of at least one of the first connector and the second connector, and a lower organic insulating layer is provided on another portion of at least one of the first connector and the second connector.

[0025] According to one or more embodiments, a display device includes: an island-shaped portion, a first connector extending from the island-shaped portion in a first direction, and a third connector spaced apart from the first connector and extending from the island-shaped portion in a direction parallel to the first direction; a display unit, arranged on the island-shaped portion and including thin film transistors and display elements respectively connected to the thin film transistors; data lines, respectively connected to the thin film transistors and arranged on the same layer on the island-shaped portion; and connecting wiring, arranged on the first connector and the third connector and respectively connected to the data lines, wherein the connecting wiring includes an upper conductive pattern, an intermediate conductive pattern, and a lower conductive pattern arranged on different layers.

[0026] In an embodiment, in the first connector, the intermediate conductive pattern is connected to a first data line of the data lines, wherein the first data line is arranged on the same layer as the intermediate conductive pattern, the lower conductive pattern is arranged below the intermediate conductive pattern and connected to a second data line of the data lines, and the upper conductive pattern is arranged on the intermediate conductive pattern and connected to a third data line of the data lines.

[0027] In an embodiment, in the third connector, the middle conductive pattern is connected to the third data line provided on the same layer as the middle conductive pattern, the lower conductive pattern is provided below the middle conductive pattern and connected to the first data line, and the upper conductive pattern is provided on the middle conductive pattern and connected to the second data line.

[0028] In an embodiment, the lower conductive pattern includes a first lower conductive pattern and a second lower conductive pattern, a first interlayer insulating layer is interposed between the first lower conductive pattern and the second lower conductive pattern, and a second interlayer insulating layer is interposed between the second lower conductive pattern and the middle conductive pattern.

[0029] In an embodiment, the connection wiring includes a first wiring and a second wiring.

[0030] The first wiring of the first connector is provided on the same layer as a semiconductor layer of the thin film transistor, and a second wiring of the first connector is connected to an opposing electrode of the display element.

[0031] In an embodiment, the lower conductive pattern includes a first conductive pattern and a second conductive pattern, a first interlayer insulating layer is interposed between the first conductive pattern and the second conductive pattern, and the first conductive pattern and the second conductive pattern extend to the island portion and are connected by a contact hole passing through the first interlayer insulating layer.

[0032] In an embodiment, the island-shaped portion further includes a second connector extending from the island-shaped portion in a second direction intersecting the first direction, and the second connector includes a second wiring connected to the relative electrode of the display element and a first wiring arranged on the second wiring, wherein the second wiring is arranged on the same layer as the semiconductor layer of the thin film transistor.

[0033] In an embodiment, the connection wiring further includes at least one scan line transmitting a scan signal, and the at least one scan line includes a first scan line and a second scan line provided on the first interlayer insulating layer covering the first scan line. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a plan view of a display device according to an embodiment.

[0035] Figure 2 is a plan view of a substrate stretched in a first direction and a second direction.

[0036] Figure 3A and Figure 3B is an equivalent circuit diagram of one pixel included in a display device according to an embodiment.

[0037] Figure 4 is a plan view of a structure on a base unit of a display device according to an embodiment.

[0038] Figure 5 It is along Figure 4 sectional views of the display device taken along lines AA′, BB′, and CC′.

[0039] Figure 6 It is along Figure 4 sectional views of the display device taken along lines DD' and EE'.

[0040] Figure 7 Simulation results of stress distribution when an external force pulling the substrate is applied are shown.

[0041] Figure 8 is a plan view of a structure on a base unit of a display device according to an embodiment.

[0042] Figure 9 is a plan view of some wirings in a structure on a base unit of a display device according to an embodiment.

[0043] Figure 10A yes Figure 9 Magnified view of region X in FIG.

[0044] Figure 10B yes Figure 9 Magnified view of area Y in .

[0045] Figure 10C yes Figure 9 Magnified view of region Z in .

[0046] Figure 11 It is along Figure 8 sectional views of the display device taken along lines FF', GG', and HH'.

[0047] Figure 12A It is along Figure 8 A cross-sectional view of the display device taken along line II'.

[0048] Figure 12B is along the lines of Figure 8 A cross-sectional view of the display device taken along line II' in FIG.

[0049] Figure 13 It is along Figure 8 A cross-sectional view of the display device taken along line JJ' in FIG.

[0050] Figure 14 It is along Figure 8A cross-sectional view of the display device taken along line KK' in FIG.

[0051] Figure 15 is along the lines of Figure 8 sectional views of the display device taken along lines FF', GG', and HH'.

[0052] Figure 16 is along the lines of Figure 8 1-1' is a cross-sectional view of the display device taken along line II'.

[0053] Figure 17 is along the lines of Figure 8 A cross-sectional view of the display device taken along line JJ'.

[0054] Figure 18 is along the lines of Figure 8 sectional view of the display device taken along line K-K'. DETAILED DESCRIPTION

[0055] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the descriptions set forth herein.

[0056] An expression used in the singular encompasses the expression in the plural unless the expression used in the singular has an obviously different meaning in the context.

[0057] It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, region, or element, the layer, region, or element may be directly or indirectly formed on the other layer, region, or element.

[0058] The sizes of elements in the drawings may be exaggerated for convenience of explanation.

[0059] It will also be understood that when a layer, region or component is connected to another part, it can be directly connected to the other part or intervening layers, regions or components may be present.

[0060] Figure 1 is a plan view of a display device according to an embodiment.

[0061] Reference Figure 1 , the display device 1 according to the embodiment includes a substrate 100 and a display unit 200 on the substrate 100 .

[0062] According to an embodiment, the display device 1 displays an image and may be a portable mobile device such as a game console, a multimedia device, or a mini PC. The display device 1 described below may include a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface conduction electron emission display, a quantum dot display, a plasma display, or a cathode ray tube display. Hereinafter, although an organic light-emitting display will be described as an example of the display device 1 according to an embodiment, various other types of display devices as described above may also be used in the embodiment.

[0063] According to an embodiment, the substrate 100 includes one or more of various materials such as glass, metal, or organic materials. In an embodiment, the substrate 100 includes a flexible material. For example, the substrate 100 may include ultra-thin flexible glass or a polymer resin having a thickness of, for example, tens to hundreds of micrometers (μm). When the substrate 100 includes a polymer resin, the polymer resin may be one or more of polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, and cellulose acetate propionate.

[0064] According to an embodiment, the substrate 100 includes a plurality of island portions 101 spaced apart from each other, a plurality of connectors 102 connecting the plurality of island portions 101 , and a plurality of separation regions V between the plurality of connectors 102 penetrating the substrate 100 .

[0065] According to an embodiment, the plurality of island-shaped portions 101 are spaced apart from one another. For example, the plurality of island-shaped portions 101 form a planar lattice pattern that is repeatedly arranged in a first direction, such as the y-direction, and a second direction, such as the x-direction, that intersects the first direction. In an embodiment, the first and second directions are perpendicular to each other. In another embodiment, the first and second directions form an obtuse or acute angle. Hereinafter, for ease of description, the case where the first and second directions are perpendicular to each other will be primarily described in detail.

[0066] According to an embodiment, the display unit 200 is provided on a plurality of island-shaped portions 101 and defines at least one pixel area. The pixel includes at least one thin film transistor and a display element connected to the at least one thin film transistor and emitting light in the visible light band. In an embodiment, a red pixel, a green pixel, and a blue pixel are provided on each of the island-shaped portions 101. In another embodiment, a red pixel, a green pixel, a blue pixel, and a white pixel are provided on each of the island-shaped portions 101. Hereinafter, the case where the red pixel, the green pixel, and the blue pixel are provided on each of the island-shaped portions 101 will be mainly described in detail.

[0067] According to an embodiment, a plurality of connectors 102 connect adjacent island-shaped portions 101 to each other. For example, four connectors 102 are connected to each of the island-shaped portions 101. The four connectors 102 connected to one island-shaped portion 101 extend in different directions, and each of the connectors 102 is connected to the connector 102 of the adjacent island-shaped portion 101. In this case, the connectors 102 connecting adjacent island-shaped portions 101 are provided integrally. For example, one island-shaped portion 101 can be connected to four adjacent island-shaped portions 101 surrounding the one island-shaped portion 101 through four connectors 102, respectively.

[0068] According to the embodiment, the plurality of island-shaped portions 101 and the plurality of connectors 102 are continuously formed of the same material. That is, the plurality of island-shaped portions 101 and the plurality of connectors 102 are integrally provided.

[0069] Hereinafter, according to an embodiment, for the convenience of description, one island portion 101 and the connector 102 connected to the one island portion 101 are referred to as one basic unit U, and the structure of the substrate 100 and the structure of the display device will be described in detail based on the one basic unit U. The basic units U are repeatedly arranged in the first direction and the second direction, and the substrate 100 is provided with the repeatedly arranged basic units U. Two basic units U adjacent to each other are symmetrical to each other. For example, in Figure 1 In , two horizontally adjacent basic units U are horizontally symmetric with respect to a symmetry axis between the basic units U and parallel to the y direction. Similarly, in Figure 1 In the embodiment, two vertically adjacent basic units U are vertically symmetric with respect to a symmetry axis between the basic units U and parallel to the x-direction.

[0070] According to an embodiment, such as Figure 1 Adjacent basic units U of the four basic units U shown in FIG. 2 form a closed curve CL between the adjacent basic units U, and the closed curve CL defines a separation region V, which is an empty space. The closed curve CL is formed by the edges of the plurality of island-shaped portions 101 and the edges of the plurality of connectors 102. Furthermore, the separation region V is bounded by the closed curve CL. Furthermore, a first spacing d1 in the x-direction and a second spacing d2 in the y-direction exist between the island-shaped portions 101 of adjacent basic units U.

[0071] According to an embodiment, each separation region V extends through the upper and lower surfaces of the substrate 100. Each separation region V separates the plurality of island-shaped portions 101, reducing the weight of the substrate 100 and improving the flexibility of the substrate 100. In addition, when an external force such as bending or pulling is applied to the substrate 100, the shape of the separation region V changes. Therefore, the stress generated by the deformation of the substrate 100 is easily reduced, thereby preventing abnormal deformation of the substrate 100 and improving durability. Therefore, when using the display device 1, user convenience is improved, and the display device 1 can be easily incorporated into a wearable device.

[0072] In the embodiment, the angle (θ) between the edge of the island portion 101 in one unit cell U and the edge of each connector 102 is an acute angle. Figure 2 As shown in , the angle θ′ between the edge of the island portion 101 and the edge of each connector 102 increases, where θ′>θ, the area or shape of the separation region V′ changes, and the position of the island portion 101 also changes.

[0073] According to an embodiment, Figure 2 is a plan view of the substrate 100 when stretched in the first and second directions. When the external force is applied, each island portion 101 rotates by a certain angle due to the change in the angle θ', thereby increasing the area of ​​the separation region V' or deforming its shape. Due to the rotation of each island portion 101, the intervals between the island portions 101, such as the first interval d1' and the second interval d2', vary at different locations.

[0074] According to an embodiment, when external force acts to pull the substrate 100 , since stress is concentrated on the connector 102 connected to the edge of the island portion 101 , the closed curve CL around the separation region V bends to prevent damage to the substrate 100 .

[0075] Figure 3A and Figure 3B is an equivalent circuit diagram of one pixel in the display device according to the embodiment.

[0076] Reference Figure 3A According to an embodiment, the pixel PX includes a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC.

[0077] According to an embodiment, the pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. Each pixel PX emits, for example, one of red light, green light, or blue light from an organic light emitting diode OLED. Alternatively, each pixel PX emits, for example, one of red light, green light, blue light, or white light from an organic light emitting diode OLED.

[0078] According to an embodiment, the switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits a data voltage received from the data line DL to the driving thin film transistor T1 based on a switching voltage received from the scan line SL. The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a first power supply voltage ELVDD received from the driving voltage line PL.

[0079] According to an embodiment, the driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and controls a driving current corresponding to the voltage value stored in the storage capacitor Cst and flowing from the driving voltage line PL to the organic light emitting diode OLED. The organic light emitting diode OLED emits light with a brightness corresponding to the driving current. A common electrode, such as a cathode, of the organic light emitting diode OLED receives a second power supply voltage ELVSS from the common voltage line PSL.

[0080] According to an embodiment, Figure 3A The pixel circuit PC is shown to include two thin film transistors and one storage capacitor, but the embodiment is not limited thereto. The number of thin film transistors and the number of storage capacitors may vary depending on the design of the pixel circuit PC. For example, in other embodiments, in addition to the two thin film transistors described above, the pixel circuit PC may further include one or more thin film transistors.

[0081] Reference Figure 3B According to an embodiment, the pixel circuit PC includes a plurality of thin film transistors and storage capacitors, which are connected to the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0082] exist Figure 3B In the embodiment, each pixel PX is connected to the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, the common voltage line PSL, and the driving voltage line PL. However, in another embodiment, at least one of the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, the common voltage line PSL, the driving voltage line PL, etc. is shared by adjacent pixels.

[0083] According to an embodiment, the plurality of thin film transistors include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 and a second initialization thin film transistor T7 .

[0084] According to an embodiment, the signal lines include a scan line SL that transmits a scan signal Sn, a previous scan line SIL that transmits a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL that transmits an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL that transmits a data signal Dm to the driving thin film transistor T1. A driving voltage line PL transmits a first power supply voltage ELVDD to the driving thin film transistor T1, and an initialization voltage line VL transmits an initialization voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0085] According to an embodiment, the driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL via the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2, and converts the driving current I OLED Supplied to the organic light emitting diode OLED.

[0086] According to an embodiment, a switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, a switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to a scan signal Sn received through the scan line SL and performs a switching operation to transmit a data signal Dm received through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0087] According to an embodiment, a compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, a compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and is connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6, and a compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to a scan signal Sn received through the scan line SL and electrically connects the driving gate electrode G1 to the driving drain electrode D1 of the driving thin film transistor T1, thereby connecting the driving thin film transistor T1 in a diode manner.

[0088] According to an embodiment, a first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SIL, a first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and a first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SIL, and initializes the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0089] According to an embodiment, the operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0090] According to an embodiment, the emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0091] According to an embodiment, the operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line EL, so that the first power voltage ELVDD is transmitted to the organic light emitting diode OLED and the driving current I OLED Flow through the organic light emitting diode OLED.

[0092] According to an embodiment, a second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SIL, a second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SIL to initialize the pixel electrode of the organic light emitting diode OLED.

[0093] According to the embodiment, although Figure 3B A case is shown in which the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the same initialization voltage line VL, but in another embodiment, the first initialization thin film transistor T4 is connected to the first initialization voltage line, and the second initialization thin film transistor T7 is connected to the second initialization voltage line.

[0094] In addition, according to the embodiment, although Figure 3B A case is shown in which the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SIL, but in another embodiment, the first initialization thin film transistor T4 is connected to the previous scan line SIL and is driven according to the previous scan signal Sn-1, and the second initialization thin film transistor T7 is connected to a separate signal line such as the next scan line and is driven according to a signal received through the signal line.

[0095] According to an embodiment, the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED is connected to the common voltage line PSL to receive the second power supply voltage ELVSS. Therefore, the organic light emitting diode OLED receives the driving current I from the driving thin film transistor T1. OLED , and emits light to display images.

[0096] According to an embodiment, Figure 3B The compensation thin film transistor T3 and the first initialization thin film transistor T4 are shown to have dual gate electrodes. However, in other embodiments, the compensation thin film transistor T3 and the first initialization thin film transistor T4 have one gate electrode.

[0097] Figure 4 is a plan view of a structure on a base unit of a display device according to an embodiment.

[0098] Reference Figure 4The display device according to the embodiment includes a substrate including an island portion 101 and a connector 102, a display unit 200 on the island portion 101, and connection wirings CW on the connector 102. In this embodiment, at least one of the connection wirings CW is provided on the same layer as the semiconductor layer of the thin film transistor included in the display unit 200.

[0099] According to an embodiment, the display unit 200 includes a pixel region. The pixel includes at least one thin film transistor and a display element connected to the at least one thin film transistor that emits visible light. Light is emitted from the display element through a light-emitting region on a plane. For example, the display unit 200 includes a red light-emitting region, a blue light-emitting region, and a green light-emitting region. The display unit 200 is disposed on the island portion 101 of the substrate. The display unit 200 is completely surrounded by an inorganic contact area ICA, which will be described below.

[0100] According to an embodiment, connection wiring CW is provided on connector 102 of the substrate. Connection wiring CW includes a driving voltage line PL that transmits a first power supply voltage ELVDD to the display unit 200, and a common voltage line PSL that transmits a second power supply voltage ELVSS to the display unit 200. Furthermore, connection wiring CW also includes a lower driving voltage line UPL, which is on a different layer from the driving voltage line PL and connected to the driving voltage line PL via a first contact portion CNP1; and a lower common voltage line UPSL, which is on a different layer from the common voltage line PSL and connected to the common voltage line PSL via a second contact portion CNP2. Furthermore, connection wiring CW also includes signal lines such as data lines and scan lines.

[0101] According to an embodiment, the connector 102 includes a first connector 102a extending from the island portion 101 in a first direction, such as the -y direction, and a second connector 102b extending from the island portion 101 in a second direction, such as the -x direction. In addition, the connector 102 includes a third connector 102c extending from the island portion 101 in a direction parallel to the first direction, and a fourth connector 102d extending from the island portion 101 in a direction parallel to the second direction.

[0102] In this case, according to the embodiment, the connection wiring CW connected to the display unit 200 includes the first to fourth connectors 102 a to 102 d .

[0103] According to an embodiment, the driving voltage line PL extends from the display unit 200 to the second connector 102b and the fourth connector 102d. In addition, the driving voltage line PL is connected to the lower driving voltage line UPL through the first contact portion CNP1 located in the island portion 101. In this case, the lower driving voltage line UPL extends to the first connector 102a and the third connector 102c.

[0104] According to an embodiment, the common voltage line PSL extends from the display unit 200 to the first connector 102a and the third connector 102c. In addition, the common voltage line PSL is connected to the lower common voltage line UPSL through the second contact portion CNP2 located in the island portion 101. The lower common voltage line UPSL extends to the second connector 102b and the fourth connector 102d.

[0105] According to an embodiment, the lower driving voltage line UPL is located in the first central area CA1 or the first adjacent area AA1 of the first connector 102a. The first connector 102a includes the first central area CA1, a first adjacent area AA1 adjacent to the first central area CA1, and a second adjacent area AA2 adjacent to the first central area CA1 and opposite the first adjacent area AA1. The first adjacent area AA1 is located farthest from the center of the island 101 in the area adjacent to the first central area CA1. Furthermore, the second adjacent area AA2 is located closest to the center of the island 101 in the area adjacent to the first central area CA1. In this case, the width LL1 of the first adjacent area AA1 is smaller than the width LL2 of the second adjacent area AA2. The width LL2 of the second adjacent area AA2 is approximately 20% of the width of the first connector 102a. When the first connector 102a is tensioned to prevent the lower driving voltage line UPL located in the first central area CA1 and the first adjacent area AA1 from breaking, the first central area CA1 and the first adjacent area AA1 are subjected to relatively less stress.

[0106] According to an embodiment, the lower drive voltage line UPL extends from the first connector 102a in the island 101 and is connected to the drive voltage line PL in the island 101 via the first contact portion CNP1. The first contact portion CNP1 is formed at various locations in the island 101. The lower drive voltage line UPL extends from the first connector 102a in the first direction and connects to another adjacent island. Since the common voltage line PSL also extends in the first direction in the first connector 102a, the lower drive voltage line UPL overlaps with the common voltage line PSL. In this case, the lower drive voltage line UPL is provided on a different layer from the common voltage line PSL.

[0107] According to an embodiment, the lower common voltage line UPSL is located in the second central area CA2 or the third adjacent area AA3 of the second connector 102b. The second connector 102b includes the second central area CA2, a third adjacent area AA3 adjacent to the second central area CA2, and a fourth adjacent area AA4 adjacent to the second central area CA2 and opposite the third adjacent area AA3. The third adjacent area AA3 is located farthest from the center of the island 101 in the area adjacent to the second central area CA2. Furthermore, the fourth adjacent area AA4 is located closest to the center of the island 101 in the area adjacent to the second central area CA2. In this case, the width LL3 of the third adjacent area AA3 is smaller than the width LL4 of the fourth adjacent area AA4. The width LL4 of the fourth adjacent area AA4 is approximately 20% of the width of the second connector 102b. When the second connector 102b is tensioned to prevent the lower common voltage line UPSL located in the second central area CA2 and the third adjacent area AA3 from breaking, the second central area CA2 and the third adjacent area AA3 are subjected to relatively less stress.

[0108] According to an embodiment, the lower common voltage line UPSL extends from the second connector 102b in the island 101 and is connected to the common voltage line PSL in the island 101 via the second contact portion CNP2. Similar to the first contact portion CNP1 to which the driving voltage line PL and the lower driving voltage line UPL are connected, the second contact portion CNP2 to which the common voltage line PSL and the lower common voltage line UPSL are connected are positioned at various locations in the island 101. The lower common voltage line UPSL extends from the second connector 102b in a second direction, such as the -x direction, and is connected to another adjacent island. Since the driving voltage line PL also extends in the second direction in the second connector 102b, the lower common voltage line UPSL overlaps with the driving voltage line PL. In this case, the lower common voltage line UPSL and the driving voltage line PL are located on different layers.

[0109] exist Figure 4 In the embodiment, the driving voltage line PL is connected to the display unit 200 in the island portion 101, and the common voltage line PSL is also connected to the display unit 200 in the island portion 101. However, in another embodiment, the driving voltage line PL is connected to a conductive pattern located in a layer above or below the layer in which the driving voltage line PL is located, and the conductive pattern is connected to the display unit 200. That is, the driving voltage line PL is connected to the display unit 200 through the conductive pattern located in the other layer. Furthermore, in another embodiment, the common voltage line PSL is connected to the display unit 200 in the island portion 101 through a conductive pattern located in a layer above or below the layer in which the common voltage line PSL is provided through a contact hole.

[0110] According to an embodiment, the connection wiring CW is positioned on a third connector 102c and a fourth connector 102d, respectively, which are similar to the first connector 102a and the second connector 102b. More specifically, the lower drive voltage line UPL and the common voltage line PSL are positioned on the third connector 102c, which is similar to the first connector 102a. The drive voltage line PL and the lower common voltage line UPSL are positioned on the fourth connector 102d, which is similar to the second connector 102b. Because the configuration of the lower drive voltage line UPL and the common voltage line PSL in the third connector 102c is similar to that of the first connector 102a, and the configuration of the drive voltage line PL and the lower common voltage line UPSL in the fourth connector 102d is similar to that of the second connector 102b, a detailed description will be omitted herein.

[0111] In an embodiment, the island portion 101 is completely surrounded by the inorganic contact area ICA. The inorganic contact area ICA is formed by directly contacting at least two layers including inorganic materials and prevents moisture from penetrating into the display element in each pixel. The inorganic contact area ICA extends along the edge of the island portion 101, and the pixels are arranged in the inorganic contact area ICA.

[0112] Thus, according to an embodiment, the driving voltage lines PL and the lower driving voltage lines UPL are respectively arranged on the plurality of connectors 102. The driving voltage lines PL and the lower driving voltage lines UPL have a mesh structure and provide the first power supply voltage ELVDD to the display unit 200. More specifically, the driving voltage lines PL and the lower driving voltage lines UPL are directly or indirectly connected to the driving thin film transistors and provide the first power supply voltage ELVDD. In addition, the common voltage lines PSL and the lower common voltage lines UPSL are respectively arranged on the plurality of connectors 102. The common voltage lines PSL and the lower common voltage lines UPSL have a mesh structure and provide the second power supply voltage ELVSS to the display unit 200. More specifically, the common voltage lines PSL and the lower common voltage lines UPSL are directly or indirectly connected to the opposing electrodes of the display elements and provide the second power supply voltage ELVSS.

[0113] In this embodiment, the lower driving voltage line UPL and the lower common voltage line UPSL are provided on the same layer, and specifically, on the same layer as the semiconductor layer of the thin film transistor. In addition, the lower driving voltage line UPL and the lower common voltage line UPSL include the same material as the semiconductor layer. Figure 5 Describe this in detail.

[0114] Figure 5 It is along Figure 4 A cross-sectional view of the display device taken along line AA', line BB' and line CC'. Figure 5 In, with Figure 4 The same reference numerals used in the drawings denote the same elements, and repeated description will not be given herein.

[0115] Reference Figure 5 According to the embodiment, the pixel circuit PC and the organic light emitting diode OLED as a display element electrically connected to the pixel circuit PC are provided on the island portion 101 of the substrate 100. Figure 3A As described above, the pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The display unit 200 includes a buffer layer 201, a gate insulating layer 203, a first interlayer insulating layer 205, a second interlayer insulating layer 207, a first organic insulating layer 209, a second organic insulating layer 211, a third organic insulating layer 213, and a pixel defining layer 215, which are sequentially stacked and described below. A first contact conductive pattern CM1 is provided on the first organic insulating layer 209, and a second contact conductive pattern CM2 is provided on the second organic insulating layer 211. The organic light emitting diode OLED includes a pixel electrode 221, an intermediate layer 222, and an opposing electrode 223, which are described below.

[0116] According to an embodiment, a buffer layer 201 is provided between the substrate 100 and the pixel circuit PC and prevents impurities from penetrating into the thin film transistor TFT. The buffer layer 201 includes an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide, and may have a single-layer structure or a multi-layer structure including the above-mentioned inorganic insulating material.

[0117] According to an embodiment, the thin film transistor TFT includes a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 5 A top-gate thin film transistor is shown, in which the gate electrode GE is on the semiconductor layer Act and the gate insulating layer 203 is interposed between the gate electrode GE and the semiconductor layer Act. However, according to another embodiment, the thin film transistor TFT is a bottom-gate type.

[0118] According to an embodiment, the semiconductor layer Act includes polycrystalline silicon. Alternatively, in another embodiment, the semiconductor layer Act includes one or more of amorphous silicon, an oxide semiconductor, and an organic semiconductor. The gate electrode GE includes a low-resistance metal. The gate electrode GE includes a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti). The gate electrode GE may have a single-layer structure or a multi-layer structure including the above materials.

[0119] According to an embodiment, the gate insulating layer 203 is provided on the buffer layer 201 between the semiconductor layer Act and the gate electrode GE, and includes an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. The gate insulating layer 203 may have a single-layer structure or a multi-layer structure including the above materials.

[0120] According to an embodiment, the source electrode SE and the drain electrode DE are provided on the same layer, such as the second interlayer insulating layer 207, and include the same material. The source electrode SE and the drain electrode DE include a material having good electrical conductivity. The source electrode SE and the drain electrode DE include a conductive material such as Mo, Al, Cu, or Ti, and can be formed into a single-layer structure or a multilayer structure including the above materials. In an embodiment, the source electrode SE and the drain electrode DE have a multilayer structure including a Ti layer, an Al layer, and a Ti layer (Ti / Al / Ti).

[0121] According to an embodiment, the storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap each other, with the first interlayer insulating layer 205 interposed between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst overlaps the thin film transistor TFT. In this regard, Figure 5 The gate electrode GE of the thin film transistor TFT is shown as the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst does not overlap with the thin film transistor TFT. The storage capacitor Cst is covered by the second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst includes a conductive material such as Mo, Al, Cu, or Ti. The upper electrode CE2 of the storage capacitor Cst can have a single-layer structure or a multi-layer structure including the above materials.

[0122] According to an embodiment, first and second interlayer insulating layers 205 and 207 each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. First and second interlayer insulating layers 205 and 207 may have a single layer structure or a multilayer structure including the above materials.

[0123] According to an embodiment, the second interlayer insulating layer 207 , the thin film transistor TFT, and the storage capacitor Cst are covered by the first organic insulating layer 209 .

[0124] According to an embodiment, the driving voltage line PL is provided on the first organic insulating layer 209. The driving voltage line PL is connected to the intermediate driving voltage line MPL located on the same layer as the source electrode SE and the drain electrode DE via a contact hole penetrating the first organic insulating layer 209. When the driving voltage line PL and the intermediate driving voltage line MPL are provided in a display unit having a plurality of structures connected to each other with an insulating layer interposed between the driving voltage line PL and the intermediate driving voltage line MPL, an increase in resistance in the driving voltage line PL can be prevented, and the width of the driving voltage line PL can be reduced. In another embodiment, one of the driving voltage line PL and the intermediate driving voltage line MPL is included.

[0125] According to an embodiment, a second organic insulating layer 211 and a third organic insulating layer 213 are sequentially disposed on the first organic insulating layer 209. The first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213 each include an organic insulating material. The organic insulating material includes a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, or a mixture thereof.

[0126] According to an embodiment, the pixel electrode 221 is disposed on the second organic insulating layer 211. In some embodiments, an inorganic insulating layer is disposed on the third organic insulating layer 213, and the pixel electrode 221 is disposed on the inorganic insulating layer.

[0127] According to an embodiment, the pixel electrode 221 is electrically connected to the thin film transistor TFT of the pixel circuit PC. In this regard, Figure 5 It is shown that the thin film transistor TFT and the pixel electrode 221 are electrically connected to each other through a first contact conductive pattern CM1 disposed on the first organic insulating layer 209 and a second contact conductive pattern CM2 disposed on the second organic insulating layer 211 .

[0128] According to an embodiment, the pixel electrode 221 includes a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 221 includes a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir or Cr or a compound thereof. In another embodiment, the pixel electrode 221 also includes a film formed of ITO, IZO, ZnO or In2O3 above or below the reflective layer. For example, the pixel electrode 221 can have a three-layer structure in which an ITO layer, a silver (Ag) layer and an ITO layer are stacked.

[0129] According to an embodiment, the pixel defining layer 215 covers an edge of the pixel electrode 221 and includes an opening 215OP exposing a central portion of the pixel electrode 221. The opening 215OP of the pixel electrode 221 defines a light emitting region.

[0130] According to an embodiment, the pixel defining layer 215 includes an organic insulating material such as polyimide. Alternatively, in another embodiment, the pixel defining layer 215 includes an inorganic insulating material. Alternatively, in yet another embodiment, the pixel defining layer 215 includes an organic insulating material and an inorganic insulating material.

[0131] According to an embodiment, an intermediate layer 222 is provided on the pixel defining layer 215. The intermediate layer 222 includes a light-emitting layer 222b. The light-emitting layer 222b includes an organic light-emitting material that emits light of a predetermined color, such as a polymer organic material or a low-molecular-weight organic material. Alternatively, in other embodiments, the light-emitting layer 222b includes an inorganic light-emitting material or may include quantum dots.

[0132] According to an embodiment, the first functional layer 222 a and the second functional layer 222 c are disposed below and above the light emitting layer 222 b , respectively.

[0133] Depending on the embodiment, the first functional layer 222a may include a single layer or multiple layers. For example, in some embodiments, the first functional layer 222a is a single-layer hole transport layer HTL and includes poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). Alternatively, in other embodiments, the first functional layer 222a includes a hole injection layer HIL and a hole transport layer HTL.

[0134] According to an embodiment, the second functional layer 222c may include a single layer or a multilayer.The second functional layer 222c includes one or more of an electron transport layer (ETL) and an electron injection layer (EIL).

[0135] According to an embodiment, Figure 5 The intermediate layer 222 is shown to include both the first functional layer 222a and the second functional layer 222c. However, in another embodiment, the intermediate layer 222 may alternatively include the first functional layer 222a and the second functional layer 222c. For example, the intermediate layer 222 may not include the second functional layer 222c.

[0136] According to an embodiment, the light emitting layer 222 b of the intermediate layer 222 is provided for each pixel, and the first and second functional layers 222 a and 222 c are formed as a single entity to cover a plurality of pixels.

[0137] According to an embodiment, the relative electrode 223 includes a conductive material with a low work function. For example, the relative electrode 223 includes a (semi) transparent layer such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li) or calcium (Ca) or an alloy thereof. Alternatively, in another embodiment, the relative electrode 223 also includes a layer such as ITO, IZO, ZnO or In2O3, which is located on the (semi) transparent layer including the above-mentioned materials. The relative electrode 223 is formed as a single whole to cover a plurality of pixels. For example, the relative electrode 223 completely covers the island portion 101 of the substrate 100. The area of ​​the relative electrode 223 is different from the area of ​​the above-mentioned first functional layer 222a and the second functional layer 222c.

[0138] According to an embodiment, the upper portion of the opposing electrode 223 is covered with an encapsulation layer. The encapsulation layer includes at least one inorganic encapsulation layer, at least one organic encapsulation layer, or a combination thereof. In an embodiment, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially.

[0139] According to an embodiment, each of the first inorganic encapsulation layer and the second inorganic encapsulation layer includes one or more inorganic insulating materials. The inorganic insulating materials include aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride. The organic encapsulation layer includes a polymer-based material. Examples of polymer-based materials include acrylic resin, epoxy resin, polyimide, or polyethylene. Acrylic resins include, for example, polymethyl methacrylate or polyacrylic acid.

[0140] According to an embodiment, the organic encapsulation layer is provided only on the island portion 101 of the substrate 100. Therefore, referring to Figure 1 and Figure 2 The display device 1 is described as including an organic encapsulation layer on the island portion 101 in addition to the rest of the display device 1 .

[0141] In this embodiment, the lower driving voltage line UPL is provided on the same layer as the semiconductor layer Act. The driving voltage line PL is provided on the first organic insulating layer 209 and is covered by the second organic insulating layer 211. The common voltage line PSL is provided on the second organic insulating layer 211, and the third organic insulating layer 213 covers the common voltage line PSL. At least one of the first functional layer 222a, the second functional layer 222c, and the opposite electrode 223 is located on the third organic insulating layer 213. Figure 5 , the counter electrode 223 is shown.

[0142] In this embodiment, the lower driving voltage line UPL is connected to the driving voltage line PL through the first contact portion CNP1. In this case, the first contact portion CNP1 includes a first contact hole CNT1 and a second contact hole CNT2. The first contact hole CNT1 penetrates the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, and the second contact hole CNT2 can be provided in the first organic insulating layer 209.

[0143] In more detail, according to an embodiment, the lower drive voltage line UPL is connected to the drive voltage line PL via a connection conductive pattern MPL1 located on the same layer as the source electrode SE or the drain electrode DE. The connection conductive pattern MPL1 is connected to the lower drive voltage line UPL via a first contact hole CNT1. In this case, the connection conductive pattern MPL1 includes the same material as the source electrode SE or the drain electrode DE. Furthermore, the drive voltage line PL is connected to the connection conductive pattern MPL1 via a second contact hole CNT2. In this case, the first contact hole CNT1 and the second contact hole CNT2 overlap each other. In some embodiments, the first contact hole CNT1 and the second contact hole CNT2 are spaced apart from each other.

[0144] Therefore, according to an embodiment, the first power supply voltage ELVDD (see Figure 3A ) is supplied to the driving voltage line PL through the lower driving voltage line UPL, or is supplied to the lower driving voltage line UPL through the driving voltage line PL.

[0145] In this embodiment, the lower common voltage line UPSL is provided on the same layer as the semiconductor layer Act. The common voltage line PSL is provided on the second organic insulating layer 211 and is covered by the third organic insulating layer 213. In this case, the lower common voltage line UPSL is connected to the common voltage line PSL via a first connection pattern MPSL1 provided on the second interlayer insulating layer 207 and a second connection pattern MPSL2 provided on the first organic insulating layer 209.

[0146] In addition, according to an embodiment, the lower common voltage line UPSL and the common voltage line PSL are connected to each other through a second contact portion CNP2. In this case, the second contact portion CNP2 includes a third contact hole CNT3, a fourth contact hole CNT4, and a fifth contact hole CNT5. The third contact hole CNT3 penetrates the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. The fourth contact hole CNT4 penetrates the first organic insulating layer 209. The fifth contact hole CNT5 penetrates the second organic insulating layer 211.

[0147] In more detail, according to an embodiment, the first connection pattern MPSL1 is connected to the lower common voltage line UPSL through the third contact hole CNT3. The second connection pattern MPSL2 is connected to the first connection pattern MPSL1 through the fourth contact hole CNT4. In addition, the common voltage line PSL is connected to the second connection pattern MPSL2 through the fifth contact hole CNT5. In this case, the first connection pattern MPSL1 includes the same material as the source electrode SE or the drain electrode DE, and the second connection pattern MPSL2 includes the same material as the driving voltage line PL.

[0148] In this case, according to an embodiment, the third contact hole CNT3, the fourth contact hole CNT4, and the fifth contact hole CNT5 overlap each other. In another embodiment, at least some of the third contact hole CNT3, the fourth contact hole CNT4, and the fifth contact hole CNT5 are spaced apart from each other in a direction parallel to the upper surface of the substrate.

[0149] According to an embodiment, the second power supply voltage ELVSS (see Figure 3A ) is supplied to the common voltage line PSL through the lower common voltage line UPSL, or is supplied to the lower common voltage line UPSL through the common voltage line PSL. The common voltage line PSL contacts the opposite electrode 223. In this case, the common voltage line PSL is electrically connected to the opposite electrode 223. Therefore, the second power supply voltage ELVSS (see Figure 3A ) is supplied to the relative electrode 223.

[0150] In this embodiment, the lower drive voltage line UPL and the lower common voltage line UPSL comprise the same material as the semiconductor layer Act. In this case, after forming a preliminary semiconductor pattern, the preliminary semiconductor pattern is doped to form the lower drive voltage line UPL and the lower common voltage line UPSL. When forming the semiconductor layer Act, the lower electrode CE1 is used as a mask to dope both sides of a region overlapping with the lower electrode CE1, hereinafter referred to as the channel region. However, since the lower electrode CE1 is not positioned over the lower drive voltage line UPL and the lower common voltage line UPSL, the lower drive voltage line UPL and the lower common voltage line UPSL are fully doped and serve as connecting wiring.

[0151] Figure 6 It is along Figure 4 A cross-sectional view of the display device taken along line DD' and line EE'. Figure 6 In, with Figure 5 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted.

[0152] Reference Figure 6According to an embodiment, the lower driving voltage line UPL is disposed on the first connector 102a, and the common voltage line PSL is disposed on the lower driving voltage line UPL. The lower driving voltage line UPL is disposed on the same layer as the semiconductor layer of the thin film transistor.

[0153] In this embodiment, the lower driving voltage line UPL and the common voltage line PSL overlap each other. In more detail, the lower driving voltage line UPL and the common voltage line PSL overlap each other to be substantially aligned with each other. Therefore, the width of the first connector 102a can be minimized.

[0154] In this embodiment, the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 are disposed on the first connector 102a. In this case, the lower driving voltage line UPL is interposed between the buffer layer 201 and the gate insulating layer 203. In some embodiments, at least some of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 may be omitted. Hereinafter, an embodiment in which all of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 are disposed on the first connector 102a will be primarily described in detail.

[0155] In this embodiment, an inorganic insulating layer is provided on a portion of the first connector 102a, namely, the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, and a lower organic insulating layer 208 is provided on another portion of the first connector 102a. In other words, the width W1 of the inorganic insulating layer provided on the first connector 102a is smaller than the width W2 of the first connector 102a.

[0156] In this case, according to an embodiment, the edges of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 are covered by the lower organic insulating layer 208. For example, the lower organic insulating layer 208 covers the edges of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, which are aligned with each other and form an oblique angle with the upper surfaces of the first connector 102a and the second connector 102b. Furthermore, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 have a step relative to the upper surface of the first connector 102a overlapping with the lower driving voltage line UPL and the upper surface of the second connector 102b overlapping with the lower common voltage line UPSL. The lower organic insulating layer 208 relieves stress at the edge of the first connector 102a, for example, near the edge of the first connector 102a. The lower organic insulating layer 208 includes an organic insulating material such as polyimide.

[0157] According to an embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 cover the second interlayer insulating layer 207 and the lower organic insulating layer 208. A common voltage line PSL is provided on the second organic insulating layer 211, and a third organic insulating layer 213 covers the common voltage line PSL. An opposing electrode 223 is provided on the third organic insulating layer 213.

[0158] In this embodiment, the lower common voltage line UPSL is provided on the second connector 102b, and the driving voltage line PL is provided on the lower common voltage line UPSL. In this case, the lower common voltage line UPSL is located on the same layer as the semiconductor layer of the thin film transistor. Specifically, the lower common voltage line UPSL is located on the same layer as the lower driving voltage line UPL.

[0159] In this embodiment, the lower common voltage line UPSL and the driving voltage line PL overlap each other. More specifically, the lower common voltage line UPSL and the driving voltage line PL overlap each other to be substantially aligned with each other. Therefore, the width of the second connector 102b can be minimized.

[0160] In this embodiment, similar to the configuration on the first connector 102a, the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, the second interlayer insulating layer 207, and the lower organic insulating layer 208 are disposed on the second connector 102b. In this case, the lower common voltage line UPSL is interposed between the buffer layer 201 and the gate insulating layer 203.

[0161] According to an embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 are provided on the second connector 102b and cover the second interlayer insulating layer 207 and the lower organic insulating layer 208. In this case, the driving voltage line PL is provided on the first organic insulating layer 209. More specifically, the driving voltage line PL is interposed between the first organic insulating layer 209 and the second organic insulating layer 211. Therefore, the driving voltage line PL and the common voltage line PSL are positioned on different layers.

[0162] In this embodiment, the lower drive voltage line UPL and the lower common voltage line UPSL are located on the same layer as the semiconductor layer of the thin film transistor. In this case, wiring other than the drive voltage line PL can be provided between the first organic insulating layer 209 and the second organic insulating layer 211 on the first connector 102a. Furthermore, wiring other than the common voltage line PSL can be provided between the second organic insulating layer 211 and the third organic insulating layer 213 on the second connector 102b. Therefore, even if the display device requires additional connection wiring, the increase in the width of the first connector 102a and the width of the second connector 102b can be minimized. Consequently, the area of ​​the island portion can be increased, and the resolution of the display device can be improved.

[0163] Figure 7 Simulation results of stress distribution when an external force pulling the substrate is applied are shown.

[0164] Reference Figure 7 According to an embodiment, when an external force pulls the substrate, the island portion of the substrate is subjected to relatively small stress, while relatively large stress acts on the connector extending from the island portion of the substrate.

[0165] Specifically, according to the embodiment, referring to Figure 4 and Figure 7 , the first connector 102a extending in the first direction includes a first central area CA1, a first adjacent area AA1 farthest from the center of the island 101, and a second adjacent area AA2 closest to the center of the island 101. In this case, it can be seen from the simulation results that more stress acts on the second adjacent area AA2 of the first connector 102a than on the first central area CA1 or the first adjacent area AA1.

[0166] Therefore, according to an embodiment, when the lower driving voltage line UPL or the lower common voltage line UPSL is disposed on the first central area CA1 or the first adjacent area AA1 of the first connector 102a, cracks or the like due to stress may be prevented from occurring.

[0167] Figure 8is a plan view of a structure on a base unit of a display device according to an embodiment. Figure 9 is a plan view of some wirings in a structure on a base unit of a display device according to an embodiment. Figure 10A yes Figure 9 A magnified view of region X in Figure 10B yes Figure 9 A magnified view of region Y in FIG, and Figure 10C yes Figure 9 Magnified view of region Z in .

[0168] exist Figure 8 、 Figure 9 and Figures 10A to 10C In, with Figure 4 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0169] Reference Figure 8 and Figure 9 The display device according to the embodiment includes a substrate 100 having an island portion 101 and a connector 102, display units 200a and 200b located on the island portion 101, and connection wirings CW located on the connector 102. In this embodiment, at least one of the connection wirings CW is positioned on the same layer as the semiconductor layer of the thin film transistors included in the display units 200a and 200b.

[0170] According to an embodiment, the display units 200a and 200b include a first display unit 200a and a second display unit 200b. The first display unit 200a and the second display unit 200b respectively define a pixel region. The pixel region includes at least one thin film transistor and a display element emitting visible light connected to the at least one thin film transistor.

[0171] According to an embodiment, the substrate 100 includes a first island portion 1011 and a second island portion 1012 adjacent to the first island portion 1011. The first display unit 200a is disposed on the first island portion 1011 of the substrate 100, and the second display unit 200b is disposed on the second island portion 1012.

[0172] According to an embodiment, the substrate 100 includes first to fourth connectors 1021a to 1021d extending from the first island portion 1011. In this case, connection wirings CW connected to the first display unit 200a are provided on the first to fourth connectors 1021a to 1021d of the first island portion 1011.

[0173] In addition, according to an embodiment, the substrate 100 includes first to fourth connectors 1022a to 1022d extending from the second island portion 1012. In this case, connection wirings CW connected to the second display unit 200b are provided on the first to fourth connectors 1022a to 1022d of the second island portion 1012.

[0174] In this embodiment, the first connector 1021a of the first island 1011 and the third connector 1022c of the second island 1012 extend to connect to each other. In this case, the first connector 1021a of the first island 1011 and the third connector 1022c of the second island 1012 are provided integrally. Therefore, the connection wiring in the first connector 1021a extends in the first direction to the third connector 1022c of the second island 1012. In addition, the connection wiring extends to the second island 1012 and is connected to the second display unit 200b. As described above, the wiring positioned on the connector 1021 of the first island 1011 extends to connect to the adjacent island.

[0175] According to an embodiment, since the first island portion 1011 and the connector 1021 of the first island portion 1011 are similar to the second island portion 1012 and the connector 1022 of the second island portion 1012, the first island portion 1011 and the connector 1021 of the first island portion 1011 will be mainly described in detail below.

[0176] According to an embodiment, the first connector 1021a of the first island portion 1011 and the third connector 1021c of the first island portion 1011 respectively include a lower driving voltage line UPL, a common voltage line PSL, and conductive patterns MDL, UDL, and DDL connected to the data line DL. The lower driving voltage line UPL, the common voltage line PSL, and the conductive patterns MDL, UDL, and DDL extend in the first direction.

[0177] In this embodiment, the first island portion 1011 includes data lines DL connected to the thin film transistors of the first display unit 200a. In this case, the data lines DL include a first data line DL1, a second data line DL2, and a third data line DL3 that are spaced apart from each other. In this embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 are positioned on the same layer. In this embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 transmit data signals to red pixels, green pixels, and blue pixels, respectively.

[0178] According to an embodiment, at least one of the first data line DL1 , the second data line DL2 , and the third data line DL3 is connected to a conductive pattern on another layer on the connector 102 .

[0179] In more detail, according to the embodiment, referring to Figure 9 and Figure 10A In the first connector 1021a of the first island portion 1011, the connection wiring CW includes a first middle conductive pattern MDL1, a second lower conductive pattern DDL2 located below the first middle conductive pattern MDL1, and a third upper conductive pattern UDL3 located above the first middle conductive pattern MDL1, wherein the first middle conductive pattern MDL1, the second lower conductive pattern DDL2, and the third upper conductive pattern UDL3 are respectively connected to the first data line DL1, the second data line DL2, and the third data line DL3.

[0180] According to an embodiment, the first middle conductive pattern MDL1 is provided on the same layer as the first data line DL1. In this case, the first middle conductive pattern MDL1 is formed integrally with the first data line DL1. The second lower conductive pattern DDL2 is connected to the second data line DL2 in the first island portion 1011. More specifically, the second lower conductive pattern DDL2 is connected to the second data line DL2 via a contact hole penetrating the insulating layer. The third upper conductive pattern UDL3 is connected to the third data line DL3 in the first island portion 1011. More specifically, the third upper conductive pattern UDL3 is connected to the third data line DL3 via a contact hole penetrating the first organic insulating layer 209.

[0181] In this embodiment, in the first connector 1021a of the first island 1011, the width of the first middle conductive pattern MDL1 is greater than the width of the first data line DL1. In this case, the first middle conductive pattern MDL1 overlaps with the second lower conductive pattern DDL2 and the third upper conductive pattern UDL3. In the first connector 1021a of the first island 1011, the width of the third upper conductive pattern UDL3 is greater than the width of the third data line DL3. In this case, the third upper conductive pattern UDL3 overlaps with the first middle conductive pattern MDL1 and the second lower conductive pattern DDL2.

[0182] Reference Figure 9 and Figure 10B According to an embodiment, in the third connector 1021c of the first island portion 1011, the connection wiring CW includes a first lower conductive pattern DDL1, a second upper conductive pattern UDL2 located above the first lower conductive pattern DDL1, and a third middle conductive pattern MDL3 interposed between the first lower conductive pattern DDL1 and the second upper conductive pattern UDL2. The first lower conductive pattern DDL1, the second upper conductive pattern UDL2, and the third middle conductive pattern MDL3 are connected to the first data line DL1, the second data line DL2, and the third data line DL3, respectively.

[0183] According to an embodiment, the first lower conductive pattern DDL1 is connected to the first data line DL1 in the first island portion 1011. More specifically, the first lower conductive pattern DDL1 is connected to the first data line DL1 via a contact hole penetrating the insulating layer. The second upper conductive pattern UDL2 is connected to the second data line DL2 in the first island portion 1011. More specifically, the second upper conductive pattern UDL2 is connected to the second data line DL2 via a contact hole penetrating the first organic insulating layer 209. The third intermediate conductive pattern MDL3 is provided on the same layer as the third data line DL3. In this case, the third intermediate conductive pattern MDL3 is formed integrally with the third data line DL3.

[0184] In this embodiment, in the third connector 1021c of the first island 1011, the width of the second upper conductive pattern UDL2 is greater than the width of the second data line DL2. In this case, the second upper conductive pattern UDL2 overlaps with the first lower conductive pattern DDL1 and the third intermediate conductive pattern MDL3. In the third connector 1021c of the first island 1011, the width of the third intermediate conductive pattern MDL3 is greater than the width of the third data line DL3. The third intermediate conductive pattern MDL3 overlaps with the first lower conductive pattern DDL1 and the second upper conductive pattern UDL2.

[0185] Reference Figure 9 and Figure 10C According to an embodiment, in the first connector 1022a of the second island portion 1012, the connection wiring CW includes a first upper conductive pattern UDL1, a second middle conductive pattern MDL2 located below the first upper conductive pattern UDL1, and a third lower conductive pattern DDL3 located below the second middle conductive pattern MDL2. The first upper conductive pattern UDL1, the second middle conductive pattern MDL2, and the third lower conductive pattern DDL3 are connected to the first data line DL1, the second data line DL2, and the third data line DL3, respectively.

[0186] According to an embodiment, the first upper conductive pattern UDL1 is connected to the first data line DL1 in the second island portion 1012. More specifically, the first upper conductive pattern UDL1 is connected to the first data line DL1 via a contact hole penetrating the first organic insulating layer 209. The second intermediate conductive pattern MDL2 is positioned on the same layer as the second data line DL2. In this case, the second intermediate conductive pattern MDL2 is integrally formed with the second data line DL2. The third lower conductive pattern DDL3 is connected to the third data line DL3 in the second island portion 1012. In this case, the third lower conductive pattern DDL3 is connected to the third data line DL3 via a contact hole penetrating the insulating layer.

[0187] In this embodiment, in the first connector 1022a of the second island-shaped portion 1012, the width of the first upper conductive pattern UDL1 is greater than the width of the first data line DL1. In this case, the first upper conductive pattern UDL1 overlaps with the second middle conductive pattern MDL2 and the third lower conductive pattern DDL3. In the first connector 1022a of the second island-shaped portion 1012, the width of the second middle conductive pattern MDL2 is greater than the width of the second data line DL2. In this case, the second middle conductive pattern MDL2 overlaps with the first upper conductive pattern UDL1 and the third lower conductive pattern DDL3.

[0188] As described above, according to an embodiment, the width of at least a portion of the conductive patterns MDL, UDL, and DDL is greater than the width of the data lines DL, making it possible to reduce the resistance of the conductive patterns MDL, UDL, and DDL in the connector 102. When the data lines DL are located on the same layer, as the width of the data lines DL increases, the width of the connector 102 increases to reduce the resistance of each of the data lines DL. In this embodiment, since the conductive patterns MDL, UDL, and DDL are located on different layers, the resistance of the wiring can be reduced without increasing the width of the connector 102.

[0189] Furthermore, according to an embodiment, the specific conductive patterns MDL, UDL, and DDL connected to the data lines DL are periodically changed as described above to maintain a substantially uniform resistance value in each data line DL. For example, the first data line DL1 is connected to the first middle conductive pattern MDL1 at the first connector 1021a of the first island 1011, to the first lower conductive pattern DDL1 at the third connector 1021c of the first island 1011, and to the first upper conductive pattern UDL1 at the first connector 1022a of the second island 1012. In this way, the specific conductive patterns connected to the second and third data lines DL2 and DL3 are also periodically changed, allowing the resistance values ​​of the wiring serving as the data lines DL to remain substantially uniform. This prevents the occurrence of an afterimage effect only on display elements that emit light based on a specific data signal.

[0190] Refer again Figure 8 According to an embodiment, the lower common voltage line UPSL, the driving voltage line PL, the scan line SL, the previous scan line SIL, the emission control line EL, and the initialization voltage line VL are provided on the second connector 1021b and the fourth connector 1021d of the first island portion 1011.

[0191] According to an embodiment, the lower common voltage line UPSL extends to the first island portion 1011 and is connected to the common voltage line PSL. The common voltage line PSL, the driving voltage line PL, the scan line SL, the previous scan line SIL, the emission control line EL, and the initialization voltage line VL extend to the first island portion 1011 and are connected to the first display unit 200a.

[0192] In the present embodiment, the lower common voltage line UPSL is spaced apart from the scan line SL and the previous scan line SIL in a direction parallel to the upper surface of the substrate 100 .

[0193] exist Figure 8 According to an embodiment, the lower common voltage line UPSL, the emission control line EL, and the initialization voltage line VL are spaced apart from each other. However, in some embodiments, one of the lower common voltage line UPSL, the emission control line EL, and the initialization voltage line VL overlaps with the other lines.

[0194] Figure 11 It is along Figure 8 A cross-sectional view of the display device taken along line FF', line GG' and line HH'. Figure 11 In, with Figure 8 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0195] Reference Figure 11 According to an embodiment, the common voltage line PSL is disposed on the lower drive voltage line UPL, and the lower drive voltage line UPL is disposed on the same layer as the semiconductor layer. In addition, the data line DL is disposed on the same layer as the island portion. The data line DL is connected to the upper conductive pattern UDL, the middle conductive pattern MDL, and the lower conductive pattern DDL, respectively. The upper conductive pattern UDL, the middle conductive pattern MDL, and the lower conductive pattern DDL are disposed on different layers.

[0196] In this embodiment, the lower drive voltage line UPL is disposed on the buffer layer 201 covering the substrate 100. The lower drive voltage line UPL is covered by the gate insulating layer 203. The lower conductive pattern DDL is disposed on the gate insulating layer 203 and covered by the first interlayer insulating layer 205. In this case, the lower drive voltage line UPL and the lower conductive pattern DDL are spaced apart from each other in a direction parallel to the upper surface of the substrate 100. For example, the lower drive voltage line UPL and the first lower conductive pattern DDL1 are spaced apart from each other in a direction parallel to the upper surface of the substrate 100. Therefore, even if the lower drive voltage line UPL includes the same material as the semiconductor layer, the lower drive voltage line UPL can be used as a connection wiring by being fully doped.

[0197] According to an embodiment, the data lines DL are connected to the lower conductive patterns DDL through contact holes penetrating the insulating layers. For example, the first data line DL1 is connected to the first lower conductive pattern DDL1 through a contact hole penetrating the first interlayer insulating layer 205 and the second interlayer insulating layer 207. The lower conductive pattern DDL includes the same material as the gate electrode GE.

[0198] According to an embodiment, the data lines DL are disposed on the second interlayer insulating layer 207 covering the first interlayer insulating layer 205. In this case, the data lines DL are spaced apart from each other. In this case, the data lines DL are each formed integrally with the intermediate conductive pattern MDL. For example, the first data line DL1 is formed integrally with the first intermediate conductive pattern MDL1. The intermediate conductive pattern MDL includes the same material as the source electrode SE or the drain electrode DE.

[0199] According to an embodiment, the data lines DL are connected to the upper conductive patterns UDL through contact holes penetrating the first organic insulating layer 209. For example, the first data line DL1 is connected to the first upper conductive pattern UDL1 through a contact hole penetrating the first organic insulating layer 209. The upper conductive pattern UDL includes the same material as the driving voltage line PL.

[0200] According to an embodiment, the second organic insulating layer 211 covers the upper conductive pattern UDL, and the common voltage line PSL is disposed on the second organic insulating layer 211. Figure 11 In the embodiment, the common voltage line PSL does not overlap with the lower driving voltage line UPL, the lower conductive pattern DDL, the middle conductive pattern MDL, or the upper conductive pattern UDL. However, in some embodiments, the common voltage line PSL overlaps with at least one of the lower driving voltage line UPL, the lower conductive pattern DDL, the middle conductive pattern MDL, and the upper conductive pattern UDL.

[0201] Figure 12A It is along Figure 8 A cross-sectional view of the display device taken along line II' in FIG. Figure 12A In, with Figure 6 and Figure 8 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0202] Reference Figure 12A According to an embodiment, the substrate 100 includes a first connector 1021a of the first island portion extending in a first direction from the first island portion, and the first connector 1021a of the first island portion includes a connection wiring CW connected to the first display unit of the first island portion. In this case, the lower driving voltage line UPL of the connection wiring CW is provided on the same layer as the semiconductor layer of the thin film transistor in the first display unit.

[0203] According to an embodiment, the lower driving voltage line UPL is disposed on the buffer layer 201 at the first connector 1021 a of the first island portion, and the gate insulating layer 203 is disposed on the lower driving voltage line UPL and the buffer layer 201 .

[0204] According to an embodiment, the second lower conductive pattern DDL2 is disposed on the gate insulating layer 203, and in one embodiment, the second lower conductive pattern DDL2 is spaced apart from the lower driving voltage line UPL in a direction parallel to the upper surface of the substrate 100. In this case, the second lower conductive pattern DDL2 corresponds to the center of the first middle conductive pattern MDL1 or the third upper conductive pattern UDL3.

[0205] According to an embodiment, the first interlayer insulating layer 205 and the second interlayer insulating layer 207 sequentially cover the second lower conductive pattern DDL2 and the gate insulating layer 203 , and the first middle conductive pattern MDL1 is disposed on the second interlayer insulating layer 207 .

[0206] According to an embodiment, the first organic insulating layer 209 covers the first middle conductive pattern MDL1 and the second interlayer insulating layer 207, and the third upper conductive pattern UDL3 is provided on the first organic insulating layer 209. The second organic insulating layer 211 covers the third upper conductive pattern UDL3 and the first organic insulating layer 209, and the common voltage line PSL is provided on the second organic insulating layer 211. In addition, the third organic insulating layer 213 covers the common voltage line PSL and the second organic insulating layer 211, and the opposite electrode 223 is provided on the third organic insulating layer 213.

[0207] In this embodiment, one of the second lower conductive pattern DDL2 , the first middle conductive pattern MDL1 , and the third upper conductive pattern UDL3 may overlap with the other of the second lower conductive pattern DDL2 , the first middle conductive pattern MDL1 , or the third upper conductive pattern UDL3 .

[0208] Figure 12B is along the lines of Figure 8 A cross-sectional view of the display device taken along line II' in FIG. Figure 12B In, with Figure 12A The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0209] Reference Figure 12BAccording to an embodiment, the center of the first middle conductive pattern MDL1 corresponds to the center of the lower driving voltage line UPL and the center of the second lower conductive pattern DDL2. In addition, the common voltage line PSL overlaps the third upper conductive pattern UDL3. In an embodiment, the width of the common voltage line PSL is greater than the width of the second lower conductive pattern DDL2. In addition, Figure 12B In the embodiment, the width of the lower driving voltage line UPL is smaller than the width of the common voltage line PSL. However, in some embodiments, the width of the lower driving voltage line UPL is equal to the width of the common voltage line PSL.

[0210] In this embodiment, the lower driving voltage line UPL, the first intermediate conductive pattern MDL1, the second lower conductive pattern DDL2, the third upper conductive pattern UDL3, and the common voltage line PSL are positioned on different layers, and at least some of the lower driving voltage line UPL, the first intermediate conductive pattern MDL1, the second lower conductive pattern DDL2, the third upper conductive pattern UDL3, and the common voltage line PSL overlap with each other. Therefore, the width of the first connector 1021a of the first island portion can be minimized.

[0211] Figure 13 It is along Figure 8 A cross-sectional view of the display device taken along line J-J'. Figure 13 In, with Figure 8 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0212] Reference Figure 13 According to an embodiment, the substrate 100 includes a first island portion 1011 and a second connector 1021 b of the first island portion 1011 extending from the first island portion 1011 in a second direction (−x direction), and the second connector 1021 b of the first island portion 1011 includes a connection wiring of the first display unit 200 a connected to the first island portion 1011.

[0213] In the present embodiment, the previous scan line SIL is disposed on the gate insulating layer 203 , and the first interlayer insulating layer 205 covers the previous scan line SIL.

[0214] According to an embodiment, the second interlayer insulating layer 207 and the first organic insulating layer 209 are disposed on the first interlayer insulating layer 205, and the driving voltage line PL is disposed on the first organic insulating layer 209. In this case, the previous scan line SIL and the driving voltage line PL overlap each other.

[0215] According to an embodiment, the second organic insulating layer 211 , the third organic insulating layer 213 , and the opposite electrode 223 are sequentially disposed on the driving voltage line PL.

[0216] Figure 14 It is along Figure 8 A cross-sectional view of the display device taken along line K-K' in FIG. Figure 14 In, with Figure 6 and Figure 8 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0217] Reference Figure 14 According to an embodiment, the substrate 100 includes a first island portion 1011 and a second connector 1021 b of the first island portion 1011 extending in the second direction from the first island portion 1011, and the second connector 1021 b of the first island portion 1011 includes a connection wiring CW of the first display unit 200a connected to the first island portion 1011. In this case, the lower common voltage line UPSL of the connection wiring CW is provided on the same layer as the semiconductor layer of the thin film transistor in the first display unit 200a.

[0218] According to an embodiment, the lower common voltage line UPSL is disposed on the buffer layer 201 at the second connector 1021 b of the first island portion 1011 , and the gate insulating layer 203 is disposed on the lower common voltage line UPSL.

[0219] According to an embodiment, the scan line SL and the previous scan line SIL are disposed on the gate insulating layer 203. In this embodiment, the lower common voltage line UPSL is spaced apart from the scan line SL and the previous scan line SIL in a direction parallel to the upper surface of the substrate 100, and the scan line SL is spaced apart from the previous scan line SIL in a direction parallel to the upper surface of the substrate 100. Therefore, even if the lower common voltage line UPSL includes the same material as that of the semiconductor layer, the lower common voltage line UPSL can be fully doped and used as a connection wiring.

[0220] According to an embodiment, a first interlayer insulating layer 205 and a second interlayer insulating layer 207 are provided on the gate insulating layer 203, the scan line SL, and the previous scan line SIL. The emission control line EL is provided on the second interlayer insulating layer 207. In some embodiments, another wiring may be further provided on the second interlayer insulating layer 207.

[0221] According to an embodiment, the first organic insulating layer 209 covers the emission control line EL and the second interlayer insulating layer 207, and the driving voltage line PL is disposed on the first organic insulating layer 209. The driving voltage line PL overlaps at least some of the lower common voltage line UPSL, the scan line SL, the previous scan line SIL, and the emission control line EL.

[0222] According to an embodiment, the second organic insulating layer 211 covers the driving voltage line PL and the first organic insulating layer 209, and the initialization voltage line VL is provided on the second organic insulating layer 211. In some embodiments, the initialization voltage line VL includes a first initialization voltage line and a second initialization voltage line spaced apart from the first initialization voltage line. In this case, the first initialization voltage line and the second initialization voltage line are provided on the second organic insulating layer 211.

[0223] According to an embodiment, the third organic insulating layer 213 covers the initialization voltage line VL and the second organic insulating layer 211 , and the opposite electrode 223 is disposed on the third organic insulating layer 213 .

[0224] As described above, according to the embodiment, since the connection wirings CW overlap each other in the direction perpendicular to the upper surface of the substrate 100 , the width of the second connector 1021 b of the first island portion 1011 may be minimized.

[0225] Figure 15 is along the lines of Figure 8 A cross-sectional view of the display device taken along line FF', line GG' and line HH'. Figure 15 In, with Figure 8 and Figure 11 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0226] Reference Figure 15 According to an embodiment, the common voltage line PSL is on the lower driving voltage line UPL, which is provided on the same layer as the semiconductor layer. In addition, the data line DL is provided on the same layer as the island portion 101. The data line DL is connected to the upper conductive pattern UDL, the middle conductive pattern MDL, and the lower conductive pattern DDL, respectively. The upper conductive pattern UDL, the middle conductive pattern MDL, and the lower conductive pattern DDL are provided on different layers.

[0227] In this embodiment, the lower conductive pattern DDL includes a first conductive pattern DDLa and a second conductive pattern DDLb. The first conductive pattern DDLa includes the same material as the gate electrode GE. The second conductive pattern DDLb includes the same material as the upper electrode CE2.

[0228] According to an embodiment, a first conductive pattern DDLa is disposed on the gate insulating layer 203, and a second conductive pattern DDLb is disposed on the first interlayer insulating layer 205. The first conductive pattern DDLa and the second conductive pattern DDLb are connected to each other through a contact hole penetrating the first interlayer insulating layer 205. The second conductive pattern DDLb and the data line DL are connected to each other through a contact hole penetrating the second interlayer insulating layer 207.

[0229] For example, according to an embodiment, the first lower conductive pattern DDL1 includes a first conductive pattern DDL1a and a second conductive pattern DDL1b. The first conductive pattern DDL1a is connected to the second conductive pattern DDL1b via a contact hole penetrating the first interlayer insulating layer 205. The second conductive pattern DDL1b is connected to the first data line DL1 via a contact hole penetrating the second interlayer insulating layer 207.

[0230] As another example, according to an embodiment, the second lower conductive pattern DDL2 includes a first conductive pattern DDL2a and a second conductive pattern DDL2b. The first conductive pattern DDL2a is connected to the second conductive pattern DDL2b via a contact hole penetrating the first interlayer insulating layer 205. The second conductive pattern DDL2b is connected to the second data line DL2 via a contact hole penetrating the second interlayer insulating layer 207.

[0231] As another example, the third lower conductive pattern DDL3 includes a first conductive pattern DDL3a and a second conductive pattern DDL3b. The first conductive pattern DDL3a is connected to the second conductive pattern DDL3b via a contact hole penetrating the first interlayer insulating layer 205. The second conductive pattern DDL3b is connected to the third data line DL3 via a contact hole penetrating the second interlayer insulating layer 207.

[0232] Therefore, according to the embodiment, the resistance of the lower conductive pattern DDL may be reduced, and an afterimage that may occur due to high resistance may be prevented.

[0233] Figure 16 is along the lines of Figure 8 A cross-sectional view of the display device taken along line II'. Figure 16 In, with Figure 12A The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0234] As another example, according to an embodiment, the second lower conductive pattern DDL2 includes a first conductive pattern DDL2a and a second conductive pattern DDL2b. In this case, the first conductive pattern DDL2a is disposed on the gate insulating layer 203 and is spaced apart from the lower driving voltage line UPL in a direction parallel to the upper surface of the substrate 100.

[0235] In this embodiment, the second conductive pattern DDL2b is disposed on the first interlayer insulating layer 205. In this case, at least a portion of the second conductive pattern DDL2b overlaps with the lower driving voltage line UPL disposed on the buffer layer 201. Therefore, the width of the first connector 1021a of the first island portion 1011 can be minimized. In addition, the second conductive pattern DDL2b overlaps with the first middle conductive pattern MDL1.

[0236] According to the embodiment, since the first conductive pattern DDL2a and the second conductive pattern DDL2b are provided on different layers, the resistance of the second lower conductive pattern DDL2 can be reduced. As a result, afterimages that may occur due to high resistance can be prevented. In addition, since the connection wirings overlap each other on different layers, the width of the first connector 1021a of the first island portion 1011 can be minimized.

[0237] Figure 17 is along the lines of Figure 8 A cross-sectional view of the display device taken along line J-J'. Figure 17 In, with Figure 13 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0238] Reference Figure 17 According to an embodiment, the previous scan line SIL includes a first previous scan line SIL1 and a second previous scan line SIL2. The first previous scan line SIL1 is disposed on the gate insulating layer 203, and the second previous scan line SIL2 is disposed on the first interlayer insulating layer 205 covering the first previous scan line SIL1. The first previous scan line SIL1 and the second previous scan line SIL2 are connected to each other via a contact hole CNT. More specifically, the first previous scan line SIL1 is connected to the second previous scan line SIL2 via a contact hole CNT in the first interlayer insulating layer 205. Therefore, the resistance of the previous scan line SIL can be reduced, and afterimages that may occur due to high resistance can be prevented.

[0239] Figure 18 is along the lines of Figure 8 A cross-sectional view of the display device taken along line K-K'. Figure 18 In, with Figure 14 The same reference numerals used in the drawings denote the same elements, and repeated descriptions will be omitted here.

[0240] Reference Figure 18 , the scan lines SL include a first scan line SL1 and a second scan line SL2 , and the previous scan lines SIL include a first previous scan line SIL1 and a second previous scan line SIL2 .

[0241] According to an embodiment, the first scan line SL1 and the first previous scan line SIL1 are disposed on the gate insulating layer 203. In this embodiment, the lower common voltage line UPSL is spaced apart from the first scan line SL1 and the first previous scan line SIL1 in a direction parallel to the upper surface of the substrate 100. Therefore, even if the lower common voltage line UPSL includes the same material as the semiconductor layer, the lower common voltage line UPSL can be used as a connection wiring by being fully doped.

[0242] According to an embodiment, the second scan line SL2 and the second previous scan line SIL2 are disposed on the first interlayer insulating layer 205 . Figure 18 The second scan line SL2 and the second previous scan line SIL2 are shown overlapping the first scan line SL1 and the first previous scan line SIL1, respectively. However, in some embodiments, the second scan line SL2 does not overlap the first scan line SL1 and the second previous scan line SIL2 does not overlap the first previous scan line SIL1.

[0243] In some embodiments, the second scan line SL2 and the second previous scan line SIL2 overlap with the lower common voltage line UPSL. In other embodiments, the second scan line SL2 and the second previous scan line SIL2 overlap with at least one of the emission control line EL, the driving voltage line PL, and the initialization voltage line VL.

[0244] According to the embodiment, since the scan line SL and the previous scan line SIL are provided on different layers, the resistance of the scan line SL and the resistance of the previous scan line SIL can be reduced, respectively, and afterimages that may occur due to high resistance can be prevented. In addition, since the connection wirings overlap each other, the width of the second connector 1021b of the first island portion 1011 can be minimized.

[0245] Furthermore, although the display device according to various embodiments has been described using the terms of the lower driving voltage line UPL and the lower common voltage line UPSL, the lower driving voltage line UPL may be understood as a first wiring, and the lower common voltage line UPSL may be understood as a second wiring.

[0246] As described above, according to the embodiment, a display device is provided that can minimize the width of a connector in which wiring is provided. Therefore, the embodiment provides a high-resolution display device.

[0247] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, wherein: The display device includes: a substrate including an island portion, a first connector extending from the island portion in a first direction, and a second connector extending from the island portion in a second direction intersecting the first direction; a display unit provided on the island portion and including at least one thin film transistor and at least one display element connected to the at least one thin film transistor; and connecting wiring provided on the first connector and the second connector and connected to the display unit, wherein at least one of the connection wirings is provided on the same layer as the semiconductor layer of the at least one thin film transistor, and Wherein, the connecting wiring includes a first wiring and a second wiring, the first wiring of the first connector is arranged on the same layer as the semiconductor layer, and the second wiring of the first connector is electrically connected to the relative electrode of the at least one display element, the first wiring and the second wiring overlap each other, and an insulating layer is interposed between the first wiring and the second wiring.

2. The display device according to claim 1, wherein The connecting wiring includes a first wiring and a second wiring, the first wiring of the first connector is provided on the same layer as the semiconductor layer, and the second wiring of the first connector is electrically connected to an opposing electrode of the at least one display element, A first data line, a second data line, and a third data line connected to the display unit are disposed on the island portion, and The connection wiring of the first connector includes: an intermediate conductive pattern connected to the first data line disposed on the same layer as the intermediate conductive pattern; a lower conductive pattern disposed below the middle conductive pattern and connected to the second data line; and an upper conductive pattern disposed on the middle conductive pattern and connected to the third data line, wherein at least one insulating layer is interposed between the upper conductive pattern and the middle conductive pattern, and The lower conductive pattern and the first wiring are spaced apart from each other in a direction parallel to an upper surface of the substrate.

3. The display device according to claim 2, wherein: The lower conductive pattern includes a first conductive pattern and a second conductive pattern, at least one first insulating layer is interposed between the first conductive pattern and the second conductive pattern, At least one second insulating layer is interposed between the second conductive pattern and the middle conductive pattern, and The first conductive pattern and the second conductive pattern extend to the island portion and are connected to each other through a contact hole penetrating the at least one first insulating layer.

4. The display device according to claim 2, wherein The connection wiring is further provided on a third connector extending from the island portion in a direction parallel to the first direction, Wherein, the third connector includes: The lower conductive pattern is connected to the first data line; The upper conductive pattern is connected to the second data line; and The middle conductive pattern is connected to the third data line.

5. The display device according to claim 1, wherein the second wiring of the second connector is electrically connected to the opposite electrode of the display element, and the first wiring of the second connector is provided on the second wiring, The second wiring is provided on the same layer as the semiconductor layer. The display device according to claim 5 , wherein: The connection wiring further includes at least one scanning line for transmitting a scanning signal, and The at least one scan line is provided on a first insulating layer covering the second wiring.

7. The display device according to claim 6, wherein: The at least one scan line and the second wiring are spaced apart from each other in a direction parallel to the upper surface of the substrate, The at least one scan line includes a first scan line and a second scan line, The first scanning line is provided on the first insulating layer covering the second wiring, and The second scan line is disposed on a second insulating layer covering the first scan line.

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