Electronic circuit and manufacturing method

Abstract

An electronic circuit is described, the electronic circuit comprising: a first power rail; a second power rail; and a field effect transistor FET, the FET comprising: a first terminal, which is directly or indirectly coupled to the first power rail; a second terminal, which is directly or indirectly coupled to the second power rail; a channel of semiconductor material, which connects the first terminal and the second terminal; a gate terminal, to which a voltage can be applied to control the conductivity of the channel, the channel providing a conductive path from the first terminal to the second terminal; and a gate dielectric, which is arranged to insulate the gate terminal from the channel. The circuit also includes a dielectric material layer or other dielectric material body, the gate dielectric being a first portion of the dielectric material layer or other dielectric material body. The first power rail includes a first rail portion arranged on a first side of a second portion of the dielectric material layer or other dielectric material body, and the second power rail includes a second rail portion arranged on a second side of the second portion of the dielectric material layer or other dielectric material body, the second side being opposite to the first side. The second portion of the dielectric material layer or other dielectric material body separates the first and second rail portions, and the first and second rail portions provide capacitance for the circuit.

Description

Technical Field

[0001] The present invention relates to an electronic circuit comprising first and second power supply rails and at least one field effect transistor. Certain embodiments relate to a circuit arranged to generate a DC voltage across the first and second power supply rails in dependence on a received wireless signal. Background Art

[0002] In many electronic circuits, such as an RFID integrated circuit that may receive its power and data from an RF signal via an antenna, there is a challenge in providing a stable, low-noise power supply to the circuit. Power supply can be achieved by using large on-board capacitors between the power rails (e.g., across Vdd and ground). However, such large capacitors occupy a large area of ​​the integrated circuit, limiting its ultimate miniaturization. Alternatively, the large capacitors between the power rails can be provided as discrete (off-chip) components, but this approach increases the complexity, size, and cost of circuit assembly.

[0003] It is known from US 5202751 that capacitance can be provided for conventional silicon-based semiconductor integrated circuits by arranging the conductors of two power rails in two parallel layers laminated to each other and placing a dielectric substance between the two layers. However, this arrangement complicates the circuit and its manufacturing method.

[0004] Certain aspects of the present invention are directed to at least partially addressing one or more problems associated with the prior art. Summary of the invention

[0005] A first aspect of the invention provides an electronic circuit comprising: a first power rail (1); a second power rail (2); and a field effect transistor (3) FET, the field effect transistor comprising: a first terminal (31) directly or indirectly coupled to the first power rail; a second terminal (32) directly or indirectly coupled to the second power rail; a channel (33) of semiconductor material connecting the first terminal and the second terminal; a gate terminal (34) to which a voltage can be applied to control the conductivity of the channel, the channel providing a conductive path from the first terminal to the second terminal; and a gate dielectric (35) arranged to insulate the gate terminal from the channel, the electronic circuit being characterized in that the circuit comprises a layer of dielectric material or other dielectric material body (4) , the gate dielectric (35) is a first portion (41) of the dielectric material layer or other dielectric material body, and is further characterized in that the first power rail includes a first rail portion (11) arranged on a first side (421) of a second portion (42) of the dielectric material layer or other dielectric material body, and the second power rail includes a second rail portion (22) arranged on a second side (422) of the second portion (42) of the dielectric material layer or other dielectric material body, the second side being opposite to the first side, whereby the second portion (42) of the dielectric material layer or other dielectric material body separates the first rail portion and the second rail portion (11, 22), and the first rail portion and the second rail portion provide capacitance to the circuit (or in other words, form a capacitor).

[0006] Advantageously, the layer or other body of dielectric material has a dual purpose in that a first portion thereof provides a gate dielectric for the FET and a second portion thereof forms a capacitance together with the first rail portion and the second rail portion. Thus, in addition to or as an alternative to the capacitance provided by a separate capacitor integrated in the electronic circuit, capacitance (e.g. for power smoothing purposes) is provided by portions of first and second power rails arranged to overlap each other to a desired degree (in other words, to provide a desired overlap area), the two power rails being separated by the same dielectric material already present in the circuit to provide the FET gate dielectric. The gate dielectric material may be a high-k material, and / or the layer of dielectric material may be thin, so that, in essence, capacitance is provided to the circuit by the overlapping portions of the power rails having the high-k and / or thin dielectric material therebetween.

[0007] Advantageously, the manufacture of electronic circuits embodying the invention is simpler than methods for constructing prior art circuits because the gate dielectric and the dielectric for the "power rail capacitance" (formed by the overlapping portion of the first and second power rails) can be formed simultaneously, i.e., by a single processing step (e.g., by deposition or other suitable technique). Furthermore, the first and second FET terminals and the first rail portion can be formed simultaneously with each other (i.e., by a single processing step), and the gate terminal and the second rail portion can be formed simultaneously with each other by another single processing step.

[0008] In some embodiments, the layer or other body of dielectric material (4) is a layer.

[0009] In certain embodiments, the thickness of the layer is in the range of 1 nm to 500 nm, for example 5 nm to 50 nm. Subject to any other constraints, it is advantageous to make the layer as thin as possible, thereby resulting in providing greater capacitance.

[0010] In some embodiments, the dielectric material has a dielectric constant greater than 3.9, such as greater than 4, 5, 6, or 77, 12, or 19. For example, the dielectric material may be Al2O3 with a K of about 8. 2 O 3 , K is about 13 Y 2 O 3 (Can be used for polysilicon TFT), tantalum oxide Ta with K of about 20 2 O 5 (which can be used in organic TFTs) or one of the many other high-K materials identified at, for example, https: / / pubs.acs.org / doi / 10.1021 / acs.chemrev.8b00045.

[0011] In some embodiments, the FET is a thin film transistor.

[0012] In certain embodiments, the first and second terminals (31, 32) and the first rail portion (11) are respectively substantially flat and coplanar with each other.

[0013] In some embodiments, the first terminal (31) is directly connected to the first rail portion.

[0014] In certain embodiments, the first terminal (31) and the first rail portion (11) are respective portions of a flat layer of conductive material or other body of conductive material.

[0015] In certain embodiments, the gate terminal (34) and the second rail portion (22) are each substantially flat and coplanar with one another.

[0016] In certain embodiments, the first rail portion (11) is in direct contact with the first side (421).

[0017] In certain embodiments, the second rail portion (22) is in direct contact with the second side (422).

[0018] In some embodiments, the circuit further comprises an antenna (101) arranged to receive a wireless signal; a rectifying device (102) connected to the antenna and the first and second power rails and arranged to generate a DC voltage between (across) the first and second power rails in accordance with the received wireless signal.

[0019] In some embodiments, the circuit further comprises a capacitor (103) connected between the first and second power rails to smooth the DC voltage.

[0020] In some embodiments, the circuit also includes a semiconductor material layer (5), the first and second terminals (31, 32) and the first rail portion (11) are formed on a first surface of the semiconductor material layer, the channel (33) is provided by a portion of the semiconductor material layer (5), the dielectric material layer or other dielectric material body (4) is formed on the first and second terminals and the first rail portion, and the gate terminal (34) and the second rail portion (22) are formed on the first surface of the dielectric material layer or other dielectric material body.

[0021] In some embodiments, the circuit further comprises a substrate (6), the substrate being located below the semiconductor material layer (5).

[0022] In some embodiments, the circuit further comprises a substrate (6) and a semiconductor material layer (5), wherein the first and second terminals (31, 32) and the first rail portion (11) are formed on a first surface of the substrate, the semiconductor material layer (5) is formed above the first and second terminals and the first rail portion, the dielectric material layer or other dielectric material body (4) is formed above the semiconductor material layer, and the gate terminal (34) and the second rail portion (22) are formed on a first surface of the dielectric material layer or other dielectric material body (4).

[0023] In some embodiments, the circuit further comprises a substrate (6) and a semiconductor material layer (5), wherein the first and second terminals (31, 32) and the first rail portion (11) are formed on a first surface of the substrate, the semiconductor material layer (5) is formed at least between the first and second terminals to provide the channel (33), the dielectric material layer or other dielectric material body (4) is formed above the semiconductor material layer and the first and second terminals and the first rail portion, and the gate terminal (34) and the second rail portion (22) are formed on a first surface of the dielectric material layer or other dielectric material body (4).

[0024] In some embodiments, the circuit further comprises a substrate (6) and a semiconductor material layer (5), wherein the gate terminal (34) and the second rail portion (22) are formed on a first surface of the substrate, the dielectric material layer or other dielectric material body (4) is formed above the gate terminal and the second rail portion, the first and second terminals (31, 32) and the first rail portion (11) are formed above the dielectric material layer or other dielectric material body, and the semiconductor material layer (5) is formed at least between the first and second terminals to provide the channel.

[0025] In some embodiments, the circuit further comprises a substrate (6) and a semiconductor material layer (5), wherein the gate terminal (34) and the second rail portion (22) are formed on a first surface of the substrate, the dielectric material layer or other dielectric material body (4) is formed above the gate terminal and the second rail portion, the semiconductor material layer (5) is formed above at least a portion of the dielectric material layer or other dielectric material body (4) covering the gate terminal, and the first and second terminals (31, 32) and the first rail portion (11) are formed above the semiconductor material layer and the dielectric material layer or other dielectric material body.

[0026] Another aspect of the present invention provides an electronic circuit, the electronic circuit comprising: a first power rail (1); a second power rail (2); and a layer or other dielectric material body (4), wherein the first power rail comprises a first rail portion (11) arranged on a first side of the layer or other dielectric material body (4), and the second power rail comprises a second rail portion (22) arranged on a second side of the layer or other dielectric material body, the second side being opposite to the first side, the first rail portion comprising a first grid or mesh of crossed and intersecting conductive elements (11a-11i), and the second rail portion comprising a second grid or mesh of crossed and intersecting conductive elements (22a-22i), the first and second grids or meshes having the same shape (or in other words, having the same footprint, i.e., projection on a plane) on the opposing first and second sides and being aligned with each other so as to form a capacitor together with a portion (42) of the layer or other dielectric material body sandwiched therebetween.

[0027] In some embodiments, the circuit further comprises a field effect transistor (3), the field effect transistor comprising: a first terminal (31) coupled directly or indirectly to the first power rail; a second terminal (32) coupled directly or indirectly to the second power rail; a channel (33) of semiconductor material connecting the first terminal and the second terminal; a gate terminal (34) to which a voltage can be applied to control the conductivity of the channel, the channel providing a conductive path from the first terminal to the second terminal; and a gate dielectric (35) arranged to insulate the gate terminal from the channel, wherein the gate dielectric comprises a portion (41) of the dielectric material layer or other dielectric material body (4).

[0028] In some embodiments, the electronic circuit comprises a further capacitor (103) connected between the power rails, the further capacitor comprising a first capacitor plate (1031) connected to the first power rail (1) and arranged on the first side, a second capacitor plate (1032) connected to the second power rail and arranged on the second side, and a further portion (400) of the dielectric material layer or other dielectric material body, the further portion being a portion located between the first and second capacitor plates.

[0029] In some embodiments, the circuit further comprises an antenna (101) arranged to receive a wireless signal; a rectifying device (102) connected to the antenna and the first and second power rails (1, 2) and arranged to generate a DC voltage between (across) the first and second power rails in accordance with the received wireless signal.

[0030] Another aspect of the invention provides a method of manufacturing an electronic circuit, the electronic circuit comprising a first power rail (1), a second power rail (2) and a field effect transistor (3) FET, the field effect transistor comprising a first terminal (31) directly or indirectly coupled to the first power rail; a second terminal (32) directly or indirectly coupled to the second power rail; a channel (33) of semiconductor material connecting the first terminal and the second terminal; a gate terminal (34) to which a voltage can be applied to control the conductivity of the channel, the channel providing a conductive path from the first terminal to the second terminal; and a gate dielectric (35) arranged so that the gate dielectric (35) The gate terminal is insulated from the channel, the method comprising: forming a dielectric material layer or other dielectric material body including a first portion and a second portion; forming the first and second terminals and a first rail portion of the first power rail simultaneously on a first side of the dielectric material layer or other dielectric material body; forming the gate terminal and a second rail portion of the second power rail simultaneously on a second side of the dielectric material layer or other dielectric material body, wherein the first and second rail portions are positioned on opposite sides of the second portion so as to form a capacitor with the second portion, and wherein the gate terminal and the first and second terminals are positioned so that the first portion provides the gate dielectric.

[0031] In some embodiments, the forming of the first and second terminals and the first rail portion is performed before forming the dielectric material layer or other dielectric material body, and the forming of the gate terminal and the second rail portion is performed after forming the dielectric material layer or other dielectric material body.

[0032] In some embodiments, the forming of the first and second terminals and the first rail portion is performed after forming the dielectric material layer or other dielectric material body, and the forming of the gate terminal and the second rail portion is performed before forming the dielectric material layer or other dielectric material body.

[0033] It will be appreciated that while the concept of arranging power and ground conductors in two parallel layers with a dielectric in between to provide capacitance for conventional silicon based ICs is known from US 5,202,751, embodiments of various aspects of the present invention are significantly different and provide numerous advantages.

[0034] For example, when provided in a grid or mesh-like form in certain embodiments, the distributed capacitance of the first and second rail portions provides a majority of the overall power rail capacitance of the integrated circuit, rather than just small local charge containers.

[0035] Silicon integrated circuits do not have flat, planar metal layers with high capacitance dielectrics between them (and certainly not between device layers). Although these layers can be placed between back-end interconnect layers stacked above the device layers, they typically use low-k dielectrics to minimize coupling between layers and are relatively thick, further weakening coupling between layers. Therefore, conventional silicon processing cannot effectively incorporate the novel structures described in this patent specification into layers that already exist in its processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0037] Figure 1 is a schematic diagram of an electronic circuit embodying the present invention;

[0038] Figure 2 is a schematic cross-sectional view of a portion of another electronic circuit embodying the present invention;

[0039] Figures 3 to 5 is a schematic cross-sectional view of alternative electronic circuits embodying the present invention, each electronic circuit having a top-gate structure;

[0040] Figures 6 to 9 is a schematic cross-sectional view of a portion of other electronic circuits embodying the present invention, each electronic circuit having a bottom gate structure;

[0041] Fig.10 and Fig.11 is a schematic cross-sectional view of a portion of other electronic circuits embodying the present invention, each electronic circuit including two FETs;

[0042] Fig.12 is a schematic diagram of a method for manufacturing an electronic circuit embodying the present invention;

[0043] Fig.13 is a schematic plan view of another circuit embodying the present invention;

[0044] Fig.14 as well as Figures 14b to 14e is a schematic diagram of an overlapping power grid used in certain embodiments of the present invention; and

[0045] Fig.15 is a schematic cross-sectional view of a portion of another electronic circuit embodying the present invention. DETAILED DESCRIPTION

[0046] Reference now Figure 1, which shows an electronic circuit embodying the present invention. The circuit 100 comprises an antenna 101 (or antenna arrangement) arranged to receive a wireless signal and to provide a corresponding alternating voltage generated by the received signal to a rectifier or rectifying means 102 via antenna terminals 201, 202. The rectifier 102 generates a DC supply voltage Vdd between two power rails, namely a first power rail 1 and a second power rail 2. The circuit also comprises a capacitor 103, which is arranged to provide some smoothing of the DC supply voltage Vdd. The circuit further comprises a FET 3, which has: a first terminal 31, which is coupled to the first power rail by a coupling means 106; and a second terminal 32, which is coupled to the second power rail by a coupling means 107; a channel 33 of semiconductor material, which connects the first terminal and the second terminal; a gate terminal 34, to which a voltage can be applied to control the conductivity of the channel 33; a gate dielectric 35, which is arranged to insulate the gate terminal from the channel. In this example, the control voltage provided to the gate terminal of the FET 3 is provided from another part 104 of the electronic circuit, the details of which are not necessary for understanding the present invention. Therefore, this other part 104 of the circuit is only represented by a dotted line in the figure. Similarly, the voltage at the second terminal 32 of the FET 3 is provided to another part 105 of the circuit, the details of which are not necessary for understanding the present invention. In some embodiments, the first terminal 31 is directly coupled to the first power rail 1, that is, it is connected to the first power rail by a conductive device with a weak resistance (such as one or more conductive rails), and there are no circuit components between the terminal 31 and the first power rail 1. However, in alternative embodiments, the first terminal 31 can be indirectly coupled to the first power rail 1, for example, through one or more circuit components (such as one or more resistors, or one or more other passive circuit components, or one or more active components). Similarly, in various embodiments of the present invention, the second terminal 32 can be directly or indirectly coupled to the second power rail 2.

[0047] In this first example, the circuit includes a dielectric material layer or other dielectric material body, and the gate dielectric 35 is provided by a first portion 41 of the dielectric material layer or other dielectric material body. In addition, the first power rail 1 includes a first rail portion 11 arranged on a first side of a second portion 42 of the dielectric material layer or other dielectric material body, and the second power rail 2 includes a second rail portion 22 arranged on a second side of the second portion 42 of the dielectric material layer or other dielectric material body, the second side being opposite to the first side. Therefore, the second portion 42 of the dielectric material layer or other dielectric material body separates the first rail portion 11 and the second rail portion 22, and in addition to the capacitance provided by the capacitor 103, the first and second rail portions also provide capacitance to the circuit.

[0048] will understand, Figure 1is highly schematic, and in actual embodiments of the invention, the overlapping portions 11 and 22 of the first and second power rails may be separated by a small distance, which is the thickness of the second portion 42 of the dielectric material layer or other dielectric material body, which in some embodiments is itself a thin high-K material layer.

[0049] Reference now Figure 2 , which shows a cross-sectional view of a portion of an electronic circuit embodying the present invention. The circuit comprises a layer of semiconductor material 5 formed on a suitable substrate 6, which in some embodiments may be flexible. On top of the semiconductor layer 5 (i.e., on a first surface of the semiconductor layer) are formed first and second terminals 31, 32 of the FET 3 and at least a portion of the first power rail 1. In the figure, neither the first terminal 31 or the terminal 32 is directly connected to the power rail 1, but in alternative embodiments, one of these terminals (e.g., the first terminal 31) may be directly connected to the first power rail 1. Such direct connection or direct coupling may be achieved, for example, by forming the first terminal 31 and the first power rail 1 as part of a single body, layer, region or area of ​​conductive material. Such optional direct connection is indicated in the figure by a dashed line Y. A layer of high-k dielectric material 4 has been formed over the first and second terminals and the first power rail 1, such that the first and second terminals and the first power rail 1 are arranged on the lower side of the dielectric layer 4. On the upper surface or upper side of the dielectric layer 4, a gate terminal 34 and at least a portion of the second power rail 2 are formed. The gate terminal 34 is typically arranged over the gap between the first terminal 31 and the second terminal 32, such that a voltage applied to the gate terminal 34 can be used to control the conductivity of the semiconductor channel 33 in the semiconductor layer 5, thereby providing a conductive path between the first terminal 31 and the second terminal 32. It will be appreciated that the first rail portion 11 of the first power rail 1 overlaps the second rail portion 22 of the second power rail, with only the second portion 42 of the dielectric material layer separating them in this example. Thus, the first and second rail portions 11, 12 together with the second portion 42 of the dielectric material form a capacitor, which is represented in the figure by the arrow marked C. The first portion 41 of the same dielectric material layer 4 provides the gate dielectric 35 of the FET 3. It will be appreciated that in certain embodiments, the structure may also include one or more other device layers, which are generally represented by the reference numeral 800.

[0050] Therefore, in Figure 2In the embodiment of the invention, the first rail portion 11 is arranged on a first side 421 of the second portion 42 of the dielectric material layer 4 and the second rail portion 22 is arranged on a second side 422 of the second portion 42 of the dielectric material layer 4. In other words, the first and second power rails 1, 2 are arranged with portions 11 and 22 aligned with each other on opposite sides of the dielectric layer 4, which also provides the gate dielectric. The area of ​​these overlapping portions 11, 22, as well as the thickness of the dielectric layer 4 and the dielectric constant k of the dielectric material 4 can be selected (i.e. designed) to provide the required capacitance C for the circuit.

[0051] Reference now Figure 3 , which shows an alternative electronic circuit also having a top gate structure. Here, instead of providing a semiconductor layer 5 below the first and second terminals, the semiconductor layer 5 is formed above the first and second terminals and the first rail portion 11. A gate dielectric layer 4 is then formed above the semiconductor layer 5, and a gate terminal 34 and a second rail portion 22 are provided on top of the gate dielectric layer 4. In addition, a first portion 41 of the gate dielectric layer provides a gate dielectric 35 to the FET 3, and a second portion 42 provides a portion of capacitive material between the aligned and overlapping first and second portions 11, 22. These first and second rail portions 11, 22 are also separated by a portion 52 of the semiconductor material layer 5. It will be appreciated that this arrangement forms a "power rail capacitor" having a capacitance that is lower than if there were no semiconductor material portion 52 between the rail portions 11 and 22, but this may be possible or desirable depending on the device requirements.

[0052] Reference now Figure 4 In an alternative electronic circuit incorporating a top gate FET 3, no extended layer of semiconductor material is provided, but semiconductor material is provided only between the first terminal 31 and the second terminal 32 to provide a channel portion 33. In this example, the second and first terminals 32, 31 are not directly connected to the first rail portion 11, as indicated by arrow B (with Figure 3 3 and 4). The dielectric layer 4 is formed over the first and second terminals and the first rail portion 11 and the semiconductor channel 33, so that in this example, the first and second rail portions 11 and 22 are separated only by the dielectric material 4, in particular the second portion 42 of the dielectric layer 4.

[0053] exist Figure 5 In the example shown, the semiconductor material layer 5 is formed over the first and second FET terminals 31, 32 and over a portion of the first power rail 1. However, the semiconductor material layer 5 does not extend between the first rail portion 11 and the second rail portion 22 which are separated only by the thickness of the second portion 42 of the dielectric layer 4.

[0054] Reference now Figures 6 to 9, these figures show a series of alternative embodiments generally described as incorporating bottom gate structures. Figure 6 , a gate terminal 34 and a second rail portion 22 are formed on the surface of a substrate 6, and a dielectric material layer 4 has been formed on top of the gate and second rail portion 22. The first and second terminals 31, 32 and the first rail portion 11 are formed on top of the dielectric material layer 4, and in this example the first terminal 31 is directly connected (see arrow A) to the first rail portion 11. In this example, the FET channel 33 is provided by a semiconductor material arranged just between the first terminal 31 and the second terminal 32, which in turn are on top of the dielectric material layer 4.

[0055] exist Figure 7 In the example shown, the semiconductor material is formed as a wider layer or body 5 covering the first and second terminals 31 , 32 , neither of which is directly connected to the first rail portion 11 .

[0056] Figure 8 An alternative structure is shown in which the semiconductor channel 33 is provided by a portion of a layer of semiconductor material 5 formed on top of a dielectric layer 4, and the first and second terminals 31, 32 and the first rail portion 11 are formed on top of (i.e., on the upper surface of) the semiconductor layer 5. In this example, the capacitance C provided by the overlapping portions 11 and 22 of the power rails is determined by the area of ​​these portions 11, 22, the thickness of the dielectric layer between the rail portions 11 and 22 and the portions 42 and 52 of the semiconductor layer, and the dielectric constants of the semiconductor material 5 and the dielectric material 4.

[0057] Fig. 9 An alternative bottom gate structure is shown in which a region of semiconductor material 5 is deposited on top of the gate dielectric layer 4 to provide a FET channel 33, and the first terminal 31 and the second terminal 32 are formed so as to partially overlap the semiconductor material layer or body 5. In this example, the semiconductor material layer 5 does not extend between the first and second rail portions 11, 22 which are separated only by the second portion 42 of the dielectric layer 4.

[0058] The principle of overlapping power rail sections providing additional capacitance can even be applied to circuits where the device terminals connected to the power plane are separated by large vertical distances. Fig.10An example of such a circuit is shown in . In this example, the circuit includes stacked device layers, wherein two layers in the integrated circuit contain thin film transistor (TFT) channels 33a, 33b. In this example, the stacked TFT devices 3a and 3b share a common gate terminal 34. The topmost and bottommost device terminal layers (source-drain of each device) are connected to the power planes Vdd and Gnd, respectively. In order to increase the capacitance between the Vdd plane and the Gnd plane, a metal plane 22 is inserted between them, and then the metal plane 22 is connected to one or the other of these planes. In this example, the insertion layer 22 is conveniently formed in the gate metal layer and connected to the Vdd layer. The coupling degree of the inserted layer to the Gnd layer is higher than the coupling degree to the Vdd layer, so the capacitance between them is increased. The same principle applies to other stepped gate structures, such as a gate structure using two gate terminal layers, and a gate structure with a bottom-gate thin film transistor.

[0059] In more detail, Fig.10 The example shown includes a first FET 3a having a first terminal 31a, a second terminal 32a, a common gate terminal 34, a semiconductor channel 33a provided by a portion of a semiconductor layer 5a formed on a substrate 6, and a gate dielectric 35a provided by a first portion 41a of a first dielectric material layer 4a. In this example, a first rail portion 11 directly connected to the first terminal 31a is provided in the same plane as the first and second terminals 31a, 32a. An intervening layer provides a second rail portion 22, which is separated from the first rail portion 11 by a second portion 42a of dielectric material, and the second rail portion 22 is in the same plane as the common gate terminal 34. A second dielectric material layer 4b is formed over the common gate 34 and the second rail portion 22, and a first terminal 31b and a second terminal 32b of a second FET 3b (stacked over the first FET 3a) are formed on top of the second dielectric layer 4b. A first through hole 71 connects the respective second terminals 32a and 32b, passing through the dielectric layers 4a and 4b. The second via 72 connects the first terminal 31b of the second FET 3b to the second rail portion 22 and extends through the second dielectric layer 4b. The first portion 41b of the second dielectric layer 4b provides the gate dielectric 35b of the second FET 3b. Thus, in this compact arrangement, the gate terminal 34 controls the conductivity of the channels 33a and 33b in both FETs simultaneously, and the conductive material 22 formed in the same plane as the common gate 34 combines with the second portion 42a of the first rail portion 11 to provide capacitance for the circuit.

[0060] Reference now Fig.11 , which shows a portion of another circuit embodying the present invention and also including stacked FETs. This example is similar to Fig.10The example shown, however, here the semiconductor material is only provided between the respective first and second terminals of each device 3a, 3b. The circuit may additionally comprise one or more further device layers, which are generally indicated at 800.

[0061] Reference now Fig.12 , which shows a method for manufacturing an electronic circuit according to an embodiment of the present invention. In step A, a suitable substrate 6 is first provided. In step B, a semiconductor material layer 5 is formed on the substrate 6. However, it will be understood that in alternative embodiments, the semiconductor material layer 5 can be formed in another step in the sequence, depending on the desired FET structure. An illustrative example of a FET structure manufactured in a circuit by this method is shown in Figures 2 to 11 . In step C, the first and second FET terminals 31, 32 are formed simultaneously with at least the first rail portion 11 of the first power rail 1 (i.e., by the same processing step or operation). Thus, the terminals 31 and 32 and the first rail portion 11 may be provided by a conductive material suitably patterned on the upper surface of the semiconductor layer 5. In step D, a layer of dielectric material 4 is formed, comprising at least a first portion 41 and a second portion 42. In this example, the dielectric layer is formed over the first and second terminals and the first rail portion 11, but in alternative embodiments, the dielectric layer may be formed before the first and second terminals and the first rail portion, for example over the bottom gate and the second rail portion. In this example, in step E, a gate terminal 34 is formed simultaneously with at least the second rail portion 22 of the second power rail 2 (again, by the same processing step or operation) on the upper surface of the dielectric layer 4, suitably positioned so that the gate terminal 34 can be used to control the conductivity of the channel 33 in the semiconductor layer 5 between the first FET terminal 31 and the second FET terminal 32. However, in alternative embodiments (e.g. in conjunction with a bottom gate FET), the gate 34 and the second rail portion may be formed before the dielectric layer 4, for example on the substrate. The second power rail is suitably positioned so that the second rail portion 22 is located above the first rail portion 11 of the first power rail 1, and the second portion 42 of the dielectric layer 4 is sandwiched therebetween to provide a capacitor. The first portion 41 of the dielectric layer 4 provides the gate dielectric 35 of the FET 3. In step F, additional device layers 80 and 81 have been formed above the underlying structure. It will be appreciated that this method of manufacturing provides the following advantages:

[0062] The first and second FET terminals and the first rail portion are formed together simultaneously by the same processing step or operation.

[0063] The gate dielectric 35 and the power rail capacitor dielectric (41 and 42) are formed together at the same time by the same processing step or operation, and they are part of a single dielectric material layer 4; and

[0064] The gate terminal and second rail portion 22 are formed together simultaneously by the same processing step or operation.

[0065] Thus, no additional processing steps (beyond those required to create only the FETs) are required to provide additional capacitance to the circuit.

[0066] Reference now Fig.13 , which is a highly schematic representation of a portion of another electronic circuit embodying the present invention. The electronic circuit 200 includes antenna contacts 201, 202 adapted to be attached to an antenna arranged to receive wireless signals (e.g., RF signals). The footprint or portion of the area of ​​the circuit 200 is occupied by the plates of a capacitor 103 connected between the power rails of the circuit so as to smooth the power supply voltage generated from the AC voltage received via the antenna terminals 201, 202. Another portion 203 of the overall circuit area contains the circuit and circuit elements (including one or more FETs). The area 203 also includes at least a portion of first and second power rails, which include at least a first rail portion and a second rail portion separated by a layer of dielectric material and providing additional capacitance to the circuit (i.e., capacitance in addition to the capacitance provided by the capacitor 103). In certain embodiments of the present invention, the overlapping area of ​​the first and second power rails (i.e., the area of ​​the first and second rail portions 11, 22) is selected so that the individual capacitors 103 together provide the required total capacitance between the power rails.

[0067] Fig.14 A schematic perspective view shows a power grid structure that can be incorporated into certain embodiments of the present invention. In this example, the electronic circuit includes a first power rail 1, a second power rail 2, and a dielectric material layer or other dielectric material body 4 (the layer 4 is located at Fig.14 1 and 2). The first power rail comprises a first rail portion 11 arranged on a first side of a dielectric material layer or other dielectric material body, and the second power rail comprises a second rail portion 22 arranged on an opposite side of the dielectric material layer or other dielectric material body. The first rail portion 11 comprises a first grid or mesh of crossed and / or intersecting conductive elements 11a-11i, and the second rail portion 22 comprises a second grid or mesh of crossed and / or intersecting conductive elements 22a-22i. The first and second grids or meshes have substantially the same shape (or in other words, they have substantially the same footprint or projection on a plane parallel thereto). The first and second grids or meshes are aligned with each other so as to form a capacitor together with a portion of the dielectric material layer or other dielectric material body 4 sandwiched therebetween.

[0068] Therefore, in adopting Fig.14In the illustrated embodiment of the power rail, the power rail capacitance is at least mostly distributed in a power grid structure that can place the Vdd and Gnd lines in different metal layers and then arrange these lines overlapping each other within the circuit layout. In some embodiments, circuit elements such as components, devices, or cells are placed in the area between the overlapping conductive elements of the grid and are appropriately connected to these conductive elements according to a given circuit design.

[0069] Fig.14 The coincident / overlapping grid or mesh structure shown has significant advantages in reducing the circuit footprint because the area of ​​Vdd and Gnd is shared and directly reduces the integrated circuit area that needs to be occupied by dedicated capacitors. In fact, in some embodiments, using Fig.14 The overlapping / coinciding grid structure may reduce the area of ​​dedicated capacitors, and in further embodiments, if the power rail capacitance is only provided by the overlapping / coinciding first and second rail portions 11, 22, no separate or dedicated capacitors are required at all.

[0070] In addition, Fig.14 The electronic circuit shown in combination with a power rail grid / mesh structure can simplify layout and routing because all cells have the same orientation. Fig.14b , 14c , 14d and 14e illustrate example methods of layout, which show offset plan views and cross-sections of each method. In these figures, the upper and lower grids are separated by a layer of dielectric material, which is not shown for clarity. Fig.14b In the embodiment, connections from each power grid to a circuit unit or device can extend from the power grid on different sides of each window between intersecting members. Fig.14b In the specific example of , the power rail connections from the upper grid extend out of the top side of the grid window, while the power rail connections from the lower grid extend out of the bottom side of the window. Fig.14c As shown, connections from each power grid to a circuit unit or device can extend from the grid on the same side of each window between intersecting members. Fig.14c In a specific example of , the power rail connections from both the upper and lower grids extend out of the top side of the grid window. In a further example, connections from either grid may extend out of more than one side of the window. Fig.14b and 14c In the method of , both power rails are coupled to the devices, circuits or cells in the lower grid. In some cases, it may be more appropriate to couple the power rails to the devices, circuits or cells in the upper power grid, such as Fig.14d and Fig.14e As shown. Fig.14dIn the example, the power rail connections from the upper grid extend out of the top side of the grid window, while the power rail connections from the lower grid extend out of the bottom side of the window. Fig.14e Connections from each power grid to a circuit cell or device are shown extending from the grid on the same side of each window between intersecting members. In further examples, connections from any grid may extend from more than one side of a window. The details of the layout may reflect the requirements of the design and application. Figures 14b to 14e The electronic circuit shown incorporating a power rail grid / mesh structure also has the advantage of increasing capacitance between these power rails locally in the circuit element, which can reduce switching noise. In other words, the circuit element can have overlapping / coincident first and second rail portions 11, 12 close to them, rather than having capacitance provided remotely.

[0071] In some cases, high capacitance between power rails is provided by placing one power rail in the FET (e.g., TFT) source-drain layer and another power rail (or power line) in the FET gate layer, with, for example, an aluminum oxide high-k dielectric disposed between the two power rails.

[0072] It will be appreciated that the capacitance C of a capacitor is given by the equation: C = eA / d (C = capacitance, e = dielectric constant, A = area of ​​parallel plates, d = separation of parallel plates). Thus, high capacitance is provided by using a high dielectric constant dielectric, a large plate area and a small plate separation.

[0073] Embodiments of the present invention, by increasing the capacitance between power rails and optionally providing additional capacitance in a distributed fashion, have a number of positive effects, including:

[0074] This circuit is more robust to ESD events

[0075] Reduces input noise on the power rail

[0076] Improved immunity to internal dynamic IR drops, and

[0077] Reduces noise crosstalk between gates.

[0078] Reference now Fig.15, which shows a cross-section of a portion of another electronic circuit embodying the present invention. Here, the circuit includes a capacitor C, which is arranged, for example, to achieve smoothing purposes for smoothing the supply voltage between power rails and is formed by capacitor plates 1031 and 1032 separated by a portion 400 of a dielectric material layer 4. The circuit also includes a power rail structure, which includes a plurality of first power rail portions 11a-11c and a plurality of second rail portions 22a-22c. Each second rail portion 22 is arranged above a respective first rail portion 11 to provide a respective power rail capacitance Cp to the circuit together with a respective portion 42 of the dielectric layer sandwiched therebetween. In some embodiments, each of the first rail portions 11a-11c may be part of a grid or grid of a first power rail, and each of the second rail portions 22a-22c may be part of a second power rail grid or grid, for example as Fig.14 As shown. In some embodiments, the dielectric layer 4 that provides the capacitor dielectric also provides the gate dielectric of one or more FETs in the electronic circuit. Thus, at least the power grid capacitance can share the same dielectric material with one or more active devices in the circuit. Thus, the total capacitance between power rails in some electronic circuits embodying the present invention can be shared and distributed between dedicated capacitors and the power rails, and the power rail capacitance can be distributed over the area where one or more active devices are located.

[0079] Throughout the detailed description and claims of this specification, the words "comprise" and "include" and their variations mean "including but not limited to", and they are not intended to (and do not) exclude other parts, additions, components, integers or steps. Throughout the detailed description and claims of this specification, the singular includes the plural, unless the context requires otherwise. In particular, where the indefinite article is used, the specification should be understood to contemplate the plural as well as the singular, unless the context requires otherwise.

[0080] Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All features disclosed in this specification (including any accompanying claims, abstract and drawings) and / or all steps of any method or process disclosed in this manner may be combined in any combination, excluding combinations in which at least some of such features and / or steps are mutually exclusive. The invention is not limited to the details of any foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel step or any novel combination of steps of any method or process disclosed in this manner.

[0081] The reader's attention is directed to all papers and documents filed concurrently with or before the present application, which are related to the present specification and which are available to the public for inspection at the time of the present specification, and the contents of all these papers and documents are incorporated herein by reference.

Claims

1. An electronic circuit comprising: A first power rail (1); A second power rail (2); as well as a dielectric material layer or other dielectric material body (4), wherein the first power rail comprises a first rail portion (11) arranged on a first side of the dielectric material layer or other dielectric material body (4), and the second power rail comprises a second rail portion (22) arranged on a second side of the dielectric material layer or other dielectric material body, the second side being opposite to the first side, The first track portion comprises a first grid or mesh of crossed and intersecting conductive elements (11a-11i), and the second track portion comprises a second grid or mesh of crossed and intersecting conductive elements (22a-22i), The first grid or mesh and the second grid or mesh have substantially the same shape on the opposing first and second sides and are aligned with each other so as to form a capacitor with a portion (42) of the dielectric material layer or other dielectric material body sandwiched therebetween, and wherein the circuit further comprises at least one circuit element located in an area formed between the aligned conductive elements of the first grid or mesh and the second grid or mesh, the area being laterally bounded by the aligned conductive elements of the first grid or mesh and the second grid or mesh, the at least one circuit element being connected to the aligned conductive elements of the respective first grid or mesh and the second grid or mesh.

2. The electronic circuit according to claim 1, further comprising a field effect transistor (3), the field effect transistor comprising: a first terminal (31) coupled directly or indirectly to the first power rail; a second terminal (32) coupled directly or indirectly to the second power rail; a channel (33) of semiconductor material connecting the first terminal and the second terminal; a gate terminal (34) to which a voltage can be applied to control the conductivity of the channel, the channel providing a conductive path from the first terminal to the second terminal; as well as a gate dielectric (35) arranged to insulate the gate terminal from the channel, The gate dielectric comprises a portion (41) of the dielectric material layer or other dielectric material body (4).

3. An electronic circuit according to claim 1 or claim 2, comprising another capacitor (103) connected between the power rails, the other capacitor comprising a first capacitor plate (1031) connected to the first power rail (1) and arranged on the first side, a second capacitor plate (1032) connected to the second power rail and arranged on the second side, and another part (400) of the dielectric material layer or other dielectric material body, the other part being the part located between the first capacitor plate and the second capacitor plate.

4. The circuit according to claim 1, further comprising: an antenna (101) arranged to receive wireless signals; A rectifying device (102) is connected to the antenna and the first and second power rails (1, 2) and is arranged to generate a DC voltage between the first and second power rails in accordance with the received wireless signal.

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