Semiconductor structure with extended gate structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate and a fin structure formed above the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed above the fin structure and a second portion formed above the isolation structure, and the second portion of the gate structure includes an extension portion extending into the isolation structure.

Description

[0001] This application is a divisional application, the parent application has the application number 201510694354.5, the application date is October 21, 2015, and the invention name is “Semiconductor structure with extended gate structure and method for forming the same”. Technical Field

[0002] The present invention relates to the field of semiconductors, and more particularly to a semiconductor structure with an extended gate structure and a method for forming the same. Background Art

[0003] Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0004] One of the important drivers of improving computer performance is higher integration of circuits. This higher integration is achieved by miniaturization, or reducing the size of the devices on a given chip. Tolerance plays an important role in enabling the reduction of size on a chip.

[0005] However, although existing semiconductor manufacturing processes have generally been able to meet their intended purposes, as devices continue to be scaled down, existing processes can no longer fully meet all requirements. Summary of the invention

[0006] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a substrate; a fin structure formed above the substrate; an isolation structure formed around the fin structure; and a gate structure formed across the fin structure, wherein the gate structure comprises a first portion formed above the fin structure and a second portion formed above the isolation structure, and the second portion of the gate structure comprises an extension portion extending into the isolation structure.

[0007] According to one embodiment of the present invention, the extension portion of the second portion of the gate structure has a width of about to about Thickness within the range.

[0008] According to an embodiment of the present invention, the method further comprises: a spacer formed on a sidewall of the second portion of the gate structure, wherein the spacer does not extend into the isolation structure.

[0009] According to one embodiment of the present invention, a bottom surface of the spacer is not flush with a bottom surface of the second portion of the gate structure above the isolation structure.

[0010] According to one embodiment of the present invention, the spacer has a first height, and the second portion of the gate structure has a second height greater than the first height.

[0011] According to one embodiment of the present invention, a dielectric layer is formed under the spacer and in direct contact with the gate structure.

[0012] According to one embodiment of the present invention, the first portion of the gate structure has a first width, and the extension portion of the second portion of the gate structure has a second width greater than the first width.

[0013] According to one embodiment of the present invention, the difference between the first width and the second width is about to about within the range.

[0014] According to an embodiment of the present invention, the gate structure has a bottom surface, which is substantially flush with or lower than a bottom surface of the fin structure.

[0015] According to another aspect of the present invention, a semiconductor structure is provided, comprising: a substrate; a fin structure formed above the substrate; an isolation structure formed around the fin structure; a gate structure formed across the fin structure and extending above the isolation structure; and a spacer formed on a side wall of the gate structure, wherein a portion of the spacer formed on the side wall of the gate structure above the isolation structure has a first height, and a portion of the gate structure formed above the isolation structure has a second height greater than the first height.

[0016] According to one embodiment of the present invention, the difference between the first height and the second height is about to about within the range.

[0017] According to one embodiment of the present invention, a dielectric layer is formed under the spacer and in direct contact with the gate structure.

[0018] According to one embodiment of the present invention, the portion of the gate structure formed above the shallow trench includes an extension portion extending into the isolation structure.

[0019] According to one embodiment of the present invention, the extension portion further extends to a position below the spacer, so that a portion of the extension portion of the gate structure overlaps the spacer.

[0020] According to another aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: forming a fin structure above a substrate; forming an isolation structure around the fin structure above the substrate; forming a dummy gate structure across the fin structure; forming spacers on the sidewalls of the dummy gate structure; removing the dummy gate structure to form a trench between the spacers; removing a portion of the isolation structure to form an extended trench extending into the isolation structure; and forming a gate structure in the extended trench.

[0021] According to one embodiment of the present invention, the spacer located above the isolation structure has a first height and the gate structure located above the isolation structure has a second height greater than the first height.

[0022] According to one embodiment of the present invention, it further includes: forming a dielectric layer before the dummy gate structure and the spacer are formed, so that the dummy gate structure is formed on a first portion of the dielectric layer and the spacer is formed on a second portion of the dielectric layer; and after removing the dummy gate structure, removing the first portion of the dielectric layer, wherein the second portion of the dielectric layer is in direct contact with the gate structure.

[0023] According to an embodiment of the present invention, the method further includes: removing a portion of the second portion after removing the dummy gate structure.

[0024] According to one embodiment of the present invention, a portion of the extension groove further extends to a position below the spacer.

[0025] According to one embodiment of the present invention, forming a gate structure in a trench further comprises: depositing a gate dielectric layer over the bottom surface and sidewalls of the trench; depositing a work function metal layer over the gate dielectric layer; and depositing a metal gate electrode layer over the work function metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] When read in conjunction with the accompanying drawings, various aspects of the present invention can be better understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0027] Figures 1A to 1J are cross-sectional views of various stages in forming a semiconductor structure according to some embodiments.

[0028] FIG. 2A to FIG. 2B is a cross-sectional view of a semiconductor structure according to some embodiments.

[0029] FIG. 3A to FIG. 3B is a cross-sectional view of a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0030] The following invention provides different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the present invention may repeat reference symbols and / or characters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself represent the relationship between the various embodiments and / or configurations described.

[0031] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0032] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure may include a gate structure formed by a "gate last" process. That is, a dummy gate structure is first formed and then replaced by a gate structure. After removing the dummy gate structure, a portion of an isolation structure is also removed so that the gate structure formed thereafter can extend into the isolation structure and improve the performance of the structure.

[0033] Figures 1A to 1J 1 is a cross-sectional view of various stages of forming a semiconductor structure 100 according to some embodiments. Figure 1A As shown, a substrate 102 is provided according to some embodiments. The substrate 102 may be a semiconductor wafer such as a silicon wafer. Alternatively or in addition, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may be, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0034] In addition, the substrate 102 may include structures such as doped regions, interlayer dielectric (ILD) layers, conductive features, and / or isolation structures. In addition, the substrate 102 may also include a single or multiple material layers to be patterned. For example, the material layer may include a silicon layer, a dielectric layer, and / or a doped polysilicon layer.

[0035] like Figure 1A As shown, according to some embodiments, a dielectric layer 104 and a mask layer 106 are formed over the substrate 102, and a photosensitive layer 108 is formed over the mask layer 104. The dielectric layer 104 may serve as an adhesion layer between the substrate 102 and the mask layer 106. In addition, the dielectric layer 104 may also serve as an etch stop layer for etching the mask layer 106. In some embodiments, the dielectric layer 104 is made of silicon oxide. The dielectric layer 104 may be formed using a thermal oxidation process, but other deposition processes may be used in some other embodiments.

[0036] During the subsequent photolithography process, the mask layer 106 can be used as a hard mask. In some embodiments, the mask layer 106 is made of silicon nitride. The mask layer 106 can be formed by using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), but other deposition processes can also be used in some other embodiments.

[0037] Then, if Figure 1B As shown, according to some embodiments, the fin structure 110 is formed by sequentially etching the mask layer 106, the dielectric layer 104, and the substrate 102 through the photosensitive layer 108. Thereafter, the photosensitive layer 108 is removed.

[0038] like Figure 1C As shown, according to some embodiments, after forming the fin structure 110, an insulating layer 112 is formed to cover the fin structure 110 above the substrate 102. In some embodiments, the insulating layer 112 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or other low-K dielectric materials. The insulating layer 112 can be formed by using a high-density plasma (HDP) CVD process, but other deposition processes can be used in other embodiments.

[0039] Then, if Figure 1D As shown, according to some embodiments, the insulating layer 112 is recessed to form an isolation structure 114 such as a shallow trench isolation structure around the fin structure 110. The insulating layer 112 may be recessed by a wet etching process or a dry etching process. In addition, the mask layer 106 and the dielectric layer 104 are removed.

[0040] Afterwards, if Figure 1E As shown, a dielectric layer 116 is formed to cover the fin structure 110 and the isolation structure 114 , and a dummy gate structure 118 is formed over the fin structure 110 , in accordance with some embodiments.

[0041] In some embodiments, the dielectric layer 116 is made of silicon nitride, silicon oxide, silicon oxynitride, or other applicable dielectric materials. The dielectric layer 116 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0042] The dummy gate structure 118 is formed across the fin structure 110 and extends over the isolation structure 114. In some embodiments, the dummy gate structure 118 is made of polysilicon.

[0043] According to some embodiments, after forming the dummy gate structure 118, a spacer 120 is formed on the sidewall of the dummy gate structure 118. Figure 1E As shown, a dummy gate structure 118 is formed on a first portion 116 a of the dielectric layer 116 , and a spacer is formed on a second portion 116 b of the dielectric layer 116 .

[0044] Because the spacers 120 are formed on the sidewalls of the dummy gate structure 118 , each of the spacers 120 has a first height H1 substantially equal to a height of the dummy gate structure 118 .

[0045] In some embodiments, the spacer 120 is made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide or other suitable dielectric materials. The spacer 120 may include a single layer or multiple layers.

[0046] Next, as shown in FIG1F , according to some embodiments, a source / drain structure 122 is formed in the fin structure 110 . More specifically, the portion of the dielectric layer 116 that is not covered by the dummy gate structure 118 and the spacer 120 is removed. Figure 1F As shown, the first portion 116a of the dielectric layer 116 and the second portion 116b of the dielectric layer 118 below the dummy gate structure 118 are not removed in this step. After removing the exposed dielectric layer 116, the portion of the fin structure 110 adjacent to the dummy gate structure 118 is recessed to form grooves on both sides of the fin structure 110. Next, a strained material is grown in the groove by an epitaxial (epi) process. In addition, the lattice constant of the strained material may be different from the lattice constant of the substrate 102. In some embodiments, the source / drain structure 122 includes Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, etc.

[0047] like Figure 1GAs shown, according to some embodiments, after forming the source / drain structure 122, a contact etch stop layer (CESL) 124 is formed over the substrate 102, and an interlayer dielectric (ILD) layer 126 is formed on the contact etch stop layer 124. In some embodiments, the contact etch stop layer 124 is made of silicon nitride, silicon oxynitride, and / or other applicable materials. The contact etch stop layer 124 can be formed by plasma enhanced CVD, low pressure CVD, ALD, or other applicable processes.

[0048] The interlayer dielectric layer 126 may include multiple layers made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bis(p-chloromethyl)benzene (BCB), or polyimide. The interlayer dielectric layer 126 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0049] Next, according to some embodiments, a polishing process is performed on the interlayer dielectric layer 126 and the contact etch stop layer 124 to expose the top surface of the dummy gate structure 118. In some embodiments, a chemical mechanical polishing (CMP) process is performed until the top surface of the dummy gate structure 118 is exposed.

[0050] like Figure 1H As shown, according to some embodiments, after performing the polishing process, the dummy gate structure 118 is removed, so that the trench 128 is formed. In some embodiments, the dummy gate structure 118 is removed by performing a dry etching process. In some embodiments, the dummy gate structure 118 is removed by performing a dry etching process and a wet etching process. Figure 1H As shown, the bottom surface of each spacer 120 is substantially flush with the bottom surface of the groove 128 .

[0051] like Fig. 1I As shown, according to some embodiments, after removing the dummy gate structure 118, the first portion 116a of the dielectric layer 116 exposed by the trench 128 and the upper portion of the isolation structure 114 located below the first portion 116a of the dielectric layer 116 are removed. In some embodiments, the first portion 116a of the dielectric layer 116 is removed by a first etching process and the upper portion of the isolation structure 114 is removed by a second etching process. In some embodiments, the first portion 116a of the dielectric layer 116 and the upper portion of the isolation structure 114 are removed by the same etching process.

[0052] like Fig. 1IAs shown, because part of the upper portion of the isolation structure 114 is removed, the trench 128 further extends into the isolation structure 114 to form an extended trench 129 , so that the bottom surface of each spacer 120 is not flush with (eg, higher than) the bottom surface of the extended trench 129 .

[0053] like Figure 1J As shown, according to some embodiments, after removing the upper portion of the isolation structure 114 to form the extension trench 129, a metal gate structure 130 is formed in the extension trench 129. In some embodiments, the metal gate structure 130 includes a gate dielectric layer 132, a work function metal layer 134, and a metal gate electrode layer 136.

[0054] In some embodiments, the gate dielectric layer 132 is made of a high-k dielectric material. Examples of high-k dielectric materials may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, or hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy.

[0055] According to some embodiments, a work function metal layer 134 is formed on the gate dielectric layer 132. The work function metal layer 134 is tailored to have a suitable work function. For example, if a P-type work function metal (P-metal) for a PMOS device is desired, TiN, WN, or W may be used. On the other hand, if an N-type work function metal (N-metal) for an NMOS device is desired, TiAl, TiAlN, or TaCN may be used.

[0056] According to some embodiments, a metal gate electrode layer 136 is formed over the work function metal layer 134. In some embodiments, the metal gate electrode layer 136 is made of a conductive material such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. The gate dielectric layer 132, the work function metal layer 134, and the metal gate electrode layer 136 can be formed by any suitable process to any suitable thickness.

[0057] It should be noted that additional layers such as liner layers, interfacial layers, seed layers, adhesion layers, barrier layers, etc. may be formed over and / or under the gate dielectric layer 132, the work function metal layer 134, and the metal gate electrode layer 136. Furthermore, the gate dielectric layer 132, the work function metal layer 134, and the metal gate electrode layer 136 may include more than one layer made of various materials.

[0058] like Figure 1J As shown, the metal gate structure 130 is formed to cross the fin structure 110 and extend over the isolation structure 114. More specifically, the metal gate structure 130 includes a first portion 130a formed over the fin structure 110 and a second portion 130b formed over the isolation structure 114. Because the upper portion of the isolation structure 114 is removed so that the extension trench 129 can extend into the isolation structure 114, the second portion 130b of the metal gate structure 130 formed over the extension trench 129 also extends into the isolation structure 114. Therefore, the second portion 130a of the metal gate structure 130 has a second height H2 greater than the first height H1 of the spacer 120.

[0059] More specifically, the second portion 130b includes an extension portion 130c extending into the isolation structure 114. The formation of the extension portion 130c can expand the effective area of ​​the metal gate structure 130 and / or can be used to adjust the electrical properties of the semiconductor structure 100. Figure 1J As shown, the extension portion 130c has a thickness T1, which can also be defined as the difference between the first height H1 and the second height H2. In some embodiments, the thickness T1 of the extension portion 130c is about to about Although the formation of the extension portion 130c can expand the effective area of ​​the structure, if the extension portion 130c is too thick, the risk of leakage can also be increased.

[0060] The thickness T1 of the extension portion 130c can be adjusted by changing the etching time of the isolation structure 114. In some embodiments, the thickness T1 of the extension portion 130c is about to about In some embodiments, the thickness T1 of the extension portion 130c is about to about In some embodiments, the thickness T1 of the extension portion 130c is about to about In some embodiments, the thickness T1 of the extension portion 130c is about to about In some embodiments, the thickness T1 of the extension portion 130c is about to about The extension portion 130c having different thicknesses may have different electrical properties, and thus the thickness T1 of the extension portion 130c may be adjusted according to its application. In some embodiments, the bottom surface of the gate structure 130 is substantially flush with or lower than the bottom surface of the fin structure 110. Optionally, the bottom surface of the gate structure 130 is higher than the bottom surface of the fin structure 110.

[0061] FIG. 2A to FIG. 2B is a cross-sectional view of various stages of forming a semiconductor structure 100' according to some embodiments. Methods and materials for forming the semiconductor structure 100' and Figures 1A to 1J The methods and materials used to form the semiconductor structure 100 are similar or identical to those described in , except that the extended portion of the metal gate structure further extends underneath the spacer.

[0062] More specifically, implementation Figures 1A to 1H The process shown in FIG. 1 is a process for performing a multi-functional circuit, and the details are not repeated here. Figure 2A As shown, according to some embodiments, after removing the dummy gate structure 118 , the trench 128 is further extended into the isolation structure 114 to form an extended trench 129 ′ by etching the dielectric layer 116 and the isolation structure 114 .

[0063] and Fig. 1I Similarly, first portion 116a of dielectric layer 116 exposed by trench 128 and upper portion of isolation structure 114 below first portion 116a of dielectric layer 116 are removed. In addition, second portion 116b of dielectric layer 116 and some portions of isolation structure 114 below spacer 120 are also removed.

[0064] According to some embodiments, Figure 2A As shown, after the etching process, the extension trench 129' further extends to below the spacer 120, so that the metal gate structure 130' formed in the extension trench 129' also extends to below the spacer 120, as shown in FIG. Figure 2B In some embodiments, the metal gate structure 130' is Figure 1J The metal gate 130 shown is similar and includes a gate dielectric layer 132 , a work function metal layer 134 , and a metal gate electrode layer 136 .

[0065] like Figure 2B As shown, the metal gate structure 130' is formed to cross the fin structure 110 and extend above the isolation structure 114. More specifically, the metal gate structure 130' includes a first portion 130a' formed above the fin structure 110 and a second portion 130b' formed above the isolation structure 114. In addition, the second portion 130b' further includes an extension portion 130c' extending into the isolation structure 114 and extending to below the spacer 120.

[0066] More specifically, the extension portion 130c' extends to a position below the spacer 120 such that a portion of the extension portion 130c' overlaps the spacer 120. In some embodiments, the portion of the extension portion 130c' that overlaps the spacer 120 has a width of about 100 mm. to about The formation of the extension portion 130c' extending to a position below the spacer 120 can expand the effective area of ​​the structure. However, if the width W' is too large, the risk of bridging may also increase.

[0067] like Figure 2B As shown, the width of the extension portion 130c' is greater than the width of the first portion 130a' of the metal gate structure 130' formed above the fin structure 110. In some embodiments, the first portion 130a' of the metal gate structure 130' has a first width W1', and the extension portion 130c' of the metal gate structure 130' has a second width W2' greater than the first width W1'. In some embodiments, the difference between the first width W1' and the second width W2' is about to about The electrical performance can be adjusted by changing the second width W2' of the extending portion 130c'. However, if the second width W2' of the extending portion 130c' is too large, the risk of leakage may increase.

[0068] With Figure 1J Similar to the example shown, the second portion 130a' of the metal gate structure 130 has a second height H2' that is greater than the first height H1 of the spacer 120. In addition, the extension portion 130c' has a thickness T1', which can also be defined as a difference between the first height H1' and the second height H2'. In some embodiments, the thickness T1' of the extension portion 130c' is in a range similar to or the same as the range of the thickness T1 of the extension portion 130c described above.

[0069] FIG. 3A to FIG. 3B is a cross-sectional view of various stages of forming a semiconductor structure 100 ″ according to some embodiments. The methods and materials used to form the semiconductor structure 100 ″ are similar or identical to the methods and materials used to form the semiconductor structures 100 and 100 ′ described above, except that the second portion of the dielectric layer formed under the spacer is completely removed and the extension portion extends to under the spacer.

[0070] More specifically, implementation Figures 1A to 1H The process shown in FIG. 1 is a process for performing a multi-functional circuit, and the details are not repeated here. Figure 3AAs shown, according to some embodiments, after removing the dummy gate structure 118 , by etching the dielectric layer 116 and the isolation structure 114 , the trench 128 is further extended into the isolation structure 114 to form an extended trench 129 ″.

[0071] and Fig. 1I Similar to the example shown in FIG. 1 , the first portion 116a of the dielectric layer 116 exposed by the trench 128 and the upper portion of the isolation structure 114 located below the first portion 116a of the dielectric layer 116 are removed. In addition, the second portion 116b of the dielectric layer 116 and the portion of the isolation structure 114 located below the spacer 120 are also removed. That is, in the embodiment, the dielectric layer 116 is completely removed. Figure 1F Dielectric layer 116 is shown.

[0072] like Figure 3A As shown, after the etching process, Figure 3B As shown, according to some embodiments, the extension trench 129 ″ further extends below the spacer 120, and a metal gate structure 130 ″ is formed in the extension trench 129 ″. In some embodiments, the metal gate structure 130 ″ is Figure 1J The metal gate structure 130 shown is similar and includes a gate dielectric layer 132 , a work function metal layer 134 , and a metal gate electrode layer 136 .

[0073] like Figure 3B As shown, the metal gate structure 130" is formed to span the fin structure 110 and extend above the isolation structure 114. More specifically, the metal gate structure 130" includes a first portion 130a" formed above the fin structure 110 and a second portion 130b" formed above the isolation structure 114. In addition, the second portion 130b" further includes an extension portion 130c" extending into the isolation structure 114 and extending below the spacer 120.

[0074] like Figure 3B As shown, the second portion of the dielectric layer 116 formed under the spacer 120 is completely removed, and the portion of the extension portion 130c' overlapping the spacer 120 has a width W" substantially equal to the width of the spacer 120. In some embodiments, the width W" of the portion of the extension portion 130c' overlapping the spacer 120 is about to about in the range between.

[0075] In some embodiments, the first portion 130a" of the metal gate structure 130" has a first width W1", and the extended portion 130c" of the metal gate structure 130" has a second width W2" greater than the first width W1". In some embodiments, the difference between the first width W1" and the second width W2" is about to about in the range between.

[0076] and Figure 1J Similar to the example shown, the second portion 130a" of the metal gate structure 130 has a second height H2", which is greater than the first height H1 of the spacer 120. In addition, the extension portion 130c" has a thickness T1", which can also be defined as the difference between the first height H1 and the second height H2". In some embodiments, the range of the thickness T1" of the extension portion 130c" is similar to or the same as the range of the thickness T1 of the aforementioned extension portion 130c.

[0077] In planar transistors, electrical properties can be controlled by implantation. However, for finFET transistors, it is difficult to control electrical properties by implantation. Therefore, in some embodiments of the present invention, metal gate structures such as metal gate structures 130, 130' and 130" are used to adjust the electrical properties of the structure.

[0078] More specifically, a metal gate structure is formed in a "gate last" process. That is, a dummy gate structure 118 is formed to span the fin structure 110 and extend above the isolation structure 114, and a spacer 120 is formed on the sidewalls of the dummy gate structure 118. Thereafter, a portion of the dummy gate structure 118 and the isolation structure 114 are removed to form extension trenches, such as extension trenches 129, 129', and 129". Therefore, the metal gate structure formed in the extension trench may have an extension portion extending into the isolation structure 114, such as extension portions 130c, 130c', and 130c".

[0079] The extension portion of the metal gate structure provides a larger effective area for the metal gate structure and thus can improve the performance of a semiconductor structure such as a FinFET structure. In addition, the extension portion can also be used to adjust the electrical properties of the semiconductor structure. In some embodiments, the extension portion such as the extension portion 130' and 130" further extends to a position below the spacer 120 to have a larger effective area. That is, the size of the extension portion can be adjusted according to its application.

[0080] It should be noted that although a relatively tall metal gate structure can also be formed by forming a tall dummy gate structure, the process of forming the tall dummy gate structure may face very great challenges. For example, a fin with a high aspect ratio should be formed and a large amount of insulating layer should be etched to form a shallow trench isolation structure. These processes may result in poor uniformity and may reduce the yield of manufacturing the structure.

[0081] On the other hand, by using Figures 1A to 3BThe process described can form a metal gate structure with a relatively large height without using the above-mentioned process. Therefore, the uniformity of the manufactured structure can be improved. In addition, the above-mentioned method can be implemented in the present manufacturing process without using additional complex processes such as masks or alignment. Therefore, the metal gate structures 130, 130' and 130" can be formed without changing or affecting other manufacturing processes. Therefore, the performance of the semiconductor structures 100, 100' and 100" can be improved and the yield can be increased.

[0082] Embodiments of a semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a fin structure and an isolation structure formed around the fin structure. A gate structure is formed to span the fin structure and extend over the isolation structure. In addition, the gate structure includes an extension portion extending into the isolation structure, so that the effective area of ​​the structure is increased. Therefore, the electrical properties of the semiconductor structure can be adjusted by the extension portion of the gate structure, and the performance and uniformity of the semiconductor structure can be improved.

[0083] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a fin structure formed above the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed above the fin structure and a second portion formed above the isolation structure, and the second portion of the gate structure includes an extension portion extending into the isolation structure.

[0084] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a fin structure formed above the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure and extending above the isolation structure. The semiconductor structure further includes a spacer formed on a sidewall of the gate structure. In addition, a portion of the spacer formed on the sidewall of the gate structure above the isolation structure has a first height, and a portion of the gate structure formed above the isolation structure has a second height greater than the first height.

[0085] In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a fin structure above a substrate and forming an isolation structure around the fin structure above the substrate. The method for manufacturing a semiconductor structure further includes forming a dummy gate structure across the fin structure. The method for manufacturing a semiconductor structure further includes forming a spacer on a sidewall of the dummy gate structure. The method for manufacturing a semiconductor structure further includes removing the dummy gate structure to form a trench between the spacers. The method for manufacturing a semiconductor structure further includes removing a portion of the isolation structure to form an extended trench extending into the isolation structure and forming a gate structure in the extended trench, wherein a portion of the gate structure extends into the isolation structure.

[0086] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be easily used as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: substrate; a fin structure formed above the substrate and extending vertically in a vertical direction, wherein the fin structure includes a source / drain structure and a fin middle portion located between the source / drain structures, and the source / drain structure is configured as a part of the fin structure; an isolation structure formed around a bottom of the fin structure; Gate structure; a spacer formed on a sidewall of the gate structure, wherein the spacer and the gate structure are formed across the middle of the fin, and a bottom surface of the spacer is higher than a top surface of the isolation structure; an interlayer dielectric layer formed beside the spacer and covering the top surface and sidewalls of the source / drain structure; and A dielectric layer, located between the spacer and the fin structure, wherein the bottom surface of the dielectric layer is flush with the bottom surface of the spacer and is higher than the top surface of the isolation structure; an etch stop layer located on the fin structure on a side of the spacer opposite to the gate structure and extending downwardly along a side of the spacer beyond a bottom surface of the spacer and the dielectric layer to a top surface of the isolation structure; The gate structure includes a first portion formed above the top of the fin structure and a second portion formed above the isolation structure, and the second portion of the gate structure includes an extension portion that is lower than the bottom surface of the spacer and extends into the isolation structure. Wherein, the extension portion also extends laterally to be directly below the spacer and the dielectric layer so that the extension portion is in direct contact with the bottom surfaces of the spacer and the dielectric layer, and the extension portion is in contact with the side surface of the etching stop layer, and the side surface of the extension portion is flush with the side surface of the etching stop layer.

2. The semiconductor structure according to claim 1, wherein: The extension of the second portion of the gate structure has a to Thickness within the range.

3. The semiconductor structure according to claim 1, wherein: The spacer does not extend into the isolation structure.

4. The semiconductor structure according to claim 3, wherein: A bottom surface of the spacer is not flush with a bottom surface of the second portion of the gate structure over the isolation structure.

5. The semiconductor structure according to claim 3, wherein: The spacer has a first height, and the second portion of the gate structure has a second height greater than the first height.

6. The semiconductor structure according to claim 3, wherein: The dielectric layer is in direct contact with the etch stop layer.

7. The semiconductor structure according to claim 1, wherein: The first portion of the gate structure has a first width, and the extension of the second portion of the gate structure has a second width greater than the first width.

8. The semiconductor structure according to claim 7, wherein: The difference between the first width and the second width is to within the range.

9. The semiconductor structure according to claim 1, wherein: The etch stop layer is also formed between the interlayer dielectric layer and the top surface and sidewalls of the source / drain structure.

10. The semiconductor structure according to claim 1, wherein: The extension portion protrudes beyond the source / drain structure in the direction in which the gate structure extends and extends to directly under the spacer, but does not extend directly under and between the source / drain structures.

11. The semiconductor structure according to claim 10, wherein: Each layer constituting the gate structure extends to below the spacer, and the layers constituting the gate structure include a gate dielectric layer formed as the lowermost layer of the gate structure.

12. A semiconductor structure comprising: substrate; a fin structure formed above the substrate and extending vertically in a vertical direction, wherein the fin structure includes a source / drain structure and a fin middle portion located between the source / drain structures, and the source / drain structure is configured as a part of the fin structure; an isolation structure formed around a bottom of the fin structure; a gate structure; and a spacer formed on a sidewall of the gate structure, wherein the spacer and the gate structure are formed across the middle of the fin, and a bottom surface of the spacer is higher than a top surface of the isolation structure; an interlayer dielectric layer formed beside the spacer and covering the top surface and sidewalls of the source / drain structure; and A dielectric layer is disposed between the spacer and the fin structure, wherein a bottom surface of the dielectric layer is flush with a bottom surface of the spacer and is higher than a top surface of the isolation structure; an etch stop layer located on the fin structure on a side of the spacer opposite to the gate structure and extending downwardly along a side of the spacer beyond a bottom surface of the spacer and the dielectric layer to a top surface of the isolation structure; wherein a portion of the spacer formed above the isolation structure and on the sidewall of the gate structure has a first height, and a portion of the gate structure formed above the isolation structure has a second height greater than the first height, the portion constituting the gate structure includes an extension portion that is lower than the bottom surface of the spacer and extends to below the spacer, and a portion on the sidewall of the gate structure extends to be lower than the bottom surface of the interlayer dielectric layer on the sidewall of the source / drain structure, The extension portion also extends laterally to be directly below the spacer and the dielectric layer so that the extension portion is in direct contact with the bottom surfaces of the spacer and the dielectric layer, and the extension portion is in contact with the side of the etch stop layer, and the side of the extension portion is flush with the side of the etch stop layer.

13. The semiconductor structure according to claim 12, wherein: The difference between the first height and the second height is to within the range.

14. The semiconductor structure according to claim 12, wherein: The dielectric layer is in direct contact with the etch stop layer.

15. The semiconductor structure according to claim 12, wherein: The extending portion of the gate structure protrudes beyond the source / drain structure in the direction in which the gate structure extends and extends to directly under the spacer but does not extend directly under the source / drain structure and between the source / drain structure.

16. A method for manufacturing a semiconductor structure, comprising: forming a fin structure over the substrate; forming an isolation structure around a bottom of the fin structure above the substrate; forming a dielectric layer covering the fin structure and the isolation structure, forming a dummy gate structure over the dielectric layer and spanning the fin structure; forming a spacer on the sidewall of the dummy gate structure, wherein the bottom surface of the spacer is higher than the top surface of the isolation structure; removing the dielectric layer not covered by the dummy gate structure and the spacer to form an epitaxially grown source / drain structure in the fin structure, wherein the epitaxially grown source / drain structure is configured as a part of the fin structure; Form an etch stop layer beside the spacer and along the side of the spacer to the top surface of the isolation structure, and form an interlayer dielectric layer beside the spacer and covering the top surface and sidewall of the source / drain structure and the etch stop layer; removing the dummy gate structure to form a trench between the spacers exposing a first portion of the dielectric layer; Removing a portion of the isolation structure and the first portion of the dielectric layer to form an extension trench extending into the isolation structure, the extension trench extending laterally on the sidewall of the fin structure to directly under the spacer and exposing the bottom surface of the spacer, but not extending directly under the source / drain structure and between the source / drain structure, so that the bottom surface of the dielectric layer is flush with the bottom surface of the spacer and higher than the top surface of the isolation structure, the extension trench also extends laterally to expose the side of the etch stop layer so that the side of the extension trench is flush with the side of the etch stop layer, and the second portion of the retained dielectric layer is disposed between the spacer and the fin structure; as well as A gate structure filling the extension trench is formed in the extension trench, wherein each layer constituting the gate structure extends to below the spacer, and each layer constituting the gate structure includes a gate dielectric layer formed as the lowest layer of the gate structure, The bottom surface of the dielectric layer is higher than the bottom surface of the gate dielectric layer, and the gate dielectric layer of the gate structure is in direct contact with the dielectric layer and the spacer.

17. The method for manufacturing a semiconductor structure according to claim 16, wherein: The spacer over the isolation structure has a first height and the gate structure over the isolation structure has a second height greater than the first height.

18. The method for manufacturing a semiconductor structure according to claim 16, wherein: The dielectric layer is in direct contact with the etch stop layer.

19. The method for manufacturing a semiconductor structure according to claim 18, further comprising: A portion of the second portion is removed after removing the dummy gate structure.

20. The method for manufacturing a semiconductor structure according to claim 16, wherein: Forming a gate structure in the extended trench further comprises: depositing the gate dielectric layer over the bottom and side surfaces of the extension trench; depositing a work function metal layer over the gate dielectric layer; and A metal gate electrode layer is deposited over the work function metal layer.

Images