Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods for manufacturing the same. A method includes: forming a hard mask over an epitaxial layer of a substrate; forming a patterned mask over the hard mask; etching the hard mask and the epitaxial layer to form a trench in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the trench exposes the sidewall of the epitaxial layer; forming a P-well region by directing a p-type ion beam into the trench along an inclined direction that is not parallel to a normal line of the uppermost surface of the epitaxial layer, wherein during the directing of the p-type ion beam into the trench, the uppermost surface of the epitaxial layer is protected from the p-type ion beam by the remaining portion of the hard mask; and after directing the p-type ion beam into the trench, forming a gate structure in the trench.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Such advances have increased the complexity and challenges of IC processing and manufacturing.

[0003] Vertically conductive trench MOSFETs (metal oxide semiconductor field effect transistors) can be used as power electronic devices. When the trench MOSFET is in the on state, current flows vertically between the source region and the substrate. Reducing the cell pitch of the MOSFET is crucial to reducing the device size and increasing the number of active devices on a semiconductor chip. In addition, the cell pitch also affects the device performance, such as the resistivity (Rdson) between the source and the drain when the device is turned on. Reducing the cell pitch is limited by manufacturing process technology, such as the ability of lithography tools to resolve minimum critical dimensions and align different patterned layers. In this context, the following disclosure is proposed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; forming a patterned mask over the hard mask; etching the hard mask and the epitaxial layer using the patterned mask as an etching mask to form a groove in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the groove exposes the sidewall of the epitaxial layer; forming a P-well region by guiding a p-type ion beam into the trench along an inclined direction that is not parallel to a normal to the uppermost surface of the epitaxial layer, wherein during guiding the p-type ion beam into the trench, the uppermost surface of the epitaxial layer is protected from the influence of the p-type ion beam by the remaining portion of the hard mask; and forming a gate structure in the trench after guiding the p-type ion beam into the trench.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; etching the hard mask and the epitaxial layer through an opening to form a groove in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the groove exposes the sidewall of the epitaxial layer; depositing a first oxide layer over the epitaxial layer and overfilling the trench; etching back the first oxide layer until the sidewall of the epitaxial layer is exposed by the trench; forming a second oxide layer, the second oxide layer covering the sidewall of the epitaxial layer exposed by the trench; after forming the second oxide layer, forming a P-well region in the epitaxial layer; removing the remaining portion of the hard mask, the first oxide layer and the second oxide layer; and forming a gate structure in the trench.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate having a semiconductor region and an epitaxial layer located above the semiconductor region; a first gate structure and a second gate structure, which are arranged in the epitaxial layer, the first gate structure and the second gate structure having a circular bottom surface, wherein the epitaxial layer has a P-well region laterally located between the first gate structure and the second gate structure, and the dopant concentration in the P-well region varies along a direction from the first gate structure to the second gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 14 are cross-sectional views of semiconductor devices at various fabrication stages according to some embodiments of the present disclosure.

[0009] Fig.15A and Fig. 15B A method for forming a semiconductor device according to some embodiments of the present disclosure is provided.

[0010] Fig.16 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figures 17 to 23 are cross-sectional views of semiconductor devices at various fabrication stages according to some embodiments of the present disclosure.

[0012] Fig.24 A method for forming a semiconductor device according to some embodiments of the present disclosure is provided. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] Figures 1 to 14 are cross-sectional views of semiconductor devices at various fabrication stages according to some embodiments of the present disclosure.

[0016] refer to Figure 1 The semiconductor region 102 is provided as a part of the semiconductor substrate 100. The semiconductor region 102 may have a crystalline silicon structure. Alternatively, the semiconductor region 102 may be formed of other semiconductor materials such as silicon germanium. In some embodiments, the semiconductor region 102 is a heavily doped layer doped with n-type impurities such as phosphorus or arsenic, for example, with an impurity concentration of about 10 19 / cm 3 and about 10 21 / cm 3 In the described embodiments, the term "heavily doped" refers to a concentration greater than about 10 19 / cm 3 However, those skilled in the art will recognize that "heavily doped" is a technical term that depends on the specific device type, technology generation, minimum feature size, etc. Therefore, it is intended that the term be interpreted according to the technology being evaluated and is not limited to the described embodiments.

[0017] Above the heavily doped semiconductor region 102, the semiconductor substrate 100 further includes an epitaxial layer 104. The epitaxial layer 104 is formed by epitaxy and is lightly doped with n-type impurities. The impurity concentration of the epitaxial layer 104 may be about 10 15 / cm 3 and about 10 18 / cm 3 As a result, the impurity concentration of epitaxial layer 104 is lower than the impurity concentration of semiconductor region 102. In some embodiments, epitaxial layer 104 may be a crystalline silicon layer, although other semiconductor materials may be used.

[0018] Then, a pad oxide layer 110 and a hard mask 112 are formed over the epitaxial layer 104. In some embodiments, the pad oxide layer 110 is formed by thermally oxidizing the top region of the epitaxial layer 104, and thus the pad oxide layer 110 may include silicon oxide (SiO2). The hard mask 112 may be formed of silicon nitride such as Si3N4, and may be formed by a suitable process such as CVD, PVD, ALD, or other suitable processes.

[0019] Then, a patterned mask M1 is formed on the hard mask 112. In some embodiments, the patterned mask M1 has a plurality of openings O1, which define the locations of gate structures to be formed in subsequent steps (eg, Figure 10-Figure 14 In some embodiments, the patterned mask M1 is a photoresist and can be formed by a photolithography process.

[0020] refer to Figure 2 . The pad oxide layer 110, the hard mask 112, and the epitaxial layer 104 are etched through the opening O1 of the patterned mask M1, thereby forming a plurality of trenches T1 in the epitaxial layer 104. In more detail, the hard mask 112 is patterned using the patterned mask M1 as an etching mask. Then, the pad oxide layer 110 and the epitaxial layer 104 are patterned using the hard mask 112 as an etching mask. In some embodiments, the pad oxide layer 110, the hard mask 112, and the epitaxial layer 104 may be etched using dry etching, wet etching, or a combination thereof. In some embodiments, each trench T1 has a circular bottom surface. Alternatively, each trench T1 has a U-shaped cross-sectional profile. In some embodiments, the bottommost end of the trench T1 is separated from the semiconductor region 102.

[0021] refer to Figure 3. The patterned mask M1 is removed by an appropriate process (e.g., stripping). Then, an oxide layer 120 is deposited over the hard mask 112 and fills the trench T1. In some embodiments, the oxide layer 120 completely fills the trench T1. That is, there is no portion of the trench T1 that is not filled by the oxide layer 120. In some embodiments, the oxide layer 120 is made of SiO2. In some embodiments, the oxide layer 120 can be formed by CVD, PVD, ALD, flowable CVD, or other suitable deposition processes.

[0022] refer to Figure 4 . The oxide layer 120 is etched back to lower the top surface of the oxide layer 120. The remaining oxide layer 120 remains in the lower portion of the trench T1. For example, the oxide layer 120 is lowered so that the uppermost surface of the remaining oxide layer 120 is lower than the uppermost surface of the epitaxial layer 104. In other words, the remaining portion of the oxide layer 120 is disposed at the bottom of the trench T1. The oxide layer 120 may be etched using dry etching, wet etching, or a combination thereof. In some other embodiments, before etching back the oxide layer 120, a chemical mechanical polishing (CMP) process is performed on the oxide layer 120 to make the top surface of the oxide layer 120 flush with the top surface of the hard mask 112. In some embodiments, after the etch back process, the maximum height H1 of the oxide layer 120 is in the range of about 0.5 μm to about 3.5 μm.

[0023] refer to Figure 5A . An oxide layer 130 is deposited over the hard mask 112 and on the sidewalls of the trench T1. In some embodiments, the oxide layer 130 is conformal with the hard mask 112, the pad oxide layer 110, and the epitaxial layer 104. As a result, the oxide layer 130 is formed by a conformal deposition process (e.g., CVD or ALD) for a duration short enough to form a conformal layer without filling the trench T1. In some embodiments in which both the oxide layer 120 and the oxide layer 130 are formed by CVD, the deposition time of the oxide layer 120 may be longer than the deposition time of the oxide layer 130 because the oxide layer 120 is deposited to completely fill the trench T1 (see Figure 3 ), while the oxide layer 130 is a thin layer that conforms to the underlying structure. As a result, Figure 3 The thickness of the oxide layer 120 is greater than Figure 5A The oxide layer 130 in the embodiment is thicker. In some embodiments, the oxide layer 130 is made of SiO2. Figure 5A In some embodiments, oxide layers 120 and 130 are made of the same material, and thus there is no distinguishable interface between oxide layers 120 and 130. In some cases where oxide layers 120 and 130 are made of different materials, oxide layers 120 and 130 may include a distinguishable interface therebetween.

[0024] refer to Figure 5B . Figure 5B Shown with Figure 5A In other embodiments different from the embodiments of the present invention, an oxide layer 131 is selectively formed on the surface of the epitaxial layer 104 exposed by the trench T1. In some embodiments, the oxide layer 131 may be formed via a thermal oxidation process. In this way, the oxide layer 131 may have a faster growth rate on the exposed surface of the epitaxial layer 104 than on the hard mask 112. In some embodiments, the surface of the hard mask 112 is not covered by the oxide layer 131. That is, after the oxide layer 131 is formed, the surface of the hard mask 112 remains exposed.

[0025] refer to Fig. 6A and Figure 6B ,in, Fig. 6A follow Figure 5A An embodiment of Figure 6B follow Figure 5B A directional implantation process is performed to form a plurality of P-well regions 140 in the epitaxial layer 104 , wherein directional ions are directed to the epitaxial layer 104 at an oblique angle relative to a vertical direction of an uppermost surface of the epitaxial layer 104 . Fig. 6A and Figure 6B The dotted arrows in FIG. 1 represent ion beams incident on epitaxial layer 104. In more detail, the ion beams are guided from the sidewalls of epitaxial layer 104 through trench T1 to epitaxial layer 104, while hard mask 112 blocks the incident ion beams so that the ion beams cannot reach the top surface of epitaxial layer 104.

[0026] In some embodiments, the directional implantation process may be performed, for example, by: implanting the first side of the trench T1 (eg, Fig. 6A and Figure 6B The first directional ions I1 are directed to the epitaxial layer 104 at a first angle A1 in a range of about 30° to about 60°, thereby forming a portion of the P-well region 140 in the epitaxial layer 104 through the first side of the trench T1. Here, the angle A1 represents the angle between the incident direction of the first directional ions I1 and the normal to the uppermost surface of the epitaxial layer 104. After the first directional ions I1 are directed, the first directional ions I1 are directed to the epitaxial layer 104 through the second side (for example, the first side) of the trench T1 (opposite to the first side of the trench T1). Fig. 6A and Figure 6BThe first deposition angle A1 and the second deposition angle A2 are formed at the right side of the trench T1 in the epitaxial layer 104 at a second angle A2 in the range of about 30° to about 60° to guide the second directional ions I2 to the epitaxial layer 104, thereby forming the other part of the P-well region 140 in the epitaxial layer 104 via the second side of the trench T1. Here, the angle A2 represents the angle between the incident direction of the second directional ions I2 and the normal to the uppermost surface of the epitaxial layer 104. In some embodiments, the first deposition angle A1 and the second deposition angle A2 have substantially the same value but opposite directions. In some embodiments, if the first angle A1 and the second angle A2 are too small (e.g., much less than 30°), the trajectory of the ions may be too steep and therefore fail to reach the desired lateral depth in the epitaxial layer 104. On the other hand, if the first angle A1 and the second angle A2 are too large (e.g., much greater than 60°), the trajectory of the ions may be too horizontal and therefore blocked by the hard mask 112.

[0027] In some embodiments, after the directional implantation process, the epitaxial layer 104 has an undoped region 1042 that is laterally adjacent to the P-well region 140. This is because the directional ions I1 and I2 cannot reach the undoped region 1042 from the sidewall of the epitaxial layer 104. For example, Fig. 6A and Figure 6B As shown in the region S1 in FIG. 1 (drawn in dotted lines), the region S1 is a region of the epitaxial layer 104 located between two adjacent trenches T1 (and / or Figures 10 to 14 1042 is located between two adjacent gate structures). As shown, the undoped region 1042 is laterally located between the two P-well regions 140. In some embodiments, the uppermost end of the undoped region 1042 is substantially flush with the uppermost surface of the epitaxial layer 104. In other words, after the directional implantation process, the uppermost surface of the region S1 of the epitaxial layer 104 is at least partially undoped. In some embodiments, the region S1 has a higher dopant concentration on its opposite sides than in its middle. For example, the middle portion of the region S1 (e.g., the undoped region 1042) is free of the dopant of the P-well region 140.

[0028] In some embodiments, Fig. 6A and Figure 6B The oxide layers 130 and 131 are used as protective layers (eg, shielding layers) of the epitaxial layer 104 during the directional implantation process, and are used to perform implantation shielding and reduce channeling during the directional implantation process. Fig. 6A and Figure 6B In some embodiments where the oxide layers 130 and 131 are missing, the sidewalls of the epitaxial layer 104 may be exposed by the trench T1, and thus the ions I1 and I2 may directly attack the exposed sidewalls of the epitaxial layer 104 and may cause defects in the epitaxial layer 104. Accordingly, Fig. 6A and Figure 6BThe oxide layers 130 and 131 may protect the epitaxial layer 104 by suppressing defects in the epitaxial layer 104 caused by the directional implantation process described herein.

[0029] In some embodiments, the oxide layer 120 may also act as a mask to block the ions I1 and I2, thereby preventing the ions I1 and I2 from reaching the unwanted regions of the epitaxial layer 104, and thus the height H1 of the oxide layer 120 affects the vertical depth of the P-well region 140. As described above, the height H1 of the oxide layer 120 is in the range of about 0.5 μm to about 3.5 μm. In some embodiments, if the height H1 of the oxide layer 120 is too low, the P-well region 140 may be too long in the vertical direction; if the height H1 of the oxide layer 120 is too large, the P-well region 140 may be too short in the vertical direction.

[0030] In some embodiments of the present disclosure, the hard mask 112 is used to pattern the epitaxial layer 104 to form the trench T1 in the epitaxial layer 104. Then, the same hard mask 112 can be used to form the P-well region 140 in the epitaxial layer 104 by performing a directional implantation process. In some embodiments, all of the P-well regions 140 are formed in the region below the hard mask 112, and thus the P-well regions 140 can be considered to be substantially self-aligned with the hard mask 112. However, in some embodiments in which the P-well region is formed in a subsequent step (e.g., after removing the hard mask 112), an additional mask can be applied to define the position of the P-well region in the epitaxial layer 104. Accordingly, embodiments of the present disclosure provide a method for forming a self-aligned P-well region, and can also save costs.

[0031] refer to Figure 7 . Remove Fig. 6A The hard mask 112, the pad oxide 110, the oxide layer 120 and the oxide layer 130 (and Figure 6B In some embodiments, the hard mask 112, the pad oxide 110, the oxide layer 120, and the oxide layer 130 (or the oxide layer 131) can be removed by a suitable etching process such as dry etching, wet etching, or a combination thereof. After the etching process, the uppermost surface of the epitaxial layer 104 is exposed. In some embodiments, after the etching process, the undoped region 1042 is exposed.

[0032] refer to Fig. 8A . An annealing process is performed to Figure 7 The P-well region 140 is redistributed to form a P-well region 142. In more detail, an annealing process is performed to laterally diffuse Figure 7 For example, as shown in the region S1 between two adjacent trenches T1, Figure 7The dopant in the P-well region 140 is diffused into Figure 7 The undoped region 1042 is transformed into the doped region 1044, such as Fig. 8A In other words, after the annealing process, the uppermost surface of the epitaxial layer 104 in the region S1 is a fully doped region. In some embodiments, the annealing process may be performed at a temperature between about 800° C. and about 1200° C. for about 30 minutes to about 240 minutes.

[0033] refer to Figure 8B ,in, Figure 8B It is shown Fig. 8A FIG. 5 is a graph showing the dopant concentration distribution in region S1. Figure 8B The vertical axis is the dopant concentration, and Figure 8B The horizontal axis is Fig. 8A The lateral position of the region S1 in (eg, from the left trench T1 to the right trench T1). Figure 8B As shown, the dopant concentration varies laterally in region S1. In more detail, region S1 has a dopant concentration that varies laterally in region S1 on its opposite side (which is close to Fig. 8A The trench T1 in the region S1 has a higher dopant concentration. This is because the dopant is initially driven into the region S1 from the opposite side of the region S1. Fig. 6A and Figure 6B As shown. On the other hand, because the annealing process diffuses the dopant from the opposite side of the region S1 to the middle of the region S1, the dopant concentration at the middle of the region S1 is lower than the dopant concentration at the opposite side of the region S1. This characteristic can be found at the uppermost surface of the region S1. That is, the dopant concentration varies along the uppermost surface of the region S1 of the epitaxial layer 104.

[0034] refer to Fig. 9 . A gate dielectric layer 150 is deposited conformally to the epitaxial layer 104. The gate dielectric layer 150 lines the trench T1. The gate dielectric layer 150 may be an oxide layer, for example, silicon oxide, silicon dioxide (SiO2). In some embodiments, the gate dielectric layer 150 may be formed by a suitable process such as CVD, ALD, or a thermal oxidation process. In some embodiments in which the gate dielectric layer 150 is formed by a thermal oxidation process, the temperature during the thermal oxidation process may be high enough to cause Fig. 6A and Figure 6B The diffusion of the P-well region 140 shown in FIG. 1 and the redistribution of dopants in the P-well region 140 to form the P-well region 142 may be caused. Fig. 8A and Figure 8B In this way, in some embodiments, Fig. 8A and Figure 8B The annealing process described in can be skipped as long as Fig. 9The temperature of the thermal oxidation process is high enough to cause dopant redistribution. In this case (e.g., skipping Fig. 8A and Figure 8B annealing process discussed in Fig. 9 The temperature of the thermal oxidation process is high enough to cause redistribution of dopants, Fig. 9 The area S1 in can still have Figure 8B Similar dopant concentration profiles as discussed in .

[0035] refer to Fig.10 The gate electrode layer 160 is deposited over the gate dielectric layer 150 and fills the trench T1. In some embodiments, the gate electrode layer 160 may be polysilicon. In some embodiments, the gate electrode layer 160 may be doped polysilicon. In some embodiments, the gate electrode layer 160 is formed by thermally decomposing silane (SiH4) in a low-pressure process chamber. The gate electrode layer 160 is formed to have a thickness that fills the trench T1.

[0036] refer to Fig.11 A chemical mechanical polishing (CMP) process is performed to remove excess gate electrode layer 160 (see Fig.10 ) and the gate dielectric layer 150 until the epitaxial layer 104 is exposed. After the CMP process, the remaining portion of the gate electrode layer 160 in the trench T1 may be referred to as a gate electrode 162, and the remaining portion of the gate dielectric layer 150 in the trench T1 may be referred to as a gate dielectric 152. In some embodiments, within each trench T1, the gate electrode 162 and the gate dielectric 152 may be collectively referred to as a gate structure 170.

[0037] refer to Fig.12 . A patterned mask M2 is formed over the epitaxial layer 104. In some embodiments, the patterned mask M2 has an opening O2 that exposes the top surface of the gate structure 170 and a portion of the epitaxial layer 104 adjacent to the gate structure 170. On the other hand, a portion of the epitaxial layer 104 is covered by the patterned mask M2. Then, an implantation process is performed to form a plurality of N+ source regions 180 in the exposed portion of the epitaxial layer 104 through the opening O2. The N+ source region 180 may be referred to as a heavily doped N+ region 180.

[0038] In some embodiments, Fig.12The implantation process includes directing ions I3 to the epitaxial layer 104. In some embodiments, the incident direction of the ions I3 is substantially perpendicular to the top surface of the epitaxial layer 104. That is, the incident direction of the ions I3 is substantially aligned with the normal to the top surface of the epitaxial layer 104. In some other embodiments, the angle between the incident direction of the ions I3 and the normal to the top surface of the epitaxial layer 104 is in the range of about 0° to about 7°. In the depicted embodiment, because the gate structure 170 is not covered by the patterned mask M2, at least the uppermost portion of the gate structure 170 may be unintentionally doped with the ions I3. In some other embodiments, the gate structure 170 is covered by the patterned mask M2 so that the gate structure 170 will not be doped with the ions I3.

[0039] As mentioned above about Fig. 6A and Figure 6B As discussed, the directional ions I1 and I2 are incident on the epitaxial layer 104 at an oblique angle. In some embodiments, Fig.12 The ion I3 and Fig. 6A and Figure 6B ions I1 and I2 described in FIG. 1 are more perpendicular to the top surface of epitaxial layer 104 than those described in FIG. Fig.12 The angle between the incident direction of the ions I3 and the normal to the top surface of the epitaxial layer 104 is less than Fig. 6A and Figure 6B The angle between the incident direction of the ions I1 and I2 and the normal to the top surface of the epitaxial layer 104 is .

[0040] refer to Fig.13 . The patterned mask M2 is removed, and a patterned mask M3 is formed over the epitaxial layer 104. In some embodiments, the patterned mask M3 has an opening O3 that exposes a portion of the epitaxial layer 104. On the other hand, the N+ source region 180 and the gate structure 170 are covered by the patterned mask M3. Then, an implantation process is performed to form a plurality of P+ body regions in the exposed portion of the epitaxial layer 104 through the opening O3. In some embodiments, the dopant concentration in the P+ body region 190 is higher than the dopant concentration in the P-well region 142.

[0041] In some embodiments, Fig.13 The implantation process includes directing ions I4 to the epitaxial layer 104. In some embodiments, the incident direction of the ions I4 is substantially perpendicular to the top surface of the epitaxial layer 104. That is, the incident direction of the ions I4 is substantially aligned with the normal to the top surface of the epitaxial layer 104. In some other embodiments, the angle between the incident direction of the ions I4 and the normal to the top surface of the epitaxial layer 104 is in the range of about 0° to about 7°.

[0042] As mentioned above about Fig. 6A and Figure 6BAs discussed, the directional ions I1 and I2 are incident on the epitaxial layer 104 at an oblique angle. In some embodiments, Fig.13 The ratio of ions I4 Fig. 6A and Figure 6B ions I1 and I2 described in FIG. 1 are more perpendicular to the top surface of epitaxial layer 104 than those described in FIG. Fig.13 The angle between the incident direction of the ion I4 and the normal to the top surface of the epitaxial layer 104 is less than Fig. 6A and Figure 6B The angle between the incident direction of the ions I1 and I2 and the normal to the top surface of the epitaxial layer 104 is .

[0043] refer to Fig.14 The patterned mask M3 is removed. Thus, the semiconductor device 10 is formed. In some embodiments, the semiconductor device 10 is a metal oxide silicon field effect transistor (MOSFET) device. Because the gate structure 170 is formed in the trench T1 of the epitaxial layer 104, the semiconductor device 10 may also be referred to as a trench MOSFET. In some other embodiments, the semiconductor device 10 may also be referred to as a UMOS (U-shaped trench MOSFET).

[0044] Note that the P-well region 142 has a portion 142T, wherein the portion 142T of the P-well region 142 is Fig.12 and Fig.13 The P-well region 142 is protected by the patterned masks M2 and M3 during the process of the semiconductor device 10. In some embodiments, a portion 142T of the P-well region 142 is located in the terminal region 10T of the semiconductor device 10. The terminal region 10T can be regarded as a region located at the boundary of the semiconductor device 10. Typically, this region of the semiconductor device 10 does not have a circuit function, and therefore the portion 142T of the P-well region 142 located in this region does not experience Fig.12 and Fig.13 On the other hand, other parts within the cell region 10C of the semiconductor device 10 may undergo an implantation process. Fig.12 and Fig.13 The cell region 10C may be regarded as a region of the semiconductor device 10 that performs certain functional operations.

[0045] Fig.15A and Fig. 15BA manufacturing method 1000 according to some embodiments of the present disclosure is shown. Although method 1000 is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions can be performed in an order different from the illustrated order, and / or the actions can be performed simultaneously. In addition, in some embodiments, the illustrated actions or events can be subdivided into multiple actions or events, which can be performed at separate times, or performed simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events can be omitted, and other unillustrated actions or events can be included.

[0046] At block S101 , a pad oxide layer, a hard mask layer, and a first patterned mask are formed over an epitaxial layer of a substrate. Figure 1 A schematic diagram of some embodiments corresponding to the actions in block S101 is shown.

[0047] At block S102 , the pad oxide layer, the hard mask, and the epitaxial layer are etched to form trenches in the epitaxial layer. Figure 2 A schematic diagram of some embodiments corresponding to the actions in block S102 is shown.

[0048] At block S103 , the first patterned mask is removed, and a first oxide layer is deposited over the hard mask layer and fills the trenches of the epitaxial layer. Figure 3 A schematic diagram of some embodiments corresponding to the actions in block S103 is shown.

[0049] At block S104 , the first oxide layer is etched back. Figure 4 A schematic diagram of some embodiments corresponding to the actions in block S104 is shown.

[0050] At block S105 , a second oxide layer is deposited on the sidewalls of the trenches of the epitaxial layer. Figure 5A and Figure 5B A schematic diagram of some embodiments corresponding to the actions in block S105 is shown.

[0051] At block S106 , a directional implantation process is performed to form a plurality of P-well regions in the epitaxial layer. Fig. 6A and Figure 6B A schematic diagram of some embodiments corresponding to the actions in block S106 is shown.

[0052] At block S107 , the hard mask layer, the pad oxide, the first oxide layer, and the second oxide layer are removed. Figure 7 A schematic diagram of some embodiments corresponding to the actions in block S107 is shown.

[0053] At block S108, an annealing process is performed to redistribute the P-well region. Fig. 8 shows a schematic diagram of some embodiments corresponding to the action in block S108.

[0054] At block S109 , a gate dielectric layer is deposited in the trenches of the epitaxial layer. Fig. 9 A schematic diagram of some embodiments corresponding to the actions in block S109 is shown.

[0055] At block S110 , a gate electrode layer is deposited over the gate dielectric layer and fills the trenches of the epitaxial layer. Fig.10 A schematic diagram of some embodiments corresponding to the actions in block S110 is shown.

[0056] At block S111 , a chemical mechanical polishing (CMP) process is performed to remove excess gate electrode layers and gate dielectric layers to form a gate structure. Fig.11 A schematic diagram of some embodiments corresponding to the actions in block S111 is shown.

[0057] At block S112 , a second patterned mask is formed over the epitaxial layer, and a first implantation process is performed to form an N+ source region in the epitaxial layer. Fig.12 A schematic diagram of some embodiments corresponding to the actions in block S112 is shown.

[0058] At block S113 , the second patterned mask is removed, a third patterned mask is formed over the epitaxial layer, and a second implantation process is performed to form a P+ body region in the epitaxial layer. Fig.13 A schematic diagram of some embodiments corresponding to the actions in block S113 is shown.

[0059] At block S114 , the third patterned mask is removed. Fig.14 A schematic diagram of some embodiments corresponding to the actions in block S114 is shown.

[0060] refer to Fig.16 . Fig.16 are semiconductor devices according to some embodiments of the present disclosure. Fig.16 Semiconductor devices and Fig.14 The difference between semiconductor devices in Fig.16 The semiconductor region 202 in the embodiment is a P-type region. In some embodiments, the semiconductor region 202 is a heavily doped layer doped with p-type impurities such as boron (B), gallium (Ga), indium (In), aluminum (Al), etc., for example, with an impurity concentration of about 10 19 / cm 3 and about 10 21 / cm 3In the described embodiments, the term "heavily doped" refers to a concentration greater than about 10 19 / cm 3 impurity concentration. Fig.16 The semiconductor device in can be regarded as an insulated gate bipolar transistor (IGBT). In some embodiments, Fig.16 Some components of Figures 1 to 14 Those elements described in , and therefore such elements are labeled the same and will not be repeated for the sake of brevity.

[0061] Figures 17 to 23 are cross-sectional views of semiconductor devices at various fabrication stages according to some embodiments of the present disclosure.

[0062] refer to Fig.17 . Fig.17 The structure is similar to Fig. 8A and Figure 8B The structure described in . Fig.17 Some components of Fig. 8A Elements of the present invention are the same or similar, and therefore such elements are labeled the same, and structural details will not be repeated for the sake of brevity. Fig.17 and Fig. 8A The difference is that the trench T2 of the epitaxial layer 104 is larger than Fig. 8A In some embodiments, Fig.17 The P-well region 142 is connected to Figures 3 to 8B The present invention is formed by the same or similar methods as described in the above, and therefore the relevant details will not be repeated.

[0063] refer to Fig.18 . A gate dielectric layer 300 is formed over the epitaxial layer 104 and in the trench T2. The gate dielectric layer 300 lines the trench T2. The gate dielectric layer 300 may be an oxide layer, for example, silicon oxide, silicon dioxide (SiO2). In some embodiments, the gate dielectric layer 300 may be formed by a suitable process such as CVD, ALD, or a thermal oxidation process. In some embodiments, based on device optimization for low Rds and high breakdown voltage, the gate dielectric layer 300 is grown to have a desired thickness. The thick gate dielectric layer 300 reduces the silicon surface electric field, thereby allowing the use of higher doping and producing lower Rds for the same breakdown rating.

[0064] refer to Fig.19. A plurality of gate electrodes 310 are formed in the trenches T2 and over the gate dielectric layer 300. In some embodiments, the gate electrodes 310 may be polysilicon. In some embodiments, the gate electrodes 310 may be formed, for example, by depositing a blanket gate electrode layer over the epitaxial layer 104 and filling the trenches T2, and then lowering the top surface of the gate electrode layer by an etch-back process using an etchant that etches the gate electrode material (e.g., polysilicon) at a faster etch rate than etching the gate dielectric material (e.g., silicon oxide). In some embodiments, an etch-back process is performed on the gate electrode layer so that the top surface of the gate electrode 310 is lower than the topmost surface of the epitaxial layer 104. In some other embodiments, an etch-back process is performed on the gate electrode layer so that the top surface of the gate electrode 310 is lower than the bottommost end of the P-well region 142.

[0065] refer to Fig. 20 . Portions of the gate dielectric layer 300 are removed using, for example, wet etching until the top surface and sidewalls of the epitaxial layer 104 located in the area not sealed by the gate electrode 310 are clean. In some embodiments, the etching process is performed so that the portion of the gate dielectric layer 300 located within the lower portion of the trench T2 is not etched. That is, after the etching process, at least a portion of the gate dielectric layer 300 remains between the gate electrode 310 and the epitaxial layer 104. The etching process can be, for example, a selective etching process using an etchant (e.g., diluted HF) that etches the gate dielectric material (e.g., silicon oxide) without etching the epitaxial material (e.g., single crystal silicon) and the gate electrode material (e.g., polycrystalline silicon) in the layer 104.

[0066] refer to Fig.21 A gate dielectric layer 320 is formed over the gate electrode 310 and along the exposed surface of the epitaxial layer 104. In some embodiments, the gate dielectric layer 320 is formed to cover and seal the gate electrode 310. In some embodiments, the gate electrode 310 may be interchangeably referred to as a bottom shield electrode 310. In some embodiments, the gate dielectric layer 320 is formed to cover and seal the gate electrode 310. Fig.18 The gate dielectric layer 300 formed in the gate trench is thinner. The thin gate dielectric layer 320 on the gate trench sidewalls provides the advantage of reducing the gate threshold voltage.

[0067] refer to Fig. 22. A plurality of gate electrodes 330 are formed in the trenches T2 of the epitaxial layer 104. In some embodiments, the gate electrode 330 may be polysilicon. In some embodiments, the gate electrode 330 may be formed, for example, by depositing a blanket gate electrode layer over the epitaxial layer 104 and filling the trenches T2, and then removing the excess gate electrode layer by a CMP process until the top surface of the epitaxial layer 104 is exposed. In some embodiments, in each trench T2, the remaining gate dielectric layer 300, the gate electrode 310, the remaining gate dielectric layer 320, and the gate electrode 330 may be collectively referred to as a gate structure 340.

[0068] refer to Fig.23 An N+ source region 180 and a P+ body region 190 are formed in the epitaxial layer 104, and a semiconductor device 20 is formed. In some embodiments, Fig.23 The semiconductor device 20 may be referred to as a shielded gate trench (SGT) FET. Typically, the SGT FET includes a shield electrode (e.g., gate electrode 310) below a gate electrode (e.g., gate electrode 330). The shield gate (e.g., gate electrode 310) and the gate electrode (e.g., gate electrode 330) are insulated from each other by a dielectric layer (e.g., gate dielectric layer 320) serving as an inter-electrode dielectric.

[0069] In some embodiments, the semiconductor device 20 includes a cell region 20C and a terminal region 20T. Fig.14 The cell region 10C and the terminal region 10T of the semiconductor device 10 described in the embodiment are similar. The N+ source region 180 and the P+ body region 190 are connected to the Figure 12 to Figure 14 Similar or identical methods are formed as discussed in the present invention, and therefore the relevant details will not be repeated for the sake of brevity.

[0070] Fig.24 It is a method for forming a semiconductor device according to some embodiments of the present disclosure. Although method 2000 is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions may be performed in an order different from the illustrated order, and / or the actions may be performed simultaneously. In addition, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

[0071] In some embodiments, some operations may be performed before block 201 of method 2000, such as in Figures 1 to 8B The operations described in blocks S101 to 108 of . Accordingly, Fig.17An initial structure of box 201 of method 2000 is shown.

[0072] At block S201 , a first gate dielectric layer is formed over the epitaxial layer and in the trenches of the epitaxial layer. Fig.18 A schematic diagram of some embodiments corresponding to the actions in block S201 is shown.

[0073] At block S202 , a plurality of first gate electrodes are formed in the trenches and over the first gate dielectric layer. Fig.19 A schematic diagram of some embodiments corresponding to the actions in block S202 is shown.

[0074] At block S203 , a portion of the first gate dielectric layer 300 is removed to expose a surface of the epitaxial layer. Fig. 20 A schematic diagram of some embodiments corresponding to the actions in block S203 is shown.

[0075] At block S204 , a second gate dielectric layer is formed over the first gate electrode and along the exposed surface of the epitaxial layer. Fig.21 A schematic diagram of some embodiments corresponding to the actions in block S204 is shown.

[0076] At block S205 , a plurality of second gate electrodes are formed in the trenches of the epitaxial layer. Fig. 22 A schematic diagram of some embodiments corresponding to the actions in block S205 is shown.

[0077] At block S206 , an N+ source region and a P+ body region are formed in the epitaxial layer. Fig.23 A schematic diagram of some embodiments corresponding to the actions in block S206 is shown.

[0078] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages in this article, and specific advantages are not required for all embodiments. One advantage is that the hard mask layer is used to pattern the epitaxial layer to form a groove in the epitaxial layer. Then, the same hard mask layer can be used to form a P-well region in the epitaxial layer by a directional implantation process. The P-well region is formed in the region of the epitaxial layer below the hard mask layer, and therefore the P-well region can be considered to be substantially self-aligned with the hard mask layer, and therefore the additional mask for defining the position of the P-well region can be omitted, which will reduce process costs and process time.

[0079] In some embodiments of the present disclosure, a method includes: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; forming a patterned mask over the hard mask; using the patterned mask as an etching mask to etch the hard mask and the epitaxial layer to form a trench in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the trench exposes the sidewall of the epitaxial layer; forming a P-well region in the trench by directing a p-type ion beam into the trench along an inclined direction that is not parallel to a normal to the uppermost surface of the epitaxial layer, wherein the uppermost surface of the epitaxial layer is protected from the p-type ion beam by the remaining portion of the hard mask during the directing of the p-type ion beam into the trench; and forming a gate structure in the trench after directing the p-type ion beam into the trench.

[0080] In some embodiments of the present disclosure, a method includes: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; etching the hard mask and the epitaxial layer through an opening to form a trench in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the trench exposes the sidewalls of the epitaxial layer; depositing a first oxide layer over the epitaxial layer and overfilling the trench; etching back the first oxide layer until the sidewalls of the epitaxial layer are exposed by the trench; forming a second oxide layer covering the sidewalls of the epitaxial layer exposed by the trench; after forming the second oxide layer, forming a P-well region in the epitaxial layer; removing the remaining portion of the hard mask, the first oxide layer, and the second oxide layer; and forming a gate structure in the trench.

[0081] In some embodiments of the present disclosure, a semiconductor device includes a substrate, a first gate structure, and a second gate structure. The substrate has a semiconductor region and an epitaxial layer located above the semiconductor region. The first gate structure and the second gate structure are arranged in the epitaxial layer, and the first gate structure and the second gate structure have a circular bottom surface, wherein the epitaxial layer has a P-well region laterally located between the first gate structure and the second gate structure, and the dopant concentration in the P-well region changes along the direction from the first gate structure to the second gate structure.

[0082] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0083] Example 1. A method for manufacturing a semiconductor device, comprising: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; forming a patterned mask over the hard mask; using the patterned mask as an etching mask to etch the hard mask and the epitaxial layer to form a groove in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the groove exposes the sidewall of the epitaxial layer; forming a P-well region by directing a p-type ion beam into the trench along an inclined direction that is not parallel to a normal to the uppermost surface of the epitaxial layer, wherein during the directing of the p-type ion beam into the trench, the uppermost surface of the epitaxial layer is protected from the influence of the p-type ion beam by the remaining portion of the hard mask; and after directing the p-type ion beam into the trench, forming a gate structure in the trench.

[0084] Example 2. The method according to Example 1 further includes: before forming the gate structure in the trench, removing the remaining portion of the hard mask to expose the uppermost surface of the epitaxial layer.

[0085] Example 3. The method of Example 1, wherein the P-well region is located directly below the remaining portion of the hard mask.

[0086] Example 4. The method according to Example 1 further includes: before directing the p-type ion beam, forming a first oxide layer in the bottom of the trench, wherein an upper portion of the sidewall of the epitaxial layer remains exposed after forming the first oxide layer.

[0087] Example 5. The method according to Example 4 further includes: after forming the first oxide layer and before directing the p-type ion beam, forming a second oxide layer covering an upper portion of the sidewall of the epitaxial layer.

[0088] Example 6. The method of Example 5 further includes: removing the first oxide layer and the second oxide layer after directing the p-type ion beam.

[0089] Example 7. The method according to Example 1 further includes: after forming the gate structure, directing an n-type ion beam from the uppermost surface of the epitaxial layer to the epitaxial layer to form an n-type source region in the epitaxial layer.

[0090] Example 8. A method according to Example 7, wherein a first angle between the tilt direction of the p-type ion beam and the normal to the uppermost surface of the epitaxial layer is greater than a second angle between the incident direction of the n-type ion beam and the normal to the uppermost surface of the epitaxial layer.

[0091] Example 9. The method according to Example 1 further includes: performing an annealing process on the P-well region before forming the gate structure.

[0092] Example 10. A method for manufacturing a semiconductor device, comprising: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; etching the hard mask and the epitaxial layer through an opening to form a groove in the epitaxial layer, wherein the remaining portion of the hard mask covers the uppermost surface of the epitaxial layer and the groove exposes the sidewall of the epitaxial layer; depositing a first oxide layer over the epitaxial layer and overfilling the trench; etching back the first oxide layer until the sidewall of the epitaxial layer is exposed by the trench; forming a second oxide layer, the second oxide layer covering the sidewall of the epitaxial layer exposed by the trench; after forming the second oxide layer, forming a P-well region in the epitaxial layer; removing the remaining portion of the hard mask, the first oxide layer and the second oxide layer; and forming a gate structure in the trench.

[0093] Example 11. The method of Example 10, wherein depositing the first oxide layer is performed so that the first oxide layer has a first thickness, forming the second oxide layer is performed so that the second oxide layer has a second thickness, and the first thickness is greater than the second thickness.

[0094] Example 12. The method of Example 10, wherein forming the second oxide layer is performed such that the second oxide layer extends from a top surface of the remaining portion of the hard mask to the sidewalls of the epitaxial layer.

[0095] Example 13. The method of Example 10, wherein the second oxide layer is formed by oxidizing the sidewalls of the epitaxial layer.

[0096] Example 14. A method according to Example 10, wherein forming the P-well region in the epitaxial layer includes: directing a p-type ion beam to the epitaxial layer at an inclined angle relative to a normal to the uppermost surface of the epitaxial layer, wherein the P-well region is formed below a remaining portion of the hard mask.

[0097] Example 15. The method of Example 14, wherein the remaining portion of the hard mask prevents the ion beam from reaching the uppermost surface of the epitaxial layer.

[0098] Example 16. The method of Example 14, wherein the inclination angle is in the range of about 30° to about 60°.

[0099] Example 17. A method according to Example 10, wherein forming the gate structure includes: forming a gate dielectric in the trench, wherein the gate dielectric is formed by a thermal oxidation process and a profile of the P-well region after the thermal oxidation process is different from a profile of the P-well region before the thermal oxidation process; and forming a gate electrode above the gate dielectric.

[0100] Example 18. A semiconductor device, comprising: a substrate having a semiconductor region and an epitaxial layer located above the semiconductor region; a first gate structure and a second gate structure, arranged in the epitaxial layer, the first gate structure and the second gate structure having a circular bottom surface, wherein the epitaxial layer has a P-well region laterally located between the first gate structure and the second gate structure, and the dopant concentration in the P-well region varies along a direction from the first gate structure to the second gate structure.

[0101] Example 19. A semiconductor device according to Example 18, wherein, along the direction from the first gate structure to the second gate structure, the P-well region: has a first dopant concentration at a first side of the P-well region close to the first gate structure; has a second dopant concentration at a second side of the P-well region close to the second gate structure; and has a third dopant concentration in the middle of the P-well region, wherein the first dopant concentration and the second dopant concentration are higher than the third dopant concentration.

[0102] Example 20. The semiconductor device according to Example 19 further includes: a plurality of heavily doped N-type regions located above the first side and the second side of the P-well region; and a heavily doped P-type region located above the middle portion of the P-well region.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; forming a patterned mask over the hard mask; etching the hard mask and the epitaxial layer using the patterned mask as an etch mask to form a trench in the epitaxial layer, wherein a remaining portion of the hard mask covers an uppermost surface of the epitaxial layer and the trench exposes a sidewall of the epitaxial layer; forming a first oxide layer in a bottom portion of the trench, wherein an upper portion of the sidewall of the epitaxial layer remains exposed after forming the first oxide layer; forming a P-well region by directing a p-type ion beam into the trench along an inclined direction that is non-parallel to a normal to the uppermost surface of the epitaxial layer, wherein the uppermost surface of the epitaxial layer is protected from the p-type ion beam by the remaining portion of the hard mask during directing the p-type ion beam into the trench; and After directing the p-type ion beam into the trench, a gate structure is formed in the trench.

2. The method according to claim 1, further comprising: Prior to forming the gate structure in the trench, the remaining portion of the hard mask is removed to expose the uppermost surface of the epitaxial layer.

3. The method according to claim 1, wherein: The P-well region is located directly below the remaining portion of the hard mask.

4. The method according to claim 1, further comprising: After forming the first oxide layer and before directing the p-type ion beam, a second oxide layer is formed, the second oxide layer covering an upper portion of the sidewall of the epitaxial layer.

5. The method according to claim 4, further comprising: After directing the p-type ion beam, the first oxide layer and the second oxide layer are removed.

6. The method according to claim 1, further comprising: After forming the gate structure, an n-type ion beam is directed from the uppermost surface of the epitaxial layer to the epitaxial layer to form an n-type source region in the epitaxial layer.

7. The method according to claim 6, wherein: A first angle between an inclined direction of the p-type ion beam and a normal to the uppermost surface of the epitaxial layer is greater than a second angle between an incident direction of the n-type ion beam and a normal to the uppermost surface of the epitaxial layer.

8. The method according to claim 1, further comprising: Before forming the gate structure, an annealing process is performed on the P-well region.

9. A method for manufacturing a semiconductor device, comprising: forming a hard mask over an epitaxial layer of a substrate, wherein the epitaxial layer has N-type impurities; etching the hard mask and the epitaxial layer through the opening to form a trench in the epitaxial layer, wherein a remaining portion of the hard mask covers an uppermost surface of the epitaxial layer and the trench exposes a sidewall of the epitaxial layer; depositing a first oxide layer over the epitaxial layer and overfilling the trench; Etching back the first oxide layer until the sidewall of the epitaxial layer is exposed by the trench; forming a second oxide layer, wherein the second oxide layer covers the sidewall of the epitaxial layer exposed by the trench; After forming the second oxide layer, forming a P-well region in the epitaxial layer; removing the remaining portion of the hard mask, the first oxide layer, and the second oxide layer; and A gate structure is formed in the trench.

10. The method according to claim 9, wherein: Depositing the first oxide layer is performed such that the first oxide layer has a first thickness, forming the second oxide layer is performed such that the second oxide layer has a second thickness, and the first thickness is greater than the second thickness.

11. The method according to claim 9, wherein: Forming the second oxide layer is performed such that the second oxide layer extends from a top surface of the remaining portion of the hard mask to the sidewalls of the epitaxial layer.

12. The method according to claim 9, wherein: The second oxide layer is formed by oxidizing the sidewall of the epitaxial layer.

13. The method according to claim 9, wherein: Forming the P-well region in the epitaxial layer includes directing a p-type ion beam to the epitaxial layer at an oblique angle relative to a normal to the uppermost surface of the epitaxial layer, wherein the P-well region is formed below a remaining portion of the hard mask.

14. The method according to claim 13, wherein: The remaining portion of the hard mask prevents the ion beam from reaching the uppermost surface of the epitaxial layer.

15. The method according to claim 13, wherein: The inclination angle is in the range of 30° to 60°.

16. The method according to claim 9, wherein: Forming the gate structure includes: forming a gate dielectric in the trench, wherein the gate dielectric is formed by a thermal oxidation process, and a profile of the P-well region after the thermal oxidation process is different from a profile of the P-well region before the thermal oxidation process; and A gate electrode is formed over the gate dielectric.

17. A semiconductor device comprising: A substrate having a semiconductor region and an epitaxial layer located above the semiconductor region; A first gate structure and a second gate structure are disposed in the epitaxial layer, the first gate structure and the second gate structure having a circular bottom surface, wherein: The epitaxial layer has a P-well region laterally located between the first gate structure and the second gate structure, and a dopant concentration in the P-well region varies along a direction from the first gate structure to the second gate structure; Wherein, along the direction from the first gate structure to the second gate structure, the P-well region: having a first dopant concentration at a first side of the P-well region proximate to the first gate structure; having a second dopant concentration at a second side of the P-well region proximate to the second gate structure; and A third dopant concentration is provided at a middle portion of the P-well region, wherein the first dopant concentration and the second dopant concentration are higher than the third dopant concentration.

18. The semiconductor device according to claim 17, further comprising: a plurality of heavily doped N-type regions located above the first side and the second side of the P-well region; as well as The heavily doped P-type region is located above the middle portion of the P-well region.

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