Semiconductor structure and method for forming the same

Abstract

A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and a first side of a second interposer, respectively, wherein the first interposer is laterally adjacent to the second interposer; sealing the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposite to the first side of the first interposer; forming a second recess in a second side of the second interposer opposite to the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material. Embodiments of the present invention also relate to semiconductor structures.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, the increase in integration density comes from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area.

[0003] As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative semiconductor die packaging technologies. An example of such a packaging system is a stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is a chip on wafer on substrate (CoWoS) structure. In some embodiments, in order to form a CoWoS structure, a plurality of semiconductor chips are attached to a wafer, and then a cutting process is performed to separate the wafer into a plurality of interposers, each of which has one or more semiconductor chips attached. The interposer with semiconductor chips attached is called a chip on wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form a CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and a smaller footprint. Summary of the invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising: respectively bonding a first tube core and a second tube core to a first side of a first interposer and a first side of a second interposer, wherein the first interposer is laterally adjacent to the second interposer; sealing the first interposer and the second interposer with a first molding material; forming a first groove in a second side of the first interposer opposite to the first side of the first interposer; forming a second groove in a second side of the second interposer opposite to the first side of the second interposer; and filling the first groove and the second groove with a first dielectric material.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising: attaching a first tube core and a second tube core to a first interposer and a second interposer, respectively, wherein, after the attachment, the first tube core is laterally adjacent to the second tube core, and the first interposer is laterally adjacent to the second interposer; surrounding the first interposer and the second interposer with a first molding material; forming a first groove in a first surface of the first interposer away from the first tube core; forming a second groove in a first surface of the second interposer away from the second tube core; and filling the first groove and the second groove with a polymer layer.

[0006] Yet another embodiment of the present invention provides a semiconductor structure comprising: a plurality of interposers laterally adjacent to each other and having through substrate vias (TSVs); a first molding material located around the plurality of interposers; at least one die bonded to and electrically connected to at least one of the plurality of interposers; and a dielectric layer located on the back side of the plurality of interposers away from the at least one die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1 to 9 Cross-sectional views of a chip-on-wafer (CoW) structure at various stages of fabrication in an embodiment are shown.

[0009] Fig.10 A cross-sectional view of a CoW structure in another embodiment is shown.

[0010] Fig.11 A cross-sectional view of a CoW structure in another embodiment is shown.

[0011] Fig.12 A cross-sectional view of a CoW structure in another embodiment is shown.

[0012] Figures 13 to 17 Cross-sectional views of a CoW structure at various stages of fabrication in another embodiment are shown.

[0013] Fig.18 A flow chart of a method of forming a semiconductor structure in some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. Throughout the specification, unless otherwise stated, the same reference numerals in different figures refer to the same or similar components formed by the same or similar methods using the same or similar materials.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] In some embodiments, a chip-on-wafer (CoW) structure is formed by forming a composite interposer and attaching a plurality of dies to the composite interposer. The composite interposer includes a first interposer and a second interposer embedded in a first molding material. A first redistribution structure may optionally be formed above the first molding material and above the first interposer and the second interposer. After attaching the plurality of dies to the composite interposer, a second molding material is formed around the plurality of dies. Next, each of the first interposer and the second interposer is thinned from a side away from the die. After the thinning process, for each of the first interposer and the second interposer, a groove is formed on a side away from the die, wherein the groove exposes an end of a through hole in the corresponding interposer (the first interposer or the second interposer). Next, a dielectric material (e.g., a polymer material) is formed in the groove. Subsequently, a dielectric layer is formed above the dielectric material, and an external connector is formed above the dielectric layer, and the external connector is electrically coupled to the through hole of the first interposer and the second interposer.

[0017] Figures 1 to 9 1 shows a cross-sectional view of a chip-on-wafer (CoW) structure 100 at various stages of fabrication in an embodiment. Figure 1, the two interposers 110 are attached to the carrier 150, for example, by an adhesive layer 151. The carrier 150 may be made of a suitable material, such as silicon, a polymer, a polymer composite, a metal foil, a ceramic, a glass, a glass epoxy, beryllium oxide, a tape, or other suitable materials for structural support. In some embodiments, the adhesive layer 151 is deposited or laminated over the carrier 150. The adhesive layer 151 may be photosensitive and may be easily separated from the carrier 150 by irradiating, for example, ultraviolet (UV) light on the carrier 150 in a subsequent carrier debonding process. For example, the adhesive layer 151 may be a light-to-heat conversion (LTHC) coating.

[0018] Each interposer 110 includes a substrate 101 , a through hole 103 (also referred to as a through hole, through substrate via (TSV) or conductive pillar) in the substrate 101 , a redistribution structure 107 on a first surface 101A of the substrate 101 , and a conductive pad 109 over and electrically coupled to the redistribution structure 107 . Figure 1 Also shown is an electronic component 105 formed in the substrate 101 (eg, near the first surface 101A).

[0019] The substrate 101 may be, for example, a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate. However, the substrate 101 may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide suitable protection and / or interconnection functions. In the illustrated embodiment, the substrate 101 is a silicon substrate (e.g., a bulk silicon substrate).

[0020] In some embodiments, substrate 101 includes electronic components 105, such as resistors, capacitors, signal distribution circuits, circuits designed to implement specific functions (e.g., signal processing functions or logic functions), combinations of these, etc. These electronic components can be active, passive, combinations of these, etc. In other embodiments, there are no active and passive electronic components in substrate 101. All such combinations are fully intended to be included within the scope of the present invention. In the illustrated embodiment, electronic components 105 such as deep trench capacitors (DTCs) are formed in substrate 101. Multiple DTCs can be formed and connected in parallel to provide large capacitance and significantly increase capacitance density, allowing the construction of various devices, such as higher quality power delivery networks (PDNs).

[0021] The via 103 extends from the first surface 101A of the substrate 101 toward but does not reach the second surface 101B of the substrate 101. In a subsequent substrate thinning process, the substrate 101 is thinned from the second surface 101B so that the via 103 is exposed at the second surface 101B (e.g., extends through the substrate 101). The via 103 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, alloys, combinations thereof, and the like. A barrier layer 104 may be formed between the via 103 and the substrate 101 (at Figure 1 Not shown, but in Fig. 9 ). The barrier layer 104 may include a suitable conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, etc. may alternatively be utilized. In some embodiments, the barrier layer 104 is formed of a dielectric material such as SiO2 or SiN. As an example, the width (e.g., diameter) of the through hole 103 is between about 2 μm and about 50 μm.

[0022] Still refer to Figure 1 , a redistribution structure 107 is formed above each interposer 110. The redistribution structure 107 includes conductive subcomponents, such as one or more layers of conductive lines and vias formed in one or more dielectric layers. Figure 1 The conductive subcomponents and dielectric layers of the redistribution structure 107 are not shown separately. In some embodiments, the redistribution structure 107 provides electrical connections between the vias 103, the electronic components 105, and the conductive pads 109.

[0023] In some embodiments, one or more dielectric layers of the redistribution structure 107 are formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron-doped phosphosilicate glass (BPSG), etc. The one or more dielectric layers may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or a combination thereof.

[0024] In some embodiments, the conductive subcomponents of the redistribution structure 107 include conductive lines and / or conductive vias formed of a suitable conductive material such as copper, titanium, tungsten, aluminum, etc. The conductive subcomponents may be formed by, for example, forming openings in a dielectric layer to expose the conductive subcomponents below, forming a seed layer over the dielectric layer and in the openings, forming a patterned photoresist having a designed pattern over the seed layer, plating (e.g., electroplating or chemically plating) a conductive material in the designed pattern and over the seed layer, and removing portions of the photoresist and seed layer on which the conductive material is not formed. Other methods of forming the conductive subcomponents of the redistribution structure 107 are possible and are fully intended to be included within the scope of the present invention.

[0025] Conductive pads 109 are formed over and electrically coupled to the conductive subcomponents of the redistribution structure 107. The conductive pads 109 may be of any suitable type, such as microbumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless nickel electroless palladium immersion gold (ENEPIG) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb, combinations of these, and the like.

[0026] exist Figure 1 In the example of FIG. 1 , the redistribution structure 107 is formed to have the same width W1 as the substrate 101 so that the sidewalls of the redistribution structure 107 are aligned with the corresponding sidewalls of the substrate 101 . In some embodiments, the width W1 is between about 1 mm and about 52 mm. Figure 1 Two interposers 110 are shown for forming the CoW structure 100 , but other numbers of interposers 110 may be used to form the CoW structure 100 as will be readily appreciated by those skilled in the art.

[0027] Next, in Figure 2 In the embodiment of the present invention, a molding material 108 is formed over a carrier 150 around an interposer 110, and a redistribution structure 112 is formed over the molding material 108 and the interposer 110. A conductive connector 114 is formed over the redistribution structure 112.

[0028] As an example, the molding material 108 may include an epoxy resin, an organic polymer, a polymer with or without a silica-based filler or a glass filler, or other materials. In some embodiments, the molding material 108 includes a liquid molding compound (LMC), which is a gel-type liquid when applied. When applied, the molding material 108 may also include a liquid or a solid. Optionally, the molding material 108 may include other insulating and / or sealing materials. In some embodiments, the molding material 108 is applied using a wafer-level molding process. The molding material 108 may be molded using, for example, compression molding, transfer molding, molded underfill (MUF), or other methods.

[0029] Next, in some embodiments, a curing process is used to cure the molding material 108. The curing process may include heating the molding material 108 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination thereof with a heating process. Alternatively, other methods may be used to cure the molding material 108. In some embodiments, a curing process is not included.

[0030] After forming the molding material 108, a planarization process, such as chemical and mechanical planarization (CMP), may be performed to remove excess portions of the molding material 108 so that the molding material 108 and the conductive pad 109 have coplanar upper surfaces. Figure 2 As shown, the molding material 108 surrounds the interposer 110 and is in physical contact with the sidewalls of the interposer 110 .

[0031] Next, a redistribution structure 112 is formed over the upper surface of the molding material 108 and electrically coupled to the conductive pads 109. The redistribution structure 112 includes one or more layers of conductive subcomponents 111 (e.g., conductive lines and vias) formed in one or more dielectric layers 113. The materials and formation methods of the redistribution structure 112 may be the same or similar to those of the redistribution structure 107, and thus the details will not be repeated. Figure 2 In the example of FIG. 1 , the redistribution structure 112 is formed to be coterminal (eg, have the same width) as the molding material 108 , such that sidewalls of the redistribution structure 112 are aligned with corresponding sidewalls of the molding material 108 . Figure 2 The redistribution structure 112 in FIG. 1 continuously extends from the interposer 110 on the left to the interposer 110 on the right.

[0032] Next, a conductive connector 114 is formed over the redistribution structure 112 and electrically coupled to the conductive subcomponent 111 of the redistribution structure 112. The conductive connector 114 may be of any suitable type, such as a microbump, a copper pillar, a copper layer, a nickel layer, a lead-free (LF) layer, an electroless nickel electroless palladium immersion gold (ENEPIG) layer, a Cu / LF layer, a Sn / Ag layer, Sn / Pb, a combination of these, etc. Figure 2 As shown, solder regions 115 may be formed over the conductive connectors 114 .

[0033] exist Figure 2 In the example of FIG. 1 , the interposer 110, the molding material 108, the redistribution structure 112, and the conductive connector 114 form a composite interposer 160, which is used as an interposer in the CoW structure 100. Since multiple interposers 110 are used to form the composite interposer 160, each interposer 110 may also be referred to as a chiplet interposer.

[0034] Next, in Figure 3In the embodiment, semiconductor die 121 (also referred to as die or integrated circuit (IC) die) is attached to conductive connector 114, for example, by a reflow process, so that die connector 117 of die 121 is bonded to corresponding conductive connector 114. In some embodiments, die 121 can be of different types. For example, one of die 121 can be a logic die, while another die 121 can be a memory die. In some embodiments, all die 121 are of the same type. Figure 3 In the example of FIG. 1 , one of the dies 121 (e.g., the middle die 121A) overlaps the interposer 110 on the left and overlaps the interposer 110 on the right. In other words, a first portion of the die 121A is within the lateral extent of the interposer 110 on the left, and a second portion of the die 121A is disposed within the lateral extent of the interposer 110 on the right.

[0035] Each die 121 includes a substrate, electronic components (e.g., transistors, resistors, capacitors, diodes, etc.) formed in / on the substrate, and an interconnect structure located above the substrate that connects the electronic components to form the functional circuitry of the die 121. The die 121 also includes a die connector 117 that provides electrical connection to the circuitry of the die 121.

[0036] The substrate of the die 121 can be a doped or undoped semiconductor substrate, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate includes a semiconductor material layer such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0037] The electronic components of die 121 include a variety of active devices (e.g., transistors) and passive devices (e.g., capacitors, resistors, inductors), etc. The electronic components of die 121 can be formed in or on the substrate of die 121 using any suitable method. The interconnect structure of die 121 includes one or more metallization layers (e.g., copper layers) formed in one or more dielectric layers, and is used to connect various electronic components to form functional circuits. In an embodiment, the interconnect structure is formed of alternating layers of dielectric and conductive material (e.g., copper), and can be formed by any suitable process (such as deposition, inlay, dual inlay, etc.).

[0038] One or more passivation layers may be formed over the interconnect structures of die 121 to provide a degree of protection for the underlying structures of die 121. The passivation layers may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations of these, etc. The passivation layers may be formed by a process such as chemical vapor deposition (CVD), but any suitable process may be utilized.

[0039] The conductive pad may be formed over the passivation layer and may extend through the passivation layer to make electrical contact with the interconnect structure of the die 121. The conductive pad may include aluminum, although other materials, such as copper, may alternatively be used.

[0040] Die connectors 117 of die 121 are formed on the conductive pads to provide conductive areas for electrically connecting to circuits of die 121. Die connectors 117 may be copper pillars, contact bumps such as microbumps, etc., and may include materials such as copper, tin, silver, or other suitable materials.

[0041] Next, in Figure 4 In the embodiment, an underfill material 119 is formed between the die 121 and the redistribution structure 112 of the composite interposer 160 and between adjacent dies 121. After the underfill material 119 is formed, a molding material 118 is formed over the redistribution structure 112 around the die 121.

[0042] The underfill material 119 may include a liquid epoxy resin that is dispensed into the gap between the die 121 and the redistribution structure 112 using, for example, a dispensing needle or other suitable dispensing tool, and then cured to harden. Figure 4 As shown, the underfill material 119 fills the gap between the die 121 and the redistribution structure 112. In some embodiments, the die 121 is attached to the redistribution structure 112 so that the gap between adjacent dies 121 is less than about 10 μm (e.g., ≤ 10 μm), so that the dispensed underfill material 119 can fill the gap between the sidewalls of the die 121 by capillary force. In other embodiments, the underfill material 119 is omitted.

[0043] Next, a molding material 118 is formed over the composite interposer 160 and around the die 121. The material and formation method of the molding material 118 may be the same or similar to the molding material 108, so the details are not repeated here. In some embodiments, the underfill material 119 is not formed, and a molded underfill (MUF) material is used as the molding material 118, which fills the gap between the die 121 and the composite interposer 160, and fills the gap between adjacent dies 121.

[0044] Next, in Figure 5 In Figure 4 The structure is flipped over, and the die 121 is attached to the carrier 153, for example, by the adhesive layer 152. The carrier 153 and the adhesive layer 152 may be the same or similar to the carrier 150 and the adhesive layer 151, respectively, so the details are not repeated. Next, the carrier 150 is removed by a carrier debonding process. The carrier debonding process may use any suitable process (such as etching, grinding, and mechanical stripping) to remove the carrier 150. In some embodiments, the carrier 150 is debonded by irradiating a laser or UV light over the surface of the carrier 150. The laser or UV light destroys the chemical bonds of the adhesive layer 151 bonded to the carrier 150, and then the carrier 150 can be easily debonded. The adhesive layer 151 can be removed by the carrier debonding process. In some embodiments, an additional cleaning process is performed to remove the adhesive layer 151.

[0045] After the carrier debonding process, a thinning process is performed to reduce the thickness of the substrate 101 and the thickness of the molding material 108. The thinning process may be any suitable process, such as a CMP process. The thinning process is performed from the second surface 101B of the substrate 101 exposed by removing the carrier 150. The thinning process continues until the through hole 103 is exposed. Therefore, after the thinning process, the through hole 103, the substrate 101, and the molding material 108 are Figure 5 Note that due to the thinning process, Figure 5 The distance between the first surface 101A and the second surface 101B of the substrate 101 (eg, the thickness of the substrate 101) is less than Figure 1 The distance in.

[0046] Next, in Figure 6 in Figure 5 A patterned mask layer 125, such as a photoresist layer, is formed over the structure. The patterned mask layer 125 is formed to cover (eg, completely cover) Figure 6 In some embodiments, the patterned mask layer 125 covers the upper surface of the molding material 108 in the patterned mask layer 125. In addition, the patterned mask layer 125 also covers the portion of the substrate 101 directly below the patterned mask layer 125 (e.g., the portion that is in physical contact with the molding material 108). In other words, in addition to covering the upper surface of the molding material 108, the patterned mask layer 125 also overlaps a portion of the substrate 101. In some embodiments, a distance W2 measured between a sidewall 125C of the patterned mask layer 125 (overlapping the substrate 101) and a nearest sidewall 101S of the substrate (in contact with the molding material 108) is between about 0 mm and about 10 mm (e.g., 0 mm<W2<10 mm).

[0047] Next, the portion of the substrate 101 (e.g., the upper layer) exposed by the opening of the patterned mask layer 125 is removed to form a groove 124 at the second surface 101B of the substrate 101. An etching process (such as anisotropic etching) may be performed to form the groove 124. The etching process may use an etchant that is selective to the material of the substrate 101 (e.g., has a high etching rate), so that the substrate 101 is etched without substantially corroding the through hole 103 and the barrier layer 104 (see Fig. 9 ). After the etching process is completed, the end of the through hole 103 is exposed by the groove 124. In other words, the end of the through hole 103 extends into the groove 124. Figure 6 A depth D of each groove 124 measured in a vertical direction between the second surface 101B of the substrate 101 and the bottom of the groove 124 is between about 0 μm and about 10 μm (eg, 0 μm<D<10 μm).

[0048] Next, in Figure 7 , a material 123 (e.g., a dielectric material) is formed in the groove 124, and the patterned mask layer 125 is removed. In an example embodiment, the material 123 is a polymer material, such as polyimide, and is formed by a suitable formation method, such as spin coating. In addition to polymer materials, other suitable dielectric materials, such as SiN or SiO2, may also be used to form the material 123 by any suitable formation method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The material 123 may overfill the groove 124 and may be formed above the molding material 108, and therefore, a planarization process such as CMP may be performed to remove an excess portion of the material 123 so that the material 123, the substrate 101, the through hole 103, and the molding material 108 are flat. Figure 7 As an example, after the planarization process, the thickness T1 of the material 123 may be between 0 μm and about 5 μm (eg, 0 μm < T1 < 5 μm). Figure 7 As shown, material 123 is embedded in substrate 101 (e.g., silicon substrate) and has a width W3 (measured along the horizontal direction) that is smaller than the width W1 of substrate 101. In the illustrated embodiment, material 123 covers (e.g., surrounds) the sidewalls of the ends of through-hole 103. In some embodiments, by forming material 123 using a relatively inexpensive formation method (e.g., spin coating), a subsequent isolation deposition process, such as a CVD process with a high vacuum degree to form a SiN layer around through-hole 103, is avoided, thereby avoiding the higher cost of the high vacuum CVD process.

[0049] Next, in Figure 8In the embodiment, a redistribution structure 126 is formed over material 123, substrate 101, and molding material 108, after which a polymer layer 128 is formed over redistribution structure 126. External connectors 127 are formed over polymer layer 128 and are electrically coupled to vias 103.

[0050] In some embodiments, the redistribution structure 126 includes one or more dielectric layers and conductive subcomponents (eg, conductive lines, vias) formed in the one or more dielectric layers using the same or similar formation methods as the redistribution structure 112. Figure 8 The redistribution structure 126 may be shown as a single layer in the and subsequent figures, while it is understood that the redistribution structure 126 may have one or more layers of conductive subcomponents formed in one or more dielectric layers. In some embodiments, the redistribution structure 126 is omitted, and the polymer layer 128 is formed directly on (e.g., in contact with) the material 123. The polymer layer 128 is formed of the same polymer material as the material 123, such as polyimide, but in some embodiments, the polymer layer 128 may be formed of a different polymer material than the material 123. The polymer layer 128 may serve as a passivation layer for the CoW structure 100. As an example, the thickness of the polymer layer 128 is greater than 0 μm and less than about 20 μm.

[0051] Next, an external connector 127 is formed over the polymer layer 128. In the embodiment shown, the external connector 127 extends through the polymer layer 128 and is electrically coupled to the via 103. The external connector 127 can be, for example, a micro bump, a copper pillar, a copper layer, a nickel layer, a lead-free (LF) layer, an electroless nickel electroless palladium immersion gold (ENEPIG) layer, a Cu / LF layer, a Sn / Ag layer, Sn / Pb, a combination of these, or the like. As an example, the width (e.g., diameter) of the external connector 127 can be between about 20 μm and about 300 μm. Figure 8 As shown, solder regions 129 may be formed over external connectors 127 .

[0052] Next, in Fig. 9 In the embodiment, the carrier 153 and the adhesive layer 152 are removed, for example, by a carrier debonding process, and a chip on wafer (CoW) structure 100 is formed. Although not shown, as is readily understood by those skilled in the art, a dicing process may be performed to separate the CoW structure 100 from other CoW structures formed simultaneously with the CoW structure 100 during the manufacturing process. The external connectors 127 of the CoW structure 100 may then be bonded to a substrate (e.g., a printed circuit board (PCB)) to form a chip on wafer on substrate (CoWoS) structure.

[0053] Fig.10A cross-sectional view of a CoW structure 100A in another embodiment is shown. The CoW structure 100A is similar to Fig. 9 The CoW structure is 100, but Fig. 9 The polymer layer 128 and the redistribution structure 126 (if formed) in the embodiment are replaced by the redistribution structure 132. In some embodiments, by following Figures 1 to 9 The same or similar processing steps as in the above are used to form the CoW structure 100A, but in Figure 8 In the processing step of , instead of the polymer layer 128 and the redistribution structure 126 , a redistribution structure 132 (including the conductive subcomponent 131 and one or more dielectric layers 133 ) is formed.

[0054] Fig.11 FIG. 1 shows a cross-sectional view of a CoW structure 100B in another embodiment. The CoW structure 100B is similar to Fig. 9 However, the CoW structure 100B does not have the redistribution structure 112 formed in the composite interposer 160. In some embodiments, by following Figures 1 to 9 The same or similar processing steps as in the above are used to form the CoW structure 100B. Figure 2 In the processing step of , the redistribution structure 112 is omitted, and the conductive connector 114 is directly formed on the corresponding underlying conductive pad 109. Next, in the process for the CoW structure 100B Figure 3 In a similar process, the die connector 117 of the die 121 is bonded to the conductive connector 114 .

[0055] Fig.12 A cross-sectional view of a CoW structure 100C in yet another embodiment is shown. The CoW structure 100C is similar to Fig.10 100A, but the number of dies 121 may be less, and the width of the molding material 118 of the CoW structure 100C is less than the width of the molding material 118 of the CoW structure 100A. For example, in the CoW structures 100, 100A, and 100B, the molding material 118 and the molding material 108 have the same width, so that the sidewalls of the molding material 118 are aligned with the corresponding sidewalls of the molding material 108. In the structure 100C, the left sidewall of the molding material 118 is aligned with the left sidewall of the molding material 108, while the right sidewall of the molding material 118 is not aligned with (e.g., laterally spaced apart from) the right sidewall of the molding material 108. By, for example, performing an etching process to remove a portion of the molding material 118 (e.g., Fig.12 The shape of the molding material 118 in the CoW structure 100C can be formed by using a suitable forming method (such as an injection molding process) to directly have Fig.12The CoW structure 100C may be suitable for optical connection applications, where an optical waveguide formed in the substrate 101 is exposed by the molding material 118 .

[0056] Embodiments can achieve advantages. For example, by forming an electronic component 105 in the substrate 101 of the interposer 110, the interposer 110 can be designed to include various functional circuits for implementing different functions, rather than simply serving the function of electrical routing (e.g., only having through holes and wires in the interposer). As the integration density of the CoW structure increases, the size of the interposer can be increased to accommodate the number of dies attached to the interposer. However, large interposers may require higher standards for the planarity of the interposer (and therefore higher costs) to avoid problems related to the non-planarity of the interposer, such as cold joints and stress-related structural failures. The present invention allows a large composite interposer 160 to be easily formed using multiple smaller chiplet interposers 110, thereby avoiding the costs associated with maintaining the planarity of a larger interposer. In addition, by forming an electronic component 105 such as a DTC in the interposer 110 and electrically coupling the DTCs in all interposers 110 by, for example, a redistribution structure 112, the number of DTCs formed in the composite interposer 160 can be greatly increased. As another example, the formation of material 123 eliminates the need to perform a high vacuum CVD process, thereby reducing manufacturing costs.

[0057] Figures 13 to 17 A cross-sectional view of a CoW structure 100D at various stages of fabrication in another embodiment is shown. The CoW structure 100D is similar to the CoW structure 100, but may be formed in different processing steps.

[0058] refer to Fig.13 , semiconductor die 121 is attached to carrier 153, for example, by adhesive layer 152. Next, molding material 118 is formed over carrier 153 around semiconductor die 121. A planarization process, such as CMP, may be performed to achieve a coplanar upper surface between die connector 117 and molding material 118 of the semiconductor die.

[0059] Next, in Fig.14 In the embodiment shown, a plurality of interposers 110 are attached to a die 121. In the embodiment shown, the conductive pads 109 of the interposers 110 are bonded to the die connectors 117 of the die 121 through solder regions 115. Each of the interposers 110 has a through hole 103 formed in its substrate 101. Fig.14 In the embodiment, the through hole 103 does not extend through the substrate 101. In a subsequent substrate thinning process, the substrate 101 is thinned so that the through hole 103 extends through the substrate 101.

[0060] Next, in Fig.15In the embodiment, the molding material 108 is formed over the molding material 118 and around the interposer 110. A thinning process such as a grinding process is performed to thin the substrate 101 so that Fig.15 In FIG. 1 , the through hole 103 is exposed at the upper surface of the substrate 101. As a result of the thinning process, a coplanar upper surface is achieved between the substrate 101 and the molding material 108. Fig.15 Also shown are molded through vias 106, which may be formed by forming openings in the molding material 108 (e.g., using a laser drilling process, photolithography, or etching techniques) to expose corresponding die connectors 117, and filling the openings with a conductive material (e.g., copper) using an acceptable formation method (such as plating). As a non-limiting example, Figures 13 to 15 While the molding material (e.g., 118 and 108) is shown formed in two separate processing steps, other ways of forming the molding material around the die 121 and the interposer 110 are possible and are fully intended to be included within the scope of the present invention. In some embodiments, the interposer 110 is attached to the die 121 after the die 121 is attached to the carrier 153 and before the molding material (e.g., 118) is formed. Then, after the interposer 110 is attached, a single molding process is performed to form the molding material around the die 121 and the interposer 110.

[0061] Next, in Fig.16 In some embodiments, material 123 is formed in substrate 101 around (eg, contacting) the sidewalls of via 103. Figure 6 to Figure 7 1 to form material 123. After formation, material 123, via 103, substrate 101, and molding material 108 have coplanar upper surfaces.

[0062] Next, in Fig.17 , an optional redistribution structure 126 is formed over the molding material 108. Next, a polymer layer 128 is formed over the molding material 108 and over the redistribution structure 126 (if formed). External connectors 127 are formed extending through the polymer layer 128 and electrically coupled to the vias 103. A solder region 129 may be formed on top of the external connectors 127.

[0063] Fig.18 1 is a flow chart of a method 1000 of forming a semiconductor device in some embodiments. It should be understood that Fig.18 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the embodiments may be added, removed, replaced, rearranged, and repeated. Fig.18 The individual processing boxes shown.

[0064] refer to Fig.18 At block 1010, a first die and a second die are bonded to a first side of a first interposer and a first side of a second interposer, respectively, wherein the first interposer is laterally adjacent to the second interposer. At block 1020, the first interposer and the second interposer are sealed with a first molding material. At block 1030, a first recess is formed in a second side of the first interposer opposite to the first side of the first interposer. At block 1040, a second recess is formed in a second side of the second interposer opposite to the first side of the second interposer. At block 1050, the first recess and the second recess are filled with a first dielectric material.

[0065] According to an embodiment, a method of forming a semiconductor structure includes: bonding a first die and a second die to a first side of a first interposer and a first side of a second interposer, respectively, wherein the first interposer is laterally adjacent to the second interposer; sealing the first interposer and the second interposer with a first molding material; forming a first groove in a second side of the first interposer opposite to the first side of the first interposer; forming a second groove in a second side of the second interposer opposite to the first side of the second interposer; and filling the first groove and the second groove with a first dielectric material. In an embodiment, the method further includes attaching the first interposer and the second interposer to a carrier before bonding the first die and the second die. In an embodiment, the method further includes sealing the first die and the second die with a second molding material after bonding the first die and the second die. In an embodiment, the method further includes filling a gap between the first die and the second die with an underfill material. In an embodiment, the method further includes attaching the first die and the second die to a carrier before bonding the first die and the second die. In an embodiment, the first molding material also seals the first die and the second die. In an embodiment, the method further includes sealing the first die and the second die with a second molding material. In an embodiment, the method further comprises forming a through hole in the first molding material. In an embodiment, the first dielectric material is a polymer. In an embodiment, the method further comprises forming a conductive connector on the first dielectric material, wherein the conductive connector is electrically coupled to the first conductive pillar in the first interposer.

[0066] According to an embodiment, a method of forming a semiconductor structure includes: attaching a first die and a second die to a first interposer and a second interposer, respectively, wherein, after the attachment, the first die is laterally adjacent to the second die, the first interposer is laterally adjacent to the second interposer, the first interposer and the second interposer are surrounded by a first molding material; forming a first groove in a first surface of the first interposer away from the first die; forming a second groove in a first surface of the second interposer away from the second die; and filling the first groove and the second groove with a polymer layer. In an embodiment, a surface of the polymer layer away from the first die is flush with the first surface of the first interposer and the first surface of the second interposer. In an embodiment, wherein forming the first groove includes: forming a patterned mask layer on a first surface of the first interposer, wherein the patterned mask layer covers the first molding material, covers a first portion of the first interposer in contact with the first molding material, and exposes a second portion of the first interposer; and performing an anisotropic etching process to remove an outer layer of the second portion of the first interposer. In an embodiment, the width of the first groove is formed to be smaller than the width of the first interposer, so that the sidewalls of the first groove are spaced apart from the corresponding sidewalls of the first interposer in contact with the first molding material. In an embodiment, a first interposer includes a first substrate and a first through substrate via (TSV) in the first substrate, wherein after forming a first recess, the first TSV extends into the first recess.

[0067] According to an embodiment, a semiconductor structure includes: a plurality of interposers, laterally adjacent to each other and having through substrate vias (TSVs); a first molding material, located around the plurality of interposers; at least one die, bonded to and electrically connected to at least one of the plurality of interposers; and a dielectric layer, located on the back side of the plurality of interposers away from the at least one die. In an embodiment, the semiconductor structure further includes: a second molding material, located around the at least one die; and a bottom fill material, located between the plurality of interposers and the at least one die. In an embodiment, the first molding material surrounds the at least one die. In an embodiment, the semiconductor structure further includes a through hole located in the first molding material, wherein the through hole is electrically connected to the at least one die. In an embodiment, the dielectric layer is a polymer layer, wherein the semiconductor structure further includes an external connector located on the dielectric layer.

[0068] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, the method comprising: bonding a first die and a second die to a first side of a first interposer and a first side of a second interposer, respectively, wherein the first interposer is laterally adjacent to the second interposer; sealing the first interposer and the second interposer with a first molding material; forming a first groove in a second side of the first interposer opposite to the first side of the first interposer, wherein a bottom of the first groove is located between the first side of the first interposer and the second side of the first interposer, and the bottom of the first groove exposes a first surface of a first substrate of the first interposer; forming a second recess in a second side of the second interposer opposite to the first side of the second interposer; and The first recess and the second recess are filled with a first dielectric material, wherein the first dielectric material contacts the first surface of the first substrate and extends along the first surface of the first substrate.

2. The method according to claim 1, further comprising: Prior to bonding the first die and the second die, the first interposer and the second interposer are attached to a carrier.

3. The method according to claim 2, further comprising: After bonding the first die and the second die, the first die and the second die are encapsulated with a second molding material. 4 . The method of claim 3 , further comprising filling a gap between the first die and the second die with an underfill material.

5. The method according to claim 1, further comprising: Prior to bonding the first die and the second die, the first die and the second die are attached to a carrier.

6. The method according to claim 5, wherein: The first molding material also encapsulates the first die and the second die. 7 . The method of claim 5 , further comprising encapsulating the first die and the second die with a second molding material.

8. The method of claim 5, further comprising forming a through hole in the first molding material.

9. The method according to claim 1, wherein: The first dielectric material is a polymer.

10. The method according to claim 9, wherein: The method also includes forming a conductive connector on the first dielectric material, wherein the conductive connector is electrically coupled to a first conductive pillar in the first interposer.

11. A method for forming a semiconductor structure, the method comprising: attaching a first die and a second die to a first interposer and a second interposer, respectively, wherein after the attaching, the first die is laterally adjacent to the second die and the first interposer is laterally adjacent to the second interposer, wherein the first interposer includes a first substrate and a first through substrate via (TSV) in the first substrate; surrounding the first interposer and the second interposer with a first molding material; forming a first recess in a first surface of the first interposer remote from the first die, wherein after forming the first recess, the first substrate through-via extends into the first recess; forming a second recess in a first surface of the second interposer away from the second die; and The first groove and the second groove are filled with a polymer layer.

12. The method according to claim 11, wherein: A surface of the polymer layer distal from the first die is flush with the first surface of the first interposer and the first surface of the second interposer.

13. The method according to claim 11, wherein: Forming the first groove includes: forming a patterned mask layer on the first surface of the first interposer, wherein the patterned mask layer covers the first molding material, covers a first portion of the first interposer in contact with the first molding material, and exposes a second portion of the first interposer; and An anisotropic etching process is performed to remove an outer layer of the second portion of the first interposer.

14. The method according to claim 13, wherein: A width of the first groove is formed to be smaller than a width of the first interposer, so that a sidewall of the first groove is spaced apart from a corresponding sidewall of the first interposer in contact with the first molding material.

15. The method according to claim 11, wherein: The first groove exposes a sidewall of the first through substrate hole.

16. A semiconductor structure comprising: a plurality of interposers laterally adjacent to each other and having through substrate vias (TSVs); a first molding material disposed around the plurality of interposers; at least one die bonded to and electrically connected to at least one of the plurality of interposers; as well as A dielectric layer is located on a back side of the plurality of interposers away from the at least one die, wherein the dielectric layer contacts a sidewall of the through substrate via.

17. The semiconductor structure of claim 16, further comprising: a second molding material disposed around the at least one die; as well as An underfill material is disposed between the plurality of interposers and the at least one die.

18. The semiconductor structure according to claim 16, wherein: The first molding material surrounds the at least one die.

19. The semiconductor structure of claim 16, further comprising a through hole in the first molding material, wherein The via is electrically connected to the at least one die.

20. The semiconductor structure of claim 16, wherein: The dielectric layer is a polymer layer, wherein the semiconductor structure further comprises an external connector located on the dielectric layer.

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