Integrated chip and method for forming a memory device

Abstract

Various embodiments of the present application relate to an integrated chip. The integrated chip includes an array, located above a substrate, and includes a plurality of memory stacks along a plurality of rows and a plurality of columns. Each memory stack includes a data storage structure having a variable resistance. A plurality of word lines are arranged below the array and extend along corresponding rows of the array. The word lines are electrically connected to the memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to the top surface contacting the corresponding word lines. According to other embodiments of the present application, a method for forming a memory device is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated chips and methods for forming memory devices. Background Art

[0002] Many modern electronic devices include electronic memory. A cross-point memory architecture having a one selector one memory cell (1S1MC) stack is gaining increasing attention due to its high density and is suitable for next generation electronic memory. Examples of next generation electronic memory include resistive random access memory (RRAM), phase change random access memory (PCRAM), and magnetoresistive random access memory (MRAM). Summary of the invention

[0003] According to one embodiment of the present application, an integrated chip is provided, comprising: a substrate; an array located above the substrate and comprising a plurality of memory stacks along a plurality of rows and a plurality of columns, wherein each memory stack comprises a data storage structure having a variable resistance; a plurality of word lines arranged below the array and extending along corresponding rows of the array, wherein the word lines are electrically connected to the memory stacks of the array in the corresponding rows; and a plurality of upper conductive vias extending from above the array of the memory stacks to contact the top surfaces of the corresponding word lines.

[0004] According to another embodiment of the present application, an integrated chip is provided, comprising: a substrate; an interconnect structure located on the substrate, wherein the interconnect structure comprises a plurality of conductive lines and a plurality of conductive vias arranged in a dielectric structure; an array of memory stacks arranged in the dielectric structure along a plurality of rows and a plurality of columns, wherein the memory stacks respectively comprise memory cells located above a selector; a plurality of bit lines arranged in the dielectric structure and extending in a first direction along corresponding columns of the array, wherein the bit lines are located on the memory stacks and electrically connected to the memory cells of the array in the corresponding columns; a plurality of word lines arranged in the dielectric structure and extending in a second direction along corresponding rows of the array, wherein the second direction is orthogonal to the first direction, and wherein the word lines are located below the memory stacks and electrically connected to the memory cells of the array in the corresponding rows; and wherein the bottom surface of each word line is completely separated from the conductive vias and the conductive lines.

[0005] According to another embodiment of the present application, a method for forming a memory device is provided, the method comprising: forming a lower interconnect structure located above a substrate, wherein the lower interconnect structure includes conductive vias and conductive lines arranged in a dielectric structure; forming an etch stop layer along the upper surface of the lower interconnect structure; forming a plurality of word lines located above the etch stop layer, such that the conductive vias and conductive lines are offset from the bottom surfaces of the word lines, wherein the word lines extend along a first direction and are parallel to each other; forming a plurality of memory stacks respectively along the top surfaces of the word lines; forming a plurality of bit lines located above the memory stacks, such that the bit lines extend along a second direction orthogonal to the first direction, wherein the bit lines are parallel to each other; forming an upper interlayer dielectric layer located above the bit lines; and forming a plurality of upper conductive vias located in the upper interlayer dielectric layer, such that the upper conductive vias contact the top surfaces of the corresponding word lines, wherein the respective top surfaces of the upper conductive vias are arranged above the bit lines.

[0006] Embodiments of the present application provide bit line and word line connections for a memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1-Figure 3 Various views of some embodiments of a memory device having a plurality of memory cells disposed between upper bit lines and lower word lines in an interconnect structure, wherein upper conductive vias extend from above the memory cells to top surfaces of respective word lines;

[0009] Figure 4A-4C Shows Figures 1 to 3 Various views of some alternative embodiments of a memory device;

[0010] Figure 5 A cross-sectional view of some embodiments of a three-dimensional (3D) memory array including a first memory array and a second memory array located above a substrate is shown;

[0011] Figure 6A-6B A top view of some embodiments of a package structure having an independent memory area and an embedded memory area, respectively, is shown;

[0012] Figure 7 Shows Figure 1-Figure 3 A perspective view of some embodiments of a portion of a memory device;

[0013] Figure 8-Figure 19A series of cross-sectional views illustrating some embodiments of a method for forming a memory device having a plurality of memory cells disposed between an upper bit line and a lower word line in an interconnect structure, wherein upper conductive vias extend from above the memory cells to a top surface of the corresponding word line;

[0014] Fig. 20 Shows Figure 8-Figure 19 A block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0015] The present invention provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] A cross-point memory array may include a plurality of memory cells disposed within an interconnect structure disposed above a substrate. The memory cells define a memory array and are arranged in multiple rows and columns (e.g., in a cross-switch array). A plurality of word lines are disposed below the memory array, and a plurality of bit lines are disposed above the memory array. The word lines each extend along a single row in the memory array, and each is connected to a memory cell in a single row. The bit lines each extend along a single column in the memory array, and each is connected to a memory cell in a single column. A plurality of bit lines and a plurality of word lines are electrically connected to a semiconductor device (e.g., a transistor) disposed within / above the substrate via conductive vias and wires disposed within the interconnect structure. Therefore, a bias voltage may be applied to a plurality of bit lines and a plurality of word lines via conductive vias and wires in the interconnect structure to select a single memory cell (e.g., to read / write / erase the cell).

[0018] One challenge of a cross-point memory array is the connection between a word line and a corresponding lower conductive via within an interconnect structure. For example, the interconnect structure includes a lower conductive via and a lower conductor that are directly electrically connected to a transistor disposed within and / or on a substrate. During manufacturing, a first word line may be formed above a lower conductive via that is directly electrically connected to the transistor, so that an electrical path exists between the first word line and the transistor. A process for forming the first word line may include reactive ion etching of a conductive material of the first word line. The plasma used in the reactive ion etching may add charge carriers (e.g., electrons) to the first word line. Since the first word line is relatively long, the first word line may act as an antenna, and therefore a large amount of charge carriers may accumulate in the first word line. A large amount of charge carriers may travel through the lower conductive via to the transistor, causing a breakdown of the gate dielectric layer of the transistor.

[0019] In addition, the first word line may include a first material (e.g., tungsten) that is different from a second material (e.g., aluminum, copper, the aforementioned alloys, etc.) of the lower conductive via. During manufacturing, the first word line and the lower conductive via are exposed to one or more processing fluids (e.g., etching residue cleaning solution, deionized water, etc.). When the lower conductive via is exposed to the one or more processing fluids, electrical corrosion of the lower conductive via may occur (e.g., due to a reaction between the one or more processing fluids and the second material). This may result in the formation of an oxide at the interface between the lower conductive via and the first word line, thereby resulting in delamination between the lower conductive via and the first word line, and / or resulting in delamination of a layer disposed above the first word line (e.g., a layer constituting a memory cell). As a result, the performance of the cross-point memory array may be adversely affected (e.g., reduced yield, memory cell breakdown, transistor breakdown, etc.).

[0020] Various embodiments of the present invention are directed to an integrated chip having a cross-point memory array having a plurality of memory cells disposed between a plurality of word lines and a plurality of bit lines. In various embodiments, the bit lines are located above the memory cells, and the word lines are located below the memory cells. The memory array is disposed in an interconnect structure including a conductive component, the conductive component being disposed in a dielectric structure and being electrically connected to the bit lines and the word lines. The conductive component comprises a lower conductive via and a lower conductor located below the word lines, and an upper conductive via and an upper conductor located above the bit lines. The lower conductive via and the conductor are offset from the bottom surface of each word line at a non-zero distance so that the dielectric structure extends continuously along the bottom surface of each word line, and the bottom surface of each word line is completely spaced apart from the lower conductive via and the conductor. In addition, the upper conductive via extends from the upper conductor disposed above the bit line to contact the top surface of each word line. This forms an electrical connection between each word line and a corresponding semiconductor device (e.g., a transistor) disposed in and / or on a substrate.

[0021] During the manufacture of the integrated chip, the upper conductive via is formed after the word line, thereby forming an electrical path between the word line and the corresponding semiconductor device after the word line is manufactured. Before the upper conductive via is formed above the top surface of each word line, the charge carriers (e.g., electrons) accumulated in the word line (e.g., due to reactive ion etching) can be dispersed. For example, before the upper conductive via is formed, a charge carrier removal process can be implemented on the word line to remove the accumulated charge carriers. This can reduce the breakdown of the semiconductor device. In addition, since the lower conductive via and the wire offset the bottom surface of each word line, electrical corrosion may not occur between the word line and the lower conductive via. Therefore, this reduces the stratification of the word line and / or the memory cell, thereby improving the performance (e.g., yield rate) of the cross-point memory array.

[0022] Figure 1-Figure 3 Various views of some embodiments of a memory device 100 are shown having a plurality of one selector one memory cell (1S1MC) stacks 126 disposed between a plurality of word lines 120 and a plurality of bit lines 128 . Figure 3 A top view of some embodiments of a memory device 100 is shown. Figure 1 Shown along Figure 3 FIG. 1 is a cross-sectional view of some embodiments of the memory device 100 taken along line AA′. Figure 2 Shown along Figure 3 1 and 1 are cross-sectional views of some alternative embodiments of the memory device 100 taken along line BB′.

[0023] The memory device 100 includes an interconnect structure 104 located above a substrate 102. A semiconductor device 106 is disposed within and / or above the substrate 102. In some embodiments, the semiconductor device 106 may be configured as a transistor. In such an embodiment, the semiconductor device 106 may include a gate structure 110 and a source / drain region 108 disposed within the substrate 102 on opposite sides of the gate structure 110. In some embodiments, the gate structure 110 includes a gate electrode disposed above a gate dielectric layer. An isolation structure 112 is disposed within the substrate 102 between adjacent semiconductor devices 106. The interconnect structure 104 includes an interconnect dielectric structure 114, a plurality of conductive vias 116, and a plurality of conductive wires 118. The conductive vias 116 and the conductive wires 118 are disposed within the interconnect dielectric structure 114 and are configured to electrically connect the devices disposed within the memory device 100 to each other.

[0024] A plurality of word lines 120 and a plurality of bit lines 128 are disposed within the interconnect dielectric structure 114 between the upper and lower layers of the conductive vias 116 and the conductive lines 118. In some embodiments, the word lines 120 may be referred to as first conductive lines and the bit lines 128 may be referred to as second conductive lines. The plurality of word lines 120 each extend laterally along a first direction (e.g., along the x-axis). In various embodiments, the word lines 120 are arranged parallel to each other. In addition, the plurality of bit lines 128 each extend laterally along a second direction (e.g., along the y-axis) that is transverse to the first direction. In some embodiments, the bit lines 128 are arranged parallel to each other. In other embodiments, the first direction is orthogonal to the second direction. In some embodiments, the word lines 120 and the bit lines 128 may, for example, be or include copper, aluminum, tungsten, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing. In other embodiments, the word lines 120 and the bit lines 128 may, for example, respectively include a single material such as tungsten.

[0025] A plurality of 1S1MC stacks 126 are disposed between a plurality of word lines 120 and a plurality of bit lines 128. In various embodiments, the 1S1MC stacks 126 are arranged in an array having a plurality of rows and a plurality of columns. In some embodiments, individual word lines 120 and individual bit lines 128 are connected to individual 1S1MC stacks 126. In other embodiments, respective word lines 120 are connected to respective rows of 1S1MC stacks 126. In still other embodiments, respective bit lines 128 are connected to respective columns of 1S1MC stacks 126.

[0026] Each 1S1MC stack 126 includes a memory cell 124 located above the threshold selector 122. The memory cell 124 is configured to store data and may be a non-volatile memory cell or a volatile memory cell. In some embodiments, the memory cell 124 may be a resistance switching memory cell (e.g., a resistance random access memory (RRAM) cell, a phase change random access memory (PCRAM) cell, a metal cation RRAM, etc.) configured to store data according to the resistance state of the data storage structure. For example, the data storage structure may have a high resistance state associated with a first data state (e.g., binary "0"), or a low resistance state associated with a second data state (e.g., binary "1"). In some embodiments, the data storage structure may include, for example, chalcogenides, oxides, nitrides, high-k dielectrics, some other suitable dielectrics, or any combination of the foregoing. In another embodiment, the memory cell 124 may be a magnetoresistive random access memory (MRAM) cell. In such an embodiment, the data storage structure may include a magnetic tunnel junction (MTJ) configured to store data according to the magnetic orientation of the MTJ. In addition, the threshold selector 122 is configured to switch between a low resistance state and a high resistance state according to a voltage applied to the threshold selector 122. For example, if the voltage applied to the threshold selector 122 is less than the threshold voltage, the threshold selector 122 may be in the high resistance state, and if the voltage applied to the threshold selector 122 is greater than the threshold voltage, the threshold selector 122 may be in the low resistance state.

[0027] In some embodiments, the interconnect dielectric structure 114 extends continuously along the bottom surface 120bs of each word line 120 between the opposite outer sidewalls of each word line 120. Therefore, the conductive vias 116 and the conductive lines 118 disposed in the lower region 1041r of the interconnect structure 104 are offset from the bottom surface 120bs of each word line 120. In some embodiments, the bottom surface 120bs does not directly contact any conductive vias 116 and / or is completely spaced apart from the conductive vias 116. In some embodiments, the bottom surface 120bs directly contacts the interconnect dielectric structure 114 throughout the bottom surface 120bs. In addition, the upper conductive lines 118u and the upper conductive vias 116u are located above the plurality of bit lines 128 and the word lines 120. The upper conductive vias 116u extend continuously from the upper conductive lines 118u to the top surface 120ts of the corresponding word lines 120. Therefore, the word lines 120 can be electrically connected to the corresponding semiconductor devices 106 through the upper conductive vias 116u.

[0028] In some embodiments, during the manufacture of the memory device 100, a process for forming the word line 120 may include: depositing a conductive material (e.g., tungsten) over the lower region 1041r of the interconnect structure 104; and then performing dry etching on the conductive material to define the word line 120. The dry etching may include exposing the conductive material to a plasma, and charge carriers (e.g., electrons) accumulate in the word line 120. Since the upper conductive via 116u is formed after the word line 120 is formed, the charge carriers accumulated in the word line 120 may be dispersed before forming an electrical path between the word line 120 and the corresponding semiconductor device 106. This may reduce the possibility of gate dielectric layer breakdown in the semiconductor device 106. In addition, in some embodiments, the conductive via 116 and the conductive line 118 within the lower region 1041r of the interconnect structure 104 are offset from the bottom surface 120bs of each word line 120, and / or are completely spaced apart from the bottom surface 120bs of each word line 120. This prevents electrical corrosion between the word line 120 and the conductive vias 116 and the conductive lines 118 in the lower region 1041r of the interconnect structure 104. Thus, delamination of the word line 120, the 1S1MC stack 126, and / or the bit line 128 is reduced, thereby improving the performance of the memory device 100.

[0029] like Figure 3 As shown in the top view of FIG. 1 , the word lines 120 extend continuously along a first direction (e.g., the x-axis) and are parallel to each other. In addition, the bit lines 128 extend along a second direction (e.g., the y-axis) and are parallel to each other. In some embodiments, the first direction is orthogonal to the second direction. In addition, one or more upper conductive vias 116u are located directly above the corresponding word lines 120 and the corresponding bit lines 128.

[0030] Figure 4A 4 shows a cross-sectional view of some embodiments of an integrated chip 400 including a plurality of one selector one memory cell (1S1MC) stacks 126 disposed between a plurality of word lines 120 and a plurality of bit lines 128. In some embodiments, Figure 4A The cross-sectional view can be taken along the xz plane. In another embodiment, Figure 4A Shown along Figure 3 Some alternative cross-sectional views of the memory device 100 taken along line AA′.

[0031] The integrated chip 400 includes an interconnect structure 104 located on a substrate 102. In some embodiments, the substrate 102 may be, for example, or include a single crystal silicon / CMOS block, silicon germanium (SiGe), silicon on insulator (SOI), or another suitable substrate material, and / or may include a first doping type (e.g., p-type). The interconnect structure 104 includes a plurality of conductive vias 116, a plurality of conductive lines 118, and an interconnect dielectric structure. In some embodiments, the interconnect dielectric structure includes a plurality of interlayer dielectric (ILD) layers 402, an etch stop layer 404, and passivation layers 406, 408. In some embodiments, the plurality of conductive vias 116 and conductive lines 118 may be, for example, or include aluminum, copper, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing. In other embodiments, the plurality of ILD layers 402 may be, for example, or include an oxide such as silicon dioxide, a low-k dielectric material, another suitable dielectric material, or any combination of the foregoing. In still other embodiments, the etch stop layer 404 may be, for example, or include silicon dioxide, a low-k dielectric material, silicon nitride, silicon carbide, an extremely low-k (ELK) dielectric material, another suitable dielectric material, or any combination of the foregoing. In various embodiments, the passivation layers 406, 408 may be, for example, or include silicon dioxide, silicon oxynitride, silicon oxycarbide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing.

[0032] A plurality of semiconductor devices 106 are disposed in and / or above the substrate 102. In some embodiments, the semiconductor devices 106 may be configured, for example, as transistors or other suitable semiconductor devices. In such embodiments, the semiconductor devices 106 may include corresponding source / drain regions 108, corresponding gate structures 110, and corresponding gate capping layers 401. In some embodiments, the source / drain regions 108 are disposed in the substrate 102 and may include a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In other embodiments, the gate structure 110 may include a corresponding gate electrode located above a corresponding gate dielectric layer. In various embodiments, the gate electrode may be, for example, or include a metal (e.g., aluminum, tungsten, titanium, any combination of the foregoing, etc.), polysilicon, another suitable conductive material, or any combination of the foregoing. In other embodiments, the gate dielectric layer may be, for example, or include silicon dioxide, a high-k dielectric material, another suitable dielectric material, or any combination of the foregoing. The gate cap layer 401 is conductive and may be, for example, or include tantalum, titanium, silicide, another suitable material, or any combination of the foregoing. In addition, the isolation structure 112 is disposed within the substrate 102 and may laterally surround the corresponding semiconductor device 106. In some embodiments, the isolation structure 112 may be, for example, configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or another suitable isolation structure. In other embodiments, the isolation structure 112 may be, for example, or include silicon dioxide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing.

[0033] A plurality of word lines 120 and a plurality of bit lines 128 are disposed within an upper ILD layer 402u located above a lower region 1041r of the interconnect structure 104. In some embodiments, the etch stop layer 404 extends continuously along a top surface of the uppermost ILD layer 402 in the lower region 1041r. A top surface 404ts of the etch stop layer 404 extends continuously and laterally along a bottom surface 120bs of each word line 120. In some embodiments, the top surface 404ts of the etch stop layer 404 extends continuously along an uninterrupted path along a bottom surface 120bs of each word line 120 and / or directly contacts the entire bottom surface 120bs of each word line 120. In still other embodiments, the etch stop layer 404 is configured to separate (e.g., completely separate) the word lines 120 from the conductive vias 116 and the conductive lines 118 disposed within the lower region 1041r of the interconnect structure 104. In various embodiments, the conductive vias 116 and the conductive lines 118 disposed within the lower region 1041r of the interconnect structure 104 are offset from the bottom surface of the respective word lines by a non-zero distance.

[0034] In other embodiments, the etch stop layer 404 may be, for example, or include an oxide such as silicon dioxide, a low-k dielectric material, another dielectric material, or any combination of the foregoing, and / or may have a thickness t1 in the range of about 100 angstroms to 1000 angstroms or less than about 1000 angstroms. It should be understood that other values ​​of thickness t1 are within the scope of the present disclosure. In some embodiments, the top surface 404ts of the etch stop layer 404 is substantially flat (e.g., a flat top surface within the tolerance of a chemical mechanical planarization (CMP) process). For example, in some embodiments, the height of the top surface 404ts of the etch stop layer 404 can vary in the range of about -5% to +5% of the thickness t1 at any point from a horizontal line 407 located between the top surface 404ts of the etch stop layer 404 and the bottom surface 120bs of the word line 120. For example, if thickness t1 is about 1000 angstroms, the height of top surface 404ts of etch stop layer 404 varies from about -50 angstroms to +50 angstroms from horizontal line 407. In other embodiments, the height of top surface 404ts of etch stop layer 404 varies from about -5 angstroms to +5 angstroms at any point from horizontal line 407.

[0035] In some embodiments, during fabrication, word lines 120 are deposited along a top surface 404ts of etch stop layer 404. Thus, since top surface 404ts of etch stop layer 404 is substantially flat, bottom surface 120bs of word lines 120 may be substantially flat. In some embodiments, word lines 120 include a single material such as tungsten. The single material may have a relatively high hardness such that substantially flat top surface 404ts of etch stop layer 404 may prevent stress in word lines 120. This partially alleviates delamination of word lines 120 from structures located above word lines 120 (e.g., bit lines 128 and / or 1S1MC stack 126).

[0036] A plurality of 1S1MC stacks 126 are disposed between a plurality of word lines 120 and a plurality of bit lines 128 so that the 1S1MC stacks 126 are located above the top surfaces 120ts of the corresponding word lines 120. In various embodiments, the 1S1MC stacks 126 are arranged in an array having a plurality of rows and a plurality of columns. In some embodiments, a separate word line 120 and a separate bit line 128 are connected to each separate 1S1MC stack 126. In other embodiments, a respective word line 120 is connected to a respective row of the 1S1MC stack 126. In still other embodiments, a respective bit line 128 is connected to a respective column of the 1S1MC stack 126. Each 1S1MC stack 126 includes a memory cell 124 located above the threshold selector 122. The memory cell 124 is configured to store data and may be a nonvolatile memory cell or a volatile memory cell.

[0037] The upper conductive line 118u and the upper conductive via 116u are disposed in the upper ILD layer 402u. In some embodiments, the upper conductive line 118u is disposed vertically above the bit line 128. The upper conductive via 116u extends from the upper conductive line 118u to the word line 120, the bit line 128, and / or the conductive line 118 disposed in the lower region 1041r of the interconnect structure 104. Therefore, the upper conductive via 116u is configured to electrically connect the word line 120 and / or the bit line 128 to the semiconductor device 106 and / or another integrated chip (not shown). Since the upper conductive via 116u contacts the top surface 120ts of the word line 120 instead of the bottom surface 120bs of the word line 120, damage to the semiconductor device 106 (e.g., due to charge carriers accumulated in the word line 120) and / or damage to the word line 120 (e.g., due to delamination of the word line 120) can be reduced. This in turn improves the performance of the integrated chip 400 .

[0038] The passivation layers 406, 408 are located above the upper ILD layer 402u and the upper conductive vias 116u and the conductive lines 118u. In addition, the bonding pads 405 are disposed within the first passivation layer 406 and are located above the corresponding upper conductive lines 118u. In some embodiments, the bonding pads 405 may extend through the second passivation layer 408 and / or may include non-visible openings (e.g., see FIG. 4 ). Figure 4C ). In addition, the second passivation layer 408 is located on the first passivation layer. The bonding pad 405 can be configured to electrically connect the conductive line 118 and the conductive via 116 to other semiconductor devices disposed on another integrated chip (not shown).

[0039] Figure 4B Shows Figure 4A 400 of some alternative embodiments of the integrated chip. In some embodiments, Figure 4B The cross-sectional view can be taken along the yz plane orthogonal to the xz plane. In another embodiment, Figure 4B Shown along Figure 3 Some alternative cross-sectional views of the memory device 100 taken along line BB′.

[0040] like Figure 4B, in some embodiments, the memory cell layer 409 is disposed along the bottom surface 128bs of each bit line 128. In such an embodiment, the memory cell layer 409 is disposed between the bit lines 128 and the corresponding columns of the threshold selectors 122. In other embodiments, the memory cells 124 are defined in the region of the memory cell layer 409 disposed between the bit lines 128 and the corresponding threshold selectors 122. In still other embodiments, the memory cell layer 409 includes a data storage structure disposed between the bit lines 128 and the threshold selectors 122. In some embodiments, the data storage structure may include, for example, a chalcogenide, an oxide, a nitride, a high-k dielectric, or some other suitable dielectric.

[0041] For example, in some embodiments, the memory cells 124 may each be configured as an RRAM cell. In such embodiments, the data storage structure of the memory cell layer 409 may be, for example, or include gold and / or hafnium oxide, copper and hafnium oxide, aluminum and hafnium oxide, arsenic and hafnium oxide, gold tellurium and hafnium oxide, silicon oxide, titanium oxide, aluminum oxide (e.g., Al2O3), tantalum oxide, zirconium oxide, or another suitable material. In such embodiments, by applying appropriate bias conditions to the bit line 128 and the word line 120, each memory cell 124 may be switched between a first state having a low resistance and a second state having a high resistance. In other embodiments, in the first state, a conductive filament may be made in the data storage structure of the memory cell layer 409 between the bit line 128 and the corresponding threshold selector 122 disposed below the memory cell layer 409. In some embodiments, the conductive filament may be confined within a dashed box showing the location of the corresponding memory cell 124, thereby ensuring that the data states of adjacent memory cells 124 are isolated from each other. In still other embodiments, in the second state, at least a portion of the conductive filament is not formed in the memory cell layer 409 between the bit line 128 and the corresponding threshold selector 122. Each memory cell 124 can be individually switched between the first state and the second state as described above.

[0042] Figure 4C Shows Figure 4A 400, wherein the bonding pad 405 is disposed within the first passivation layer 406 and the second passivation layer 408. In some embodiments, the bonding pad 405 may, for example, include aluminum, and / or may be electrically connected to another integrated chip via a contact line (not shown). It should be understood that bonding pads 405 including other materials are also within the scope of the present disclosure.

[0043] Figure 5Cross-sectional views of some alternative embodiments of a three-dimensional (3D) memory array 500 including a first memory array 501 and a second memory array 503 located above a substrate 102 are shown.

[0044] The first memory array 501 and the second memory array 503 are stacked such that the second memory array 503 is located above the first memory array 501 and is spaced apart from the first memory array 501. In some embodiments, the first memory array 501 includes a plurality of one selector one memory cell (1S1MC) stacks 126 disposed between a plurality of word lines 120 and a plurality of bit lines 128. The 1S1MC stacks 126 each include a memory cell 124 located above a threshold selector 122. In addition, the second memory array 503 includes a plurality of upper 1S1MC stacks 508 disposed between a plurality of bit lines 128 and a plurality of upper word lines 506. In some embodiments, the plurality of upper word lines 506 extend parallel to the word lines 120 and / or include the same material as the word lines 120. In some embodiments, the plurality of upper 1S1MC stacks 508 include respective upper memory cells 504 located above respective upper threshold selectors 502. In some embodiments, the upper memory cells 504 may be configured as follows: Figure 1 , Figure 2 , Figure 4A , Figure 4B ,or Figure 4C In another embodiment, the upper threshold selector 502 can be configured as follows: Figure 1 , Figure 2 , Figure 4A , Figure 4B ,or Figure 4C Threshold selector 122.

[0045] Fig. 6A 600 includes a plurality of electrical connectors 604 extending from an integrated chip 602. In some embodiments, the integrated chip 602 may be configured as follows: Figure 1-Figure 3 Memory device 100. In such an embodiment, multiple 1S1MC stacks ( Figure 1-Figure 3 126) is laterally disposed on the memory region 606. In other embodiments, the memory region 606 extends continuously over a majority of the integrated chip 602. In still other embodiments, the electrical connector 604 is configured to electrically connect the devices disposed in the memory region 606 to another integrated chip (not shown). In some embodiments, the memory region 606 is the only type of semiconductor region on the integrated chip 602, and / or the memory region may also be referred to as an independent memory region.

[0046] Figure 6BA top view of some embodiments of a package structure 607 including a plurality of electrical connectors 604 extending from an integrated chip 602 is shown. In some embodiments, the integrated chip 602 is included on a single substrate (e.g., Figure 1 and Figure 2 The memory area 606, the central processing unit (CPU) area 608, the static random access memory (SRAM) area 610, and the analog area 612 are arranged laterally adjacent to each other above the substrate 102 of the embodiment. In such an embodiment, the memory area 606 can also be referred to as an embedded memory area. In some embodiments, multiple 1S1MC stacks ( Figure 1-Figure 3 126), word line ( Figure 1-Figure 3 120), and bit lines ( Figure 1-Figure 3 128) are laterally arranged in the embedded memory area 606. In addition, a CPU device (not shown) is laterally arranged in the CPU area 608, an SRAM device (not shown) is laterally arranged in the SRAM area 610, and an analog device (not shown) is laterally arranged in the analog area 610. In such an embodiment, the conductive via ( Figure 1-Figure 3 116) and wire ( Figure 1-Figure 3 The electrical connector 604 can be electrically connected to the conductive via ( Figure 1-Figure 3 116) and wire ( Figure 1-Figure 3 118).

[0047] Figure 7 A perspective view of some embodiments of a memory device 700 including a plurality of 1S1MC stacks 126 disposed between a plurality of bit lines 128 and a plurality of word lines 120 is shown.

[0048] In some embodiments, the 1S1MC stack 126 includes a corresponding memory cell 124 located above a corresponding threshold selector 122. In some embodiments, the 1S1MC stack 126 includes a lower electrode 702, an intermediate electrode 706, a threshold selector layer 704 disposed between the lower electrode 702 and the intermediate electrode 706, an upper electrode 710, and a data storage structure 708 disposed between the intermediate electrode 706 and the upper electrode 710. The lower electrode 702, the intermediate electrode 706, and the threshold selector layer 704 define the threshold selector 122. The intermediate electrode 706, the upper electrode 710, and the data storage structure 708 define the memory cell 124. In some embodiments, the upper electrode 710, the intermediate electrode 706, and the lower electrode 702 can be, for example, each or include tungsten, titanium, tantalum, another conductive material, or any combination of the foregoing.

[0049] The 1S1MC stacks 126 are arranged in a memory array including rows and / or columns. The 1S1MC stacks 126 within a row of the memory array are operably connected to the word line 120, while the 1S1MC stacks 126 within a column of the memory array are operably connected to the bit line 128. This results in multiple 1S1MC stacks 126 being associated with addresses defined by the intersection of the word line and the bit line, respectively. In some embodiments, the memory array is connected to a support circuit that is configured to read and / or write to multiple 1S1MC stacks 126 through the upper conductive vias 116u. In some embodiments, the support circuit includes a bit line (BL) decoder (not shown), a control unit (not shown), a word line (WL) decoder (not shown), and / or an access device (not shown). In some embodiments, the control unit is a microprocessor unit. In other embodiments, the access device may be a semiconductor device (e.g. Figure 1-Figure 2 106).

[0050] In some embodiments, during operation of the memory device 700, the control unit may provide an address to the WL decoder and / or the BL decoder. The address is associated with a single 1S1MC stack 126 within the memory array. The WL decoder is configured to selectively apply a signal (e.g., current and / or voltage) to one or more word lines 120 based on the received address. In addition, the BL decoder is configured to selectively apply a signal (e.g., current and / or voltage) to one or more bit lines 128 based on the received address. For example, during a read operation of the memory device 700, the BL decoder is configured to apply a read voltage to one of the plurality of bit lines 128 so that the output of at least one 1S1MC stack 126 is accessible (e.g., in a source code line). In another embodiment, during a write operation, the WL decoder is configured to apply a write voltage to at least one of the plurality of word lines 120 so that the resistance value of at least one 1S1MC stack 126 can be set and / or changed.

[0051] Figure 8-Figure 19 Cross-sectional views 800-1900 of some embodiments of methods for forming a memory device having a plurality of memory cells disposed between an upper bit line and a lower word line in an interconnect structure, wherein an upper conductive via extends from above the bit line to a top surface of the corresponding word line. Figure 8-Figure 19 The cross-sectional views 800-1900 are described, but it should be understood that Figure 8-Figure 19 The structure shown is not limited to this method, but can exist independently of this method. Figure 8-Figure 19Described as a series of actions, it should be understood that these actions are not restrictive, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted completely or partially.

[0052] like Figure 8 As shown in the cross-sectional view 800 of , a substrate 102 is provided, and an isolation structure 112 is formed in the substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate, and / or may include a first doping type (e.g., p-type). In some embodiments, a process for forming the isolation structure 112 may include: 1) selectively etching the substrate 102 to form a trench in the substrate 102; and 2) filling the trench with a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, etc.) (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.). In other embodiments, the substrate 102 is selectively etched by forming a masking layer (not shown) over the substrate 102 and then exposing the substrate 102 to an etchant configured to selectively remove unmasked portions of the substrate 102.

[0053] Still Figure 8As shown in , the semiconductor device 106 is formed above and / or inside the substrate 102. In some embodiments, the semiconductor device 106 is configured as a transistor. In such an embodiment, the process for forming the semiconductor device 106 may include depositing and / or growing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) a gate dielectric layer on the top surface of the substrate 102. Next, a gate electrode layer may be deposited on the gate dielectric layer. Subsequently, the gate dielectric layer and the electrode layer are patterned (e.g., by a photolithography / etching process) to form a gate dielectric and a gate electrode, respectively, thereby defining a gate structure 110. In another embodiment, a gate cap layer 401 is formed and / or grown above the gate electrode of the gate structure 110. In addition, source / drain regions 108 are formed on opposite sides of the gate structure 110, thereby defining the semiconductor device 106. In some embodiments, a second doping type dopant (e.g., an n-type dopant) is selectively implanted into the substrate 102 by selective ion implantation using a masking layer (not shown) disposed on the top surface of the substrate 102 to form the source / drain region 108. In some embodiments, the second doping type is opposite to the first doping type. In some embodiments, the gate electrode layer may include, for example, polysilicon, aluminum, titanium, another suitable conductive material, or any combination of the foregoing. In other embodiments, the gate dielectric layer may include, for example, silicon dioxide, another suitable oxide, a high-k dielectric material, another suitable dielectric material, or any combination of the foregoing. In still other embodiments, the gate cap layer 401 may include, for example, tantalum, titanium, titanium nitride, tantalum nitride, another suitable material, or any combination of the foregoing.

[0054] In addition, if Figure 8 As shown, the lower region 1041r of the interconnect structure 104 is formed above the substrate 102. The lower region 1041r of the interconnect structure 104 includes a plurality of interlayer dielectric (ILD) layers 402, a plurality of conductive vias 116, and a plurality of conductive wires 118. In some embodiments, the ILD layer 402 may be deposited, for example, by CVD, PVD, ALD, or another suitable growth or deposition process. In addition, the ILD layer 402 may be, for example, or include silicon dioxide, a low-k dielectric material, another suitable material, or any combination of the foregoing. In addition, in some embodiments, the plurality of conductive vias 116 and the plurality of conductive wires 118 may be formed by a single damascene process or a dual damascene process. In other embodiments, the plurality of conductive vias 116 and / or the conductive wires 118 may be, for example, or include copper, aluminum, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing, respectively.

[0055] like Fig. 9As shown in the cross-sectional view 900 of FIG. 1 , an etch stop layer 404 is formed along the upper surface of the topmost ILD layer 402 in the lower region 1041r of the interconnect structure 104. In some embodiments, the etch stop layer 404 can be formed, for example, by CVD, PVD, ALD, or another suitable growth or deposition process. In other embodiments, the etch stop layer 404 can be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, an extremely low k (ELK) dielectric material, another suitable dielectric material, or any combination of the foregoing. The ELK dielectric material can be, for example, a dielectric having a dielectric constant of less than about 2.5, about 2.0, or some other suitable value.

[0056] In other embodiments, the process for forming the etch stop layer 404 may include: 1) depositing (e.g., by a CVD process) a dielectric material (e.g., an oxide such as silicon dioxide, a low-k dielectric material, etc.) over the topmost ILD layer 402 in the lower region 1041r of the interconnect structure 104; and 2) performing a planarization process (e.g., a CMP process) on the dielectric material to thin the etch stop layer 404 and make the top surface 404ts of the etch stop layer 404 flat or substantially flat. In some embodiments, the flat or substantially flat top surface is within the tolerance of the CMP process. In some embodiments, the dielectric material is deposited so that the initial thickness ti of the etch stop layer 404 is in the range of about 3,000 angstroms to 5,000 angstroms before the planarization process. It should be understood that other values ​​of the initial thickness ti are also within the scope of the present disclosure. In some embodiments, after the planarization process, the etch stop layer 404 has a thickness t1 of about 1,000 angstroms or in the range of about 100 angstroms to 1,000 angstroms. It should be understood that other values ​​of thickness t1 are also within the scope of the present disclosure. In some embodiments, the height of the top surface 404ts of the etch stop layer 404 can vary from about -5% to +5% of the thickness t1 at any point from a horizontal line 407 located along the level of the top surface 404ts of the etch stop layer 404. For example, if the thickness t1 is about 1000 angstroms, the height of the top surface 404ts of the etch stop layer 404 varies from about -50 angstroms to +50 angstroms from the horizontal line 407. In other embodiments, the height of the top surface 404ts of the etch stop layer 404 varies from about -5 angstroms to +5 angstroms at any point from the horizontal line 407. It should be understood that other values ​​of the variation of the height of the top surface 404ts of the etch stop layer 404 from the horizontal line 407 are also within the scope of the present disclosure.

[0057] like Fig.10As shown in the cross-sectional view 1000 of FIG. 1 , a word line layer 1002 is deposited above the etch stop layer 404, and a threshold selector layer 1004 is deposited along the word line layer 1002. In some embodiments, the word line layer 1002 and / or the threshold selector layer 1004 are deposited by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. In other embodiments, the word line layer 1002 may be, for example, or include copper, aluminum, tungsten, titanium nitride, tantalum nitride, another suitable conductive material, or any combination thereof.

[0058] In some embodiments, the word line layer 1002 is deposited along the top surface 404ts of the etch stop layer 404, thereby ensuring that the top surface 1002ts of the word line layer 1002 is substantially flat (e.g., a flat top surface within the tolerance of the CMP process). In some embodiments, the word line layer 1002 may include a single material such as tungsten. The single material may have a relatively high hardness, so that the substantially flat top surface 404ts of the etch stop layer 404 may prevent stress in the word line layer 1002. This partially alleviates the delamination of the word line layer 1002 and layers and / or structures formed above the word line layer 1002 (e.g., the threshold selector layer 1004).

[0059] like Fig.11 As shown in the cross-sectional view 1100, in the word line layer ( Fig.10 1002) and the threshold selector layer ( Fig.10 A patterning process is performed on the threshold selector layer (1004) to define (some) word lines 120 and (some) threshold selector lines 1102. In some embodiments, the patterning process includes: 1) Fig.10 1004) above a masking layer (not shown); 2) forming a masking layer (not shown) on the threshold selector layer ( Fig.10 1004) and word line layer ( Fig.10 1002) to define (some) word lines 120 and (some) threshold selector lines; 3) and performing a removal process to remove the masking layer. In some embodiments, the patterned word line layer ( Fig.10 1002), so that a plurality of word lines 120 are formed, each word line extending laterally along a first direction (eg, along the x-axis), such as Figure 1-Figure 3 In such an embodiment, word lines 120 are arranged parallel to each other.

[0060] In some embodiments, the dry etching process includes reactive ion etching using plasma. Due to the power of reactive ion etching and / or plasma, charge carriers 1104 (e.g., electrons) are injected into the word lines 120. Since the length of the word lines 120 is long, a large number of charge carriers 1104 are accumulated in each word line 120. Since the conductive wires 118 and the conductive vias 116 in the lower region 1041r of the interconnect structure 104 are offset from the bottom surface 120bs of the word lines 120, the word lines 120 are electrically isolated from the semiconductor devices 106. This prevents a large number of charge carriers 1104 in the word lines 120 from traveling to the semiconductor devices 106, thereby preventing the breakdown of the semiconductor devices 106. In addition, since the conductive vias 116 and the conductive wires 118 in the lower region 1041r are offset from the bottom surface 120bs of the word lines 120, electrical corrosion may not occur between the word lines 120 and the conductive vias 116 and the conductive wires 118. This further mitigates delamination of the word line 120 and subsequently formed layers and / or structures above the word line 120 .

[0061] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a dielectric structure 1202 is formed to surround the word line 120 and the threshold selector line 1102. In some embodiments, the process for forming the dielectric structure 1202 includes: 1) depositing (e.g., by CVD, PVD, ALD, etc.) a dielectric material (e.g., silicon dioxide, a low-k dielectric material, etc.) on the word line 120 and the threshold selector line 1102; 2) performing a planarization process (e.g., a CMP process) on the dielectric material until reaching the upper surface of the threshold selector line 1102, thereby defining the dielectric structure 1202.

[0062] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a memory cell film 1302 is formed above the threshold selector line 1102, and a bit line layer 1304 is formed above the memory cell film 1302. In some embodiments, the memory cell film 1302 may be formed by one or more deposition processes such as, for example, PVD, ALD, sputtering, CVD, chemical plating, electroplating, or another suitable deposition or growth process. In other embodiments, the bit line layer 1304 may be formed by, for example, CVD, PVD, ALD, sputtering, or another suitable deposition or growth process. In some embodiments, the bit line layer 1304 may be, for example, or include aluminum, copper, titanium nitride, tantalum nitride, tungsten, another suitable conductive material, or any combination of the foregoing.

[0063] like Fig.14 As shown in the cross-sectional view 1400, Fig.13 A patterning process is performed on the structure of , thereby defining a plurality of one selector one memory cell (1S1MC) stacks 126 and a plurality of bit lines 128. In some embodiments, Figure 4B Shows Fig.14 An alternative embodiment of an orthogonal view of the cross-sectional view 1400. For example, Figure 3 It can be shown Fig.14 A top view of Fig.14 A cross-sectional view 1400 along Figure 3 The line A-A' is intercepted, Figure 4B The cross-section can be along Figure 3 Each 1S1MC stack 126 includes a memory cell 124 located above the threshold selector 122. In some embodiments, the 1S1MC stack 126 includes a memory cell layer (eg, Figure 4B 409), and located at the memory cell layer (eg Figure 4B The threshold selector 122 below the word line 120 is provided with a plurality of 1S1MC stacks 126. The plurality of bit lines 128 each extend laterally along a second direction (e.g., along the y-axis) transverse to the first direction. In some embodiments, the patterning process includes: 1) in the bit line layer ( Fig.13 1304) above the masking layer (not shown); 2) the bit line layer ( Fig.13 1304), memory cell film ( Fig.13 1302), threshold selector line ( Fig.13 1102), and the unmasked area of ​​the dielectric structure 1202 is exposed to one or more etchants to define a plurality of 1S1MC stacks 126 and a plurality of bit lines 128; and 3) performing a removal process to remove the masking layer.

[0064] In another embodiment, Fig.13 The patterning process performed on the structure may include performing reactive ion etching using plasma. Due to the power of the reactive ion etching and / or the plasma, additional charge carriers 1104 may be injected into the word line 120.

[0065] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15 , the upper ILD layer 402u is formed over the plurality of 1S1MC stacks 126. In some embodiments, the process for forming the upper ILD layer 402u includes: 1) depositing (e.g., PVD, CVD, etc.) a dielectric material (e.g., silicon dioxide, a low-k dielectric material, etc.) over the 1S1MC stack 126; and 2) performing a planarization process (e.g., a CMP process) on the dielectric material to define the upper ILD layer 402u. In some embodiments, the upper ILD layer 402u is formed between adjacent 1S1MC stacks 126 to promote electrical isolation between adjacent 1S1MC stacks 126.

[0066] In a further embodiment, before forming the upper ILD layer 402u, a charge carrier removal process is performed on the word line 120 to remove charge carriers from the word line 120 ( Fig.14 1104). In some embodiments, the charge carrier removal process may include exposing the word line 120 to ultraviolet (UV) light to eject the charge carriers from the word line 120 ( Fig.14 1104), electrically connecting word line 120 to ground to transfer charge carriers ( Fig.14 1104) from word line 120, another suitable charge carrier removal process, or any combination of the foregoing. In some embodiments, exposing word line 120 to UV light can remove charge carriers from word line 120 by the photoelectric effect ( Fig.14 1104).

[0067] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a patterning process is performed on the upper ILD layer 402u and the etch stop layer 404 to define a plurality of conductive component openings 1602. In some embodiments, the patterning process includes: 1) forming a masking layer (not shown) above the upper surface of the upper ILD layer 402u; 2) exposing the unmasked areas of the upper ILD layer 402u and the etch stop layer 404 to one or more etchants to define a plurality of conductive component openings 1602; and 3) performing a removal process to remove the masking layer. In some embodiments, the plurality of conductive component openings 1602 each include a conductive line opening located above a conductive via opening. In addition, the conductive component openings 1602 expose at least a portion of the top surface 120ts of the word line 120.

[0068] like Fig.17 As shown in the cross-sectional view 1700, a plurality of upper conductive vias 116u and a plurality of upper conductive wires 118u are formed in the conductive component opening ( Fig.16 In some embodiments, the process for forming the upper conductive via 116u and the conductive line 118u includes: 1) forming a conductive part opening ( Fig.161602) deposits (e.g., by CVD, PVD, sputtering, chemical plating, electroplating, etc.) a conductive structure within the interconnect structure 104; and 2) performs a planarization process (e.g., a CMP process) on the conductive structure until reaching the upper surface of the upper ILD layer 402u, thereby defining an upper conductive via 116u and a conductive line 118u. In other embodiments, the upper conductive via 116u is located directly above the top surface 120ts of the word line 120 and extends continuously from the upper conductive line 118u to abut against the top surface 120ts of the word line 120. In some embodiments, the upper conductive via 116u directly contacts the top surface 120ts of the word line 120. In still other embodiments, the upper conductive line 118u is electrically connected to the conductive via 116 and / or the conductive line 118 disposed in the lower region 104lr of the interconnect structure 104. In addition, in some embodiments, the upper conductive via 116u abuts against the upper surface (not shown) of each bit line 128 (e.g., see Figure 2-Figure 3 ). Since the upper conductive via 116u is formed after the word line 120, a conductive path between the word line 120 and the corresponding semiconductor device 106 can be formed after the bit line 128 is formed. In some embodiments, the charge carriers (e.g., electrons) accumulated in the word line 120 can be removed before the conductive path is formed (e.g., by performing a Fig.15 This reduces the breakdown of the semiconductor device 106.

[0069] like Fig.18 As shown in the cross-sectional view 1800 of , a first passivation layer 406 is formed over the upper ILD layer 402u, and a plurality of bonding pads 405 are formed in the first passivation layer 406. The bonding pads 405 are formed over the corresponding upper conductive lines 118u. In some embodiments, the first passivation layer 406 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process. In other embodiments, the bonding pads 405 may be formed, for example, by CVD, PVD, sputtering, chemical plating, electroplating, or another suitable deposition or growth process.

[0070] like Fig.19 As shown in the cross-sectional view 1900 of , the second passivation layer 408 is formed over the first passivation layer 406. In some embodiments, the second passivation layer 408 may be formed, for example, by CVD, PVD, ALD, or another suitable deposition process.

[0071] Fig. 20Method 2000 of some embodiments is shown, and the method 2000 is used to form a memory device with multiple memory cells, and the multiple memory cells are arranged between the upper bit line and the lower word line in the interconnect structure, wherein the upper conductive via extends from above the bit line to the top surface of the corresponding word line according to the present invention. Although method 2000 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be implemented in an order different from the order shown, and / or the actions can be implemented simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be implemented at separate times, or implemented simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0072] At act 2002 , a semiconductor device is formed within and / or over a substrate. Figure 8 Cross-sectional view 800 corresponding to some embodiments of act 2002 is shown.

[0073] At act 2004, a lower region of an interconnect structure is formed over the semiconductor device and the substrate. The interconnect structure includes a plurality of conductive vias and a plurality of conductive lines. Figure 8 A cross-sectional view 800 corresponding to some embodiments of act 2004 is shown.

[0074] At act 2006, an etch stop layer is formed along an upper surface of the lower region of the interconnect structure. Fig. 9 Cross-sectional view 900 is shown corresponding to some embodiments of act 2006 .

[0075] At act 2008, a word line layer is formed over the etch stop layer, and a threshold selector layer is formed over the word line layer.The conductive vias and wires are offset from and / or completely spaced apart from a bottom surface of the word line layer. Fig.10 Cross-sectional view 1000 is shown corresponding to some embodiments of act 2008 .

[0076] In act 2010, the word line layer and the threshold selector layer are patterned to define a word line underlying the threshold selector line. Fig.11 A cross-sectional view 1100 corresponding to some embodiments of act 2010 is shown.

[0077] At act 2012, a memory cell film is formed over the threshold selector line, and a bit line layer is formed over the memory cell film. Fig.13 A cross-sectional view 1300 corresponding to some embodiments of act 2012 is shown.

[0078] At act 2014, the bit line layer, memory cell films, and threshold selector lines are patterned to define a plurality of bit lines and a plurality of one selector one memory cell (1S1MC) stacks. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of act 2014 is shown.

[0079] In act 2016, an upper interlayer dielectric (ILD) layer is formed over the plurality of 1S1MC stacks. Fig.15 A cross-sectional view 1500 corresponding to some embodiments of act 2016 is shown.

[0080] At act 2018, the upper ILD layer is patterned to define a plurality of conductive feature openings within the upper ILD layer. The conductive feature openings are located above and expose the top surfaces of the word lines. Fig.16 A cross-sectional view 1600 corresponding to some embodiments of act 2018 is shown.

[0081] A plurality of upper conductive vias and upper conductive lines are formed within the conductive feature openings at act 2020. The upper conductive vias are located above and abut the top surfaces of the word lines and partially define a conductive path to at least one semiconductor device. Fig.17 A cross-sectional view 1700 corresponding to some embodiments of act 2020 is shown.

[0082] Thus, in some embodiments, the present invention is directed to a memory device having a plurality of memory cells disposed between upper bit lines and lower word lines in an interconnect structure, wherein upper conductive vias extend from above the memory cells to top surfaces of corresponding word lines.

[0083] In some embodiments, the present application provides an integrated chip, comprising: a substrate; an array located on the substrate and including a plurality of memory stacks along a plurality of rows and a plurality of columns, wherein each memory stack includes a data storage structure having a variable resistance; a plurality of word lines disposed below the array and extending along corresponding rows of the array, wherein the word lines are electrically connected to the memory stacks of the array in the corresponding rows; a plurality of upper conductive vias extending from above the array of the memory stacks to contact the top surface of the corresponding word lines. In one embodiment, the integrated chip further comprises: an interconnect dielectric structure located on the substrate, wherein the memory stacks, the word lines, and the upper conductive vias are disposed within the interconnect dielectric structure, and wherein the interconnect dielectric structure directly contacts the bottom surface of each word line on the entire bottom surface. In one embodiment, the bottom surface of each word line is defined between a first outer sidewall of the corresponding word line and a second outer sidewall of the corresponding word line, wherein the first outer sidewall is opposite to the second outer sidewall, and wherein the interconnect dielectric structure extends laterally continuously from the first outer sidewall to the second outer sidewall along an uninterrupted path. In one embodiment, the integrated chip further comprises: a plurality of bit lines disposed above the array and extending along corresponding columns of the array, wherein the bit lines are electrically connected to the memory stacks of the array in the corresponding columns. In one embodiment, the top surfaces of the plurality of upper conductive vias are disposed above the bit lines. In one embodiment, the memory stack comprises a corresponding memory cell located above the corresponding threshold selector. In one embodiment, the bottom surface of one of the threshold selectors is disposed along the top surface of the underlying word line. In one embodiment, the width of the word line is greater than the width of the memory stack. In one embodiment, the word line comprises a first material and the upper conductive via comprises a second material different from the first material.

[0084] In some embodiments, the present application provides an integrated chip, comprising: a substrate; an interconnect structure located on the substrate, wherein the interconnect structure includes a plurality of wires and a plurality of conductive vias arranged in a dielectric structure; an array of memory stacks arranged in the dielectric structure along a plurality of rows and a plurality of columns, wherein the memory stacks respectively include memory cells located above a selector; a plurality of bit lines arranged in the dielectric structure and extending in a first direction along the corresponding columns of the array, wherein the bit lines are located above the memory stacks and are electrically connected to the memory cells of the array in the corresponding columns; a plurality of word lines arranged in the dielectric structure and extending in a second direction along the corresponding rows of the array, wherein the second direction is orthogonal to the first direction, and wherein the word lines are located below the memory stacks and are electrically connected to the memory cells of the array in the corresponding rows; and wherein the bottom surface of each word line is completely separated from the conductive vias and the wires. In one embodiment, the plurality of conductive vias include a plurality of upper conductive vias extending from above the bit lines to directly contact the top surfaces of the corresponding word lines. In one embodiment, the dielectric structure includes an etch stop layer disposed between the word line and the conductive via and the conductive wire disposed below the word line, and wherein the top surface of the etch stop layer directly contacts the bottom surface of each word line in its entirety. In one embodiment, the top surface of the etch stop layer is substantially flat. In one embodiment, the interconnect structure does not have a conductive via that directly contacts the bottom surface of the word line. In one embodiment, the integrated chip further includes: a second array including a plurality of second memory stacks along a plurality of rows and a plurality of columns, wherein the second memory stacks respectively include second memory cells located above the second selector, wherein the bit lines extend along the corresponding columns of the second array and are electrically connected to the second memory cells of the second array in the corresponding columns; an upper word line extending along the corresponding rows of the second array and being electrically connected to the second memory cells of the second array in the corresponding rows, wherein the upper word line extends along the second direction, and wherein the bit line is disposed between the upper word line and the word line. In one embodiment, the conductive via and the conductive wire include aluminum and / or copper, and wherein the bit line and the word line include tungsten.

[0085] In some embodiments, the present application provides a method for forming a memory device, the method comprising: forming a lower interconnect structure located above a substrate, wherein the lower interconnect structure includes conductive vias and conductive lines arranged in a dielectric structure; forming an etch stop layer along the upper surface of the lower interconnect structure; forming a plurality of word lines located above the etch stop layer so that the conductive vias and conductive lines are offset from the bottom surfaces of the word lines, wherein the word lines extend along a first direction and are parallel to each other; forming a plurality of memory stacks respectively along the top surfaces of the word lines; forming a plurality of bit lines located above the memory stacks so that the bit lines extend along a second direction orthogonal to the first direction, wherein the bit lines are parallel to each other; forming an upper ILD layer located above the bit lines; and forming a plurality of upper conductive vias located in the upper ILD layer so that the upper conductive vias contact the top surfaces of the corresponding word lines, wherein the respective top surfaces of the upper conductive vias are arranged above the bit lines. In one embodiment, the method further comprises: forming a plurality of semiconductor devices on the substrate, wherein the conductive vias and the conductive lines within the lower interconnect structure are electrically connected to the semiconductor devices; wherein the word lines are electrically isolated from the semiconductor devices before forming the memory stack and the bit lines, and wherein the word lines are electrically connected to the semiconductor devices after forming the upper conductive vias. In one embodiment, forming an etch stop layer comprises: depositing a dielectric material along a top surface of the lower interconnect structure; and performing a planarization process on the dielectric material to define the etch stop layer to have a substantially planar top surface. In one embodiment, forming a plurality of word lines comprises: depositing a word line layer along a top surface of the etch stop layer; and performing a dry etching process on the word line layer to define a plurality of word lines.

[0086] According to one embodiment of the present application, an integrated chip is provided, comprising: a substrate; an array located on the substrate and comprising a plurality of memory stacks along a plurality of rows and a plurality of columns, wherein each memory stack comprises a data storage structure having a variable resistance; a plurality of word lines arranged below the array and extending along corresponding rows of the array, wherein the word lines are electrically connected to the memory stacks of the array in the corresponding rows; a plurality of upper conductive vias extending from above the array of the memory stacks to contact the top surface of the corresponding word lines. In some embodiments, the integrated chip further comprises: an interconnect dielectric structure located on the substrate, wherein the memory stacks, the word lines, and the upper conductive vias are arranged in the interconnect dielectric structure, and wherein the interconnect dielectric structure directly contacts the bottom surface of each word line on the entire bottom surface. In some embodiments, the bottom surface of each word line is defined between a first outer sidewall of the corresponding word line and a second outer sidewall of the corresponding word line, wherein the first outer sidewall is opposite to the second outer sidewall, and wherein the interconnect dielectric structure extends laterally continuously from the first outer sidewall to the second outer sidewall along an uninterrupted path. In some embodiments, the integrated chip further comprises: a plurality of bit lines disposed above the array and extending along corresponding columns of the array, wherein the bit lines are electrically connected to the memory stack of the array in the corresponding columns. In some embodiments, the top surfaces of the plurality of upper conductive vias are disposed above the bit lines. In some embodiments, the memory stack comprises a corresponding memory cell located above the corresponding threshold selector. In some embodiments, the bottom surface of one of the threshold selectors is disposed along the top surface of the underlying word line. In some embodiments, the width of the word line is greater than the width of the memory stack. In some embodiments, the word line comprises a first material, and the upper conductive via comprises a second material different from the first material.

[0087] According to another embodiment of the present application, an integrated chip is provided, comprising: a substrate; an interconnect structure located on the substrate, wherein the interconnect structure includes a plurality of wires and a plurality of conductive vias arranged in a dielectric structure; an array of memory stacks arranged in the dielectric structure along a plurality of rows and a plurality of columns, wherein the memory stacks respectively include memory cells located above a selector; a plurality of bit lines arranged in the dielectric structure and extending in a first direction along corresponding columns of the array, wherein the bit lines are located above the memory stacks and electrically connected to the memory cells of the array in the corresponding columns; a plurality of word lines arranged in the dielectric structure and extending in a second direction along corresponding rows of the array, wherein the second direction is orthogonal to the first direction, and wherein the word lines are located below the memory stacks and electrically connected to the memory cells of the array in the corresponding rows; and wherein the bottom surface of each word line is completely separated from the conductive vias and the wires. In some embodiments, the plurality of conductive vias include a plurality of upper conductive vias extending from above the bit lines to directly contact the top surfaces of the corresponding word lines. In some embodiments, the dielectric structure includes an etch stop layer disposed between the word line and the conductive via and the wire disposed below the word line, and wherein the top surface of the etch stop layer directly contacts the bottom surface of each word line throughout. In some embodiments, the top surface of the etch stop layer is substantially flat. In some embodiments, the interconnect structure does not have a conductive via that directly contacts the bottom surface of the word line. In some embodiments, the integrated chip further includes: a second array, including a plurality of second memory stacks along a plurality of rows and a plurality of columns, wherein the second memory stacks respectively include second memory cells located above the second selector, wherein the bit lines extend along the corresponding columns of the second array and are electrically connected to the second memory cells of the second array in the corresponding columns; and an upper word line, extending along the corresponding rows of the second array and being electrically connected to the second memory cells of the second array in the corresponding rows, wherein the upper word line extends in a second direction, and wherein the bit line is disposed between the upper word line and the word line. In some embodiments, the conductive via and the wire include aluminum and / or copper, and wherein the bit line and the word line include tungsten.

[0088] According to another embodiment of the present application, a method for forming a memory device is provided, the method comprising: forming a lower interconnect structure located above a substrate, wherein the lower interconnect structure includes conductive vias and conductive lines arranged in a dielectric structure; forming an etch stop layer along the upper surface of the lower interconnect structure; forming a plurality of word lines located above the etch stop layer, such that the conductive vias and conductive lines are offset from the bottom surfaces of the word lines, wherein the word lines extend along a first direction and are parallel to each other; forming a plurality of memory stacks respectively along the top surfaces of the word lines; forming a plurality of bit lines located above the memory stacks, such that the bit lines extend along a second direction orthogonal to the first direction, wherein the bit lines are parallel to each other; forming an upper interlayer dielectric layer located above the bit lines; and forming a plurality of upper conductive vias located in the upper interlayer dielectric layer, such that the upper conductive vias contact the top surfaces of the corresponding word lines, wherein the respective top surfaces of the upper conductive vias are arranged above the bit lines. In some embodiments, the method of forming a memory device further comprises: forming a plurality of semiconductor devices on a substrate, wherein the conductive vias and wires within the lower interconnect structure are electrically connected to the semiconductor devices; and wherein the word lines are electrically isolated from the semiconductor devices before forming the memory stack and the bit lines, and wherein the word lines are electrically connected to the semiconductor devices after forming the upper conductive vias. In some embodiments, forming an etch stop layer comprises: depositing a dielectric material along a top surface of the lower interconnect structure; and performing a planarization process on the dielectric material to define the etch stop layer to have a substantially flat top surface. In some embodiments, forming a plurality of word lines comprises: depositing a word line layer along a top surface of the etch stop layer; and performing a dry etching process on the word line layer to define a plurality of word lines.

[0089] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, comprising: substrate; a dielectric structure located on the substrate and comprising an etch stop layer, a plurality of conductive lines, and a plurality of conductive vias; a first memory stack located within the dielectric structure; a second memory stack located within the dielectric structure, wherein the first memory stack and the second memory stack each include a corresponding memory cell located on a corresponding threshold selector; a first bit line located in the dielectric structure and on the first memory stack; a second bit line located in the dielectric structure and on the second memory stack; A word line is located between the etch stop layer and the first memory stack, wherein a bottom surface of the word line is completely separated from the conductive via and the conductive line disposed below the word line, and the etch stop layer spans across the entire bottom surface of the word line and is in direct contact with the entire bottom surface of the word line.

2. The integrated chip according to claim 1, wherein: The dielectric structure further comprises: A dielectric layer is located above the etch stop layer, wherein the first memory stack, the second memory stack and the word line are disposed within the dielectric layer.

3. The integrated chip according to claim 2, wherein: The entire bottom surface of the word line is defined between a first outer sidewall of the word line and a second outer sidewall of the word line, wherein the first outer sidewall is opposite to the second outer sidewall, and wherein the dielectric structure extends laterally continuously along an uninterrupted path from the first outer sidewall to the second outer sidewall.

4. The integrated chip according to claim 1, wherein: The first memory stack vertically and continuously extends from a bottom surface of the first bit line to a top surface of the word line. 5 . The integrated chip according to claim 1 , further comprising top surfaces of a plurality of upper conductive vias disposed above the first bit line and the second bit line.

6. The integrated chip according to claim 5, wherein: The plurality of upper conductive vias extend from over the first memory stack and the second memory stack to a top surface of the word line.

7. The integrated chip according to claim 1, wherein: A bottom surface of one of the threshold selectors is disposed along a top surface of the underlying word line.

8. The integrated chip according to claim 1, wherein: The word line has a width greater than widths of the first memory stack and the second memory stack.

9. The integrated chip according to claim 5, wherein: The word line includes a first material, and the upper conductive via includes a second material different from the first material.

10. An integrated chip, comprising: substrate; an interconnect structure located on the substrate, wherein the interconnect structure includes a plurality of conductive lines and a plurality of conductive vias disposed within the dielectric structure; an array of memory stacks disposed within the dielectric structure along a plurality of rows and a plurality of columns, wherein the memory stacks each include a memory cell located above a selector; a plurality of bit lines disposed within the dielectric structure and extending in a first direction along respective columns of the array, wherein the bit lines are located above the memory stack and are electrically connected to memory cells of the array in the respective columns; a plurality of word lines disposed within the dielectric structure and extending in a second direction along respective rows of the array, wherein the second direction is orthogonal to the first direction, and wherein the word lines are located below the memory stack and are electrically connected to memory cells of the array in the respective rows; and The dielectric structure includes an etch stop layer located between the word line and the conductive via and the conductive wire arranged below the word line, and the top surface of the etch stop layer directly contacts the entire bottom surface of the word line, and the bottom surface of the word line is completely separated from the conductive via and the conductive wire below the word line.

11. The integrated chip according to claim 10, wherein: The plurality of conductive vias include a plurality of upper conductive vias extending from above the bit lines to directly contact top surfaces of corresponding word lines.

12. The integrated chip according to claim 10, wherein: The etch stop layer includes silicon dioxide, low-k dielectric material, silicon nitride, silicon carbide, ultra-low-k dielectric material, or a combination thereof.

13. The integrated chip according to claim 12, wherein: The top surface of the etch stop layer is substantially flat.

14. The integrated chip according to claim 10, wherein: The interconnect structure has no conductive vias that directly contact bottom surfaces of the word lines.

15. The integrated chip according to claim 10, further comprising: a second array comprising a plurality of second memory stacks along a plurality of rows and a plurality of columns, wherein the second memory stacks respectively comprise second memory cells located above the second selectors, wherein the bit lines extend along corresponding columns of the second array and are electrically connected to the second memory cells of the second array in the corresponding columns; and An upper word line extends along a corresponding row of the second array and is electrically connected to second memory cells of the second array in the corresponding row, wherein the upper word line extends in the second direction, and wherein the bit line is disposed between the upper word line and the word line.

16. The integrated chip according to claim 10, wherein: The conductive vias and conductive lines include aluminum and / or copper, and wherein the bit lines and the word lines include tungsten.

17. A method for forming a memory device, the method comprising: forming a lower interconnect structure over the substrate, wherein the lower interconnect structure comprises conductive vias and conductive lines disposed within the dielectric structure; forming an etch stop layer along an upper surface of the lower interconnect structure; forming a plurality of word lines located above the etch stop layer so that the conductive vias and the conductive lines do not contact bottom surfaces of the word lines, wherein the word lines extend along a first direction and are parallel to each other, and the etch stop layer spans across and directly contacts the entire bottom surfaces of the word lines; forming a plurality of memory stacks respectively along top surfaces of the word lines; forming a plurality of bit lines above the memory stack such that the bit lines extend along a second direction orthogonal to the first direction, wherein the bit lines are parallel to each other; forming an upper interlayer dielectric layer over the bit line; and A plurality of upper conductive vias are formed in the upper interlayer dielectric layer such that the upper conductive vias contact top surfaces of corresponding word lines, wherein respective top surfaces of the upper conductive vias are disposed above the bit lines.

18. The method according to claim 17, further comprising: forming a plurality of semiconductor devices on the substrate, wherein the conductive vias and conductive lines within the lower interconnect structure are electrically connected to the semiconductor devices; and wherein the word line is electrically isolated from the semiconductor device before forming the memory stack and the bit line, and wherein the word line is electrically connected to the semiconductor device after forming the upper conductive via.

19. The method according to claim 17, wherein: Forming the etch stop layer comprises: depositing a dielectric material along a top surface of the lower interconnect structure; and A planarization process is performed on the dielectric material to define the etch stop layer to have a substantially planar top surface.

20. The method according to claim 17, wherein: Forming the plurality of word lines comprises: depositing a word line layer along a top surface of the etch stop layer; and A dry etching process is performed on the word line layer to define the plurality of word lines.

Images