Semiconductor structure and integrated circuit and method for forming three-dimensional trench capacitor

Abstract

Various embodiments of the present invention are directed to three-dimensional (3D) trench capacitors and methods for forming the same. In some embodiments, a first substrate is located above a second substrate so that the front side of the first substrate faces the front side of the second substrate. A first trench capacitor and a second trench capacitor extend into the front side of the first substrate and the front side of the second substrate, respectively. A plurality of wires and a plurality of vias are stacked between the first trench capacitor and the second trench capacitor and are electrically connected to the first trench capacitor and the second trench capacitor. A first through-substrate via (TSV) extends from the back side of the first substrate through the first substrate, and the wire and the via electrically connect the first TSV to the first trench capacitor and the second trench capacitor. The first trench capacitor and the second trench capacitor and the electrical connection therebetween jointly define a 3D trench capacitor. According to other embodiments of the present application, a semiconductor structure and an integrated circuit are also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and integrated circuits and methods for forming three-dimensional trench capacitors. Background Art

[0002] An integrated passive device (IPD) is a collection of one or more passive devices integrated on a semiconductor substrate. Passive devices may include, for example, capacitors, resistors, inductors, etc. IPDs are formed using semiconductor manufacturing processes and packaged into integrated circuits (ICs). Compared to discrete passive devices, this can result in reduced size, reduced cost, and increased functional density. IPDs can be used to discover applications using, among other things, mobile devices and application processors. Summary of the invention

[0003] According to an embodiment of the present application, a semiconductor structure is provided, including: a first substrate and a second substrate; a first trench capacitor and a second trench capacitor, extending to the front side of the first substrate and the front side of the second substrate, respectively, wherein the front side of the first substrate and the front side of the second substrate face each other; a plurality of conductive lines and a plurality of through holes, stacked between the first trench capacitor and the second trench capacitor, and electrically connected to the first trench capacitor and the second trench capacitor; and a first through substrate via (TSV), extending through the first substrate from the back side of the first substrate opposite to the front side of the first substrate, wherein the conductive line and the through hole electrically connect the first TSV to the first trench capacitor and the second trench capacitor.

[0004] According to another embodiment of the present application, an integrated circuit (IC) is provided, comprising: a first IC die, comprising a first substrate, a first interconnect structure located below the first substrate, and a first trench capacitor, wherein the first trench capacitor extends into the first substrate and is located between the first substrate and the first interconnect structure; a second IC die, located below the first IC die and directly bonded to the first IC die, wherein the second IC die comprises a second substrate, a second interconnect structure located above the second substrate, and a second trench capacitor, and wherein the second trench capacitor extends into the second substrate and is located between the second substrate and the second interconnect structure; and a pair of through substrate vias (TSVs) extending through the first substrate and electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure.

[0005] According to another embodiment of the present application, a method for forming a three-dimensional (3D) trench capacitor is provided, the method comprising: forming a first trench capacitor extending into the front side of a first substrate; forming a first interconnect structure covering and electrically connected to the first trench capacitor on the front side of the first substrate; forming a second trench capacitor extending into the front side of a second substrate; forming a second interconnect structure covering and electrically connected to the second trench capacitor on the front side of the second substrate; bonding the first interconnect structure and the second interconnect structure together at a bonding interface where the first interconnect structure and the second interconnect structure are in direct contact with each other; and forming a first through-substrate via (TSV) extending from the back side of the first substrate through the first substrate, wherein the first TSV is electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure.

[0006] Embodiments of the present application provide a 3D trench capacitor for integrating passive devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 Cross-sectional views of some embodiments of semiconductor structures are shown in which a three-dimensional (3D) trench capacitor has trench portions electrically connected together by hybrid bonding;

[0009] Figure 2 Shows the Figure 1 The through substrate via (TSV) is electrically connected to Figure 1 A top layout of some embodiments of wires of a 3D trench capacitor;

[0010] Figure 3 Shows Figure 1 Circuit diagrams of some embodiments of 3D trench capacitors;

[0011] Figure 4A-4E Shows Figure 1 Cross-sectional views of various alternative embodiments of semiconductor structures wherein the trench portions are varied;

[0012] Figure 5A and Figure 5B Shows Figure 1 Cross-sectional views of various alternative embodiments of semiconductor structures, wherein the trench portion passes through Figure 1 More capacitor electrodes are used to define;

[0013] Figure 6 Shows the Figure 5A The TSV is electrically connected to Figure 5A A top layout of some embodiments of wires of a 3D trench capacitor;

[0014] Figure 7 Shows Figure 1 Cross-sectional views of some alternative embodiments of semiconductor structures of the type shown in FIG. 1 , wherein trench portions are electrically connected together by TSVs rather than hybrid junctions;

[0015] Figure 8A-8E Shows Figure 7 Cross-sectional views of various alternative embodiments of semiconductor structures wherein the trench portions are varied;

[0016] Fig. 9A and Fig. 9B Shows Figure 7 Cross-sectional views of various alternative embodiments of semiconductor structures, wherein the trench portion passes through Figure 7 More capacitor electrodes are used to define;

[0017] Figure 10A-10C Various embodiments of semiconductor structures are shown in cross-sectional views, wherein a 3D trench capacitor has trench portions that span at least four device layers and are electrically connected together by hybrid bonding and / or TSVs;

[0018] Fig.11 A cross-sectional view of some embodiments of a semiconductor structure package is shown, wherein a 2D trench capacitor has a trench portion having a depth partially located in an interconnect structure;

[0019] Figure 12-Figure 20 A series of cross-sectional views illustrating some embodiments of a method for forming a semiconductor structure wherein a 3D trench capacitor has trench portions electrically connected together by hybrid bonding;

[0020] Fig.21 Shows Figure 12-Figure 20 Block diagram of some embodiments of the method;

[0021] Figure 22-Figure 27 A series of cross-sectional views showing some embodiments of methods for forming a semiconductor structure with a 3D trench capacitor having trench portions electrically connected together by TSVs instead of hybrid bonding;

[0022] Fig.28 Shows Figure 22-Figure 27 A block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0024] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0025] In some embodiments, an integrated passive device (IPD) includes a single monolithic semiconductor substrate and a trench capacitor embedded in the substrate. The trench capacitor includes a plurality of capacitor electrodes and a plurality of capacitor dielectric layers. The capacitor electrodes and the capacitor dielectric layers are alternately stacked and define a trench portion extending to or protruding into the substrate. In addition, the capacitor electrodes are alternately and electrically connected to a first terminal of the trench capacitor and a second terminal of the trench capacitor through a wire and a through hole.

[0026] IPD can be used for mobile devices and access processors, among others. Mobile devices and access processors are constantly seeking to reduce size. Therefore, mobile devices and access processors are constantly seeking smaller and smaller IPDs. In order to reduce the size of IPD, the size of trench capacitors can be reduced by increasing the capacitance density of trench capacitors. The capacitance density corresponds to the capacitance per unit area in the two-dimensional (2D) projection (e.g., the footprint of trench capacitors) of the trench capacitor on the horizontal plane or the XY plane. The capacitance density can be increased by increasing the depth of the trench portion (e.g., the depth of the trench portion extending into the substrate) along the vertical dimension or the Z dimension. However, the semiconductor manufacturing process used to form the IPD may limit the depth, and therefore may limit the capacitance density.

[0027] Increasing the depth of the groove portion increases the aspect ratio of the groove portion (e.g., the ratio of height to width), and therefore increases the aspect ratio of the groove in which the groove portion is formed. At a high aspect ratio, during the deposition of the layer from which the groove portion is formed, the material may gather around the top corner of the groove. This phenomenon may be referred to as groove necking. Before the deposition is completed, the aggregation may pinch off the top of the groove. In this way, a gap may be formed in the groove. In addition, some layers from which the groove portion is formed may be restricted to the top of the groove, which reduces the surface area of ​​the electrode and therefore reduces the density of the capacitor.

[0028] Various embodiments of the present invention are directed to three-dimensional (3D) trench capacitors for IPDs, and methods for forming 3D trench capacitors. In some embodiments, a semiconductor structure in which a 3D trench capacitor is arranged includes a first IC die, a second IC die, and a pair of through-substrate vias (TSVs). The first IC die includes a first substrate, a first interconnect structure located below the first substrate, and a first trench capacitor. The first trench capacitor extends into the first substrate and is located between the first substrate and the first interconnect structure. The second IC die is located below the first IC die and is directly bonded to the first IC die. In addition, the second IC die includes a second substrate, a second interconnect structure located above the second substrate, and a second trench capacitor. The second trench capacitor extends into the second substrate and is located between the second substrate and the second interconnect structure. The first trench capacitor and the second trench capacitor jointly define a 3D trench capacitor. The TSV extends through the first substrate and is electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure.

[0029] The bonding can separate the first trench capacitor and the second trench capacitor along the vertical dimension or the Z dimension. In this way, the two-dimensional projection of the 3D trench capacitor on the horizontal plane or the XY plane may occupy a small area. In other words, the 3D trench capacitor can have a small footprint. In addition, the bonding and / or TSV can electrically connect the first trench capacitor and the second trench capacitor in parallel, so that the capacitance of the 3D trench capacitor is the sum of the capacitances of the first trench capacitor and the second trench capacitor. Since the capacitance of the 3D trench capacitor can be the sum of the capacitances of multiple trench capacitors, the 3D trench capacitor can have a high capacitance. Due to the high capacitance and small footprint, the 3D trench capacitor can have a high capacitance density. In other words, the capacitance per unit area in the footprint of the 3D trench capacitor can be very high.

[0030] refer to Figure 1, a cross-sectional view 100 of some embodiments of a semiconductor structure is provided in which a 3D trench capacitor 102 is arranged. The semiconductor structure can be, for example, an integrated circuit (IC), an IPD, or some other suitable semiconductor structure. The 3D trench capacitor 102 includes a plurality of trench portions 104 distributed on a plurality of IC dies 106, and the IC dies 106 are hybrid-bonded together at a front bonding interface 108. The front bonding interface 108 includes both metal-to-metal bonding and dielectric-to-dielectric bonding.

[0031] The plurality of IC dies 106 include a first IC die 106a and a second IC die 106b located below the first IC die 106a. The IC die 106 includes a corresponding substrate 110, a corresponding device layer 112, and a corresponding interconnect structure 114. The device layer 112 and the interconnect structure 114 are respectively located on the front side 116 of the substrate 110. The substrate 110 can be, for example, a bulk single crystal silicon substrate or some other suitable semiconductor substrate. The device layer 112 is a device level along the vertical dimension or Z dimension. The interconnect structure 114 is in direct contact at the front bonding interface 108 and surrounds and is electrically connected to the device layer 112.

[0032] The interconnect structure 114 includes a corresponding interconnect dielectric layer 118, a corresponding wire 120, and a corresponding via 122. The wire 120 and the via 122 are alternately stacked in the interconnect dielectric layer 118 to define a conductive path from the groove portion 104 to the front bonding interface 108. The interconnect dielectric layer 118 can be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, some other suitable (some) dielectric, or any combination of the foregoing. In some embodiments, the interconnect dielectric layer 118 is or includes silicon oxide and / or silicon oxynitride at the front bonding interface 108. However, other suitable (some) dielectrics are acceptable. The wire 120 and the via 122 can be or include, for example, metal and / or some other suitable (some) conductive material.

[0033] The trench portions 104 are distributed on the device layer 112. In addition, the trench portions 104 extend or protrude into the front side 116 of the substrate 110, respectively, and toward the back side 124 of the substrate 110, respectively. The trench portions 104 individually define two-dimensional (2D) trench capacitors 126. A 2D trench capacitor is a trench capacitor limited to a single device layer, while a 3D trench capacitor is a trench capacitor spanning multiple device layers. The 2D trench capacitors 126 are electrically connected in parallel through the conductive lines 120 and the vias 122, so that the capacitance of the 3D trench capacitor 102 is the sum of the capacitances of the 2D trench capacitors 126.

[0034] Since the groove portion 104 is distributed in a vertical dimension or Z dimension on multiple device layers (e.g., the device layer 112 of the first IC die 106a and the second IC die 106b), the 2D projection of the 3D trench capacitor 102 on the horizontal plane or the XY plane may occupy a small area. In other words, the 3D trench capacitor 102 can have a smaller footprint. In addition, since the capacitance of the 3D trench capacitor 102 is the sum of the capacitances of multiple 2D trench capacitors (e.g., the sum of the capacitances of the 2D trench capacitor 126), the 3D trench capacitor 102 can have a high capacitance. Due to the high capacitance and small footprint, the 3D trench capacitor 102 can have a high capacitance density. In other words, the capacitance per unit area in the footprint of the 3D trench capacitor 102 can be very high.

[0035] In some embodiments, the 3D trench capacitor 102 has a capacitance density that is about 30% or more, about 50% or more, or some other suitable percentage higher than the maximum capacitance density of the 2D trench capacitor. In some embodiments, the maximum capacitance density of the 2D trench capacitor is about 850 nanofarads, about 1100 nanofarads, or some other suitable value.

[0036] Continue to refer Figure 1 , the trench portion 104 is defined by a corresponding capacitor electrode 128 and a corresponding capacitor dielectric layer 130. The capacitor electrodes 128 and the capacitor dielectric layers 130 are alternately stacked so that the capacitor dielectric layers 130 and the capacitor electrodes 128 are separated from each other and from the substrate 110. The capacitor electrodes 128 may be or include, for example, metal, doped polysilicon, some other suitable (some) conductive material, or any combination of the foregoing. The capacitor dielectric layers 130 may be or include, for example, silicon oxide, a high-k dielectric, some other suitable (some) dielectric, or any combination of the foregoing.

[0037] Although the groove portions 104 are shown as being each defined by two capacitor electrodes and two capacitor dielectric layers, additional capacitor electrodes and / or additional capacitor dielectric layers are acceptable. In addition, although four groove portions are shown, more or fewer groove portions are acceptable. For example, there may be three groove portions on each IC die 106. In addition, although the IC die 106 has the same number of groove portions, different numbers of groove portions are acceptable. For example, the first IC die 106a may have three groove portions, while the second IC die 106b may have two or four groove portions.

[0038] The TSV 132 extends through the substrate 110 (e.g., first substrate 110a) of the first IC die 106a to a TSV wire 120a in the interconnect structure 114 (e.g., first interconnect structure 114a) of the first IC die 106a. Although not fully visible, the TSV wire 120a electrically connects the TSV 132 to the remainder of the wire 120 and the remainder of the via 122, which electrically connects the TSV wire 120a (and therefore the TSV 132) to the terminals of the 3D trench capacitor 102, respectively. In some embodiments, the TSV 132 is electrically connected to the 2D trench capacitor 126 of the second IC die 106b and / or the 2D trench capacitor of the first IC die 106a only through the TSV wire 120a. The TSV 132 provides a path from the back side 124 of the first substrate 110a to the first terminal T1 of the 3D trench capacitor 102 and to the second terminal T2 of the 3D trench capacitor 102, respectively. The TSVs 132 are separated from the first substrate 110a by corresponding TSV dielectric layers 134 and may be or include, for example, metal and / or some other suitable conductive material(s). The TSV dielectric layers 134 may be or include, for example, silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination thereof.

[0039] The first terminal T of the 3D trench capacitor 102 l The first terminal T1 and the second terminal T2 may be the anode of the 3D trench capacitor 102 and the cathode of the 3D trench capacitor 102, respectively, or vice versa. In some embodiments, during use of the 3D trench capacitor 102, the first terminal T1 and the second terminal T2 are electrically connected to a power supply voltage (e.g., VDD) and ground, respectively, or vice versa. In other embodiments, the first terminal T1 and the second terminal T2 are electrically connected to some other suitable voltages.

[0040] The trench portion 104 of the first IC die 106a has a first depth D1, and the trench portion 104 of the second IC die 106b has a second depth D2. A portion of the first depth D1 is located in the first interconnect structure 114a, and the remaining portion of the first depth D1 is located in the first substrate 110a. In addition, the second depth D2 is completely or substantially located in the substrate 110 (e.g., the second substrate 110b) of the second IC die 106b. In this way, the trench portion 104 of the first IC die 106a laterally contacts the first interconnect structure 114a, while the trench portion 104 of the second IC die 106b does not laterally contact the interconnect structure 114 (e.g., the second interconnect structure 114b) of the second IC die 106b. In some embodiments, the interconnect dielectric layer 118 of the first interconnect structure 114a is or includes silicon oxide and / or some other suitable oxide(s) at the trench portion 104 of the first IC die 106a. However, other suitable dielectric(s) are acceptable.

[0041] Because a portion of the first depth D1 is located in the first interconnect structure 114a, the first depth D1 may be greater than it would be if it were located entirely or substantially in the first substrate 110a. As such, the 2D trench capacitor 126 of the first IC die 106a may have a greater capacitance than it would otherwise have. Additionally, because the TSV 132 is formed in the first substrate 110a, process constraints (discussed in detail below) when forming the TSV 132 may limit the thickness T of the first substrate 110a. fs is limited to a smaller value. For example, the first thickness T fs The second thickness T of the second substrate 110b may be ss Therefore, if the first depth D1 is completely or substantially located in the first substrate 110a, the first depth D1 may be small. However, since a portion of the first depth D1 is located in the first interconnect structure 114a, this mitigates the negative impact from the small thickness, and the 2D trench capacitor 126 can have a high capacitance. For example, the first depth D1 can be the same as or greater than the second depth D2, and / or the capacitance of the 2D trench capacitor 126 of the first IC die 106a can be the same as or greater than the capacitance of the 2D trench capacitor 126 of the second IC die 106b.

[0042] In some embodiments, the first depth D1 is about 4 microns or less, about 6 microns or less, about 8 microns or less, about 4 microns-8 microns, or some other suitable value. In some embodiments, the second depth D2 is about 4 microns or less, about 6 microns or less, about 4 microns-6 microns, or some other suitable value. If the first depth D1 and the second depth D2 are too low (e.g., less than about 4 microns or some other suitable value), the capacitance of the 2D trench capacitor 126 may be low, and therefore the capacitance density of the 3D trench capacitor 102 may be low. If the first depth D1 and the second depth D2 are too high (e.g., greater than about 6 microns, 8 microns, or some other suitable value), the aspect ratio of the trench in which the trench portion 104 is formed may be high. In some embodiments, the portion of the first depth D1 located in the first interconnect structure 114a is approximately equal to or less than the first thickness T fs With the second thickness T ss In some embodiments, the portion of the first depth D1 located in the first interconnect structure 114a is about 20%-60%, about 20%-40%, about 40%-60%, or other suitable percentage of the first depth D1. If the portion of the first depth D1 located in the first interconnect structure 114a accounts for too small a percentage of the first depth D1 (e.g., less than about 20% or some other suitable value), the increased manufacturing cost may not outweigh the benefits obtained from the increased capacitance.

[0043] At high aspect ratios, during the deposition of the layers from which the trench portion 104 is formed, material may gather around the top corners of the trench. This phenomenon may be referred to as trench necking. Before deposition is complete, the aggregation may pinch off the top of the trench. In this way, voids may form in the trench. In addition, some layers from which the trench portion 104 is formed may be confined to the top of the trench, which may reduce the surface area of ​​the electrode and, therefore, the density of the capacitor.

[0044] refer to Figure 2 , provides Figure 1 1. The top layout 200 of some embodiments of the TSV conductive line 120a of FIG. Accordingly, for illustrative purposes, the TSV 132, the 2D trench capacitor 126, and some of the vias 122 are shown in dashed lines. Figure 2 The top layout 200 may be along the Figure 1 The line A-A' is intercepted in, and / or, Figure 1 The cross-sectional view 100 may be, for example, along Figure 2 The line BB' in is intercepted.

[0045] The TSV wire 120a includes corresponding fingers 202 that cross each other. In some embodiments, the TSV wire 120a is a mirror image of each other. The TSV wire 120a directly and separately contacts the TSV 132 and some through holes 122 at the finger 202, respectively, to electrically connect the TSV 132 to the through holes, respectively. The wire 120 and the through hole 122 including the TSV wire 120a define a conductive path leading from the TSV 132 to the terminal of the 2D trench capacitor 126, respectively, to electrically connect the 2D trench capacitor 126 to the TSV 132. In addition, as described above, the wire 120 and the through hole 122 electrically connect the 2D trench capacitor 126 to each other in parallel. Although a specific top layout is shown for the TSV line 120a, the 2D trench capacitor 126, the TSV 132, and some through holes 122, it should be understood that other top layouts are acceptable.

[0046] refer to Figure 3 , provides Figure 1 3. Circuit diagram 300 of some embodiments of the 3D trench capacitor 102. The 2D trench capacitors 126 are electrically connected in parallel from a first terminal T1 of the 3D trench capacitor 102 to a second terminal T2 of the 3D trench capacitor 102. Additionally, the 2D trench capacitors 126 are grouped by IC die.

[0047] refer to Figure 4A , provides Figure 1 A cross-sectional view 400A of some alternative embodiments of a semiconductor structure, wherein the first substrate 110a and the second substrate 110b have respective first thicknesses T fs and the second thickness T ss In addition, the first depth D1 is greater than the second depth D2.

[0048] refer to Figure 4B , provides Figure 1 400B of some alternative embodiments of the semiconductor structure of the present invention, wherein a portion of the second depth D2 is located in the second interconnect structure 114b. As such, the trench portion 104 of the second IC die 106b laterally contacts the second interconnect structure 114b. Since a portion of the second depth D2 is located in the second interconnect structure 114b, the second depth D2 may be greater than it would be if it were completely or substantially located in the second substrate 110b. As such, the 2D trench capacitor 126 of the second IC die 106b may have a larger capacitance.

[0049] refer to Figure 4C , provides Figure 1400C of some alternative embodiments of the semiconductor structure of the present invention, wherein the first depth D1 is completely or substantially located in the first substrate 110a. In addition, a portion of the second depth D2 is located in the second interconnect structure 114b. In this way, the trench portion 104 of the second IC die 106b laterally contacts the second interconnect structure 114b, but the trench portion 104 of the first IC die 106a does not laterally contact the first interconnect structure 114a.

[0050] refer to Figure 4D , provides Figure 1 FIG. 4 is a cross-sectional view 400D of some alternative embodiments of a semiconductor structure of FIG. 1 , wherein the first depth D1 is completely or substantially located in the first substrate 110 a. As such, the trench portion 104 of the first IC die 106 a does not laterally contact the first interconnect structure 114 a.

[0051] refer to Figure 4E , provides Figure 4D 400E of some alternative embodiments of the semiconductor structure of 2D trench capacitor 126, wherein some capacitor dielectric layers 130 are omitted, and some capacitor electrodes 128 are omitted. In addition, 2D trench capacitor 126 has a corresponding well region 402 in substrate 110. Well region 402 is a doped region of substrate 110 along trench portion 104 and serves as a capacitor electrode. In some embodiments, well region 402 has an opposite doping type (e.g., p-type to n-type) to an adjacent region of substrate 110. Well region 402 may also be referred to as a substrate-type capacitor electrode, and capacitor electrode 128 may also be referred to as an in-trench-type capacitor electrode.

[0052] Although Figure 1 and Figure 4A-4D Not shown Figure 4E well region 402, but it should be understood that Figure 1 and Figure 4A-4D An alternative embodiment may include a well region 402. In addition, although Figure 1 The cross-sectional view 100 depicts Figure 2 The top layout 200, but the top layout 200 can be applied to Figure 4A-4E In other words, Figure 2 The top layout 200 may alternatively be along Figure 4A-4E The line A-A' in any one of the above is intercepted, and / or, Figure 4A-4E The cross-sectional views 400A-400E may alternatively be taken along Figure 2 The line BB' in is intercepted.

[0053] refer to Figure 5A , provides Figure 1500A of some alternative embodiments of a semiconductor structure of FIG. 500A, wherein there is a one-to-many correspondence between the 2D trench capacitors 126 and the trench portions 104. Accordingly, the 2D trench capacitors 126 are formed by comparing Figure 1 The 2D trench capacitor 126 is defined by more capacitor electrodes and more capacitor dielectric layers in the 3D trench capacitor 102. The capacitor electrodes 128 and the capacitor dielectric layers 130 are stacked alternately and vertically, with their widths decreasing toward the interconnect structure 114. In addition, the capacitor electrodes 128 are electrically connected, so each 2D trench capacitor 126 can be modeled as a plurality of capacitors electrically connected in parallel (e.g., a capacitor for each pair of adjacent capacitor electrodes). An increase in the number of capacitor electrodes and an increase in the number of capacitor dielectric layers can, for example, increase the capacitance of the 2D trench capacitor 126, and thus can increase the capacitance density of the 3D trench capacitor 102.

[0054] The sidewall spacers 502 are respectively located on the sidewalls of the capacitor electrodes 128. The first capping layer 504 is located between the substrate 110 and protrudes into the 2D groove portion 104. The second capping layer 506 is located between the first capping layers 504 and is respectively located on the first capping layers 504. The sidewall spacers 502 can be or include, for example, silicon oxide, silicon nitride, some other suitable (some) dielectrics, or any combination of the above. The first capping layer 504 can be or include, for example, silicon oxide, metal, some other suitable (some) materials, or any combination of the above. The second capping layer 506 can be or include, for example, silicon nitride and / or some other suitable (some) dielectrics.

[0055] A first etch stop layer (ESL) 508 and a second ESL 510 are located between the substrate 110 and between the 2D trench capacitors 126. The first ESL 508 covers the substrate 110 and the 2D trench capacitors 126, respectively, covering the front side 116 of the substrate 110. The second ESL 510 covers the first ESL 508 on the front side 116 of the substrate 110, respectively. The first ESL 508 can be or include, for example, silicon oxide and / or some other suitable (some) dielectrics. The second ESL 510 can be or include, for example, silicon nitride and / or some other suitable (some) dielectrics.

[0056] refer to Figure 5B , provides Figure 5A500B is a cross-sectional view of some alternative embodiments of a semiconductor structure, wherein the 2D trench capacitor 126 is limited to a single trench portion. In addition, the capacitor dielectric layer 130a at the substrate 110 covers the substrate 110 and has a greater thickness than the remaining capacitor dielectric layer 130. In yet another embodiment, the sidewall spacer 502 and the second capping layer 506 are omitted, and due to the high aspect ratio of the trench portion 104, there is a gap 512 at the trench portion 104. In alternative embodiments, the semiconductor structure may include as follows Figure 5A The sidewall spacers 502 in the embodiment of the present invention may include, for example, Figure 5A In an alternative embodiment, the gap 512 may be omitted.

[0057] Although Figure 5A and Figure 5B The trench portions 104 are completely or substantially located in the substrate 110, however, one, some, or all of the trench portions 104 may be located partially in the interconnect structure 114, respectively. Figure 1 and Figure 4A-4C For example, in Figure 5A and Figure 5B In an alternative embodiment, the trench portion 104 of the first IC die 104a may be as shown in FIG. Figure 1 The portion shown is located in the first interconnect structure 114a.

[0058] refer to Figure 6 , provides Figure 5A 6 is a top layout 600 of some embodiments of TSV conductive lines 120a. Accordingly, for illustrative purposes, TSVs 132, 2D trench capacitors 126, and some vias 122 are shown in dashed lines. Figure 6 The top layout 600 may be, for example, along the lines of Figure 5A The line C-C' is intercepted in, and / or Figure 5A The cross-sectional view 500A may be, for example, along Figure 6 The TSV wires 120a are arranged around each other and contact the TSVs 132 and some of the vias 122 to electrically connect the TSVs 132 to the vias, respectively. The wires 120 and the vias 122 including the TSV wires 120a define conductive paths leading from the TSVs 132 to the terminals of the 2D trench capacitors 126, respectively, to electrically connect the 2D trench capacitors 126 to the TSVs 132.

[0059] Although a specific top layout for TSV conductors 120a, TSV 132, and some through-holes 122 is shown, it should be understood that other top layouts are acceptable. Figure 5A The cross-sectional view 500A depicts Figure 6The top layout 600, however, can be applied to Figure 5B In other words, Figure 6 The top layout 600 may alternatively be along Figure 5B The line C-C' is intercepted, and / or, Figure 5B The cross-sectional view 500B may alternatively be along Figure 6 The line D-D' in is intercepted.

[0060] refer to Figure 7 , provides Figure 1 A cross-sectional view 700 of some alternative embodiments of a semiconductor structure of the present invention, wherein, at the front bonding interface 108, the IC die 106 is melt-bonded together, rather than hybrid-bonded together. Thus, there is no metal-to-metal bonding at the front bonding interface 108. In addition, the IC die 106 includes corresponding TSV wires 120a, and the TSVs 132 electrically connect the 2D trench capacitors 126 in parallel through the TSV wires 120a. In an alternative embodiment, there is a metal-to-metal bond at the front bonding interface 108, but it is not used to electrically connect the 2D trench capacitors 126 in parallel. In some embodiments, the interconnect dielectric layer 118 is or includes silicon oxide and / or some other suitable oxide at the front bonding interface 108. However, other suitable (some) dielectrics are acceptable.

[0061] The TSVs 132 extend through the first IC die 106a and terminate in the second IC die 106b. At the first interconnect structure 114a, the TSVs 132 extend through the TSV wires 120a of the first IC die 106a, respectively, and contact the TSV wires laterally and directly. The TSV wires 120a of the first IC die 106a and the through-holes 122 of the first IC die 106a respectively electrically connect the TSVs 132 to the terminals of the 2D trench capacitors 126 of the first IC die 106a. At the second interconnect structure 114b, the TSVs 132 terminate at the TSV wires 120a of the second IC die 106b, respectively. The TSV wires 120a of the second IC die 106b and the through-holes 122 of the second IC die 106b respectively electrically connect the TSVs 132 to the terminals of the 2D trench capacitors 126 of the second IC die 106b.

[0062] In some embodiments, the 2D trench capacitor 126 of the first IC die 106 a is electrically connected to the 2D trench capacitor 126 of the second IC die 106 b only through the TSV 132. In other words, without the TSV 132, the 2D trench capacitor 126 of the first IC die 106 a would be electrically isolated from the 2D trench capacitor 126 of the second IC die 106 b. In some embodiments, the conductive path from the 2D trench capacitor 126 of the first IC die 106 a to the TSV 132 does not overlap with the conductive path from the 2D trench capacitor 126 of the second IC die 106 b to the TSV 132.

[0063] By using fusion bonding instead Figure 1 Hybrid bonding can reduce the process difficulty of hybrid bonding. Hybrid bonding may be more difficult to achieve than fusion bonding because it depends on the front bonding interface 108 (see, for example Figure 1 ) to electrically connect the IC die 106 together, whereas fusion bonding does not. On the other hand, by using Figure 1 Hybrid bonding instead of fusion bonding can reduce the process difficulty of forming TSV 132. When hybrid bonding is used, TSV 132 terminates in first interconnect structure 114a, so TSV 132 has a smaller height than when fusion bonding is used. These smaller heights reduce the aspect ratio of the through-hole opening in which TSV 132 is formed, and thus reduce the process difficulty of forming TSV 132.

[0064] refer to Fig. 8A , provides Figure 7 A cross-sectional view 800A of some alternative embodiments of a semiconductor structure, wherein the first substrate 110a and the second substrate 110b have respective first thicknesses T fs and the second thickness T ss are the same or substantially the same. Figure 8B-Figure 8E , provides Figure 7 800B-800E of some alternative embodiments of the semiconductor structure, wherein the trench portion 104 is respectively as shown in FIG. Figure 1 , Figure 4B , Figure 4C , and changes as shown in 4E.

[0065] Although Figure 7 and Figure 8A-8D Not shown Fig. 8E well region 402, but it should be understood that Figure 7 and Figure 8A-8D An alternative embodiment may include a well region 402. In addition, although Figure 1 The TSV conductor 120a describes Figure 2The top layout 200, but the top layout 200 can be applied to Figure 7 and Figure 8A-8E For example, Figure 2 An alternative embodiment may be along the lines of Figure 7 and Figure 8A-8E The line EE' in any one of the above is intercepted, and / or along Figure 7 and Figure 8A-8E The line FF′ in any one of the above is intercepted. Figure 2 An alternative embodiment may be, for example, with Figure 2 The embodiment of FIG. 1 is the same as that of FIG. 1 except that the TSV 132 extends through the TSV wire 120a of the first IC die 106a and some of the through holes 122 are omitted. Figure 2 An alternative embodiment may be, for example, with Figure 2 The embodiment is the same as that of the embodiment, except that some through holes 122 are omitted. Figure 7 and Figure 8A-8E The TSV wire 120a may have a structure similar to Figure 2 The top layout of the TSV wire 120a is shown, but other top layouts are acceptable.

[0066] refer to Fig. 9A and Fig. 9B , provides Figure 7 Cross-sectional views 900A, 900B of various alternative embodiments of a semiconductor structure, wherein Figure 1 In comparison, the trench portion 104 is defined by more capacitor electrodes and more capacitor dielectric layers. Fig. 9A and Fig. 9B The semiconductor structures can be, for example, Figure 5A and Figure 5B The semiconductor structure is depicted except that the IC die 106 are fusion bonded together at the front side bonding interface 108 and the TSVs 132 electrically connect the 2D trench capacitors 126 in parallel.

[0067] Although about Figure 5A The TSV conductor 120a describes Figure 6 The top layout 600, however, can be applied to Fig. 9A and Fig. 9B For example, Figure 6 An alternative embodiment may be along the lines of Fig. 9A and Fig. 9B The line G-G' of any one of Fig. 9A and Fig. 9B The line H-H' of any one of the above is intercepted. Figure 6An alternative embodiment may be, for example, with Figure 6 The embodiment of the present invention is the same as that of the embodiment of the present invention, except that the TSV 132 extends through the TSV wire 120a of the first IC die 106a, and some through holes 122 are omitted. Figure 6 An alternative embodiment may be, for example, with Figure 6 The embodiment is the same as that of the embodiment, except that some through holes 122 are omitted. Fig. 9A and Fig. 9B The TSV wire 120a may have a structure similar to Figure 6 The top layout of the TSV wire 120a is shown, but other top layouts are acceptable.

[0068] refer to Fig. 10A , a cross-sectional view 1000A of some embodiments of a semiconductor structure is provided, wherein a 3D trench capacitor 102 is arranged within at least four IC dies 106. The semiconductor structure may be, for example, an IC, an IPD, or some other suitable semiconductor structure. The 3D trench capacitor 102 includes a plurality of 2D trench capacitors 126 distributed on at least four IC dies 106 and electrically connected in parallel, such that the capacitance of the 3D trench capacitor 102 is the sum of the individual capacitances of the 2D trench capacitors 126. The at least four IC dies 106 include a first IC die 106a, a second IC die 106b, a third IC die 106c, and a fourth IC die 106d.

[0069] The first IC die 106a and the second IC die 106b are respectively Figure 1 The first IC die 106a and the second IC die 106b are described, except that the TSV 132 and the TSV wire 120a are located at both the first IC die 106a and the second IC die 106b. The TSV wire 120a of the first IC die 106a electrically connects the TSV 132 of the first IC die 106a to the 2D trench capacitor 126 of the first IC die 106a through the remaining portion of the wire 120 in the first IC die 106a and the remaining portion of the via 122 shown. The TSV wire 120a of the second IC die 106b electrically connects the TSV 132 of the second IC die 106b to the 2D trench capacitor 126 of the second IC die 106b through the remaining portion of the wire 120 in the second IC die 106b and the remaining portion of the via 122. The TSV conductive line 120 a of the first IC die 106 a and / or the TSV conductive line 120 a of the second IC die 106 b may have, for example, Figure 2 The third IC die 106c and the fourth IC die 106d may be respectively as shown in FIG. Figure 1A first IC die 106a and a second IC die 106b are depicted.

[0070] The bonding structure 1002 is located between the second IC die 106b and the third IC die 106c, and bonds and electrically connects the second IC die 106b and the third IC die 106c together. The bonding structure 1002 includes a bonding dielectric layer 1004, a bonding wire 1006, and a bonding via 1008. The bonding wire 1006 corresponds to the second IC die 106b and the third IC die 106c, and is in direct contact at the back bonding interface 1010. The bonding dielectric layer 1004 corresponds to the second IC die 106b and the third IC die 106c, and is in direct contact at the back bonding interface 1010. The bonding via 1008 extends from the bonding wire 1006 of the second IC die 106b and the third IC die 106c to the TSV 132, respectively. In alternative embodiments, other bonding structures are acceptable.

[0071] Since the 2D trench capacitors 126 are distributed on at least four device layers 112 along the vertical dimension or Z dimension, the 2D projection of the 3D trench capacitor 102 on the horizontal plane or XY plane may occupy a small area. In addition, since the 2D trench capacitors 126 are electrically connected in parallel, the capacitance of the 3D trench capacitor 102 is the sum of the capacitances of multiple 2D trench capacitors and can therefore be very high. Since the 3D trench capacitor 102 can occupy a small area and can have a high capacitance, the 3D trench capacitor 102 can have a high capacitance density.

[0072] refer to Fig. 10B , provides Fig. 10A 100B is a cross-sectional view of some alternative embodiments of a semiconductor structure, wherein the IC die 106 are fusion bonded together and the TSV 132 electrically connects the 2D trench capacitor 126 in parallel. The first die 106a and the second die 106b are respectively as shown in FIG. Figure 7 The first IC die 106a and the second IC die 106b are described, except that the TSV 132 is located at the substrate 110 of both the first IC die 106a and the second IC die 106b. The third IC die 106c and the fourth IC die 106d are respectively as shown in FIG. Figure 7 A first IC die 106a and a second IC die 106b are depicted.

[0073] refer to Fig. 10C , provides Fig. 10A1000C is a cross-sectional view of some alternative embodiments of a semiconductor structure, wherein the third IC die 106c and the fourth IC die 106d are fusion bonded together, and the TSVs 132 of the third IC die 106c and the fourth IC die 106d are electrically connected in parallel to the 2D trench capacitors 126 of the third IC die 106c and the fourth IC die 106d. In addition, the third IC die 106c and the fourth IC die 106d are respectively as shown in FIG. Figure 7 A first IC die 106a and a second IC die 106b are depicted.

[0074] Although Figure 10A-10C The 2D trench capacitors 126 of the first IC die 106a and the second IC die 106b are shown configured as follows Figure 1 and Figure 7 , but the 2D trench capacitor 126 may alternatively be configured as Figure 4A-4E , Figure 5A , Figure 5B , Figure 8A-8E , Fig. 9A ,and Fig. 9B Similarly, although Figure 10A-10C The 2D trench capacitors 126 of the third IC die 106c and the fourth IC die 106d are shown configured as Figure 1 and Figure 7 , but the 2D trench capacitor 126 may alternatively be configured as Figure 4A-4E , Figure 5A , Figure 5B , Figure 8A-8E , Fig. 9A ,and Fig. 9B Although the 3D trench capacitor 102 is shown as having four device layers 112 , in alternative embodiments, more or fewer device layers are acceptable.

[0075] refer to Fig.11 , a cross-sectional view 1100 of some embodiments of a semiconductor structure package is provided, wherein a composite capacitor 1102 includes a plurality of 2D trench capacitors 126 positioned to a single device layer 112 and electrically connected in parallel. In addition, the depth D of the 2D trench capacitor 126 is partially located in the interconnect structure 114 and partially located in the substrate 110. Since a portion of the depth D is located in the interconnect structure 114, the depth D may be greater than if it is completely or substantially located in the substrate 110. In this way, the 2D trench capacitor 126 may have a greater capacitance than it would otherwise have. The semiconductor structure package may be, for example, an IC package, an IPD package, or some other suitable semiconductor structure package.

[0076] In some embodiments, the depth D is about 4 microns or less, about 6 microns or less, about 8 microns or less, about 4 microns-8 microns, or some other suitable value. If the depth D is too low (e.g., less than about 4 microns or some other suitable value), the capacitance of the 2D trench capacitor 126 may be low. If the depth D is too high (e.g., greater than about 6 microns, 8 microns, or some other suitable value), the aspect ratio of the trench in which the trench portion 104 is formed may be high. In some embodiments, the portion of the depth D that is located in the interconnect structure 114 is about 20%-60%, about 20%-40%, about 40%-60%, or some other suitable percentage of the depth D. If the portion of the depth D that is located in the interconnect structure 114 is too small as a percentage of the depth D (e.g., less than about 20% or some other suitable value), the increased manufacturing cost may not outweigh the benefits obtained from the increased capacitance. In some embodiments, the portion of the depth D in the interconnect structure 114 is about 10%-50%, about 10%-20%, about 20%-30%, about 30%-40%, about 40%-50%, or some other suitable percentage of the thickness T of the substrate 110 .

[0077] The 2D trench capacitor 126 and the substrate 110 are as shown in FIG. Figure 1 In addition, the interconnect structure 114 is as described with respect to Figure 1 As described, the difference lies in the layout of the wires 120 and the vias 122. The wires 120 and the vias 122 are alternately stacked in the interconnect dielectric layer 118 to define a conductive path extending from the 2D trench capacitors 126 to the under bump metallization (UBM) layer 1104 along the top of the semiconductor structure package. Please note that the conductive path is not completely visible. In addition, the wires 120 and the vias 122 define a conductive path that electrically connects the 2D trench capacitors 126 in parallel. In alternative embodiments, the 2D trench capacitors 126 are electrically isolated from each other. In addition, in some embodiments, the wires 120b adjacent to the 2D trench capacitors 126 have the following characteristics: Figure 2 The same top layout of the TSV conductor 120a. For example, Figure 2 It may be taken along line II'. Other suitable top layouts are acceptable.

[0078] UBM layer 1104 extends through passivation layer 1106 located above interconnect structure 114, and bump 1108 is located above UBM layer 1104. UBM layer 1104 and bump 1108 can be or include, for example, metal and / or some other suitable (some) conductive material. Passivation layer 1106 can be or include, for example, silicon oxide and / or some other suitable (some) dielectric.

[0079] refer to Figure 12-Figure 20 , provides a method for forming Figure 1 A series of cross-sectional views 1200-2000 of some embodiments of a method for forming a semiconductor structure. The semiconductor structure has a trench portion located on at least two substrates and electrically connected together by hybrid bonding. Although the method forms Figure 1 The semiconductor structure of the present invention can be formed by using this method and its variants. Figure 4A-4E , Figure 5A , Figure 5B , Fig. 10A ,and Fig. 10C A semiconductor structure in any one of the above, or some other suitable semiconductor structure.

[0080] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a first interconnect dielectric layer 118a is deposited on the front side 116 of the first substrate 110a. The first interconnect dielectric layer 118a may be or include, for example, silicon oxide, some other suitable oxide, some other suitable dielectric, or any combination of the foregoing. In an alternative embodiment, the first interconnect dielectric layer 118a is omitted. In an alternative embodiment, a well region is formed in the first substrate 110a before depositing the first interconnect dielectric layer 118a, and the subsequently formed 2D trench capacitor is formed in the well region. See, for example, Figure 4E The well region 402 is formed in the vicinity of the substrate.

[0081] Also through Fig.12 The cross-sectional view 1200 shows that the first interconnect dielectric layer 118a and the first substrate 110a are patterned to form a pair of grooves 1202. In alternative embodiments, more or fewer grooves are formed. The groove 1202 has a first depth D1 that is partially located in the first interconnect dielectric layer 118a and partially located in the first substrate 110a. Since a portion of the first depth D1 is located in the first interconnect dielectric layer 118a, the first depth D1 may be greater than if it is completely or substantially located in the first substrate 110a. In this way, the 2D trench capacitor subsequently formed in the groove 1202 can have a greater capacitance than it would otherwise have. Patterning can be implemented, for example, by a lithography / etching process and / or some other suitable (some) process, or include a lithography / etching process and / or some other suitable (some) process.

[0082] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a plurality of conductive layers 1302 and a plurality of dielectric layers 1304 are alternately deposited on the first interconnect dielectric layer 118a and as the trenches 1202 (see, for example, Fig.12) liner. In alternative embodiments, one or more conductive layers, and / or one or more dielectric layers are deposited. Conductive layer 1302 may, for example, be or include metal and / or some other suitable conductive material(s). Dielectric layer 1304 may, for example, be or include silicon oxide, high-k dielectric, some other suitable dielectric(s), or any combination of the foregoing.

[0083] like Fig.14 As shown in the cross-sectional view 1400, the conductive layer 1302 (see for example Fig.13 ) and dielectric layer 1304 (see e.g. Fig.13 ) is patterned to form a plurality of 2D trench capacitors 126 defining the first device layer 112a. In alternative embodiments, more or fewer 2D trench capacitors 126 are formed. For example, in alternative embodiments, a single 2D trench capacitor 126 may be formed. The 2D trench capacitor 126 includes corresponding capacitor electrodes 128 and corresponding capacitor dielectric layers 130 that are alternately stacked and formed by conductive layers 1302 and dielectric layers 1304, respectively. In addition, the 2D trench capacitor 126 has corresponding trench portions 104. The trench portions 104 are defined by the capacitor electrodes 128 and the capacitor dielectric layers 130, and are respectively located at the first trenches 1202a (see, e.g. Fig.12 ).

[0084] Since the trench 1202 is formed with the first depth D1, the trench portion 104 is formed with the first depth D1. As such, the trench portion 104 laterally contacts the first interconnect dielectric layer 118a and the first substrate 110a. Additionally, since a portion of the first depth D1 is located in the first interconnect dielectric layer 118a, the first depth D1 may be greater than if it were completely or substantially located in the first substrate 110a. As such, the 2D trench capacitor 126 may have a greater capacitance than it would otherwise have.

[0085] The patterning of the conductive layer 1302 and the dielectric layer 1304 may include, for example: 1) performing a planarization to the top conductive layer 1302a (see, for example, Fig.13 ) and a top dielectric layer 1304a (see e.g. Fig.13 ) to expose the lower conductive layer 1302b (see, for example Fig.13 ); and 2) in the lower conductive layer 1302b and the lower dielectric layer 1304b (see, e.g. Fig.13 ) is performed on the substrate. However, other processes for performing patterning are acceptable.

[0086] like Fig.15As shown in the cross-sectional view 1500 of , the second interconnect dielectric layer 118b and the third interconnect dielectric layer 118c are formed above the 2D trench capacitor 126. The second interconnect dielectric layer 118b and the third interconnect dielectric layer 118c can be or include, for example, silicon oxide, silicon nitride, low-k dielectric, some other suitable (some) dielectrics, or any combination of the foregoing. In some embodiments, the third interconnect dielectric layer 118c is or includes silicon oxide, some other suitable oxide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing.

[0087] Also through Fig.15 The cross-sectional view 1500 shows that while the second interconnect dielectric layer 118b and the third interconnect dielectric layer 118c are being formed, a plurality of conductors 120 and a plurality of vias 122 are formed in the second interconnect dielectric layer 118b and the third interconnect dielectric layer 118c. The conductors 120 and the vias 122 are alternately stacked in the second interconnect dielectric layer 118b and the third interconnect dielectric layer 118c to define a conductive path that electrically connects the 2D trench capacitors 126 in parallel. In addition, the TSV conductor 120a defines a pad 1502 to receive a subsequently formed TSV and electrically connect the pad 1502 to the remainder of the conductor 120 and the remainder of the via 122 shown. The remainder of the conductor 120 and the remainder of the via 122 shown in turn electrically connect the TSV conductor 120a to the terminal of the 2D trench capacitor 126. In some embodiments, the TSV conductor 120a has a structure such as Figure 2 For example, Figure 2 It can be taken along line AA'. In alternative embodiments, the TSV conductive line 120a has some other suitable top layout.

[0088] The first interconnect dielectric layer 118a, the second interconnect dielectric layer 118b, the third interconnect dielectric layer 118c, the conductive line 120, and the via 122 collectively define the first interconnect structure 114a. For ease of illustration, the first interconnect dielectric layer 118a, the second interconnect dielectric layer 118b, and the third interconnect dielectric layer 118c are shown below (e.g., in Fig.16 The first device layer 112a and the first substrate 110a together define the first IC die 106a. Although the first IC die 106a is formed as shown in FIG. Figure 1 , but the first IC die 106a may alternatively be formed as Figure 4A-4E , Figure 5A ,and Figure 5B as shown in any one of the .

[0089] like Fig.16As shown in the cross-sectional view 1600 of FIG. 1 , the first IC die 106a is flipped vertically and the first substrate 110a is thinned from the back side 124 of the first substrate 110a. In addition, the first IC die 106a is patterned from the back side 124 of the first substrate 110a to form through-hole openings 1602 that expose the pads 1502, respectively. The thinning reduces the thickness T of the first substrate 110a. fs The planarization may be performed, for example, by CMP or some other suitable planarization. The patterning may be performed, for example, by a photolithography / etching process or some other suitable patterning process.

[0090] Since the through hole opening 1602 extends through the first substrate 110a, the aspect ratio (e.g., the ratio of height to width) of the through hole opening 1602 may be high. However, if the aspect ratio is too high, it may be difficult to reliably form the through hole opening 1602 and / or it may be difficult to subsequently form a TSV in the through hole opening 1602. For example, during the deposition of the layer from which the TSV is formed, material may gather around the top corner of the through hole opening 1602. This phenomenon may be referred to as trench necking. Before the deposition is completed, the aggregation may pinch off the top of the through hole opening 1602, and may therefore cause a gap to be formed in the through hole opening 1602. The gap may cause the power consumption of the TSV with high resistance to increase and / or cause the operating parameters to deviate from the specification range.

[0091] In order to alleviate the aforementioned problems, thinning is implemented. By reducing the thickness T fs , thinning can reduce the aspect ratio of the via opening 1602. However, by reducing the thickness T fs , thinning also limits the distance that the trench portion 104 can extend into the first substrate 110a. In other words, thinning limits the portion of the first depth D1 that is located in the first substrate 110a. If the trench portion 104 is completely or substantially located in the first substrate 110a, the thinning will limit the first depth D1, and therefore will limit the capacitance of the 2D trench capacitor 126. However, since a portion of the first depth D1 is also located in the interconnect dielectric layer 118, the negative impact from thinning is mitigated, and the 2D trench capacitor 126 can have a high capacitance.

[0092] like Fig.17 As shown in the cross-sectional view 1700, the TSV 132 and the TSV dielectric layer 134 are formed in the through hole opening 1602 (see, for example, Fig.16 ). TSV 132 corresponds to the first terminal T1 of the formed 3D trench capacitor and the second terminal T2 of the 3D trench capacitor. In addition, TSV 132 is electrically connected to the terminals of the 2D trench capacitor 126 through the wire 120 and the through hole 122. TSV dielectric layer 134 separates TSV 132 from the first substrate 110a.

[0093] The process for forming the TSV dielectric layer 134 may, for example, include: 1) depositing a dielectric layer over the first substrate 110a, the dielectric layer further lining the via opening 1602 and partially filling the via opening 1602; and 2) etching back the dielectric layer to expose the back side 124 of the first substrate 110a and the pad 1502. The process for forming the TSV 132 may, for example, include: 1) depositing a conductive layer over the first substrate 110a and the TSV dielectric layer 134, the conductive layer further filling the remaining portion of the via opening 1602; and 2) performing planarization from the back side 124 of the first substrate 110a into the conductive layer to expose the back side 124 of the first substrate 110a. The planarization may, for example, be or include CMP or some other suitable planarization. However, other processes for forming the TSV dielectric layer 134 and / or the TSV 132 are acceptable.

[0094] like Fig.18 As shown in the cross-sectional view 1800 of , the second device layer 112b is formed above the second substrate 110b. The second device layer 112b includes a plurality of 2D trench capacitors 126. In alternative embodiments, more or fewer 2D trench capacitors 126 are formed. For example, in an alternative embodiment, a single 2D trench capacitor 126 may be formed. The 2D trench capacitor 126 includes corresponding capacitor electrodes 128 and corresponding capacitor dielectric layers 130 that are alternately stacked and define a trench portion 104. The trench portion 104 extends or protrudes into the second substrate 110b and has a second depth D2 that is completely or substantially located in the second substrate 110b. This is different from the trench portion 104 of the first IC die 106a having a first depth D1 that is partially located in the first substrate 110a (see, e.g. Fig.17 ) is the opposite.

[0095] Also through Fig.18 The cross-sectional view 1800 of FIG. 1 shows that the second interconnect structure 114 b is formed above the second device layer 112 b and is electrically connected to the second device layer 112 b. The second interconnect structure 114 b includes an interconnect dielectric layer 118, and also includes a plurality of wires 120 and a plurality of vias 122. The wires 120 and vias 122 are alternately stacked in the interconnect dielectric layer 118 to define a conductive path that electrically connects the 2D trench capacitors 126 in parallel. In addition, the bonding wires 120 c at the top of the second interconnect structure 114 b have the same structure as their counterparts in the first IC die 106 a (in FIG. 1 ). Fig.17 The same top layout is also marked as 120c).

[0096] The second interconnect structure 114b, the second device layer 112b, and the second substrate 110b together define a second IC die 106b. In some embodiments, the second IC die 106b is connected to the Figure 12-Figure 15 The same process as described above is formed, except that the conductive line 120 and the through hole 122 have different layouts. In addition, no Fig.14 The first interconnect dielectric layer 118a in the second substrate 110b is formed so that the trench portion 104 is completely or substantially located in the second substrate 110b. In an alternative embodiment, the second IC die 106b is connected to the first interconnect dielectric layer 118a in the second substrate 110b. Figure 12-Figure 15 The same process as described above may be used to form the second IC die 106b, or may be formed by some other suitable process. Figure 1 As shown, however, the second IC die 106b may alternatively be formed as Figure 4A-4E , Figure 5A ,and Figure 5B as shown in any one of the .

[0097] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , the bonding surface 1902 of the first interconnect structure 114 a and the second interconnect structure 114 b is pretreated and then roughly aligned. In an alternative embodiment, the line alignment and / or pretreatment are omitted. The pretreatment may, for example, include a cleaning process, a plasma treatment, some other suitable (some) pretreatment process for hybrid bonding, or any combination of the foregoing. In some embodiments, the bonding surface 1902 is cleaned by plasma treatment.

[0098] Also through Fig.19 The cross-sectional view 1900 shows that the bonding surfaces 1902 are hybrid bonded together. The process for implementing hybrid bonding may, for example, include: 1) finely aligning the first IC die 106a with the second IC die 106b so that the bonding wires 120c of the first IC die 106a are respectively located above the bonding wires 120c of the second IC die 106b and aligned with the bonding wires 120c of the second IC die 106b; and 2) bringing the bonding surfaces 1902 into direct contact. However, other processes for implementing hybrid bonding are acceptable.

[0099] like Fig. 20As shown in the cross-sectional view 2000 of FIG. 2 , the first IC die 106 a and the second IC die 106 b are annealed to strengthen the front side bonding interface 108 where the first IC die 106 a and the second IC die 106 b are in direct contact. The 2D trench capacitor 126 of the first IC die 106 a is electrically connected in parallel with the 2D trench capacitor 126 of the second IC die 106 b through the conductive lines 120 and the vias 122 in the first IC die 106 a and the second IC die 106 b through the front side bonding interface 108. In addition, the conductive lines 120 of the first IC die 106 a and the vias 122 of the first IC die 106 a electrically connect the 2D trench capacitors 126 of the first IC die 106 a and the second IC die 106 b to the TSVs 132. The 2D trench capacitors 126 of the first IC die 106 a and the second IC die 106 b collectively define the 3D trench capacitor 102.

[0100] Since the 2D trench capacitors 126 are distributed over multiple device layers (e.g., the first device layer 112a and the second device layer 112b) along the vertical dimension or Z dimension, the 3D trench capacitor 102 can have a small footprint. In addition, since the capacitance of the 3D trench capacitor 102 is the sum of the capacitances of multiple 2D trench capacitors (e.g., the sum of the capacitances of the 2D trench capacitors 126 in the first IC die 106a and the second IC die 106b), the 3D trench capacitor 102 can have a high capacitance. Due to the high capacitance and small footprint, the 3D trench capacitor 102 can have a high capacitance density. That is, the capacitance per unit area in the footprint of the 3D trench capacitor 102 may be very high.

[0101] Although various embodiments of the reference method have been described Figure 12-Figure 20 , but it should be understood that Figure 12-Figure 20 The structure shown in is not limited to this method, but can exist independently outside of this method. Figure 12-Figure 20 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 12-Figure 20 A particular set of actions is shown and described, but in other embodiments, some actions shown and / or described may be omitted. In addition, other embodiments may include actions that are not shown and / or described.

[0102] refer to Fig.21 , provides Figure 12-Figure 20 Block diagram 2100 of some embodiments of the method.

[0103] At 2102, a first interconnect dielectric layer is deposited to cover the first substrate on the front side of the first substrate. See, e.g. Fig.12 In an alternative embodiment, the deposition of the first interconnect dielectric layer is omitted.

[0104] At 2104, a first trench capacitor is formed extending through the first interconnect dielectric layer on the front side of the first substrate into the first substrate. See, e.g. Figure 12-14 .

[0105] At 2106, a first interconnect structure is formed to cover and electrically connect to a first trench capacitor located on the front side of the first substrate, wherein the first interconnect structure includes a plurality of conductive lines and a plurality of vias stacked alternately. Fig.15 .

[0106] At 2108, a pair of TSVs are formed extending from the back side of the first substrate through the first substrate to the first interconnect structure, wherein the TSVs are electrically connected to the terminals of the first trench capacitor through conductive lines and vias, respectively. Fig.16 and Fig.17 .

[0107] At 2110, a second trench capacitor is formed extending into the second substrate on the front side of the second substrate. See, e.g. Fig.18 .

[0108] At 2112, a second interconnect structure is formed to cover and electrically connect to a second trench capacitor located on the front side of the second substrate, wherein the second interconnect structure includes a plurality of conductive lines and a plurality of vias stacked alternately. Fig.18 .

[0109] At 2114, the bonding surfaces of the first interconnect structure and the second interconnect structure are pre-treated. Fig.19 .

[0110] At 2116, the first interconnect structure and the second interconnect structure are aligned with each other. See, e.g. Fig.19 .

[0111] At 2118, the bonding surfaces of the first interconnect structure and the second interconnect structure are hybrid bonded to each other at a front bonding interface, wherein the wires and vias electrically connect the first trench capacitor and the second trench capacitor to the TSV and are connected in parallel through the front bonding interface. See, e.g. Fig.19 The first trench capacitor and the second trench capacitor together define a 3D trench capacitor. Since the first trench capacitor and the second trench capacitor are distributed on multiple substrates along the vertical dimension or Z dimension, the 3D trench capacitor may have both a small footprint and a high capacitance. Due to the high capacitance and small footprint, the 3D trench capacitor may have a high capacitance density.

[0112] At 2120, the front bonding interface is annealed to strengthen the front bonding interface. See e.g. Fig. 20 .

[0113] Although here Fig.21 The block diagram 2100 is shown and described as a series of actions or events, but it should be understood that the order shown in such actions or events should not be interpreted in a restrictive sense. For example, in addition to those actions or events shown and / or described herein, some actions may occur in different orders and / or occur simultaneously with other actions or events. In addition, all the actions shown may not be needed to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0114] refer to Figure 22-Figure 27 , provides a method for forming Figure 7 A series of cross-sectional views 2200-2700 of some embodiments of a method for forming a semiconductor structure having trench portions located on at least two substrates and electrically connected together by TSVs. Figure 7 The semiconductor structure of the present invention can be formed by using this method and its variants. Figure 8A-8E , Fig. 9A , Fig. 9B , Fig. 10B ,and Fig. 10C A semiconductor structure in any one of the above, or some other suitable semiconductor structure.

[0115] like Fig. 22 Cross-sectional view 2200 and Fig.23 As shown in the cross-sectional view 2300, the first IC die 106a is formed respectively (see for example Fig. 22 ) and a second IC die 106b (see e.g. Fig.23 ). The first device layer 112a is located on the front side 116 of the first substrate 110a, and the second device layer 112b is located on the front side 116 of the second substrate 110b. The first device layer 112a and the second device layer 112b include corresponding 2D trench capacitors 126. The 2D trench capacitors 126 include corresponding capacitor electrodes 128 and corresponding capacitor dielectric layers 130 that are alternately stacked and define trench portions 104. The trench portions 104 of the first IC die 106a extend into the first substrate 110a to a first depth D1 and are completely or substantially located within the first substrate 110a. The trench portions 104 of the second IC die 106b extend into the second substrate 110b to a second depth D2 and are completely or substantially located within the second substrate 110b. In some embodiments, the first depth D1 is less than the second depth D2 because the thickness T of the first substrate 110a is fs may be limited by the subsequent formation of TSVs, as described above Fig.16 and Fig.17 as described.

[0116] The first interconnect structure 114a covers and is electrically connected to the 2D trench capacitor 126 of the first IC die 106a located on the front side 116 of the first substrate 110a. Similarly, the second interconnect structure 114b covers and is electrically connected to the 2D trench capacitor 126 of the second IC die 106b located on the front side 116 of the second substrate 110b. The first interconnect structure 114a and the second interconnect structure 114b include corresponding interconnect dielectric layers 118, and corresponding wires 120 and corresponding vias 122. The wires 120 and the vias 122 are alternately stacked in the interconnect dielectric layer 118 to define a conductive path that electrically connects the 2D trench capacitors 126 in parallel. In addition, the TSV wire 120a defines a pad 1502 to receive a subsequently formed TSV, and the pad 1502 is electrically connected to the rest of the wire 120 and the rest of the via 122. The remaining portion of the conductive line 120 and the remaining portion of the via 122 then electrically connect the TSV conductive line 120a to the terminal of the 2D trench capacitor 126. In some embodiments, the TSV conductive line 120a has a Figure 2 For example, Figure 2 It may be cut along line EE', and / or cut along line FF'. In alternative embodiments, the TSV conductive line 120a has some other suitable top layout.

[0117] In some embodiments, the first IC die 106a and the second IC die 106b are symmetrical and / or formed by the same process. Forming the first IC die 106a and the second IC die 106b by the same process can, for example, reduce manufacturing costs because there is only one process instead of two separate processes for the first IC die 106a and the second IC die 106b. In addition, in some embodiments, the first IC die 106a and the second IC die 106b are formed by Figure 12-Figure 15 The process described in the above is formed separately, except that no Fig.14 The first interconnect dielectric layer 118a in the embodiment of the present invention is formed by a first IC die 106a and a second IC die 106b, and the conductive lines 120 and the through-holes 122 have different layouts. For the latter, the conductive lines can be omitted at the bonding surfaces 1902 of the first IC die 106a and the second IC die 106b, so that the bonding surfaces 1902 are limited to the dielectric material. In alternative embodiments, the first IC die 106a and / or the second IC die 106b are formed by some other suitable process.

[0118] Although the first IC die 106a is formed as Figure 7 As shown, however, the first IC die 106a may alternatively be formed as Figure 8A-8E , Fig. 9A ,and Fig. 9BSimilarly, although the second IC die 106b is formed as Figure 7 As shown, however, the second IC die 106b may alternatively be formed as Figure 8A-8E , Fig. 9A ,and Fig. 9B as shown in any one of the .

[0119] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 1 , the first IC die 106 a is flipped vertically. In addition, the bonding surfaces 1902 of the first interconnect structure 114 a and the second interconnect structure 114 b are pretreated and roughly aligned. In an alternative embodiment, the line alignment and / or pretreatment are omitted. The pretreatment may, for example, include a cleaning process, a plasma treatment, some other suitable pretreatment process(es) for fusion bonding, or any combination of the foregoing.

[0120] Also through Fig.24 The cross-sectional view 2400 of FIG. 2400 shows that the bonding surfaces 1902 are fusion bonded together. The process for implementing fusion bonding may, for example, include: 1) finely aligning the first IC die 106a with the second IC die 106b so that the pads 1502 of the first IC die 106a are respectively located above the pads 1502 of the second IC die 106b and aligned with the pads 1502 of the second IC die 106b; and 2) bringing the bonding surfaces 1902 into direct contact. However, other processes for implementing fusion bonding are acceptable.

[0121] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25, the first IC die 106a and the second IC die 106b are annealed to strengthen the front bonding interface 108 where the first IC die 106a and the second IC die 106b are in direct contact. Fig. 20 In contrast, the 2D trench capacitors 126 of the first IC die 106 a are not yet electrically connected to each other.

[0122] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 26 , the first substrate 110 a is thinned from the back side 124 of the first substrate 110 a. The thinning can reduce the thickness T of the first substrate 110 a. fs and can be implemented, for example, by CMP or some other suitable planarization. Fig.16 As described, thinning may be performed, for example, to reduce the aspect ratio of subsequently formed TSVs and alleviate challenges associated with high aspect ratios.

[0123] Also through Fig.26The cross-sectional view 2600 shows that the first IC die 106a and the second IC die 106b are patterned from the back side 124 of the first substrate 110a to form via openings 2602 extending through the pads 1502 of the first IC die 106a and respectively exposing the pads 1502 of the second IC die 106b. In addition, the TSV dielectric layer 134 is formed on the sidewalls of the via openings 2602 at the first IC die.

[0124] The process for forming the via opening 2602 and the TSV dielectric layer 134 may, for example, include: 1) performing a lithography / etching process into the back side 124 of the first substrate 110a until reaching the pad 1502 of the first IC die 106a; 2) depositing a dielectric layer over the first substrate 110a, which further acts as a liner for the via opening 2602 and partially fills the via opening 2602; 3) etching back the dielectric layer to expose the pad 1502 of the first IC die 106a and form the TSV dielectric layer 134; and 4) performing an etching process through the pad 1502 of the first IC die 106a to the pad 1502 of the second IC die 106b. During the etching process of step 4), the TSV dielectric layer 134 may, for example, be used as a lateral etch stop. Although the aforementioned processes are used to pattern the first IC die 106 a and the second IC die 106 b and to form the TSV dielectric layer 134 , other processes are acceptable.

[0125] like Fig. 27 As shown in the cross-sectional view 2700, at the through hole opening 2602 (see for example Fig.26 ) are formed in the first substrate 110a. The TSVs 132 electrically connect the 2D trench capacitors 126 of the first IC die 106a and the 2D trench capacitors 126 of the second IC die 106b in parallel. The 2D trench capacitors 126 of the first IC die 106a and the second IC die 106b together define a 3D trench capacitor 102 having a first terminal T1 and a second terminal T2 accessible from the back side 124 of the first substrate 110a. T2 .

[0126] Since the 2D trench capacitors 126 are distributed on the first device layer 112a and the second device layer 112b along the vertical dimension or Z dimension, the 3D trench capacitor 102 can have a small footprint. In addition, since the capacitance of the 3D trench capacitor 102 is the sum of the capacitances of the 2D trench capacitors 126 in the first IC die 106a and the second IC die 106b, the 3D trench capacitor 102 can have a high capacitance. Due to the high capacitance and small footprint, the 3D trench capacitor 102 can have a high capacitance density. Accordingly, since the first IC die 106a and the second IC die 106b are bonded together by fusion bonding and are electrically connected together by TSV 132, hybrid bonding (see, e.g. Figure 12-Figure 21 methods) related technical challenges.

[0127] Although various embodiments of the reference method have been described Figure 22-Figure 27 , but it should be understood that Figure 22-Figure 27 The structure shown in is not limited to this method, but can exist independently outside of this method. Figure 22-Figure 27 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 22-Figure 27 A particular set of actions is shown and described, but in other embodiments, some actions shown and / or described may be omitted. In addition, other embodiments may include actions that are not shown and / or described.

[0128] refer to Fig.28 , provides Figure 22-Figure 27 Block diagram 2800 of some embodiments of the method.

[0129] At 2802, a first trench capacitor is formed extending into the first substrate on a front side of the first substrate. See, e.g. Fig. 22 .

[0130] At 2804, a first interconnect structure is formed to cover and electrically connect to a first trench capacitor located on a front surface of the first substrate, wherein the first interconnect structure includes a plurality of conductive lines and a plurality of vias stacked alternately. Fig. 22 .

[0131] At 2806, a second trench capacitor is formed extending into the second substrate on the front side of the second substrate. See, e.g. Fig.23 .

[0132] At 2808, a second interconnect structure is formed to cover and electrically connect to a second trench capacitor located on the front side of the second substrate, wherein the second interconnect structure includes a plurality of conductive lines and a plurality of vias stacked alternately. Fig.23 .

[0133] At 2810, the bonding surfaces of the first interconnect structure and the second interconnect structure are pre-treated. Fig.24 .

[0134] At 2812, the first interconnect structure and the second interconnect structure are aligned with each other. See, e.g. Fig.24 .

[0135] At 2814, the bonding surfaces of the first interconnect structure and the second interconnect structure are respectively fusion bonded to each other at a front bonding interface, wherein the first interconnect structure and the second interconnect structure are electrically isolated from each other when the fusion bonding is completed. See, e.g. Fig.24 .

[0136] At 2816, the front bonding interface is annealed to strengthen the front bonding interface. See e.g. Fig.25 .

[0137] At 2818, a pair of TSVs are formed extending from the back side of the first substrate through the first substrate and the first interconnect structure to the second interconnect structure, wherein the TSVs are electrically connected to the first trench capacitor and the second trench capacitor through conductive lines and vias. See, e.g. Fig.26 and Fig. 27 The first trench capacitor and the second trench capacitor together define a 3D trench capacitor. Since the 2D trench capacitors are distributed on multiple substrates along the vertical dimension or Z dimension, the 3D trench capacitor may have both a small footprint and a high capacitance. Due to the high capacitance and small footprint, the 3D trench capacitor may have a high capacitance density.

[0138] Although here Fig.28 The block diagram 2800 is shown and described as a series of actions or events, but it should be understood that the order shown in such actions or events should not be interpreted in a restrictive sense. For example, in addition to those actions or events shown and / or described herein, some actions may occur in different orders and / or occur simultaneously with other actions or events. In addition, all the actions shown may not be needed to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0139] In some embodiments, the present invention provides a semiconductor structure, comprising: a first substrate and a second substrate; a first trench capacitor and a second trench capacitor, extending into the front side of the first substrate and the front side of the second substrate, respectively, wherein the front side of the first substrate and the front side of the second substrate face each other; a plurality of wires and a plurality of vias, stacked between the first trench capacitor and the second trench capacitor, and electrically connected to the first trench capacitor and the second trench capacitor; and a first TSV, extending through the first substrate from the back side of the first substrate opposite to the front side of the first substrate, wherein the wires and the vias electrically connect the first TSV to the first trench capacitor and the second trench capacitor. In some embodiments, the semiconductor structure further comprises a first dielectric layer, located between the first trench capacitor and the first substrate, wherein the first trench capacitor extends completely through the first dielectric layer into the front side of the first substrate. In some embodiments, the thickness of the first dielectric layer is approximately equal to the difference between the thickness of the first substrate and the thickness of the second substrate. In some embodiments, the plurality of wires and the plurality of vias are grouped into a first alternating stack of wires and vias and a second alternating stack of wires and vias, and wherein the first alternating stack and the second alternating stack are spaced apart from each other and electrically connected together by the first TSV. In some embodiments, a plurality of conductors and a plurality of vias define a first conductive path extending from a first TSV to a first trench capacitor, and further define a second conductive path extending from the first TSV to a second trench capacitor, and wherein the first conductive path and the second conductive path do not overlap. In some embodiments, the plurality of conductors and the plurality of vias are grouped into a first alternating stack of conductors and vias and a second alternating stack of conductors and vias, wherein the first alternating stack and the second alternating stack are in direct contact at a hybrid bonding interface, and wherein the first TSV extends from the back side of the first substrate through the first substrate and terminates between the hybrid bonding interface and the first substrate. In some embodiments, the plurality of conductors and the plurality of vias define a first conductive path extending from the first TSV to the first trench capacitor, and further define a second conductive path extending from the first TSV to the second trench capacitor, and wherein the first conductive path and the second conductive path partially overlap. In some embodiments, the semiconductor structure further includes: a second TSV extending from the back side of the first substrate through the first substrate, and wherein the conductors and the vias electrically connect the second TSV to the first trench capacitor and the second trench capacitor. In some embodiments, the first trench capacitor includes: a first electrode having a columnar profile; a capacitor dielectric layer surrounding the first electrode and separating the first electrode from the first substrate; and a second electrode surrounding the capacitor dielectric layer and separating the capacitor dielectric layer from the first substrate.

[0140] In some embodiments, the present invention provides an IC, comprising: a first IC die, comprising a first substrate, a first interconnect structure located below the first substrate, and a first trench capacitor, wherein the first trench capacitor extends into the first substrate and is located between the first substrate and the first interconnect structure; a second IC die, located below the first IC die and directly bonded to the first IC die, wherein the second IC die comprises a second substrate, a second interconnect structure located above the second substrate, and a second trench capacitor, and wherein the second trench capacitor extends into the second substrate and is located between the second substrate and the second interconnect structure; and a pair of TSVs extending through the first substrate and electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure. In some embodiments, the TSVs are positioned to the first IC die. In some embodiments, the TSVs extend completely through the first IC die and terminate in the second IC die, wherein the TSVs each directly contact the sidewall of the first TSV wire in the first interconnect structure, and wherein the TSVs each directly contact and terminate at the top surface of the second TSV wire in the second interconnect structure.

[0141] In some embodiments, the present invention provides a method for forming a 3D trench capacitor, the method comprising: forming a first trench capacitor extending into the front side of a first substrate; forming a first interconnect structure covering and electrically connected to the first trench capacitor on the front side of the first substrate; forming a second trench capacitor extending into the front side of a second substrate; forming a second interconnect structure covering and electrically connected to the second trench capacitor on the front side of the second substrate; bonding the first interconnect structure and the second interconnect structure together at a bonding interface where the first interconnect structure and the second interconnect structure are in direct contact with each other; and forming a first TSV extending through the back side of the first substrate from the back side of the first substrate, wherein the first TSV is electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure. In some embodiments, the first trench capacitor and the second trench capacitor are electrically connected in parallel by bonding. In some embodiments, bonding is performed by a hybrid bonding process, wherein the metal and dielectric material of the first interconnect structure contact the metal and dielectric material of the second interconnect structure respectively and directly at the bonding interface. In some embodiments, the method further comprises: performing etching into the back side of the first substrate before bonding, wherein the etching forms an opening and stops on the TSV wire in the first interconnect structure; and filling the opening with a conductive material to define a first TSV in the opening. In some embodiments, when the bonding is completed, the first trench capacitor and the second trench capacitor are electrically isolated from each other, and wherein the formation of the first TSV electrically connects the first trench capacitor to the second trench capacitor. In some embodiments, the bonding is performed by a fusion bonding process, wherein the dielectric material of the first interconnect structure directly contacts the dielectric material of the second interconnect structure at the bonding interface, and wherein the bonding interface does not have a conductive material. In some embodiments, the method further includes: performing etching into the back side of the first substrate after bonding, wherein the etching forms an opening and stops on the TSV wire in the second interconnect structure; and filling the opening with a conductive material to define a first TSV in the opening. In some embodiments, the method further includes: depositing a dielectric layer located on the front side of the first substrate; performing etching from the front side of the first substrate into the dielectric layer and the first substrate to form a trench; forming a multilayer capacitor film that fills the trench; and patterning the multilayer capacitor film into a first trench capacitor.

[0142] According to one embodiment of the present application, a semiconductor structure is provided, comprising: a first substrate and a second substrate; a first trench capacitor and a second trench capacitor, extending into the front side of the first substrate and the front side of the second substrate, respectively, wherein the front side of the first substrate and the front side of the second substrate face each other; a plurality of wires and a plurality of vias, stacked between the first trench capacitor and the second trench capacitor, and electrically connected to the first trench capacitor and the second trench capacitor; and a first through-substrate via (TSV), extending through the first substrate from the back side of the first substrate opposite to the front side of the first substrate, wherein the wire and the via electrically connect the first TSV to the first trench capacitor and the second trench capacitor. In some embodiments, the semiconductor structure further comprises: a first dielectric layer, located between the first trench capacitor and the first substrate, wherein the first trench capacitor extends completely through the first dielectric layer into the front side of the first substrate. In some embodiments, the thickness of the first dielectric layer is approximately equal to the difference between the thickness of the first substrate and the thickness of the second substrate. In some embodiments, the plurality of wires and the plurality of vias are grouped into a first alternating stack of wires and vias and a second alternating stack of wires and vias, and wherein the first alternating stack and the second alternating stack are spaced apart from each other and electrically connected together by the first TSV. In some embodiments, a plurality of conductors and a plurality of vias define a first conductive path extending from a first TSV to a first trench capacitor, and further define a second conductive path extending from the first TSV to a second trench capacitor, and wherein the first conductive path and the second conductive path do not overlap. In some embodiments, the plurality of conductors and the plurality of vias are grouped into a first alternating stack of conductors and vias and a second alternating stack of conductors and vias, wherein the first alternating stack and the second alternating stack are in direct contact at a hybrid bonding interface, and wherein the first TSV extends from the back side of the first substrate through the first substrate and terminates between the hybrid bonding interface and the first substrate. In some embodiments, the plurality of conductors and the plurality of vias define a first conductive path extending from the first TSV to the first trench capacitor, and further define a second conductive path extending from the first TSV to the second trench capacitor, and wherein the first conductive path and the second conductive path partially overlap. In some embodiments, the semiconductor structure further includes: a second TSV extending from the back side of the first substrate through the first substrate, and wherein the conductors and the vias electrically connect the second TSV to the first trench capacitor and the second trench capacitor. In some embodiments, the first trench capacitor includes: a first electrode having a columnar profile; a capacitor dielectric layer surrounding the first electrode and separating the first electrode from the first substrate; and a second electrode surrounding the capacitor dielectric layer and separating the capacitor dielectric layer from the first substrate.

[0143] According to another embodiment of the present application, an integrated circuit (IC) is provided, comprising: a first IC die, comprising a first substrate, a first interconnect structure located below the first substrate, and a first trench capacitor, wherein the first trench capacitor extends into the first substrate and is located between the first substrate and the first interconnect structure; a second IC die, located below the first IC die and directly bonded to the first IC die, wherein the second IC die comprises a second substrate, a second interconnect structure located above the second substrate, and a second trench capacitor, and wherein the second trench capacitor extends into the second substrate and is located between the second substrate and the second interconnect structure; and a pair of through-substrate vias (TSVs), extending through the first substrate and electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure. In some embodiments, the TSVs are positioned to the first IC die. In some embodiments, the TSVs extend completely through the first IC die and terminate in the second IC die, wherein the TSVs each directly contact the sidewall of the first TSV wire in the first interconnect structure, and wherein the TSVs each directly contact and terminate at the top surface of the second TSV wire in the second interconnect structure.

[0144] According to another embodiment of the present application, a method for forming a three-dimensional (3D) trench capacitor is provided, the method comprising: forming a first trench capacitor extending into the front side of a first substrate; forming a first interconnect structure covering and electrically connected to the first trench capacitor on the front side of the first substrate; forming a second trench capacitor extending into the front side of a second substrate; forming a second interconnect structure covering and electrically connected to the second trench capacitor on the front side of the second substrate; bonding the first interconnect structure and the second interconnect structure together at a bonding interface where the first interconnect structure and the second interconnect structure are in direct contact with each other; and forming a first through-substrate via (TSV) extending from the back side of the first substrate through the first substrate, wherein the first TSV is electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure. In some embodiments, the first trench capacitor and the second trench capacitor are electrically connected in parallel by bonding. In some embodiments, bonding is performed by a hybrid bonding process, wherein the metal and dielectric materials of the first interconnect structure contact the metal and dielectric materials of the second interconnect structure separately and directly at the bonding interface. In some embodiments, the method for forming a three-dimensional (3D) trench capacitor further includes: performing etching into the back side of the first substrate before bonding, wherein the etching forms an opening and stops on a TSV wire in the first interconnect structure; and filling the opening with a conductive material to define a first TSV in the opening. In some embodiments, wherein, when bonding is completed, the first trench capacitor and the second trench capacitor are electrically isolated from each other, and wherein the formation of the first TSV electrically connects the first trench capacitor to the second trench capacitor. In some embodiments, wherein the bonding is performed by a fusion bonding process, wherein the dielectric material of the first interconnect structure directly contacts the dielectric material of the second interconnect structure at the bonding interface, and wherein the bonding interface does not have a conductive material. In some embodiments, the method for forming a three-dimensional (3D) trench capacitor further includes: performing etching into the back side of the first substrate after bonding, wherein the etching forms an opening and stops on a TSV wire in the second interconnect structure; and filling the opening with a conductive material to define a first TSV in the opening. In some embodiments, the method for forming a three-dimensional (3D) trench capacitor also includes: depositing a dielectric layer located on the front side of a first substrate; etching into the dielectric layer and the first substrate from the front side of the first substrate to form a trench; forming a multilayer capacitor film filling the trench; and patterning the multilayer capacitor film into a first trench capacitor.

[0145] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a first substrate and a second substrate; a first trench capacitor and a second trench capacitor extending into a front side of the first substrate and a front side of the second substrate, respectively, wherein the front side of the first substrate and the front side of the second substrate face each other; a plurality of conductive lines and a plurality of vias stacked between the first trench capacitor and the second trench capacitor and electrically connected to the first trench capacitor and the second trench capacitor; and a first through substrate via extending through the first substrate from a back side of the first substrate opposite the front side of the first substrate, wherein the conductive line and the via electrically connect the first through substrate via to the first trench capacitor and the second trench capacitor, wherein the plurality of conductive lines and the plurality of vias are grouped into a first alternating stack of conductive lines and vias and a second alternating stack of conductive lines and vias, and wherein the first alternating stack and the second alternating stack are spaced apart from each other and electrically connected together through the first through substrate via.

2. The semiconductor structure according to claim 1, further comprising: A first dielectric layer is located between the first trench capacitor and the first substrate, wherein the first trench capacitor extends completely through the first dielectric layer into the front side of the first substrate.

3. The semiconductor structure according to claim 2, wherein: The thickness of the first dielectric layer is equal to the difference between the thickness of the first substrate and the thickness of the second substrate.

4. The semiconductor structure according to claim 1, wherein: The first through substrate via directly contacts sidewalls of a first through substrate via conductor in the first alternating stack, and the first through substrate via directly contacts and terminates at a top surface of a second through substrate via conductor in the second alternating stack.

5. The semiconductor structure according to claim 1, wherein: The plurality of conductive lines and the plurality of vias define a first conductive path extending from the first through substrate via to the first trench capacitor, and further define a second conductive path extending from the first through substrate via to the second trench capacitor, and wherein the first conductive path and the second conductive path do not overlap.

6. The semiconductor structure according to claim 1, wherein: The first through substrate via extends completely through the first substrate and the first alternating stack and terminates at the second alternating stack.

7. The semiconductor structure according to claim 1, wherein: The plurality of conductive lines and the plurality of vias define a first conductive path extending from the first through substrate via to the first trench capacitor, and further define a second conductive path extending from the first through substrate via to the second trench capacitor, and wherein the first conductive path and the second conductive path partially overlap.

8. The semiconductor structure according to claim 1, further comprising: A second through substrate via extends from the back side of the first substrate through the first substrate, and wherein the conductive line and the via electrically connect the second through substrate via to the first trench capacitor and the second trench capacitor.

9. The semiconductor structure according to claim 1, wherein: The first trench capacitor comprises: A first electrode having a columnar profile; a capacitor dielectric layer surrounding the first electrode and separating the first electrode from the first substrate; and A second electrode surrounds the capacitor dielectric layer and separates the capacitor dielectric layer from the first substrate.

10. An integrated circuit comprising: a first integrated circuit die comprising a first substrate, a first interconnect structure disposed below the first substrate, and a first trench capacitor, wherein the first trench capacitor extends into the first substrate and is disposed between the first substrate and the first interconnect structure; a second integrated circuit die located below the first integrated circuit die and directly bonded to the first integrated circuit die, wherein the second integrated circuit die comprises a second substrate, a second interconnect structure located above the second substrate, and a second trench capacitor, and wherein the second trench capacitor extends into the second substrate and is located between the second substrate and the second interconnect structure; and a pair of through substrate vias extending through the first substrate and electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure, wherein the first interconnect structure and the second interconnect structure are in direct contact at a hybrid bonding interface on the lower side of the front side of the first substrate, wherein the through substrate via extends from the back side of the first substrate through the first substrate and terminates between the hybrid bonding interface and the front side of the first substrate.

11. The integrated circuit of claim 10, wherein: The first interconnect structure includes a first alternating stack of conductive lines and vias, and the second interconnect structure includes a second alternating stack of conductive lines and vias, the first alternating stack and the second alternating stack being in direct contact at the hybrid bonding interface.

12. The integrated circuit of claim 10, wherein: The first interconnect structure and the second interconnect structure define a first conductive path extending from a first through-substrate via of the pair of through-substrate vias to the first trench capacitor, and also define a second conductive path extending from the first through-substrate via to the second trench capacitor, and the first conductive path and the second conductive path partially overlap.

13. A method for forming a three-dimensional (3D) trench capacitor, the method comprising: depositing a dielectric layer on the front side of the first substrate; performing an etch from the front side of the first substrate to form a trench extending through the dielectric layer into the first substrate, wherein the dielectric layer and the first substrate form conformal sidewalls in the trench when the etch is complete; forming a first trench capacitor extending into the front side of the first substrate and lining the conformal sidewalls in the trench; forming a first interconnect structure overlying the front side of the first substrate and electrically connected to the first trench capacitor; forming a second trench capacitor extending into the front side of the second substrate; forming a second interconnect structure overlying and electrically connected to the second trench capacitor on the front side of the second substrate; bonding the first interconnect structure and the second interconnect structure together at a bonding interface where the first interconnect structure and the second interconnect structure are in direct contact with each other; and A first through substrate via is formed extending through the first substrate from a back side of the first substrate, wherein the first through substrate via is electrically connected to the first trench capacitor and the second trench capacitor through the first interconnect structure and the second interconnect structure.

14. The method according to claim 13, wherein: The dielectric layer is located between the first trench capacitor and the first substrate, and the first trench capacitor extends completely through the dielectric layer to the front side of the first substrate.

15. The method according to claim 13, wherein: The bonding is performed by a hybrid bonding process, wherein the metal and dielectric material of the first interconnect structure respectively and directly contact the metal and dielectric material of the second interconnect structure at the bonding interface.

16. The method according to claim 13, further comprising: performing a second etch into the back side of the first substrate prior to the bonding, wherein the second etch forms an opening and stops on a through substrate via wire in the first interconnect structure; and The opening is filled with a conductive material to define the first through substrate via in the opening.

17. The method according to claim 13, wherein: When the bonding is completed, the first trench capacitor and the second trench capacitor are electrically isolated from each other, and wherein the forming of the first through-substrate via electrically connects the first trench capacitor to the second trench capacitor.

18. The method according to claim 13, wherein: The first substrate and the second substrate are semiconductor substrates.

19. The method according to claim 13, further comprising: performing a second etch into the back side of the first substrate after the bonding, wherein the second etch forms an opening extending through a first through substrate via wire in the first interconnect structure and stops on a second through substrate via wire in the second interconnect structure, wherein the opening exposes opposing sidewall segments of the first through substrate via wire in the opening; and The opening is filled with a conductive material to define the first through substrate via in the opening.

20. The method according to claim 13, wherein: Forming the first trench capacitor includes: forming a multilayer capacitor film filling the trench; and The multilayer capacitor film is patterned into the first trench capacitor.

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