Integrated circuit chip, semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes: a buried power rail, arranged between a first fin structure and a second fin structure on a substrate extending in a first direction in a horizontal plane, the first fin structure being located in a first unit, the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal track, arranged in an M1 layer extending in a second direction in the horizontal plane. At the intersection of the buried power rail and the M1 metal track, the semiconductor structure also includes a conductive path to provide a first voltage to the M1 metal track, the conductive path having a first metal zero (M0) metal track extending in the first direction above the boundary line. According to other embodiments of the present application, an integrated circuit chip and a method for manufacturing a semiconductor structure are also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated circuit chip, a semiconductor structure, and a method for manufacturing the semiconductor structure. Background Art

[0002] Over the past four decades, the continued demand for better performance (e.g., increased processing speed, memory capacity, etc.), shrinking form factors, extended battery life, and lower costs has driven semiconductor manufacturing processes. In response to demand, the industry has continued to reduce the size of semiconductor device elements so that a modern integrated circuit (IC) chip may include millions or billions of semiconductor devices arranged on a single semiconductor die. Summary of the invention

[0003] According to an embodiment of the present application, an integrated circuit chip is provided, comprising: a substrate; a first fin structure, arranged on the substrate extending along a first direction on a horizontal plane, the first fin structure being located in a first unit; a second fin structure, arranged on the substrate extending along the first direction, the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending along the first direction; a buried power rail, arranged between the first fin structure and the second fin structure on the substrate extending along the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal rail, arranged in the M1 layer extending in the second direction in the horizontal plane; wherein, at the intersection of the buried power rail and the M1 metal rail in the horizontal plane, the integrated circuit chip further comprises The invention discloses a method for manufacturing a metal-zero (M0) metal track in a vertical direction. The method comprises the following steps: a first vertical interconnection channel (through hole) is arranged on a buried power rail extending in a vertical direction perpendicular to a horizontal plane; a second through hole is arranged on the first vertical interconnection channel (through hole) extending in the vertical direction, the first vertical interconnection channel (through hole) electrically connecting the buried power rail and the second through hole; a first metal zero (M0) metal track is arranged in the M0 layer extending in the first direction, the first M0 metal track is above the boundary line, the second through hole electrically connects the first vertical interconnection channel (through hole) and the first M0 metal track, the M1 layer is above the M0 layer, and the M0 layer is above the buried power rail; and a third through hole is arranged on the first M0 metal track extending in the vertical direction, the third through hole electrically connecting the first M0 metal track and the M1 metal track.

[0004] According to another embodiment of the present application, a semiconductor structure is provided, including: a buried power rail, arranged between a first fin structure and a second fin structure on a substrate extending along a first direction on a horizontal plane, the first fin structure and the second fin structure are arranged on the substrate extending along the first direction, the first fin structure is located in a first unit, the second fin structure is located in a second unit, the second unit is adjacent to the first unit at a boundary line extending along the first direction, the buried power rail provides a first voltage; and a metal one (M1) metal track, arranged in an M1 layer extending in the second direction in a horizontal plane; wherein, at the intersection of the buried power rail and the M1 metal track in the horizontal plane, the semiconductor structure also includes a conductive path to provide a first voltage to the M1 metal track, the conductive path having a first metal zero (M0) metal track arranged in the M0 layer extending along the first direction, and the first M0 metal track is above the boundary line.

[0005] According to another embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising: etching a substrate to form a first fin structure and a second fin structure arranged on the substrate extending in a first direction along a horizontal plane, the first fin structure being located in a first unit, and the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending in the first direction; depositing a first dielectric layer on the first fin structure, the second fin structure, and the substrate; depositing a buried power rail on the first dielectric layer, the buried power rail being between the first fin structure and the second fin structure, extending in the first direction and providing a first voltage; depositing a high-k dielectric layer on the buried power rail and the first dielectric layer; forming a first source structure and a second source structure on the first fin structure and the second fin structure, respectively; forming a first vertical interconnection channel (through hole) on the buried power rail extending in a vertical direction perpendicular to the horizontal plane, wherein the first vertical interconnection channel (through hole) is formed in a first A fin structure and a second fin structure are extended in a bidirectional manner along a second direction on top of a first vertical interconnection channel (through hole), so that the first vertical interconnection channel (through hole) is short-circuited with a first metal diffusion (MD) metal line and a second MD metal line arranged in a metal diffusion (MD) layer, the first MD metal line is arranged on a first source structure, the second MD metal line is arranged on a second source structure, and the MD layer is above a buried power rail; a second through hole is deposited on the first vertical interconnection channel (through hole) extending along the vertical direction, the first vertical interconnection channel (through hole) electrically connecting the buried power rail and the second through hole; and a first metal zero (M0) metal track is deposited on the second through hole, the first M0 metal track extends along the first direction, the second through hole electrically connects the first vertical interconnection channel (through hole) and the first M0 metal track, the first M0 metal track is above the boundary line and arranged in the metal zero (M0) layer, and the M0 layer is above the MD layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a layout diagram of a cell structure compatible with a power tap structure according to some embodiments.

[0008] Figure 1B is with Figure 1A A cross-sectional view corresponding to the line Y1-Y1 of the unit structure.

[0009] Figure 2A is a perspective view of a first embodiment and a second embodiment of a power tap structure according to some embodiments.

[0010] Figure 2B yes Figure 2A Layout diagrams of the first and second embodiments of the power tap structure shown in FIG.

[0011] Figure 3A is a perspective view of a third embodiment of a power tap structure according to some embodiments.

[0012] Figure 3B yes Figure 3A Layout diagram of a third embodiment of a power tap structure shown in FIG.

[0013] Figure 4 is a layout diagram of another embodiment of a power tap structure according to some embodiments.

[0014] Figure 5 is a diagram showing an example of a power tap structure on an IC chip according to some embodiments.

[0015] Figure 6 is a diagram showing another example of a power tap structure on an IC chip according to some embodiments.

[0016] Fig. 7A is a layout diagram illustrating an example method of applying placement constraints according to some embodiments.

[0017] Figure 7B is corresponding to Fig. 7A A flow chart illustrating an example method of applying placement constraints according to some embodiments.

[0018] Fig. 8A is a layout diagram illustrating an example method of applying placement constraints according to some embodiments.

[0019] Figure 8B is corresponding to Fig. 8AA flow chart illustrating an example method of applying placement constraints according to some embodiments.

[0020] Fig. 9 is an illustrative high-level schematic block diagram of a system for implementing layout according to some embodiments.

[0021] Fig. 10A and Fig. 10B An example method for fabricating a semiconductor structure according to some embodiments is shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the process of forming a first component above a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0023] For ease of description, spatially relative terms such as "under," "beneath," "below," "above," and "above," and the like, may be used herein to describe the relationship of one element or component to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0024] Typically, the metal track zero layer (i.e., the "M0" layer) contains, in each cell, two power rails and a certain number (e.g., two, three) of signal tracks, limited by the IC chip area and, more specifically, by the cell height of the cell structure on the IC chip. The two power rails are used to provide different supply voltages (e.g., VDD and ground; VDD and VSS). As technology nodes (e.g., 16nm, 10nm, 7nm) advance, if the cell height shrinks more than the M0 pitch (i.e., the width and space of the M0 metal tracks), the number of signal tracks must be reduced. Due to insufficient M0 metal tracks, the IC chip area must be increased due to placement and routing issues.

[0025] The buried power rail is used to free up more M0 metal tracks for signals. However, since the buried power rail is located below the metal diffusion layer (i.e., the "MD" layer), a prohibited area is required to lift the power from the buried power rail to the metal track one layer (i.e., the "M1" layer), passing through the MD layer and the M0 layer. Ordinary cell structures cannot be placed in the prohibited area because otherwise the power tap in the M1 layer will be short-circuited to the M0 signal track. The M0 layer is above the MD layer, and the M1 layer is above the M0 layer. The existence of the prohibited area affects the IC chip area (i.e., area impact) because conventional cell structures with transistors cannot usually be placed in the prohibited area. Therefore, it is necessary to further improve the power tap structure to reduce the area impact.

[0026] In the present disclosure, a new scheme for a power tap structure is disclosed to increase the number of M0 metal tracks in a cell without the penalty of increasing the cell height. Increasing the number of M0 metal tracks can also increase the density of the IC chip. In other words, more transistors can be placed on the IC chip. Specifically, a buried power rail can be used to provide voltage to the source side of FETs in adjacent cells and simultaneously boost the voltage to the M1 layer for simultaneous power tap purposes. A conductive path is formed to provide voltage to the M1 layer. In this way, those prohibited areas that would otherwise be below the power tap can be used to place ordinary cells with FETs, thereby reducing the area impact of the IC chip.

[0027] Figure 1A An example of a cell structure 100a compatible with a power tap structure according to some embodiments is shown. By burying the power rail, the design of the power tap structure and the cell structure, four M0 metal tracks are available for signals in each cell. In this example cell structure 100a, there are adjacent cells 102a, 102b, and 102c. The boundaries of cells 102a, 102b, and 102c are shown by dotted lines. In this embodiment, cell 102a is in the middle. Cell 102b is adjacent to cell 102a and has a common boundary 101a with cell 102a. Cell 102c is adjacent to cell 102a and has a common boundary 101b with cell 102a. For simplicity, other cells are not shown. Cell 102a has a rectangular shape with edges in both the X direction and the Y direction. Both the X direction and the Y direction are located in the horizontal plane XY. In some embodiments, the X direction is perpendicular to the Y direction. In other embodiments, the X direction is substantially perpendicular to the Y direction. It should be noted that the unit 102a may have a Figure 1A It should be noted that cell 102a may have different dimensions than cell 102b and cell 102c.

[0028] The cell 102a may include at least a plurality of fin structures 106a and fin structures 106b arranged in the X direction, a plurality of polycrystalline silicon ("poly") lines 108a, polysilicon lines 108b, polysilicon lines 108c, and polysilicon lines 108d arranged in the Y direction, and a plurality of metal lines 110a, metal lines 110b, metal lines 110c, metal lines 110d, metal lines 110e, and metal lines 110f arranged in the Y direction. The fin structures 106a and fin structures 106b are arranged on a substrate (not shown) and serve as active regions of field effect transistors (FETs) in the cell 102a. Specifically, the fin structures 106a and fin structures 106b may serve as channel regions of FETs when located below any one of the polysilicon lines 108a, polysilicon lines 108b, polysilicon lines 108c, and polysilicon lines 108d. When located under any of metal line 110 a , metal line 110 b , metal line 110 c , metal line 110 d , metal line 110 e , and metal line 110 f , fin structure 106 a and fin structure 106 b may function as a source region or a drain region.

[0029] In the illustrated embodiment, polysilicon lines 108a, 108b, 108c, and 108d are disposed over the fin structures 106a and 106b and are adjacent to multiple (e.g., three or four) side surfaces of the fin structures 106a and 106b, respectively. The polysilicon lines 108a, 108b, 108c, and 108d may be used as gate regions of FETs that turn the FETs on or off. Metal lines 110a, 110b, 110c, 110d, 110e, and 110f are disposed over the fin structures 106a and 106b. The metal lines 110a, 110b, 110c, 110d, 110e, and 110f are disposed in the MD layer. In this embodiment, the metal lines 110a, 110c, and 110d are connected to the sources of the FETs (i.e., the “source side”), while the metal lines 110b, 110e, and 110f are connected to the drains of the FETs (i.e., the “drain side”). In this embodiment, the metal lines 110a, 110b, 110c, 110d, 110e, and 110f are inserted between two of the polysilicon lines 108a, 108b, 108c, and 108d.

[0030] Cell 102a and cell 102b share a buried power rail 104a extending in the X direction. Cell 102a and cell 102c share a buried power rail 104b extending in the X direction. The buried power rail 104a and the buried power rail 104b are arranged in a layer below the MD layer. In this embodiment, the buried power rail 104a is inserted between the fin structure 106a in cell 102a and the fin structure 106c in cell 102b. The buried power rail 104a can provide a first voltage to the cell 102a and the cell 102b. In one embodiment, the first voltage is VDD. In this embodiment, the buried rail 104b is inserted between the fin structure 106b and the fin structure (not shown for simplicity) in the cell 102c. The buried power rail 104b can provide a second voltage to the cell 102a and the cell 102c. In one embodiment, the second voltage is VSS. In another embodiment, the second voltage is grounded.

[0031] The buried power rail 104a is connected to the metal line 110a, the metal line 110c, and the metal line 110g through a conductive via to a buried power supply (i.e., "VB") not shown. In other words, the buried power rail 104a can provide VDD to the source side of the FETs in both the cell 102a and the cell 102b. For example, the buried power rail 104a can provide VDD to the metal line 110a and the metal line 110g through two VBs not shown. For example, the buried power rail 104a can provide VDD to the metal line 110c through the VB not shown. The buried power rail 104a is separated from the metal line 110b, the metal line 110h, and the metal line 110i. In other words, the buried power rail 104a can be used to provide VDD to the source side of the FETs in the cell 102a and the cell 102b, while the buried power rail 104a is separated from the drain side of the FETs in the cell 102a and the cell 102b. Since the drain side of the FETs is usually connected to the M0 signal rail, the separation of the buried power rail 104a and the drain side of the FETs can prevent short circuits between the M0 signal rail and the M1 metal rail. More details of VB will be discussed below.

[0032] Likewise, buried power rail 104b may be connected to metal line 110d via VB, not shown. In other words, buried power rail 104b may provide VSS to the source side of the FETs in both cell 102a and cell 102c. For example, buried power rail 104b may provide VSS to metal line 110d. For example, buried power rail 104b is separated from metal line 110e and metal line 110f. In other words, buried power rail 104b may be used to provide VSS to the source side of the FETs in cell 102a and cell 102b, while buried power rail 104a is separated from the drain side of the FETs in cell 102a and cell 102b. Likewise, since the drain side of the FETs is typically connected to the M0 signal rail, the separation of buried power rail 104b and the drain side of the FETs may prevent a short circuit between the M0 signal rail and the M1 metal rail. More details of VB will be discussed below.

[0033] A plurality of M0 metal tracks 112 are arranged in the M0 layer in the X direction above metal lines 110a, 110b, 110c, 110d, 110e, and 110f in the MD layer. From the perspective of cell 102a, M0 metal tracks 112b, 112c, 112d, and 112e can be used for signals. M0 metal track 112a is shared by cell 102a and cell 102b. Specifically, M0 metal track 112a is above buried power rail 104a. In one embodiment, M0 metal track 112a is above the boundary line 101a shown. The buried power rail 104a can be connected to M0 metal track 112a, passing through the MD layer. Specifically, buried power rail 104a can be connected to M0 track 112a through one or two VBs and conductive via diffusion (i.e., "VD") not shown. As described above, buried power rail 104a can be used to provide VDD to the source side of FETs in cells 102a and 102b while being separated from the drain side of FETs in cells 102a and 102b. Thus, buried power rail 104a can be used to provide VDD to the source side of FETs in cells 102a and 102b, and simultaneously raise VDD to the M0 layer (and further to the M1 layer for power tap purposes). In this way, those otherwise prohibited areas below the power tap can be used to place ordinary cells with FETs, thereby reducing the area impact of the IC chip. Similarly, M0 metal track 112f is shared by cells 102a and 102c. Specifically, M0 metal track 112f is above buried power rail 104b. In one embodiment, M0 metal track 112f is above boundary line 101b as shown. Buried power rail 104a can be connected to M0 metal track 112f, passing through the MD layer. Specifically, the buried power rail 104b can be connected to the M0 rail 112f through one or two VBs and a not shown VD. As described above, the buried power rail 104b can be used to provide VSS to the source side of the FETs in the cells 102a and 102c while being separated from the drain side of the FETs in the cells 102a and 102c. Therefore, the buried power rail 104b can be used to provide VSS to the source side of the FETs in the cells 102a and 102c, and at the same time raise VSS to the M0 layer (and further to the M1 layer for power tap purposes). In this way, those otherwise prohibited areas below the power tap can be used to place ordinary cells with FETs, thereby reducing the area impact of the IC chip.

[0034] Back to the perspective of cell 102a, M0 metal tracks 112b, M0 metal tracks 112c, M0 metal tracks 112d and M0 metal tracks 112e can be used for signals, while M0 metal tracks 112a and M0 metal tracks 112f can be used to raise VDD and VSS from buried power layers 104a and 104b to the M1 layer for power tap purposes. Typically, each cell corresponds to an average of five M0 metal tracks 112. Four of the five M0 metal tracks 112 (e.g., M0 metal track 112b, M0 metal track 112c, M0 metal track 112d, and M0 metal track 112e) are within the cell (e.g., 102a) and can be used for signals, while the remaining one (e.g., half of 112a plus half of 112f, thus an average of one) is shared between the cell (e.g., 102a) and the adjacent cell (e.g., 102b) and can be used for power tap purposes while being able to provide voltage to the source side of the FETs. It should be noted that for simplicity, in Figure 1A Some structures such as VBs, VDs and M1 metal tracks are not shown and will be referred to in Figure 1B Discuss it.

[0035] Figure 1B is with Figure 1A 1-1 . As shown in the example cross-sectional view, the unit 102a and the unit 102b are adjacent units in the Y direction and are separated by the boundary line 101a extending in the Z direction. In one embodiment, the Z direction is a vertical direction. In one embodiment, the Z direction is perpendicular to the Y direction. In one embodiment, the Z direction is substantially perpendicular to the Y direction. It should be noted that for the sake of simplicity, only a portion of the unit 102a and a portion of the unit 102b are shown.

[0036] In this example cross-sectional view, two fin structures 106a and fin structure 106c are arranged in the X direction perpendicular to the YZ plane. Fin structure 106a and fin structure 106c are arranged on substrate 190. Fin structure 106a is within cell 102a, and fin structure 106c is within cell 102b. Fin structure 106a and fin structure 106c are separated laterally by isolation structure 105a (e.g., shallow trench isolation (STI) region). In the middle of isolation structure 105a in the Y direction, buried power rail 104a is located on substrate 190. In one embodiment, boundary line 101a between cell 102a and cell 102b crosses buried power rail 104a in the Y direction. Buried power rail 104a extends in the X direction and is shared by cell 102a and cell 102b. Buried power rail 104a is arranged below MD layer 110. The buried power rail 104a may provide a first voltage to the cells 102a and 102b. In one embodiment, the first voltage is VDD.

[0037] Two VBs 107a and 107b are disposed above the buried power rail 104a. The two VBs 107a and 107b extend vertically in the Z direction and electrically connect the buried power rail 104a and the MD layer 110. In some embodiments, a high-k dielectric layer 192 and another high-k dielectric layer 194 are located between the VBs 107a and 107b, forming a double-layered mixed high-k dielectric layer. In some embodiments, the high-k dielectric layer 194 is removed during the etching process and filled with the same material as the VBs 107a and 107b. On the other hand, the metal lines 110a and 110g in the MD layer 110 are disposed above the fin structure 106a and the fin structure 106c, respectively. When below the metal lines 110a and 110g, the fin structure 106a and the fin structure 106c can be used as a source region. In some embodiments, metal lines 110a and 110g may be formed using one or more epitaxial (i.e., "epi") processes, and the source regions below metal lines 110a and 110g may be doped with n-type impurities in situ or with p-type impurities during the epitaxial process. In some embodiments, the source regions below metal lines 110a and 110g may be formed using one or more implantation processes to dope n-type impurities or p-type impurities into the source regions.

[0038] As described above, the buried power rail 104a can be used to provide a first voltage (e.g., VDD) to the source side of the FETs in the cell 102a and the cell 102b and simultaneously raise the first voltage (e.g., VDD) to the M0 layer 112 (and further to the M1 layer 114 for power tap purposes). Specifically, the two VBs 107a and 107b extend laterally along the Y direction at the top to form VBs 107c and VBs 107d. In other words, the two VBs 107a and 107b extend in a bidirectional manner in the Y direction. In the example cross-sectional view, the VBs 107c and 107d are disposed above and short-circuited with the metal lines 110a and 110g. In this way, the buried power rail 104a can provide a first voltage to the source side of the FETs in the cell 102a (e.g., metal line 110a) and the source side of the FETs in the cell 102b (e.g., metal line 110g). At the same time, VD 111 is disposed above VB 107c and VB 107d. VD 111 extends vertically in the Z direction and electrically connects VB 107c and VB 107d and M0 metal track 112a. In other words, buried power rail 104a can be used to boost a first voltage to M0 layer 112 (and further to M1 layer 114 for power tap purposes). In this example cross-sectional view, M0 metal track 112a is above buried power rail 104a and VD 111. Other M0 metal tracks 112b, M0 metal track 112c, M0 metal track 112d, M0 metal track 112g, M0 metal track 112h, and M0 metal track 112j can be used for signals. The M0 metal track 112a, M0 metal track 112b, M0 metal track 112c, M0 metal track 112d, M0 metal track 112g, M0 metal track 112h, and M0 metal track 112j extend in the X direction.

[0039] A conductive via (i.e., "VIA1") is disposed above the M0 metal track 112a. VIA1 113 extends vertically in the Z direction and electrically connects the M0 metal track 112a and the M1 metal track 114. The M1 metal track 114 extends in the Y direction. As described above, the buried power rail 104a can be used to boost the first voltage to the M0 layer 112. Therefore, the buried power rail 104a can be used to further boost the first voltage to the M1 layer 114 through VIA1 113. In other words, the buried power rail 104a can be used to provide the first voltage to the source side of the FETs in the cells 102a and 102b, and at the same time boost the first voltage to the M1 layer 114 for power tap purposes. A conductive path is formed to provide the first voltage to the M1 layer 114. The conductive path includes VB 107a, VB 107b, VD 111, the M0 metal track 112a, and VIA1 113. In this way, those otherwise prohibited areas under the power taps can be used to place conventional cells with FETs, thereby reducing the area impact of the IC chip.

[0040] Figure 2A is a perspective view of a first embodiment and a second embodiment of a power tap structure according to some embodiments. Figure 2B yes Figure 2A The layout diagrams of the first and second embodiments of the power tap structure are shown. The first embodiment of the power tap structure corresponds to the two source sides of the FETs in the adjacent cells. The second embodiment of the power tap structure corresponds to the two drain sides of the FETs in the adjacent cells.

[0041] like Figure 2A and Figure 2B As shown, the power tap structure 201a according to the first embodiment and the power tap structure 201b according to the second embodiment are positioned laterally in the X direction. In the Y direction, each of the power tap structure 201a and the power tap structure 201b is located in two adjacent cells 202a and 202b. The adjacent cells 202a and 202b are separated by a boundary line 202x extending in the X direction. In some embodiments, the Y direction is perpendicular to the X direction. In some embodiments, the Y direction is substantially perpendicular to the X direction. It should be noted that for the sake of simplicity, only a portion of the cell 202a and a portion of the cell 202b are shown.

[0042] The power tap structure 201a corresponds to two source sides of the FETs in the cell 202a and the cell 202b, each of which has one source side. Two fin structures 206a and 206b are arranged in the X direction. The fin structure 206a and the fin structure 206b are arranged on a substrate not shown for simplicity. The fin structure 206a and the fin structure 206b are respectively in the cell 202a and the cell 202b. The fin structure 206a and the fin structure 206b are separated laterally by an isolation structure (e.g., STI region) not shown for simplicity. In the middle of the isolation structure in the Y direction, the buried power rail 204a is located on the substrate. In one embodiment, the boundary line between the cell 202a and the cell 202b crosses the buried power rail 204a in the Y direction. The buried power rail 204a extends in the X direction and is shared by the cell 202a and the cell 202b. The buried power rail 204a is arranged below the MD layer 210. The buried power rail 204a may provide a first voltage to the cells 202a and 202b. In one embodiment, the first voltage is VDD.

[0043] Two VBs 207a and VB 207b are disposed above the buried power rail 204a. The two VBs 207a and VB 207b extend vertically in the Z direction and electrically connect the buried power rail 204a and the MD layer 210. In some embodiments, the Z direction is a direction perpendicular to the XY plane. The fin structure 206a and the fin structure 206b can be used as a source region or a drain region when they are below the MD layer 210.

[0044] Likewise, the buried power rail 204a can be used to provide a first voltage (e.g., VDD) to the source side of the FETs in the cells 202a and 102b and simultaneously raise the first voltage (e.g., VDD) to the M0 layer 212 (and further to the M1 layer 214 for power tap purposes). Specifically, the two VBs 207a and 207b extend laterally along the Y direction at the top to form VB 207c and VB 207d. In other words, the two VBs 207a and 207b extend in the Y direction in a bidirectional manner. VB 207c and VB 207d are disposed above the MD layer 210 and short-circuited with them. In this way, the buried power rail 204a can provide the first voltage to the source side of the FETs in the cells 202a and 202b. At the same time, VD 211a is disposed above VB 207c and VB 207d. VD 211a extends vertically in the Z direction and electrically connects VB 207c, VB 207d and M0 metal track 212b. In other words, buried power rail 204a can be used to raise the first voltage to M0 layer 212 (and further to M1 layer 214 for power tap purposes). In this first embodiment, M0 metal track 212b is above buried power rail 204a and VD 211a. Other M0 metal tracks 212a and M0 metal tracks 212c can be used for signals. M0 metal tracks 212a, M0 metal tracks 212b and M0 metal tracks 212c extend in the X direction.

[0045] VIA1 213a is disposed above M0 metal track 212b. VIA1 213a extends vertically in the Z direction and electrically connects M0 metal track 212b and M1 metal track 214a. M1 metal track 214a extends in the Y direction. As described above, buried power rail 204a can be used to boost the first voltage to M0 layer 212. Therefore, buried power rail 204a can be used to further boost the first voltage to M1 layer 214 through VIA1 213a. In other words, buried power rail 204a can be used to provide the first voltage to the source side of FETs in cell 202a and cell 202b, and simultaneously boost the first voltage to M1 layer 214 for power tap purposes. In this way, those otherwise prohibited areas under the power tap can be used to place ordinary cells with FETs, thereby reducing the area impact of the IC chip.

[0046] On the other hand, the power tap structure 201b corresponds to the two drain sides of the FETs in the cell 202a and the cell 202b, each of which has one drain side. Two fin structures 206a and fin structure 206b are arranged in the X direction. The fin structure 206a and the fin structure 206b are arranged on a substrate not shown for simplicity. The fin structure 206a and the fin structure 206b are respectively in the cell 202a and the cell 202b. The fin structure 206a and the fin structure 206b are laterally separated by an isolation structure (e.g., STI region) not shown for simplicity. In the middle of the isolation structure in the Y direction, the buried power rail 204a is located on the substrate. In one embodiment, the boundary line between the cell 202a and the cell 202b crosses the buried power rail 204a in the Y direction. The buried power rail 204a extends in the X direction and is shared by the cell 202a and the cell 202b. The buried power rail 204a is disposed below the MD layer 210. The buried power rail 204a can provide a first voltage to the cells 202a and 202b. In one embodiment, the first voltage is VDD.

[0047] VB 207e is disposed above buried power rail 204a. VB 207e extends vertically in the Z direction and can electrically connect buried power rail 204a and MD layer 210. Fin structure 206a and fin structure 206b can be used as a source region or a drain region when under MD layer 210. For example, in the second embodiment, fin structure 206a and fin structure 206b can be used as a drain region when under MD metal line 210a and MD metal line 210b. MD line 210a is located in cell 202a and MD metal line 210b is located in cell 202b.

[0048] Unlike VB 207a and VB 207b in the first embodiment, VB 207e does not extend laterally in the Y direction at the top to short with MD metal lines 210a and 210b. In other words, VB 207e is separated from MD metal lines 210a and 210b in the Y direction. Since buried power rail 204a can be used to boost the first voltage (e.g., VDD) to M0 layer 212 (and further to M1 layer 214 for power tapping purposes), and MD metal lines 210a and 210b can be electrically connected to M0 signal rails 212a and 212c through VD (e.g., VD 211c), the separation of VB 207e from MD metal lines 210a and 210b can prevent shorts between M0 signal rails (e.g., M0 signal rails 212c) and M1 metal rails 214. At the same time, VD 211b is arranged above VB 207e. VD 211b extends vertically in the Z direction and electrically connects VB 207e and M0 metal track 212b. In other words, buried power rail 204a can be used to boost the first voltage to M0 layer 212 (and further boost to M1 layer 214 for power tap purposes). In this second embodiment, M0 metal track 212b is above buried power rail 204a and VD 211a. Other M0 metal tracks 212a and M0 metal tracks 212c can be used for signals.

[0049] VIA1 213b is disposed above M0 metal track 212b. VIA1 213b extends vertically in the Z direction and electrically connects M0 metal track 212b and M1 metal track 214b. M1 metal track 214b extends in the Y direction. As described above, buried power rail 204a can be used to boost the first voltage to M0 layer 212. Therefore, buried power rail 204a can be used to further boost the first voltage to M1 layer 214 through VIA1 213b. In other words, buried power rail 204a can be used to boost the first voltage to M1 layer 214 for power tap purposes while preventing short circuits between M0 signal tracks (e.g., M0 signal tracks 212c) and M1 metal tracks 214b. In this way, those otherwise prohibited areas under the power tap can be used to place ordinary cells with FETs, thereby reducing the area impact of the IC chip.

[0050] Figure 3A is a perspective view of a third embodiment of a power tap structure according to some embodiments. Figure 3B yes Figure 3A The layout diagram of the third embodiment of the power tap structure is shown in FIG. The third embodiment of the power tap structure corresponds to the source side of the FETs in one cell and the drain side of the FETs in another cell.

[0051] like Figure 3A and Figure 3B As shown, the power tap structure 301a according to the third embodiment is located in two adjacent cells 302a and 302b in the Y direction. The adjacent cells 302a and 302b are separated by a boundary line 302x extending in the X direction. In some embodiments, the Y direction is perpendicular to the X direction. In some embodiments, the Y direction is substantially perpendicular to the X direction. It should be noted that for the sake of simplicity, only a portion of the cell 302a and a portion of the cell 302b are shown.

[0052] The power tap structure 301a corresponds to the source side of the FETs in the cell 302b and the drain side of the FETs in the cell 302a. Two fin structures 306a and fin structure 306b are arranged in the X direction. The fin structure 306a and the fin structure 306b are arranged on a substrate not shown for simplicity. The fin structure 306a and the fin structure 306b are respectively in the cell 302a and the cell 302b. The fin structure 306a and the fin structure 306b are separated laterally by an isolation structure (e.g., STI region) not shown for simplicity. In the middle of the isolation structure in the Y direction, the buried power rail 304a is located on the substrate. In one embodiment, the boundary line between the cell 302a and the cell 302b crosses the buried power rail 304a in the Y direction. The buried power rail 304a extends in the X direction and is shared by the cell 302a and the cell 302b. The buried power rail 304a is arranged below the MD layer 310. The buried power rail 304a may provide a first voltage to the cell 302a and / or the cell 302b. In the example shown, the buried power rail 304a may provide a first voltage to the cell 302b. In one embodiment, the first voltage is VDD.

[0053] VB 307a is disposed above buried power rail 304a. VB 307a extends vertically in the Z direction and can electrically connect buried power rail 304a and MD layer 310. In some embodiments, the Z direction is a direction perpendicular to the XY plane. Fin structure 306a and fin structure 306b can be used as a source region or a drain region when under MD layer 310.

[0054] Likewise, buried power rail 304a can be used to provide a first voltage (e.g., VDD) to the source side of the FETs in cell 302b and simultaneously boost the first voltage (e.g., VDD) to M0 layer 312 (and further to M1 layer 314 for power tap purposes). Specifically, VB 307a extends laterally along the Y direction at the top to form VB 307b. VB 307b is disposed above MD layer 310 and short-circuited with MD metal line (s). In this way, buried power rail 304a can provide a first voltage to the source side of the FETs in cell 302b. On the other hand, VB 307a does not extend laterally along the Y direction at the top to short-circuit with MD metal line 310a. In other words, VB 307a is separated from MD metal line 310a in the Y direction. In other words, VB 307a extends in a unidirectional manner along the Y direction. Since the buried power rail 304a can be used to raise the first voltage (e.g., VDD) to the M0 layer 312 (and further to the M1 layer 314 for power tap purposes), and the MD metal line 310a can be electrically connected to the M0 signal track 312c through the VD 311b, the separation of the VB 307a from the MD metal line 310a can prevent a short circuit between the M0 signal track (e.g., the M0 signal track 312c) and the M1 metal track 314a. At the same time, the VD 311a is disposed above the VB 307b. The VD 311a extends vertically in the Z direction and electrically connects the VB 307b and the M0 metal track 312b. In other words, the buried power rail 304a can be used to raise the first voltage to the M0 layer 312 (and further to the M1 layer 314 for power tap purposes). In this third embodiment, the M0 metal track 312b is above the buried power rail 304a and the VD 311a. The other M0 metal tracks 312a and 312c may be used for signals.

[0055] VIA1 313a is disposed above M0 metal track 312b. VIA1 313a extends vertically in the Z direction and electrically connects M0 metal track 312b and M1 metal track 314a. M1 metal track 314a extends in the Y direction. As described above, buried power rail 304a can be used to boost the first voltage to M0 layer 312. Therefore, buried power rail 304a can be used to further boost the first voltage to M1 layer 314 through VIA1 313a. In other words, buried power rail 304a can be used to provide the first voltage to the source side of the FETs in cell 302b, and simultaneously boost the first voltage to M1 layer 314 for power tap purposes, while preventing short circuits between M0 signal tracks (e.g., M0 signal tracks 312c) and M1 metal tracks 314a. In this way, those otherwise prohibited areas under the power tap can be used to place ordinary cells with FETs, thereby reducing the area impact of the IC chip.

[0056] Figure 4 is a layout diagram of another embodiment of a power tap structure according to some embodiments. In this embodiment, the M0 metal track above the buried power rail is extended to connect to another adjacent M0 metal track above the buried power rail that is not located below the M1 metal track to reduce IR drop. Specifically, the power tap structure 401a and the conventional structure 401b according to the first embodiment of the present disclosure described above are located on a substrate not shown. The power tap structure 401a and the conventional structure 401b are both located in two adjacent cells 402a and cell 402b. The adjacent cells 402a and cell 302b are separated by a boundary line 402x extending in the X direction. In some embodiments, the Y direction is perpendicular to the X direction. In some embodiments, the Y direction is substantially perpendicular to the X direction. Structurally, the power tap structure 401a is similar to Figure 2B 2. The power tap structure 201a of FIG. 2 is shown. One difference is that, for simplicity, only one M0 metal track 412a is shown, while the other M0 metal tracks are not shown. The relevant elements of the power tap structure 401a include, among others, a buried power rail 404a, two fin structures 406a and 406b, two VBs 407a and 407b, two laterally extending VBs 407c and 407d, VD 411a, M0 metal track 412a, VIA1 and M1 metal track 414a not shown. For simplicity, the connections, composition and functions of the relevant elements of the power tap structure 401a are not repeated.

[0057] On the other hand, conventional structure 401b is laterally adjacent to power tap structure 401a in the X direction. Conventional structure 401b is structurally similar to power tap structure 401a. However, unlike power tap structure 401a, conventional structure 401b is not located under the M1 metal track. Specifically, the relevant elements of conventional structure 401b include, among others, buried power rail 404a, fin structure 406a and fin structure 406b, two VB 407e and VB 407f, two laterally extending VB 407g and VB407h, VD 411b, and M0 metal track 412a. Conventional structure 401b does not include VIA1 or M1 metal tracks. For simplicity, the connections, composition, and functions of the relevant elements of power tap structure 401a are not repeated.

[0058] As described above, the M0 metal track 412a on the power tap structure 401a is extended to connect with another adjacent M0 metal track on the conventional structure 401b. In other words, the power tap structure 401a and the conventional structure 401b share the same M0 metal track 412a. The extended M0 metal track 412a increases the connection path to the M1 metal track 414a, so that the current can have more paths to flow, thereby reducing the resistance and IR drop of the power tap structure 401a.

[0059] Figure 5 is a diagram showing an example of a power tap structure on an IC chip according to some embodiments. Figure 5 The top portion of FIG. 5 shows an IC chip 500 having, among other things, three power tap structures 501a , 501b , and 501c . Figure 5 The bottom of the diagram shows a cross section 501ax of the power tap structure 501a in the X direction and a cross section 501ay of the power tap structure 501a in the Y direction. The IC chip 500 is located in the XY plane. In some embodiments, the X direction is perpendicular to the Y direction. In some embodiments, the X direction is substantially perpendicular to the Y direction. The Z direction is perpendicular to the XY plane.

[0060] Figure 55. A portion of an IC chip 500 is shown in FIG. The IC chip 500 is divided into a plurality of units. A plurality of M0 metal tracks 512a, M0 metal tracks 512b, and M0 metal tracks 512c extend in the X direction. It should be noted that, for the sake of simplicity, not all of the M0 metal tracks are shown. In the example shown, the M0 metal track 512a may provide a first voltage VDD; the M0 metal track 512b may provide a second voltage VSS; and the M0 metal track 512c may provide a second voltage VSS. The M0 metal tracks 512a, M0 metal tracks 512b, and M0 metal tracks 512c are above a buried power rail that is not shown for the sake of simplicity. On the other hand, a plurality of M1 metal tracks 514a and M1 metal tracks 514b extend in the Y direction. It should be noted that the IC chip 500 may have other M1 metal tracks. In the example shown, the M1 metal track 514a may provide a first voltage VDD; and the M1 metal track 514b may provide a second voltage VSS. The power tap structure may be placed at the intersection of the M0 metal track 512a, the M0 metal track 512b, and the M0 metal track 512c with the M1 metal track 514a and the M1 metal track 514b. For example, the power tap structure 501a is placed at the intersection of the M0 metal track 512a and the M1 metal track 514a; the power tap structure 501b is placed at the intersection of the M0 metal track 512c and the M1 metal track 514b; and the power tap structure 501c is placed at the intersection of the M0 metal track 512b and the M1 metal track 514b.

[0061] As shown in cross section 501ay, the power tap structure 501a is similar in structure to Figure 2B 2. The power tap structure 201a of the exemplary power tap structure 501a is shown. The illustrated elements of the exemplary power tap structure 501a include, among others, a buried power rail 504a, two fin structures 506a and 506b, a VB 507a, two laterally extending VBs 507c and 507d, a VD 511a, an M0 metal track 512a, a VIA1 513a, and an M1 metal track 514a. For simplicity, the connections, composition, and functions of the relevant elements of the power tap structure 501a are not repeated.

[0062] As shown in cross section 501ax, another power tap structure 501g can be placed next to power tap structure 501a in the X direction. Similarly, power tap structure 501g is similar to power tap structure 501a in structure. The illustrated elements of exemplary power tap structure 501g include, among others, buried power rail 504a, two fin structures 506a and fin structure 5506b, VB 507g, two laterally extending VBs not shown, VD 511g, M0 metal track 512a, VIA1 513g, and M1 metal track 514g. For simplicity, the connections, composition, and functions of the relevant elements of power tap structure 501a are not repeated. A plurality of VBs (e.g., 507d, 507e, and 507f) are placed between the power tap structure 501a and the power tap structure 501g in the X direction, and these VBs are not used to boost the first voltage VDD to the M1 metal rails (e.g., 514a and 514g). However, the plurality of VBs (e.g., 507d, 507e, and 507f) can be used to provide the first voltage VDD to the source side of the FETs in the adjacent cells.

[0063] Figure 6 is a diagram showing another example of a power tap structure on an IC chip according to some embodiments. Figure 6 The top portion of FIG. 6 shows an IC chip 600 having, among other things, a power tap structure 601 a . Figure 6 The bottom of the diagram shows a cross section 601ax of the power tap structure 601a in the X direction, a cross section 601ay1 of the power tap structure 601a in the Y direction at Y1, and a cross section 601ay2 of the power tap structure 601a in the Y direction at Y2. The IC chip 600 is located in the XY plane. In some embodiments, the X direction is perpendicular to the Y direction. In some embodiments, the X direction is substantially perpendicular to the Y direction. The Z direction is perpendicular to the XY plane. Unlike the power tap structure 501a, the power tap structure 601a is unconventional in the X direction in terms of layout.

[0064] Figure 66 shows a portion of an IC chip 600. The IC chip 600 is divided into a plurality of units. A plurality of M0 metal tracks 612a, M0 metal tracks 612b, and M0 metal tracks 612c extend in the X direction. It should be noted that, for simplicity, not all of the M0 metal tracks are shown. In the example shown, the M0 metal track 612a can provide a first voltage VDD; the M0 metal track 612b can provide a second voltage VSS; and the M0 metal track 612c can provide a second voltage VSS. The M0 metal tracks 612a, M0 metal tracks 612b, and M0 metal tracks 612c are above a buried power rail that is not shown for simplicity. On the other hand, a plurality of M1 metal tracks 614a and M1 metal tracks 614b extend in the Y direction. It should be noted that the IC chip 600 may have other M1 metal tracks. In the example shown, the M1 metal track 614a can provide a first voltage VDD; and the M1 metal track 614b can provide a second voltage VSS. The power tap structure may be placed at the intersection of M0 metal tracks 612a, 612b, and 612c with M1 metal tracks 614a and 614b. For example, a portion of the power tap structure 601a is placed at the intersection of M0 metal tracks 612a and M1 metal tracks 614a.

[0065] As shown in cross-section 601ay1 and cross-section 601ay2, in structure, the power tap structure 601a is similar to Figure 5 The power tap structure 501a is different in that the power tap structure 601a is separated and located at different positions in the X direction. Figure 5 The power tap structure 601a is referred to as "unconventional" compared to the power tap structure 501a, which is considered "conventional". The illustrated elements of the exemplary power tap structure 501a include, among others, a buried power rail 604a, two fin structures 606a and fin structure 606b, VB 607a, two laterally extending VBs 607c and VB 607d, VD 611a, M0 metal track 612a, VIA1 613a, and M1 metal track 614a. Specifically, VIA1 613a and M1 metal track 614a (collectively referred to as the "first set of elements") are located at the intersection of M0 metal track 612a and Y1, while VB 607a, laterally extending VBs 607c and VB 607d, and VD 611a (collectively referred to as the "second set of elements") are located at the intersection of M0 metal track 612a and Y2. The first component set and the second component set are separated in the X direction and are electrically connected via the M0 metal track 612a extending in the X direction. For simplicity, other connections, components and functions of related components of the power tap structure 601a that are not specifically mentioned are not repeated here.

[0066] As shown in the cross section 601ax, the first component set and the second component set are separated in the X direction and are electrically connected by the M0 metal track 612a extending in the X direction. Since the second component set is not placed under the M1 metal track 614a, the placement and routing constraints are reduced. In this way, the unconventional power tap structure 601a can reduce the area impact.

[0067] Fig. 7A is a layout diagram illustrating an example method of applying placement constraints according to some embodiments. Figure 7B is corresponding to Fig. 7A A flowchart of an example method of applying placement constraints is shown according to some embodiments. The method of applying placement constraints corresponds to Figure 2A and Figure 2B The power tap structure 201a of the first embodiment of the present disclosure is shown in FIG. As described above, the power tap structure 201a cannot be placed on the drain side of the FETs.

[0068] like Fig. 7A As shown, the power tap structure is placed at the intersection 716a of the buried power rail 704a and the M1 metal track 714a. Multiple drain sides of FETs (e.g., drain side 710a and drain side 710b) are placed in adjacent cells of the buried power rail 704a. As described above, the intersection 716a cannot overlap with the drain sides of FET 710a and FET 710b.

[0069] like Figure 7B As shown, the method 700 of applying placement constraints includes, among other things, three steps 772, step 774, and step 776. In step 772, a first attribute name is set for the drain side 710a and the drain side 710b of the FETs. In one example, the first attribute name is G2. In step 774, a second attribute name is set for the intersection 716a of the buried power rail 704a and the M1 metal rail 714a. In one example, the first attribute name is G1. In some embodiments, a second attribute name can be set for VIA1, which is not shown. In step 774, when placing and routing, the general rule is applied that the first attribute name (e.g., G2) and the second attribute name (e.g., G1) cannot overlap.

[0070] Fig. 8A is a layout diagram illustrating another example method of applying placement constraints according to some embodiments. Figure 8B is corresponding to Fig. 8A A flowchart of an example method of applying placement constraints according to some embodiments. The method of applying placement constraints corresponds to Figure 2A and Figure 2BThe power tap structure 201a of the first embodiment of the present disclosure is shown in FIG. As described above, the power tap structure 201a cannot be placed on the drain side of the FETs.

[0071] like Fig. 8A As shown, the power tap structure is placed at the intersection 816a of the buried power rail 804a and the M1 metal track 814a. The drain sides of the FETs are located in the space (e.g., space 820a) in the adjacent cell of the buried power rail 804a. As described above, the intersection 816a cannot overlap with the drain sides of the FETs.

[0072] like Figure 8B As shown, the method 800 of applying placement constraints includes, among other things, three steps 872, step 874, and step 876. In step 872, a first set of marking layers (e.g., marking layer 818a, marking layer 818b, marking layer 818c, marking layer 818d, and marking layer 818e) are placed on the drain side of the FETs. In step 874, a second marking layer 820a is placed, covering the intersection 816a of the buried power rail 804a and the M1 metal track 814a. In some embodiments, the second marking layer 820a can be placed, covering VIA1, which is not shown. In step 876, a rule that the first set of marking layers (e.g., marking layer 818a, marking layer 818b, marking layer 818c, marking layer 818d, and marking layer 818e) and the second marking layer 820a cannot be shorted when placing and routing is performed is applied.

[0073] Fig. 9 is an illustrative high-level schematic block diagram of a system for implementing a layout according to some embodiments. In the example shown, the system may include one or more computing systems 900, such as general-purpose computers for implementing one or more special purposes.

[0074] In some embodiments, one or more computing systems 900 may call upon various system resources, such as one (or more) processors or one (or more) processor cores, memory, disk, etc. The one or more computing systems 900 may also start or interact with other computing systems through a computer bus architecture (e.g., a system bus, a control bus, a data bus, or any combination thereof) to access various resources 928, which may include a floorplanner, a global routing engine, and / or a detailed routing engine 964, a layout editor 966, a design routine checker 968, a verification engine 970, etc. The one or more computing systems 900 may further write to or read from a local or remote non-transitory computer-accessible memory 962 storing thereon data or information, such as, but not limited to, one or more databases (974), such as one (or more) schematic design databases or one (or more) physical design databases, one (or more) electronic circuit design specification databases, various statistics, various data, one (or more) rule sets, various design rules, constraints, etc. (972), or other information or data (976), which may be used to facilitate the performance of various functions to achieve the intended purpose.

[0075] In some embodiments, one or more computing systems 900 may include or directly or indirectly through various resources 928, call a mechanism set 952, which includes hardware mechanisms and software modules or a combination of one or more hardware mechanisms and one or more software modules, which may include one or more track pattern processing modules 902 to insert, remove, modify, improve, optimize, or otherwise operate on tracks in a track pattern or routing tracks. The mechanism set 952 may further include a track pattern enumeration mechanism 904 to enumerate, determine, or update a legal one (or more) track pattern database to generate feasible implementation options for tracks associated with various widths.

[0076] The set of mechanisms 952 may also optionally include one or more implementation option processing mechanisms 906 to identify, determine, modify, or rank feasible implementation options based on one or more criteria. Additionally or alternatively, the set of mechanisms 952 may further include a track pattern generation mechanism 908 to generate, update, modify, or otherwise perform various operations on a track pattern and / or predict forward tracks for subsequent addition to the track pattern. In some embodiments, the set of mechanisms 952 may further include a track pattern evaluation mechanism 910 to evaluate track patterns against various design conventions, performance goals, manufacturing requirements, and / or other constraints.

[0077] The mechanism set 952 may further include a lateral filling mechanism 912 to implement a lateral filling structure or shape in the electronic design while satisfying the control design rules and constraints. Additionally or alternatively, the mechanism set 952 may include a post-layout operation mechanism 914 to perform one or more post-layout operations, including, for example, post-layout analysis, simulation, design rule checking, tape-out, verification, etc.

[0078] In some embodiments, the computing system 900 may include various resources 928 such that these various resources may be called from within the computing system via a computer bus 980 (e.g., a data bus interfacing with a microprocessor 992 and a non-transitory computer-accessible memory 998 or a system bus 990 between the microprocessor 992 and one or more engines of the various resources 928). In some other embodiments, some or all of these various resources may be located remotely from the computing system 900 such that the computing system may access some or all of these resources via the computer bus 980 and one or more network elements.

[0079] The computing system may also include one or more mechanisms in the mechanism set 952. In some embodiments, one or more mechanisms in the mechanism set 952 may include or at least be connected in series with the microprocessor 952 via a computer bus 994. In these embodiments, even in the case where the computing system 900 includes only one microprocessor 992, the microprocessor 992 may be included in more than one mechanism and thus shared between multiple mechanisms. The microprocessor 992 may further access some non-transitory memory 998 (e.g., random access memory or RAM) via a system bus 996 to read and / or write data during the process execution of the microprocessor.

[0080] Fig. 10A and Fig. 10B An example method for fabricating a semiconductor structure is shown according to some embodiments. Fig. 10A, in step 1002, the substrate is etched to form a first fin structure and a second fin structure arranged on the substrate extending in a first direction on a horizontal plane. The first fin structure is located in a first unit, and the second fin structure is located in a second unit, and the second unit is adjacent to the first unit at a boundary line extending along the first direction. In step 1004, a first dielectric layer is deposited on the first fin structure, the second fin structure, and the substrate. In step 1006, a buried power rail is deposited on the first dielectric layer. The buried power rail is located between the first fin structure and the second fin structure and extends along the first direction. The buried power rail provides a first voltage. In some embodiments, the buried power rail is made of ruthenium (Ru) deposited on a silicon seed layer. In step 1008, a high-k dielectric layer is deposited on the buried power rail and the first dielectric layer. In step 1010, a first source structure and a second source structure are formed on the first fin structure and the second fin structure, respectively. Then, the method proceeds to Fig. 10B Step 1012 in .

[0081] Reference now Fig. 10B , in step 1012, a first vertical interconnection channel (via) is formed on the buried power rail. The first via extends in a vertical direction perpendicular to the horizontal plane. The first via extends at the top of the first via in a bidirectional manner along the second direction above the first fin structure and the second fin structure, so that the first via is short-circuited with the first metal diffusion (MD) metal line and the second MD metal line arranged in the metal diffusion (MD) layer. The first MD metal line is arranged on the first source structure, and the second MD metal line is arranged on the second source structure. The MD layer is located above the buried power rail. In step 1014, a second via is deposited on the first via extending in the vertical direction. The first via electrically connects the buried power rail and the second via. In step 1016, a first metal zero (M0) metal track is deposited on the second via. The first M0 metal track extends in the first direction. The second via electrically connects the first via and the first M0 metal track. The first M0 metal track is above the boundary line and is arranged in the metal zero (M0) layer. The M0 layer is located above the MD layer.

[0082] An embodiment of the present disclosure may provide an IC chip. The IC chip includes: a substrate; a first fin structure, disposed on the substrate extending along a first direction on a horizontal plane, the first fin structure being located in a first unit; a second fin structure, disposed on the substrate extending along the first direction, the second fin structure being located in a second unit, the second unit being adjacent to the first unit on a boundary line extending along the first direction; a buried power rail, disposed between the first fin structure and the second fin structure on the substrate extending along the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal rail, disposed in the M1 layer extending in the second direction along the horizontal plane. At the intersection of the buried power rail and the M1 metal rail in the horizontal plane, the IC chip also includes: a first vertical interconnection channel (through hole), which is arranged on the buried power rail extending in a vertical direction perpendicular to the horizontal plane; a second through hole, which is arranged on the first through hole extending in the vertical direction, and the first through hole electrically connects the buried power rail and the second through hole; a first metal zero (M0) metal rail, which is arranged in the M0 layer extending in the first direction, the first M0 metal rail is above the boundary line, the second through hole electrically connects the first through hole and the first M0 metal rail, the M1 layer is above the M0 layer, and the M0 layer is above the buried power rail; and a third through hole, which is arranged on the first M0 metal rail extending in the vertical direction, and the third through hole electrically connects the first M0 metal rail and the M1 metal rail.

[0083] Embodiments of the present disclosure may provide a semiconductor structure. The semiconductor structure includes: a buried power rail, disposed between a first fin structure and a second fin structure on a substrate extending in a first direction on a horizontal plane, the first fin structure and the second fin structure being disposed on a substrate extending in the first direction, the first fin structure being located in a first cell, the second fin structure being located in a second cell, the second cell being adjacent to the first cell at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal rail, disposed in an M1 layer extending in the second direction in a horizontal plane. At the intersection of the buried power rail and the M1 metal rail in the horizontal plane, the semiconductor structure further includes a conductive path to provide a first voltage to the M1 metal rail, the conductive path having a first metal zero (M0) metal rail, disposed in the M0 layer extending in the first direction, the first M0 metal rail being above the boundary line.

[0084] An embodiment of the present disclosure may provide a method. The method includes: etching a substrate to form a first fin structure and a second fin structure arranged on the substrate extending in a first direction on a horizontal plane, the first fin structure being located in a first unit, and the second fin structure being located in a second unit, the second unit being adjacent to the first unit on a boundary line extending in the first direction; depositing a first dielectric layer on the first fin structure, the second fin structure, and the substrate; depositing a buried power rail on the first dielectric layer, the buried power rail being between the first fin structure and the second fin structure, extending in the first direction and providing a first voltage; depositing a high-k dielectric layer on the buried power rail and the first dielectric layer; forming a first source structure and a second source structure on the first fin structure and the second fin structure, respectively; forming a first vertical interconnection channel (through hole) on the buried power rail extending in a vertical direction perpendicular to the horizontal plane, wherein the first through hole A first through hole is extended at the top of the first fin structure and the second fin structure in a bidirectional manner along the second direction, so that the first through hole is short-circuited with a first metal diffusion (MD) metal line and a second MD metal line arranged in a metal diffusion (MD) layer, the first MD metal line is arranged on the first source structure, the second MD metal line is arranged on the second source structure, and the MD layer is above the buried power rail; a second through hole is deposited on the first through hole extending along the vertical direction, the first through hole electrically connecting the buried power rail and the second through hole; and a first metal zero (M0) metal track is deposited on the second through hole, the first M0 metal track extends along the first direction, the second through hole electrically connects the first through hole and the first M0 metal track, the first M0 metal track is above the boundary line and is arranged in the metal zero (M0) layer, and the M0 layer is located above the MD layer.

[0085] According to one embodiment of the present application, an integrated circuit chip is provided, comprising: a substrate; a first fin structure, arranged on the substrate extending along a first direction on a horizontal plane, the first fin structure being located in a first unit; a second fin structure, arranged on the substrate extending along the first direction, the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending along the first direction; a buried power rail, arranged between the first fin structure and the second fin structure on the substrate extending along the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal rail, arranged in the M1 layer extending in the second direction in the horizontal plane; wherein at the intersection of the buried power rail and the M1 metal rail in the horizontal plane, the integrated circuit chip further It includes: a first vertical interconnection channel (through hole), which is arranged on a buried power rail extending in a vertical direction perpendicular to a horizontal plane; a second through hole, which is arranged on the first vertical interconnection channel (through hole) extending in the vertical direction, and the first vertical interconnection channel (through hole) electrically connects the buried power rail and the second through hole; a first metal zero (M0) metal track, which is arranged in the M0 layer extending in the first direction, the first M0 metal track is above the boundary line, the second through hole electrically connects the first vertical interconnection channel (through hole) and the first M0 metal track, the M1 layer is above the M0 layer, and the M0 layer is above the buried power rail; and a third through hole, which is arranged on the first M0 metal track extending in the vertical direction, and the third through hole electrically connects the first M0 metal track and the M1 metal track. In some embodiments, a first vertical interconnection channel (via) extends in a bidirectional manner along a second direction at a top of the first vertical interconnection channel (via) over the first fin structure and the second fin structure to short the first vertical interconnection channel (via) with a first metal diffusion (MD) metal line and a second MD metal line disposed in a metal diffusion (MD) layer, the first MD metal line being disposed over the first fin structure, the second MD metal line being disposed over the second fin structure, the MD layer being over the buried power rail, and the MD layer being under the M0 layer. In some embodiments, the first MD metal line is connected to a source of a first field effect transistor (FET), and the second MD metal line is connected to a source of the second FET. In some embodiments, the first vertical interconnection channel (via) extends in a bidirectional manner along a second direction at a top of the first vertical interconnection channel (via) such that the first vertical interconnection channel (via) is shorted with the first metal diffusion metal line and separated from the second metal diffusion (MD) metal line, the first MD metal line being disposed over the first fin structure, the second MD metal line being disposed over the second fin structure, the MD layer being over the buried power rail, and the MD layer being under the M0 layer. In some embodiments, the first MD metal line is connected to the source of the third FET, and the second MD metal line is connected to the drain of the fourth FET.In some embodiments, the first vertical interconnection channel (via) does not extend at the top of the first vertical interconnection channel (via) in the second direction, so that the first vertical interconnection channel (via) is separated from the first metal diffusion (MD) metal line and the second metal diffusion (MD) metal line, the first MD metal line is arranged above the first fin structure, the second MD metal line is arranged above the second fin structure, the MD layer is located above the buried power rail, and the MD layer is below the M0 layer. In some embodiments, the first MD metal line is connected to the drain of the fifth FET, and the second MD metal line is connected to the drain of the sixth FET. In some embodiments, wherein the first four M0 metal track sets arranged in the M0 layer extending along the first direction are located in the first cell, and the second four M0 metal track sets arranged in the M0 layer extending along the first direction are located in the second cell. In some embodiments, the first cell and the second cell share the first M0 metal track, the first cell also has four M0 metal tracks arranged in the M0 layer and extending along the first direction, and the second cell further has four M0 metal tracks in the M0 layer and extending in the first direction. In some embodiments, the first direction is perpendicular to the second direction.

[0086] According to another embodiment of the present application, a semiconductor structure is provided, including: a buried power rail, arranged between a first fin structure and a second fin structure on a substrate extending along a first direction on a horizontal plane, the first fin structure and the second fin structure are arranged on the substrate extending along the first direction, the first fin structure is located in a first unit, the second fin structure is located in a second unit, the second unit is adjacent to the first unit at a boundary line extending along the first direction, the buried power rail provides a first voltage; and a metal one (M1) metal track, arranged in an M1 layer extending in the second direction in a horizontal plane; wherein, at the intersection of the buried power rail and the M1 metal track in the horizontal plane, the semiconductor structure also includes a conductive path to provide a first voltage to the M1 metal track, the conductive path having a first metal zero (M0) metal track arranged in the M0 layer extending along the first direction, and the first M0 metal track is above the boundary line. In some embodiments, the conductive path also includes: a first vertical interconnect channel (through hole), which is arranged on a buried power rail extending in a vertical direction perpendicular to the horizontal plane; a second through hole, which is arranged on the first vertical interconnect channel (through hole) extending in the vertical direction, the first vertical interconnect channel (through hole) electrically connecting the buried power rail and the second through hole, the second through hole electrically connecting the first vertical interconnect channel (through hole) and the first M0 metal track, the M1 layer is above the M0 layer, and the M0 layer is above the buried power rail; and a third through hole, which is arranged on the first M0 metal track extending in the vertical direction, the third through hole electrically connecting the first M0 metal track and the M1 metal track. In some embodiments, a first vertical interconnection channel (via) extends at a top of the first vertical interconnection channel (via) in a bidirectional manner along a second direction over the first fin structure and the second fin structure to short the first vertical interconnection channel (via) with a first metal diffusion (MD) metal line and a second MD metal line disposed in a metal diffusion (MD) layer, the first MD metal line being disposed over the first fin structure, the second MD metal line being disposed over the second fin structure, the MD layer being over the buried power rail, and the MD layer being under the M0 layer. In some embodiments, the first MD metal line is connected to a source of a first field effect transistor (FET), and the second MD metal line is connected to a source of the second FET. In some embodiments, the first vertical interconnection channel (via) extends at a top of the first vertical interconnection channel (via) in a bidirectional manner along a second direction, such that the first vertical interconnection channel (via) is shorted with the first metal diffusion (MD) metal line and separated from the second metal diffusion (MD) metal line, the first MD metal line being disposed over the first fin structure, the second MD metal line being disposed over the second fin structure, the MD layer being over the buried power rail, and the MD layer being under the M0 layer. In some embodiments, the first MD metal line is connected to the source of the third FET, and the second MD metal line is connected to the drain of the fourth FET.In some embodiments, the first vertical interconnect channel (via) does not extend at the top of the first vertical interconnect channel (via) in the second direction, so that the first vertical interconnect channel (via) is separated from a first metal diffusion (MD) metal line and a second metal diffusion (MD) metal line, the first MD metal line is disposed above the first fin structure, the second MD metal line is disposed above the second fin structure, the MD layer is located above the buried power rail, and the MD layer is below the M0 layer. In some embodiments, the first MD metal line is connected to the drain of the fifth FET, and the second MD metal line is connected to the drain of the sixth FET.

[0087] According to another embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising: etching a substrate to form a first fin structure and a second fin structure arranged on the substrate extending in a first direction along a horizontal plane, the first fin structure being located in a first unit, and the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending in the first direction; depositing a first dielectric layer on the first fin structure, the second fin structure, and the substrate; depositing a buried power rail on the first dielectric layer, the buried power rail being between the first fin structure and the second fin structure, extending in the first direction and providing a first voltage; depositing a high-k dielectric layer on the buried power rail and the first dielectric layer; forming a first source structure and a second source structure on the first fin structure and the second fin structure, respectively; forming a first vertical interconnection channel (through hole) on the buried power rail extending in a vertical direction perpendicular to the horizontal plane, wherein the first vertical interconnection channel (through hole) is formed in a first A fin structure and a second fin structure are extended in a bidirectional manner along a second direction on top of a first vertical interconnection channel (through hole), so that the first vertical interconnection channel (through hole) is short-circuited with a first metal diffusion (MD) metal line and a second MD metal line arranged in a metal diffusion (MD) layer, the first MD metal line is arranged on a first source structure, the second MD metal line is arranged on a second source structure, and the MD layer is above a buried power rail; a second through hole is deposited on the first vertical interconnection channel (through hole) extending along the vertical direction, the first vertical interconnection channel (through hole) electrically connecting the buried power rail and the second through hole; and a first metal zero (M0) metal track is deposited on the second through hole, the first M0 metal track extends along the first direction, the second through hole electrically connects the first vertical interconnection channel (through hole) and the first M0 metal track, the first M0 metal track is above the boundary line and arranged in the metal zero (M0) layer, and the M0 layer is above the MD layer. In some embodiments, the method of manufacturing a semiconductor structure also includes: depositing a first set of four M0 metal tracks in an M0 layer extending along a first direction, the first set of four M0 metal tracks being located within a first unit; and depositing a second set of four M0 metal tracks in an M0 layer extending along the first direction, the second set of four M0 metal tracks being located within a second unit.

[0088] The features of several embodiments are discussed above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that this equivalent construction does not deviate from the spirit and scope of the present invention, and they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit chip, comprising: substrate; A first fin structure is disposed on the substrate extending along a first direction on a horizontal plane, and the first fin structure is located in a first unit; a second fin structure disposed on the substrate extending along the first direction, the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending along the first direction; A buried power rail is disposed between the first fin structure and the second fin structure on the substrate extending along the first direction, and the buried power rail provides a first voltage; as well as A metal-metal track disposed in a metal layer extending in a second direction in the horizontal plane; Wherein, at the intersection of the buried power rail and the metal-metal rail in the horizontal plane, the integrated circuit chip further comprises: a first through hole disposed on the buried power rail extending in a vertical direction perpendicular to the horizontal plane; a second through hole, disposed on the first through hole extending along the vertical direction, the first through hole electrically connecting the buried power rail and the second through hole; a first metal-zero metal track disposed in a metal-zero layer extending along the first direction, the first metal-zero metal track being above the boundary line, the second via electrically connecting the first via and the first metal-zero metal track, the metal first layer being above the metal-zero layer, and the metal-zero layer being above the buried power rail; and A third through hole is provided on the first metal-zero metal track extending along the vertical direction, and the third through hole electrically connects the first metal-zero metal track and the metal-one metal track.

2. The integrated circuit chip according to claim 1, wherein: The first through-hole extends in a bidirectional manner along the second direction at a top of the first through-hole over the first fin structure and the second fin structure to short-circuit the first through-hole with a first metal diffusion metal line and a second metal diffusion metal line disposed in a metal diffusion layer, wherein the first metal diffusion metal line is disposed over the first fin structure, the second metal diffusion metal line is disposed over the second fin structure, the metal diffusion layer is over the buried power rail, and the metal diffusion layer is under the metal zero layer.

3. The integrated circuit chip according to claim 2, wherein: The first metal diffusion metal line is connected to a source of a first field effect transistor, and the second metal diffusion metal line is connected to a source of a second field effect transistor.

4. The integrated circuit chip according to claim 1, wherein: The first through hole extends at the top of the first through hole in a bidirectional manner along the second direction, so that the first through hole is short-circuited with a first metal diffusion metal line and separated from a second metal diffusion metal line, the first metal diffusion metal line is arranged above the first fin structure, the second metal diffusion metal line is arranged above the second fin structure, the metal diffusion layer is located above the buried power rail, and the metal diffusion layer is below the metal zero layer.

5. The integrated circuit chip according to claim 4, wherein: The first metal diffusion metal line is connected to a source of the third field effect transistor, and the second metal diffusion metal line is connected to a drain of the fourth field effect transistor.

6. The integrated circuit chip according to claim 1, wherein: The first through hole does not extend at the top of the first through hole in the second direction, so that the first through hole is separated from a first metal diffusion metal line and a second metal diffusion metal line, the first metal diffusion metal line is arranged above the first fin structure, the second metal diffusion metal line is arranged above the second fin structure, the metal diffusion layer is located above the buried power rail, and the metal diffusion layer is below the metal zero layer.

7. The integrated circuit chip according to claim 6, wherein: The first metal diffusion metal line is connected to a drain of a fifth field effect transistor, and the second metal diffusion metal line is connected to a drain of a sixth field effect transistor.

8. The integrated circuit chip according to claim 1, wherein: A first set of four metal zero metal tracks disposed in the metal zero layer extending along the first direction are located within the first unit, and a second set of four metal zero metal tracks disposed in the metal zero layer extending along the first direction are located within the second unit.

9. The integrated circuit chip according to claim 8, wherein: The first cell and the second cell share the first metal zero metal track, the first cell also has four metal zero metal tracks arranged in the metal zero layer and extending along the first direction, and the second cell further has four metal zero metal tracks in the metal zero layer and extending in the first direction.

10. The integrated circuit chip according to claim 1, wherein: The first direction is perpendicular to the second direction.

11. A semiconductor structure comprising: A buried power rail is arranged between a first fin structure and a second fin structure on a substrate extending along a first direction on a horizontal plane, the first fin structure and the second fin structure are arranged on the substrate extending along the first direction, the first fin structure is located in a first cell, the second fin structure is located in a second cell, the second cell is adjacent to the first cell at a boundary line extending along the first direction, and the buried power rail provides a first voltage; as well as A metal-metal track is arranged in a metal layer extending in the second direction in the horizontal plane; Wherein, at the intersection of the buried power rail and the metal-to-metal track in the horizontal plane, the semiconductor structure also includes a conductive path to provide the first voltage to the metal-to-metal track, the conductive path having a first metal-zero metal track arranged in a metal-zero layer extending along the first direction, and the first metal-zero metal track is above the boundary line.

12. The semiconductor structure according to claim 11, wherein: The conductive path further comprises: a first through hole disposed on the buried power rail extending in a vertical direction perpendicular to the horizontal plane; a second through hole, disposed on the first through hole extending in the vertical direction, the first through hole electrically connecting the buried power rail and the second through hole, the second through hole electrically connecting the first through hole and the first metal zero metal rail, the metal first layer being above the metal zero layer, and the metal zero layer being above the buried power rail; and A third through hole is provided on the first metal-zero metal track extending along the vertical direction, and the third through hole electrically connects the first metal-zero metal track and the metal-one metal track.

13. The semiconductor structure of claim 12, wherein: The first through-hole extends in a bidirectional manner along the second direction at a top of the first through-hole over the first fin structure and the second fin structure to short-circuit the first through-hole with a first metal diffusion metal line and a second metal diffusion metal line disposed in a metal diffusion layer, wherein the first metal diffusion metal line is disposed over the first fin structure, the second metal diffusion metal line is disposed over the second fin structure, the metal diffusion layer is over the buried power rail, and the metal diffusion layer is under the metal zero layer.

14. The semiconductor structure according to claim 13, wherein: The first metal diffusion metal line is connected to a source of a first field effect transistor, and the second metal diffusion metal line is connected to a source of a second field effect transistor.

15. The semiconductor structure according to claim 12, wherein: The first through hole extends at the top of the first through hole in a bidirectional manner along the second direction, so that the first through hole is short-circuited with a first metal diffusion metal line and separated from a second metal diffusion metal line, the first metal diffusion metal line is arranged above the first fin structure, the second metal diffusion metal line is arranged above the second fin structure, the metal diffusion layer is located above the buried power rail, and the metal diffusion layer is below the metal zero layer.

16. The semiconductor structure according to claim 15, wherein: The first metal diffusion metal line is connected to a source of the third field effect transistor, and the second metal diffusion metal line is connected to a drain of the fourth field effect transistor.

17. The semiconductor structure according to claim 12, wherein: The first through hole does not extend at the top of the first through hole in the second direction, so that the first through hole is separated from a first metal diffusion metal line and a second metal diffusion metal line, the first metal diffusion metal line is arranged above the first fin structure, the second metal diffusion metal line is arranged above the second fin structure, the metal diffusion layer is located above the buried power rail, and the metal diffusion layer is below the metal zero layer.

18. The semiconductor structure according to claim 17, wherein: The first metal diffusion metal line is connected to a drain of a fifth field effect transistor, and the second metal diffusion metal line is connected to a drain of a sixth field effect transistor.

19. A method of manufacturing a semiconductor structure, comprising: Etching a substrate to form a first fin structure and a second fin structure disposed on the substrate extending in a first direction along a horizontal plane, the first fin structure being located in a first unit, and the second fin structure being located in a second unit, the second unit being adjacent to the first unit at a boundary line extending along the first direction; depositing a first dielectric layer on the first fin structure, the second fin structure, and the substrate; Depositing a buried power rail on the first dielectric layer, the buried power rail is between the first fin structure and the second fin structure, extends along the first direction and provides a first voltage; depositing a high-k dielectric layer over the buried power rail and the first dielectric layer; forming a first source structure and a second source structure on the first fin structure and the second fin structure respectively; forming a first through hole on the buried power rail extending in a vertical direction perpendicular to the horizontal plane, wherein the first through hole extends in a second direction in a bidirectional manner on top of the first through hole above the first fin structure and the second fin structure, so that the first through hole is short-circuited with a first metal diffusion metal line and a second metal diffusion metal line disposed in a metal diffusion layer, the first metal diffusion metal line being disposed on the first source structure, the second metal diffusion metal line being disposed on the second source structure, and the metal diffusion layer being above the buried power rail; depositing a second via on the first via extending in the vertical direction, the first via electrically connecting the buried power rail and the second via; as well as A first metal zero metal track is deposited on the second through hole, the first metal zero metal track extends along the first direction, the second through hole electrically connects the first through hole and the first metal zero metal track, the first metal zero metal track is above the boundary line and is arranged in a metal zero metal zero layer, and the metal zero layer is above the metal diffusion layer.

20. The method according to claim 19, further comprising: Depositing first four metal zero metal track sets arranged in the metal zero layer extending along the first direction, the first four metal zero metal track sets being located within the first unit; as well as A second set of four metal-zero metal tracks are deposited in the metal-zero layer extending along the first direction, the second set of four metal-zero metal tracks being located within the second unit.

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