Integrated circuit structure

Abstract

An integrated circuit (IC) structure includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first p-type active region and the second p-type active region includes a first set of vertically stacked channel layers having a width W1, and each of the first n-type active region and the second n-type active region includes a second set of vertically stacked channel layers having a width W2, wherein W2 is less than W1. The IC structure also includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third set of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth set of vertically stacked channel layers having a width W4, wherein W3 is greater than or equal to W4.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit (IC) structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances.

[0003] As integrated circuit (IC) technology moves toward smaller technology nodes, gate-all-around (GAA) transistors have been incorporated into memory devices (including, for example, static random access memory or SRAM cells) and core devices (including, for example, standard logic or STD cells) to reduce chip footprint while maintaining reasonable processing margins. However, designing IC chips including GAA transistors for a variety of applications involves complex and often expensive processes. Therefore, while existing techniques for manufacturing GAA transistors are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0004] Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: a memory cell, comprising: a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region, which are longitudinally arranged along a first direction and spaced apart from each other in the above order along a second direction substantially perpendicular to the first direction, wherein each of the first p-type active region and the second p-type active region comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, wherein each of the first n-type active region and the second n-type active region comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type active region, the first n-type active region, the second n-type active region, and the second p-type active region extends across a boundary of the memory cell along the first direction.

[0005] Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a logic standard cell, comprising: an n-type active region and a p-type active region, which are longitudinally oriented along a first direction and spaced apart from each other along a second direction substantially perpendicular to the first direction, wherein the n-type active region comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, and wherein the p-type active region comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W1 being greater than or equal to the width W2; and a metal gate structure, longitudinally oriented along the second direction, wherein the metal gate structure is bonded to the first plurality of vertically stacked channel layers to form a p-type device, and is bonded to the second plurality of vertically stacked channel layers to form an n-type device.

[0006] Some further embodiments of the present application provide an integrated circuit (IC) structure, comprising: a memory cell, comprising: a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin, which are longitudinally arranged along a first direction and spaced apart from each other in the above order along a second direction substantially perpendicular to the first direction, wherein each of the first p-type fin and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, wherein each of the first n-type fin and the second n-type fin comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first ... second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W2 measured along the each continuously straddling a boundary of the memory cell; a standard logic cell comprising a third n-type fin and a third p-type fin, longitudinally oriented along the first direction and spaced apart from each other along the second direction, wherein the third n-type fin comprises a third plurality of vertically stacked channel layers, the third plurality of vertically stacked channel layers having a width W3 measured along the second direction, and wherein the third p-type fin comprises a fourth plurality of vertically stacked channel layers, the fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W3 being greater than or equal to the width W4; and a plurality of metal gate structures disposed over the first n-type fin, the second n-type fin, and the third n-type fin to form a p-type device, and disposed over the first p-type active region, the second p-type active region, and the third p-type active region to form an n-type device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0008] Figure 1 is a schematic plan view of a portion or all of an IC chip according to various aspects of the present invention.

[0009] Figure 2A and Fig.14A is a schematic plan view of part or all of an array of SRAM cells according to various aspects of the present invention.

[0010] Figure 2B and Fig. 14B is a schematic plan view of part or all of an array of STD units according to various aspects of the present invention.

[0011] Figure 3 and Fig.15 According to various aspects of the present invention, Figure 2A and / or Fig.14A A schematic plan view of part or all of an IC structure of an SRAM cell.

[0012] Figure 4 , Fig.16 and Fig.19 According to various aspects of the present invention, Figure 3 , Fig.15 and Fig.18 A cross-sectional view of part or all of the IC structure along line AA'.

[0013] Figure 5 , Fig.10 , Fig.17 and Fig. 20 According to various aspects of the present invention, Figure 3 , Figure 8 , Fig.15 and Fig.18 A cross-sectional view of part or all of the IC structure along line BB'.

[0014] Figure 6 , Fig.11 and Fig.13 According to various aspects of the present invention, Figure 3 , Figure 8 and Fig.12 A cross-sectional view of part or all of the IC structure along line CC'.

[0015] Fig. 7A According to various aspects of the present invention, Figure 2A and / or Fig.14A A schematic diagram of part or all of the IC structure of an SRAM cell.

[0016] Figure 7B According to various aspects of the present invention, Figure 2A and / or Fig.14A A schematic plan view of part or all of an IC structure of an SRAM cell.

[0017] Figure 8 , Fig.12 and Fig.18 According to various aspects of the present invention, Figure 2B and / or Fig. 14B A partial or complete plan view of the IC structure of the STD unit.

[0018] Fig.9A and Fig. 9B According to various aspects of the present invention, Figure 8 A cross-sectional view of part or all of the IC structure along line AA'.

[0019] Fig.21 , Fig. 22 and Fig.23 According to various aspects of the present invention, Figure 3 A cross-sectional view of part or all of the IC structure along lines BB', CC' and DD'.

[0020] Fig.24 is a flow chart of a method for manufacturing an IC chip according to various aspects of the present invention. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the present invention. The specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the present invention below, the formation of a component on another component, connected to and / or coupled to another component can include an embodiment in which the component is formed in the form of direct contact, and can also include an embodiment in which an additional component can be inserted between the components so that the components can not be directly contacted. In addition, the use of space relative terms such as "bottom", "top", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) is to facilitate the understanding of the relationship between a component of the present invention and another component. The space relative terms are intended to include different orientations of the device of the component.

[0022] In addition, when "about", "approximately", etc. are used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range including the value, such as within + / -10% of the value or other values ​​understood by those skilled in the art. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm. Further, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] The present invention relates generally to semiconductor devices, and more specifically to field effect transistors (FETs) in memories (such as three-dimensional all-around gate (GAA) FETs) and / or standard logic cells of integrated circuit (IC) structures. Typically, a GAA FET includes a plurality of vertically stacked sheets (e.g., nanosheets), wires (e.g., nanowires), or rods (e.g., nanorods) located in the channel region of the FET, allowing better gate control, lower leakage current, and improved scaling capabilities for various IC applications. While existing techniques for manufacturing GAA FETs are generally adequate for their intended applications, they are not completely satisfactory in all respects. The present invention includes multiple embodiments. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0024] refer to Figure 1 , Figure 2A and Figure 2B The present invention provides an IC structure 10 formed above a semiconductor substrate and includes at least an array 100 of memory cells and an array 200 of standard logic (STD) cells. The array 100 may include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NVRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. In the present embodiment, the array 100 includes a plurality of SRAM cells 101, which generally provide a memory or storage device that can retain data only when powered. Thus, the array 100 is hereinafter referred to as an SRAM array 100. In the present embodiment, the IC structure 10 also includes STD cells 201 (for example, such as inverters, AND, NAND, OR, XOR, NOR, other suitable devices, or combinations thereof) each configured to provide various standard logic devices (such as inverters, AND, NAND, OR, XOR, NOR, other suitable devices, or combinations thereof). Figure 8The STD cells 201A-201D described herein are STD cells 201A-201D described herein). The STD cells 201 may be pre-designed according to manufacturing technology, stored in the STD cell library, and reused in various IC designs to simplify the manufacturing process. The STD array 200 may include other frequently used circuit modules, such as trigger circuits and latches. In the present embodiment, each SRAM cell 101 and STD cell 201 provides one or more GAA FETs discussed in detail below. Although not described herein, the IC chip 10 may further include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs (such as FinFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other suitable devices, or combinations thereof. Additional components may be added to the IC structure 10, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC structure 10.

[0025] refer to Figure 2A , each SRAM cell 101 is configured to include a p-type three-dimensional fin-shaped active region 106 (hereinafter referred to as p-type fin 106) each disposed in a p-type doped region 111 (hereinafter referred to as p-well 111) and an n-type three-dimensional fin-shaped active region 108 (hereinafter referred to as n-type fin 108) each disposed in an n-type doped region 110 (hereinafter referred to as n-well 110), which is between two p-wells 111. The p-type fin 106 and the n-type fin 108 are longitudinally oriented along the Y axis and are spaced apart from each other along an X axis substantially perpendicular to the Y axis. As will be discussed in detail below, each p-type fin 106 includes a first set of vertically stacked semiconductor layers configured to provide a channel region of an n-type GAA FET, and each n-type fin 108 includes a second set of vertically stacked semiconductor layers configured to provide a channel region of a p-type GAA FET. In many embodiments, the second set of vertically stacked semiconductor layers is different from the first set of vertically stacked semiconductor layers in at least one dimension along the X axis. Each SRAM cell 101 may be composed of a long spacing S along the X-axis. x and a short spacing S along the Y axis yIn the present embodiment, the p-type fin 106 and the n-type fin 108 extend across each SRAM cell 101 along the Y-axis, so that at least two adjacent SRAM cells 101 share a common p-type fin 106 and n-type fin 108. Each SRAM cell 101 can be configured for similar applications, such as high-speed applications, low-power applications, ultra-high-speed applications, other suitable applications, or a combination thereof. Optionally, different SRAM cells 101 can be configured for different applications and correspondingly designed to have different specifications (e.g., size, layout design, etc.).

[0026] refer to Figure 2B , each STD cell 201 is configured to include a p-type three-dimensional fin-shaped active region 206 (hereinafter referred to as p-type fin 206) each disposed in a p-type doped region 211 (hereinafter referred to as p-well 211) and a three-dimensional fin-shaped active region 208 (hereinafter referred to as n-type fin 208) each disposed in an n-type doped region 210 (hereinafter referred to as n-well 210), which is interposed between the p-wells 211. The p-type fin 206 and the n-type fin 208 are longitudinally oriented along the Y axis and are spaced apart from each other along the X axis. As will be discussed in detail below, each p-type fin 206 includes a first set of vertically stacked semiconductor layers configured to provide a channel region of an n-type GAA FET, and each n-type fin 208 includes a second set of vertically stacked semiconductor layers configured to provide a channel region of a p-type GAA FET. Similar to the SRAM cell 101, each STD cell 201 can be composed of a long spacing S along the X axis. x and a short spacing S along the Y axis y However, because different STD cells 201 may be targeted at different applications, the STD cells 201 in the STD array 200 may be different in size and layout design. In some embodiments, adjacent STD cells 201 arranged along the Y-axis may be physically separated by a dielectric gate structure 240A oriented longitudinally along the X-axis, such that the p-type fins 206 and the n-type fins 208 are continuously across the adjacent STD cells 201. In some embodiments, adjacent STD cells 201 arranged along the Y-axis may be electrically separated by an isolation gate structure 240B (e.g., a conductive gate structure configured to form an isolation device having a fin structure), while the p-type fins 206 and the n-type fins 208 are not physically separated at the cell boundaries.

[0027] Various embodiments of portions of the SRAM array 100 and the STD array 200 are discussed in detail below. Figures 3 to 7B An embodiment of a portion of an SRAM array 100 including a plurality of SRAM cells 101 is described; wherein, Figure 3 and Figure 7B is a schematic plan top view of an embodiment of an SRAM cell 101, Figure 4 It is taken along line AA' Figure 3 A schematic cross-sectional view of Figure 5 It is taken along line BB' Figure 3 A schematic cross-sectional view of Figure 6 It is taken along line CC' Figure 3 A schematic cross-sectional view of Fig. 7A is a schematic diagram of an embodiment of an SRAM cell 101 . Figures 8 to 13 An embodiment of a portion of an STD array 200 comprising a plurality of STD cells 201 is described; wherein, Figure 8 and Fig.12 is a schematic plan top view of an embodiment of the STD unit 201, Fig.9A and Fig. 9B It is taken along line AA' Figure 8 A schematic cross-sectional view of Fig.10 It is taken along line BB' Figure 8 A schematic cross-sectional view of Fig.11 and Fig.13 They are respectively taken along line CC' Figure 8 and Fig.12 Schematic cross-sectional view of .

[0028] refer to Figure 3 , schematically depicts a portion of an SRAM array 100 including four SRAM cells 101A, 101B, 101C, and 101D in a planar top view. It should be noted that the SRAM array 100 has been simplified for clarity. Figure 3 To better illustrate embodiments of the present invention. Thus, additional components may be added to the SRAM array 100, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the SRAM cells 101A-101D. In the described embodiment, the SRAM cells 101A-101D are substantially the same in size, i.e., the SRAM cells 101A-101D have the same dimensions as those defined above. x and S yBasically the same. Thus, for the purpose of simplicity, the SRAM cells 101A-101D may be generally referred to as SRAM cells 101. In the present embodiment, each SRAM cell 101 includes two p-type fins 106 each disposed in a p-type well 111 and two n-type fins 108 disposed in an n-type well 110 between the two p-type wells 111. In the present embodiment, the p-type fins 106 and the n-type fins 108 extend continuously across at least two SRAM cells 101 along the Y-axis. In other words, the p-type fins 106 and the n-type fins 108 are not truncated at the cell boundary (dashed line) along the X-axis. The continuous p-type fin 106 and n-type fin 108 can benefit the overall performance of each SRAM cell 101 by providing a more uniform and symmetrical fin profile between active regions of different conductivity types, providing better line end control for PFETs (e.g., pull-up or PU transistors formed on the n-type fin 108), and as a result, extending the pinning frequency of the n-well 110 without expanding the layout size of the SRAM cell 101.

[0029] The SRAM cell 101 also includes a plurality of gate stacks, such as gate stacks 130A, 130B, 130C, and 130D described herein, oriented longitudinally along the X-axis and disposed over the p-type fins 106 and / or the n-type fins 108 to form respective transistors. Each gate stack traverses a channel region of the p-type fin 106 or the n-type fin 108. In some examples, adjacent gate stacks along the X-axis may be separated by gate isolation features 138. In the described embodiment, a portion of gate stack 130A is joined to first p-type fin 106 to form a first pass-gate transistor (PG-1); a portion of gate stack 130B is joined to first p-type fin 106 and first n-type fin 108 to form a first pull-down transistor (PD-1) and a first pull-up transistor (PU-1), respectively; a portion of gate stack 130C is joined to second p-type fin 106 and second n-type fin 108 to form a second pull-down transistor (PD-2) and a second pull-up transistor (PU-2), respectively; and a portion of gate stack 130D is joined to second p-type fin 106 to form a second pass-gate transistor (PG-2). In some embodiments, PU-1 and PU-2 are configured as p-type transistors, while PD-1, PD-2, PG-1, and PG-2 are configured as n-type transistors. In many embodiments, the pull-down transistors PD-1 and PD-2 and the pull-up transistors PU-1 and PU-2 are configured to provide two cross-coupled inverters as data storage devices, while the pass gate transistors PG-1 and PG-2 are configured to provide a control unit for reading and writing data. In some embodiments, a portion of the gate stack 130C is bonded to the first n-type fin 108 to form a first isolation transistor (IS-1), and a portion of the gate stack 130B is bonded to the second n-type fin 108 to form a second isolation transistor (IS-2). In the present embodiment, IS-1 and IS-2 are configured as a continuous structure to accommodate the n-type fin 108, and therefore have minimal or negligible operational impact on the performance of the SRAM cell 101.

[0030] Reference now Figure 4 , which is along line AA' Figure 3In the embodiment of the cross-sectional view of FIG. 1 , the SRAM array 100 (as part of the IC structure 10) is formed on a semiconductor substrate (or wafer) 12 having a plurality of p-wells (p-type doped regions) 111 and n-wells (n-type doped regions) 110 formed therein (and / or above) according to various design requirements of the SRAM array 100. In the described embodiment, the portion of the substrate 12 located within each SRAM cell 101 includes an n-well 110 disposed between two p-wells 111. The n-well 110 is configured to provide at least one PFET, such as a pull-up (PU) transistor or an isolation (IS) transistor; and each p-well 111 is configured to provide at least one NFET, such as a pull-down (PD) transistor or a pass gate (PG) transistor. In some embodiments, the substrate 12 includes additional doped regions configured to provide one or more transistors according to the design requirements of the SRAM array 100. The SRAM array 100 also includes an isolation structure 14 disposed above the substrate 12 to electrically separate the various active regions formed above the substrate 12. In the present embodiment, the isolation structure 14 includes a shallow trench isolation (STI) feature.

[0031] Still reference Figure 4 , each p-type fin 106 includes a stack of semiconductor layers 105 disposed above the base fin 102; similarly, each n-type fin 108 includes a stack of semiconductor layers 107 disposed above the base fin 104. In the present embodiment, the semiconductor layers 105 and 107 are generally oriented longitudinally along the Y axis and are stacked vertically along the Z axis. In addition, each stack of semiconductor layers 105 is interposed between an n-type source / drain (S / D) feature 114N ( Figure 4 104, and each stack of semiconductor layers 107 is interposed between p-type S / D features 114P ( Figure 4 In the present embodiment, the semiconductor layer 105 is suspended between one of the gate stacks 130A-130D (e.g., Figure 4 The gate stack 130B or gate stack 130D described above is in (or wrapped by) to form a GAA NFET (e.g., PD-1, PD-2, PG-1, or PG-2), and the semiconductor layer 107 is suspended from one of the gate stacks 130A-130D (e.g., Figure 4In other words, each stack of semiconductor layer 105 is joined with a portion of gate stacks 130A-130D to form a channel region of a GAA PFET, and each stack of semiconductor layer 107 is joined with a portion of gate stacks 130A-130D to form a channel region of a GAA PFET. Thus, for the sake of clarity, semiconductor layer 105 is hereinafter referred to as channel layer 105, and semiconductor layer 107 is hereinafter referred to as channel layer 107.

[0032] Each of the channel layers 105 and 107 may include Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof. In the present embodiment, each of the semiconductor layers 105 and 107 includes Si in the form of nanosheets, nanowires (e.g., nanowires with hexagonal cross-sections), nanorods (e.g., nanorods with square or circular cross-sections), or other suitable configurations. In some embodiments, the p-type fin 106 and the n-type fin 108 each include two to ten channel layers 105 and 107, respectively. For example, the p-type fin 106 and the n-type fin 108 may each include three channel layers 105 and three channel layers 107, respectively. Of course, the present invention is not limited to such a configuration, and the number of semiconductor layers may be adjusted according to the design requirements for the IC structure 10. Each stack of channel layers 105 and 107 can be defined by the width of the stack measured along the longitudinal direction of the gate stacks 130A-130D (described in detail below), the layer thickness measured along the stacking direction of the channel layer, and the separation distance between adjacent layers. For example, each stack of channel layer 105 has a width W1, a layer thickness T1, and a layer separation distance S1, and each stack of channel layer 107 has a width W2, a layer thickness T2, and a layer separation distance S2. In the present embodiment, W1 is greater than W2, T1 is substantially the same as T2, and S1 is substantially the same as S2. Therefore, the interlayer spacing P1 (which is the sum of the layer thickness and the layer separation distance) of the stack of channel layer 105 is substantially the same as the interlayer spacing P2 of the channel layer 107. It should be noted that "substantially the same" used in the present invention means that the difference between the two values ​​is within about ±5%. In some examples, the sheet thicknesses T1 and T2 may each be about 4 nm to about 8 nm; the sheet separation distances S1 and S2 may each be about 6 nm to about 15 nm; and the interlayer spacings P1 and P2 may be about 10 nm to about 23 nm. Of course, other dimensions of the layer thicknesses, layer separation distances, and interlayer spacings may also be suitable for embodiments of the present invention.

[0033] The term "width" as used herein refers to the lateral distance of each channel layer averaged over the plurality of channel layers in the stacking direction (i.e., Z-axis) along the overall longitudinal direction of the gate stacks 130A-130D (i.e., X-axis). As discussed above, W1 of each channel layer 105 is at least about 10% greater than W2 of the stack of channel layers 107 by at least about 10%. In some embodiments, the ratio of W1 to W2 is about 1.1 to about 4. In the present embodiment, the relatively narrower channel region of the GAA PFETs (e.g., PU-1, PU-2, etc.) located in the SRAM cell (e.g., SRAM cell 101) provides at least the benefits of reducing the cell size and increasing the write margin of the cell (i.e., processing speed). This is because the write margin of an SRAM cell is typically determined by the pass gate transistor (I on _PG) on With the pull-up transistor (I on _PU) on The ratio of W1 to W2 is determined by the ratio of W1 to W2, which is generally proportional to the ratio of W1 to W2 defined in this embodiment. In addition, because the carrier mobility in GAA NFET is generally greater than the carrier mobility in GAA PFET, especially along the vertical stacking direction of the channel layer (which is generally in crystalline Si), the carrier mobility in GAA NFET is generally greater than the carrier mobility in GAA PFET. <100> direction), so for an increased ratio of W1 to W2, an increased write margin can be achieved by increasing W1 of the channel layer 105 in the GAA NFET and / or reducing W2 of the channel layer 107 in the GAA PFET. A ratio of about 1.1 illustrates a minimum difference between the width of the channel layer 105 and the width of the channel layer 107, which can produce a gain in processing speed of the SRAM cell 101 as provided herein. Although the present embodiment is not limited to such a range of ratios, the specific ratio of W1 to W2 can be determined based on factors such as the size of the SRAM cell 101 suitable for the desired IC application. In some instances, W1 can be about 8nm to about 40nm, and W2 can be about 5nm to about 20nm.

[0034] As discussed above, each of the gate stacks 130A-130D is bonded to the channel layer 105 or the channel layer 107 to form a respective GAA FET in the SRAM cell 101. Still referring to Figure 4, PD-1, PU-1 and IS-2 share a common gate stack 130B, while the two PG-2 located in adjacent SRAM cells 101 share a common gate stack 130D. In the present embodiment, the gate stacks 130A-130D are high-k metal gate structures, and therefore each includes at least a high-k gate dielectric layer 132 wrapping each channel layer 105 and 107 and a metal gate electrode 134 disposed above the high-k gate dielectric layer 132. Although not described, the metal gate electrode 134 may include a bulk conductive layer disposed above at least one work function metal layer. Each gate stack 130A-130D may further include a gate spacer 116 disposed on its sidewall, including a top spacer 116A and an inner spacer 116B, details of which are described below with reference to FIG. Figure 6 Have a discussion.

[0035] Still reference Figure 4 The SRAM array 100 may further include an etch stop layer (ESL) 133 disposed over the gate stacks 130A-130D, an interlayer dielectric (ILD) layer 20 disposed over the ESL 133, a gate contact 122 disposed in the ILD layer 20 to contact a portion of the gate stack 130D, and a gate contact 122 disposed in the ILD layer 20 to contact a portion of the gate stack 130D. Figure 4 The BCT 124 is configured to connect the gate terminals of each of IS-1 and IS-2 (as shown in FIG. Figure 4 The gate stack 130B described above is coupled to the drain terminal so as to have minimal or negligible effect on the operation of the SRAM array 100. Fig. 7A and Figure 7B A detailed schematic diagram of an embodiment of an interconnect structure of the SRAM cell 101 is shown and discussed.

[0036] Figure 5 It is taken along line BB' Figure 3 The cross-sectional view shows Figure 4S / D regions of the GAA FETs shown. In the present embodiment, the GAA NFETs (e.g., PD-1, PD-2, PG-1, and PG-2) include an n-type S / D feature 114N grown over the S / D region of the base fin 102, and the GAA PFETs (e.g., PU-1, PU-2, IS-1, and IS-2) include a p-type S / D feature 114P grown over the S / D region of the base fin 104. The n-type S / D feature 114N and the p-type S / D feature 114P each include one or more epitaxially grown semiconductor materials doped with a dopant of a suitable conductivity type (n-type or p-type, respectively). In such an embodiment, the n-type S / D feature 114N and the p-type S / D feature 114P are grown from and wrapped around at least the top of the base fins 102 and 104, respectively. In some examples, one or more of the n-type S / D features 114N and the p-type S / D features 114P can be joined such that they span more than one fin.

[0037] refer to Figure 3 and Figure 5 , the SRAM cell 101 may further include a plurality of S / D contacts 120A, 120B, 120C, and 120D oriented longitudinally along the X-axis. Each S / D contact 120A is disposed above one S / D component 114N, each S / D contact 120B is disposed above two adjacent S / D components 114N, each S / D contact 120C is disposed above an S / D component 114N and an adjacent S / D component 114P, and each S / D contact 120D is disposed above one S / D component 114P. In this embodiment, as shown in FIG. Figure 5 As described, each of the S / D contacts 120A-120D physically contacts the top surface of one or more S / D components formed thereon. Thus, different S / D contacts 120A-120D may vary in length along the X-axis, depending on the number of S / D components and / or the separation distance between two adjacent S / D components formed thereon. In the present embodiment, each SRAM cell 101 includes at least two complete S / D contacts 120C and portions of S / D contacts 120A, 120B, and 120D. The S / D contacts 120A-120D may alternatively be referred to as device-level contacts to distinguish them from other contact components (e.g., vias) that are subsequently formed as part of a multi-layer interconnect (MLI) structure. In addition, as Figure 5 As depicted, an S / D contact (eg, S / D contact 120C) disposed over the S / D region of each of isolation transistors IS- 1 and IS- 2 is electrically coupled to the gate terminal of the same device through BCT 124 .

[0038] Further details of the individual GAA FETs of the SARM cell 101 are given in Figure 6 Described in Figure 6 is taken along the Y-axis along the line CC′ across two adjacent SRAM cells 101 (eg, vertically through one of the n-type fins 108 ). Figure 3 For example, each of the gate stacks 130A-130D (eg, Figure 6 The gate stacks 130B and 130C shown include an upper portion disposed above the topmost channel layer (107 or 105) and a lower portion that wraps around multiple channel layers (107 or 105). In the present embodiment, a top spacer 116A is disposed on the sidewall of the upper portion of each of the gate stacks 130A-130D, and an inner spacer 116B is disposed on the sidewall of the lower portion of each of the gate stacks 130A-130D and separates the gate stacks from adjacent S / D components. Each SRAM cell 101 may further include a silicide layer 123 disposed between the S / D components 114P and 114N and their corresponding S / D contacts 120A-120D.

[0039] Fig. 7A and Figure 7B Describes Figure 3 1 and 10. The embodiment of a portion of an SRAM array 100 of FIG. 10 is described in detail, and various connections between the GAA FETs provided in the SRAM cell 101 and between the GAA FETs and an additional IC structure (e.g., an MLI structure) disposed above the GAA FETs are described. In this embodiment, the gate terminal of the pull-up transistor PU-1 is connected between the source terminal (electrically coupled to the power supply voltage (V DD )) and the first common drain (CD1), and the gate terminal of the pull-down transistor PD-1 is between the source terminal (electrically coupled to the power supply voltage (V SS )) and CD1. The gate terminal of the pull-up transistor PU-2 is between the source terminal (electrically coupled to V DD ) and a second common drain (CD2), and the gate terminal of the pull-down transistor PD-2 is between the source terminal (electrically coupled to V SS ) and CD-2. In some embodiments, CD1 is a storage node (SN) that stores data in true form, and CD2 is a storage node (SNB) that stores data in complementary form. The gate terminal of the pass-gate transistor PG-1 is between the source terminal (electrically coupled to the bit line (BL)) and the drain terminal electrically coupled to CD1. The gate terminal of the pass-gate transistor PG-2 is between the source terminal (electrically coupled to the complementary bit line (BLB)) and the drain terminal electrically coupled to CD1. The gate terminals of PG-1 and PG-2 are electrically coupled to a word line (WL). In some embodiments, each SRAM cell 101 includes two cross-coupled inverters (connected by Fig. 7A : a first inverter including PU-1 and PD-1 and a second inverter including PU-2 and PD-2. In some embodiments, PG-1 and PG-2 provide access to SN and SNB, respectively, during a read operation and / or a write operation. For example, in response to a voltage applied by WL to the gate terminals of PG-1 and PG-2, respectively, PG-1 couples SN to BL, and PG-2 couples SNB to BLB. As provided herein, each GAA NFET (e.g., PG-1, PD-1, PG-2, and PD-2) each includes a stack of channel layers 105 having a width W1, and each GAA PFET (e.g., PU-1, IS-1, PU-2, and IS-2) each includes a stack of channel layers 107 having a width W2, the width W2 being less than W1 as discussed in detail above.

[0040] refer to Figure 7B ,BL,BLB,V DD 、V SS , and WL are schematically shown as a plurality of horizontal interconnect structures (also referred to as wires) disposed above the SRAM array 100 as discussed above. For example, BL, BLB, and V DD , WL is formed in the second metal layer M2, and V is formed in the third metal layer M3 SS In addition, the SRAM array 100 may further include vertical interconnect structures (also referred to as vias) to electrically connect individual GAA FETs to appropriate metal layers and / or to electrically connect two metal layers together. For example, the via 126A may be configured to connect one of the device-level S / D contacts (e.g., Figure 7B S / D contacts 120A or 120D described in DD or BLB), via 126B may be configured to connect M1 with M2, and via 126C may be configured to connect M2 (eg, WL) with M3 (eg, V SS It should be understood that the gate and drain terminals of each of IS-1 and IS-2 are internally coupled at the device level located below the MLI structure.

[0041] Now go to STD array 200, refer to Figure 8 , schematically depicts a portion of the STD array 200 in a plan top view. It should be noted that the STD array 200 has been simplified for clarity. Figure 8 To better illustrate embodiments of the present invention. Thus, additional components may be added to the STD array 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the STD unit 201. Figure 3Unlike the SRAM array 100 described above, the STD array 200 may include multiple STD cells of varying sizes. For example, in this embodiment, four STD cells 201A, 201B, 201C, and 201D are described; wherein the STD cells 201A and 201D have similar SRAM arrays. x and S y-1 , and STD units 201B and 201C have similar S x and S y-2 , where S y-2 Less than S y-1 Of course, the specific spacing of the STD cells 201A-201D can be adjusted based on specific design requirements. The STD cells 201A-201D can each include one or more p-type fins 206 each disposed in a p-type well 211 and one or more n-type fins 208 each disposed in an n-type well 210 between two p-type wells 211. In the described embodiment, the STD cells 201A-201D each include one p-type fin 206 and one n-type fin 208, which are longitudinally oriented along the Y axis. In some embodiments, the length of the p-type fin 206 in the first STD cell (e.g., STD cell 201A) is different from the length of the p-type fin 206 in the second STD cell (e.g., STD cell 201C), and the length of the n-type fin 208 in the first STD cell is different from the length of the n-type fin 208 in the second STD cell.

[0042] Each of the STD cells 201A-201D further includes one or more gate stacks, such as gate stacks 230A, 230B, and / or 230C, configured to interface with a portion (i.e., a channel region) of the p-type fin 206 to form the GAA NFET 202, and to interface with a portion (i.e., a channel region) of the n-type fin 208 to form the GAA PFET 204. Adjacent gate stacks along the X-axis may be separated by gate isolation features 238, which are similar in function (and / or composition) to the gate isolation features 138 of the SRAM cell 101. Fig.9A , Fig. 9B and Fig.11 , the gate stacks 230A-230C may be high-k metal gate structures (similar to the gate stacks 130A-130D of the SRAM cell 101), and therefore each includes at least a high-k gate dielectric layer 232 disposed over the channel region of each GAA FET and a metal gate electrode 234 disposed over the high-k gate dielectric layer 232. Although not described, the metal gate electrode 234 may include a bulk conductive layer disposed over at least one work function metal layer. In addition, each gate stack 230A-230C may include a gate spacer 216 disposed on its sidewalls ( Figure 8The top gate spacer 216A is shown in FIG. Fig.11 ). Portions of the gate spacers 230A- 230C may be electrically coupled to subsequently formed components of the MLI structure through gate contacts 222 , which are similar to the gate contacts 122 of the SRAM cell 101 discussed above.

[0043] In the present embodiment, the p-type fin 206 and the n-type fin 208 do not extend continuously across two adjacent STD cells along the Y axis. In other words, the p-type fin 206 and the n-type fin 208 of each STD cell 201A-201D are interrupted by the dielectric gate structure 240A at the cell boundary (dashed line) along the X axis. In the present embodiment, the dielectric (i.e., generally non-conductive) gate structure 240A is oriented longitudinally along the X axis, i.e., generally parallel to the gate stacks 230A-230C, which are metal (i.e., conductive) gate stacks. In some embodiments, the dielectric gate structure 240A may include a structure called continuous polysilicon on a diffusion edge (or CPODE), which may be implemented to reduce the gate spacing between adjacent gate stacks 230A-230C. The dielectric gate structure 240A may be formed before or after a gate replacement process (e.g., a gate-last process discussed in detail below).

[0044] Common Reference Figure 8 , Fig.9A and Fig. 9B, the STD array 200 is formed over a substrate 12 as part of an IC structure 10, wherein various doped regions (i.e., p-well 211 and n-well 210) are separated by isolation structures 14. In the present embodiment, each p-type fin 206 formed in the p-well 211 includes a stack of semiconductor layers 207 disposed over the base fin 203, and each n-type fin 208 formed in the n-well 210 includes a stack of semiconductor layers 209 disposed over the base fin 205. The semiconductor layers 207 and 209 may be arranged in a configuration similar to the channel layers 105 and 107 of the SRAM cell 101 discussed above. For example, in the present embodiment, the semiconductor layers 207 and 209 are generally longitudinally oriented along the Y axis and vertically stacked along the Z axis. In addition, each stack of semiconductor layer 207 is interposed between n-type S / D features 214N formed over base fin 203, and each stack of semiconductor layer 209 is interposed between p-type S / D features 214P formed over base fin 205. In addition, semiconductor layer 207 is suspended in (or wrapped by) one of gate stacks 230A-230C (e.g., gate stack 230A) to form GAA NFET 204, and semiconductor layer 209 is suspended in (or wrapped by) one of gate stacks 230A-230C (e.g., gate stack 230A) to form GAA PFET 204. In other words, each stack of semiconductor layer 207 is joined with a portion of gate stacks 230A-230C to form a channel region of GAA NFET 204, and each stack of semiconductor layer 209 is joined with a portion of gate stacks 230A-230C to form a channel region of GAA PFET 204. As such, for clarity, semiconductor layer 207 is hereinafter referred to as channel layer 207, and semiconductor layer 209 is hereinafter referred to as channel layer 209. In addition, an ESL 233 similar to the ESL 133 discussed above with respect to the SRAM cell 101 may be disposed over the gate stacks 230A-230C to protect components of the STD cells 201A-201D during subsequent manufacturing processes.

[0045] In some embodiments, the composition of channel layers 207 and 209 can be substantially the same as the composition of channel layers 105 and 107, and can include Si in the form of nanosheets, nanowires, nanorods, or any other configuration suitable for forming a GAA FET. In some instances, the p-type fin 206 and the n-type fin 208 can each include two to ten channel layers 207 and 209, respectively; although the present embodiment is not limited to this configuration, and the number of semiconductor layers can be adjusted according to the design requirements for the IC structure 10. Each stack of channel layers 207 can be defined by a width W3, a layer thickness T3, and a layer separation distance S3, all of which are similar to the definitions of channel layers 105 and 107. Similarly, each stack of channel layers 209 can be defined by a width W4, a layer thickness T4, and a layer separation distance S4. In the present embodiment, T3 is substantially the same as T4, and S3 is substantially the same as S4. In some embodiments, reference Fig.9A , W3 is substantially the same as W4. As discussed above, "substantially the same" in this embodiment generally means that the difference between the two values ​​is within about ±5%. Therefore, W3 and W4 can be within 5% in size. In some embodiments, reference Fig. 9B , W3 is less than W4. For example, the ratio of W4 to W3 may be about 1.1 to about 2, that is, W4 is at least about 10% greater than W3. In some examples, W3 may be about 10 nm to about 60 nm, and W4 may be about 10 nm to about 70 nm.

[0046] As discussed above, the carrier mobility in a GAA NFET is generally greater than the carrier mobility in a GAA PFET, especially along the stacking direction of the channel layer. on , in order to increase the I on , it may be desirable to increase the ratio of W1, which is the layer width of the channel layer 105 located in the GAA NFET (e.g., PD-1, PD-2, PG-1, or PG-2), to the ratio W2, which is the layer width of the channel layer 107 located in the GAA PFET (e.g., PU-1 or PU-2). For example, in the present embodiment, the ratio of W1 to W2 is about 1.1 to about 4, that is, W1 is greater than W2 by at least about 10% of W2. However, in the STD cells 201A-201D, it may be more desirable to balance the performance of the GAA NFET 202 with the performance of the GAA PFET 204 by adjusting W3 to be less than or substantially the same as W4. In this regard, the ratio of W4 to W3 may be less than the ratio of W1 to W2 to maintain this balance.

[0047] Now common reference Figure 8 and Fig.10, each gate stack 230A-230C (and its corresponding channel region) is between two p-type S / D components 214P or two n-type S / D components 214N, depending on the conductivity type of the underlying fin structure. The STD cells 201A-201D may further include individual S / D contacts 220A, 220B, 220C, 220D, and 220E oriented longitudinally along the X-axis. Each S / D contact 220A-220E may be disposed above and in physical contact with one or more p-type S / D components 214P or one or more n-type S / D components 214N. For example, S / D contacts 220A and 220B are disposed above at least one n-type S / D component 214N, and S / D contacts 220C, 220D, and 220E are disposed above at least one p-type S / D component 214P. In some embodiments, the S / D contacts 220A-220E differ in length along the X-axis. For example, S / D contact 220E is longer than S / D contact 220C, which is longer than S / D contact 220D. Each STD cell 201A-201D can be coupled to a respective vertical interconnect structure, such as via 226A and via 226B, configured as a component of an MLI structure interconnecting the S / D contacts 220A-220E to a via 126A of the SRAM cell 101 as discussed above.

[0048] refer to Fig.11 ,exist Figure 8 Further details of the STD cells 201A-201D are described in the cross-sectional view of , which is taken along the Y-axis across the STD cells 201A and 201C along the line CC' (e.g., longitudinally through one of the n-type fins 208). As described herein, each gate stack 230A-230C may include components similar to the gate stacks 130A-130D located in the SRAM cell 101. For example, each gate stack 230A-230C is disposed between two S / D components (214N or 214P) and includes an upper portion disposed above the topmost channel layer (207 or 209) and a lower portion that wraps around multiple channel layers (207 or 209). The gate spacer 116 may include a top spacer 216A and an inner spacer 216B arranged in a configuration similar to the top spacer 116A and the inner spacer 116B discussed above. Similar to the structure of the SRAM cell 101, each STD cell 201A-201D may further include: a silicide layer 223 disposed between each of the S / D features 214P and 214N and their corresponding S / D contacts 220A-220E, an ESL 233 disposed over the gate stacks 230A-230C, and an ILD layer 20 disposed over the ESL 233. Still referring to Fig.11, the dielectric gate structure 240A is disposed at the cell boundary between two adjacent STD cells along the X-axis, thereby truncating the p-type fin 206 and the n-type fin 208. In the present embodiment, the dielectric gate structure 240A generally extends along the Y-axis to below the bottom surface of the gate stack 230A-230C, that is, to below the top surface of the isolation structure 14.

[0049] In some embodiments, the common reference Fig.12 and Fig.13 , the STD array 200 includes a p-type fin 206 and an n-type fin 208 that extend continuously across the cell boundary along the X-axis through at least two adjacent STD cells (e.g., through STD cells 201A and 201C or through STD cells 201B and 201D). Similar to the isolation transistors IS-1 and IS-2 of the SRAM cell 101 discussed above, the continuous fin structure located in the STD cells 201A-201D can benefit from the use of n-type isolation transistors 212 and p-type isolation transistors 213 disposed at the cell boundary. In the present embodiment, the n-type isolation transistor 212 and the p-type isolation transistor 213 are formed by isolation gate structures 240B that are bonded to the channel regions of the p-type fin 206 and the n-type fin 208, respectively. As discussed above, the channel region of the p-type fin 206 is configured as a stack including a channel layer 207 having a layer width of W3, and the channel region of the n-type fin 208 is configured as a stack including a channel layer 209 having a layer width of W4. In some embodiments, adjacent isolation gate structures 240B (which may be conductive gate stacks similar to gate stacks 230A-230C) are separated by gate isolation features 238. In addition, the gate terminal of each n-type isolation transistor 212 is electrically connected to V through gate contacts 222. DD , and the gate terminal of each p-type isolation transistor 213 is electrically connected to V SS In this embodiment, isolation transistors 212 and 213 are configured to have minimal or negligible effects on STD cells 201A-201D during operation. It should be understood that Fig.12 and Fig.13 The other components of the STD array 200 are described with Figures 8 to 11 The components described are identical. Therefore, for the sake of simplicity, the detailed description of these components will not be repeated.

[0050] In some embodiments of the present invention, the common reference FIG. 14A to FIG. 19 , the IC structure 10 also includes a plurality of dielectric fins disposed in the SRAM cell and / or STD cell provided herein. For example, Fig.14A and Fig. 14B In similar Figure 2A and Figure 2BEmbodiments of the SRAM array 100 and the STD array 200 are depicted in planar top views of those depicted, except that dielectric fins 160, 162, and 164 are present in the SRAM array 100 and dielectric fins 260 and 262 are present in the STD array 200. Figures 15 to 17 Embodiments of the SRAM array 100 having dielectric fins 160-164 are discussed in detail and are referenced below. Fig.18 and Fig.19 The embodiment of the STD array 200 having dielectric fins 260 and 262 is discussed in detail. It should be noted that Figures 15 to 17 The components of the SRAM array 100 are described with Figures 3 to 7B those described, and Fig.18 and Fig.19 The components of the STD array 200 are described with Figures 8 to 11 Therefore, for the sake of clarity, no reference will be made to FIG. 14A to FIG. 19 Repeat the detailed description for these components.

[0051] refer to Fig.14A and Fig.15 , in the SRAM array 100, the dielectric fins 160-164 are generally oriented longitudinally along the Y-axis (i.e., substantially parallel to the longitudinal direction of the p-type fins 106 and the n-type fins 108), and are spaced apart from each other along the X-axis. In the present embodiment, the dielectric fins 160-164 extend through at least two adjacent SRAM cells 101 along the Y-axis. Along the X-axis, each dielectric fin 160 is disposed between two p-type fins 106, each dielectric fin 162 is disposed between a p-type fin 106 and an n-type fin 108, and each dielectric fin 164 is disposed between two n-type fins 108. In other words, the dielectric fins 160-164 are intermixed with the p-type fins 106 and the n-type fins 108 along the X-axis. In the depicted embodiment, the dielectric fin 160 is disposed at the cell boundary, and the dielectric fins 162 and 164 are disposed within the cell boundary. To further describe the embodiment, each SRAM cell 101 includes two dielectric fins 162 and one dielectric fin 164, while sharing each dielectric fin 160 with adjacent SRAM cells 101. Of course, the embodiment is not limited to this configuration, and a greater or lesser number of dielectric fins may be included according to various design requirements.

[0052] refer to Fig.16 , which describes Fig.15In a cross-sectional view of the SRAM array 100 along line AA' in FIG. 1 , each dielectric fin 160 may be defined as a width D1, each dielectric fin 162 may be defined as a width D2, and each dielectric fin 164 may be defined as a width D3. In some embodiments, D1, D2, and D3 are substantially the same in size (i.e., having a difference within approximately ±5%). In some embodiments, D1, D2, and D3 are different in size (i.e., having a difference of approximately >5%). In one such example, D1 may be greater than D2, and D2 may be greater than D3. In some embodiments, the widths D1, D2, and D3 are adjusted to accommodate the growth of the S / D components (e.g., the n-type S / D components 114N and the p-type S / D components 114P) located on each side of the dielectric fins 160-164, so that the size of the S / D components can be maximized without causing bridging issues in the SRAM cell 101 or substantially expanding the overall size of the SRAM cell 101. In some examples, D1 , D2 , and D3 may each be about 4 nm to about 20 nm; of course, other suitable sizes may also be applicable as long as the dielectric fins 160 - 164 ensure adequate performance of the SRAM cell 101 .

[0053] refer to Fig.17 , which describes Fig.15 1. In the cross-sectional view of the SRAM array 100 taken along line BB', the S / D contacts 120A-120D (eg, Fig.17 Portions of the described S / D contacts 120C) can physically contact the top surface of one or more of the dielectric fins 160-164 disposed between two adjacent S / D components (e.g., n-type S / D component 114N and p-type S / D component 114P). In some embodiments, the dielectric fins 160-164 are configured to prevent unintentional bridging between adjacent S / D components, thereby eliminating electrical shorts in the GAA FET. In addition, the dielectric fins 160-164 can expand the landing area of ​​the S / D contacts 120A-120D above the n-type S / D component 114N and the p-type S / D component 114P, thereby improving the performance of the GAA FET.

[0054] refer to Fig.18In the STD array 200, the dielectric fins 260 and 262 are generally oriented longitudinally along the Y-axis (i.e., substantially parallel to the longitudinal direction of the p-type fins 206 and the n-type fins 208) and are spaced apart from each other along the X-axis. In the present embodiment, the dielectric fins 260 and 262 extend through at least two adjacent STD cells (e.g., STD cells 201A and 201C or STD cells 201B and 201D) along the Y-axis. Along the X-axis, each dielectric fin 260 is disposed between two n-type fins 208, and each dielectric fin 262 is disposed between two p-type fins 206. In other words, the dielectric fins 260 and 262 are intermixed with the n-type fins 206 and the p-type fins 208 along the X-axis. In the depicted embodiment, the dielectric fins 260 are disposed at the cell boundaries, and the dielectric fins 262 are disposed within the cell boundaries. To further describe the embodiment, each STD cell 201A-201D includes one dielectric fin 262 and shares each dielectric fin 260 with adjacent STD cells 201A-201D. Of course, the embodiment is not limited to this configuration and may include a greater or lesser number of dielectric fins according to various design requirements.

[0055] refer to Fig.19 , which describes Fig.18In a cross-sectional view of the STD array 200 taken along line AA' in FIG. 1 , each dielectric fin 260 may be defined as a width D4, and each dielectric fin 262 may be defined as a width D5. In some embodiments, D4 and D5 are substantially the same in size (i.e., having a difference within about ±5%). In some embodiments, D4 and D5 differ in size by about >5%. In one such instance, D4 ​​may be greater than D5. In some embodiments, similar to the above discussion of widths D1, D2, and D3 in the SRAM cell 101, widths D4 and D5 are adjusted to accommodate the growth of S / D components (e.g., n-type S / D components 214N and p-type S / D components 214P) located on each side of the dielectric fins 260 and 262. For example, the dielectric fins 260 and 262 may allow the S / D components to maximize their growth without substantially increasing the overall size of the STD cells 201A-201D and / or causing short circuit issues for the various GAA devices located within the cells. In some embodiments, D4 is at least about 10% greater than D1, i.e., the dielectric fin 260 located at the cell boundary of the STD cells 201A-201D is wider than the dielectric fin 160 located at the cell boundary of the SRAM cell 101. In some examples, the ratio of D4 to D1 is about 1.1 to about 10. In some embodiments, the smaller of D4 and D5 is at least about 10% greater than the largest of D1-D3, i.e., the dielectric fins 260 and 262 are generally wider than the dielectric fins 160-164. In some examples, D4 and D5 can each be about 6 nm to about 60 nm; of course, other suitable sizes can also be applicable as long as the dielectric fins 260 and 262 ensure appropriate performance of the STD cells 201A-201D.

[0056] refer to Fig. 20 , which describes Fig.18 2. In the cross-sectional view of the STD array 200 taken along line BB', the S / D contacts 220A-220E (eg, Fig. 20 20A and 20E) can physically contact the top surface of one or both of the dielectric fins 260 and 262 disposed between two adjacent S / D components. In some embodiments, similar to the dielectric fins 160-164 discussed above, the dielectric fins 260 and 262 are configured to prevent unintentional bridging between adjacent S / D components, thereby eliminating electrical shorts in the GAA FET. In addition, the dielectric fins 260 and 262 can expand the landing area of ​​the S / D contacts 220A-220E above the n-type S / D component 214N and the p-type S / D component 214P, thereby improving the performance of the GAA FET.

[0057] In some embodiments of the present invention, alternatively or in addition to configuring the channel layer to have different widths as discussed above, the n-type S / D component (e.g., 114N or 214N) and the p-type S / D component (e.g., 114P or 214P) may also be fabricated into different configurations to improve the performance of the GAA FETs in the SRAM array 100 or the STD array 200. Fig.21 , which describes something like Figure 5 In the cross-sectional view of the SRAM array 100 (through the S / D region), the depth H1 of the n-type S / D component 114N may be greater than the depth H2 of the p-type S / D component 114P, where H1 and H2 are measured from the top surface of the isolation structure 14. Fig. 22 , which describes something like Figure 6 1 (i.e., through the n-type fin 108), H4 defines the height of the portion of the p-type S / D feature 114P that interfaces with the channel region (i.e., the stack of channel layers 107) of each GAAPFET (e.g., PU-1, PU-2, IS-1, or IS-2) during device operation. Similarly, referring to Fig.23 , which describes the SRAM array 100 along Figure 3 DD' in FIG. 1 (i.e., through the p-type fin 106), H3 defines the height of the portion of the n-type S / D feature 114N that interfaces with the channel region (i.e., the stack of channel layers 105) of each GAA NFET (e.g., PD-1, PD-2, PG-1, or PG-2) during device operation. Thus, as provided herein, the current output (e.g., I on _PU) can be smaller than the current output of a GAA NFET (e.g., I on _PG), thereby increasing I on _PG and I on _PU ratio, which may be desirable to increase the processing speed of the SRAM cell 101 as discussed above.

[0058] Fig.24 A process flow of a method 400 for forming a device 200, an exemplary IC structure 10, or portions thereof, such as in accordance with some embodiments of the present invention, is shown. Figures 2A to 23The SRAM array 100 and / or STD array 200 described herein. The method 400 is merely an example and is not intended to limit the present invention, other than what is expressly recited in the claims. Additional operations may be performed before, during, and after the method 400, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the method. After completing the various operations of the method 400, a plurality of channel layers are formed above each doped region, stacked vertically, and surrounded by gate stacks to form individual GAA FETs.

[0059] In operation 402, method 400 provides a workpiece, such as IC structure 10, which includes substrate 12 and various doped regions (e.g., n-wells 110 and 210 and p-wells 111 and 211) formed in or above substrate 12. In the present embodiment, substrate 12 includes silicon. Alternatively or additionally, substrate 12 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, substrate 12 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured by isolation by implantation of oxygen (SIMOX), wafer bonding, other suitable methods, or a combination thereof.

[0060] Each n-well may be doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. Each p-well may be doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, substrate 12 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Individual doped regions may be formed directly above and / or in substrate 12, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Each of the individual doped regions may be formed by implementing an ion implantation process, a diffusion process, other suitable doping processes, or a combination thereof.

[0061] In operation 404, method 400 forms a multilayer stack of semiconductor materials (hereinafter referred to as "multilayer stack") above substrate 12. In the present embodiment, in subsequent operations of method 400, channel layers 105, 107, 207, and 209 are formed by the multilayer stack. In some embodiments, the multilayer stack includes alternating layers of a first semiconductor and a second semiconductor different from the first semiconductor. In the present embodiment, the first semiconductor layer is a Si-containing layer, and the second semiconductor layer is a SiGe-containing layer.

[0062] In the present embodiment, the multilayer stack includes alternating layers of epitaxial semiconductor material (e.g., alternating layers of epitaxially grown Si and epitaxially grown SiGe) grown in a series of epitaxial processes. The epitaxial process may include CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the underlying substrate. In some instances, the layers of the multilayer stack may be provided in the form of nanosheets, nanowires, or nanorods. Subsequent processing may remove the second semiconductor layer (e.g., a layer containing SiGe), leaving the first semiconductor layer (e.g., a layer containing Si) in a suspended structure. This process, which will be discussed in detail below, may be referred to as a "wire release process" or a "sheet formation process," depending on the configuration of the layers located in the multilayer stack. In the present embodiment, the remaining stack of semiconductor layers including silicon becomes channel layers, such as the channel layers 105 , 107 , 207 , and 209 , configured to form a GAA NFET or a GAA PFET in the SRAM array 100 or the STD array 200 .

[0063] In operation 406, method 400 forms semiconductor fins (optionally referred to as fin active areas) in the multilayer stack, such as p-type fins 106 and n-type fins 108 of SRAM cell 101 and p-type fins 206 and n-type fins 208 of STD cell 201 (e.g., STD cells 201A-201D), so that the semiconductor fins of the present embodiment include alternating layers of Si and SiGe as discussed above with respect to the multilayer stack. In some embodiments, IC structure 10 includes semiconductor fins (not described herein) having a single semiconductor material rather than alternating layers of different semiconductor materials. The semiconductor fins can be manufactured using suitable processes including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is less than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the semiconductor fins may then be patterned using the remaining spacers or mandrels by etching the multilayer stack having alternating layers of epitaxially grown Si and SiGe as discussed above. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The resulting semiconductor fins may be doped with various dopants depending on the design requirements.

[0064] In the present embodiment, the various semiconductor fins within the SRAM cell 101 and the STD cell 201 are formed to different widths as discussed above. For the SRAM cell 101, for example, the p-type fin 106 is formed to have a width W1, and the n-type fin 108 is formed to have a width W2, which may be at least about 10% less than W1. For the STD cell 201, for example, the p-type fin 206 is formed to have a width W3, and the n-type fin 208 is formed to have a width W4, which may be greater than or substantially the same as W3.

[0065] In operation 408, method 400 forms an isolation structure 14 to isolate various components formed above substrate 12. Isolation structure 14 may include STI, field oxide, local oxidation of silicon (LOCOS), other suitable components (including silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof). Isolation structure 14 may be formed by any suitable method. In some embodiments, during the formation of semiconductor fins as discussed above, isolation structure 14 is formed by etching trenches in a multilayer stack to expose portions of substrate 12. The trenches may then be filled with a dielectric material, followed by a chemical mechanical planarization (CMP) process and / or an etch-back process. In some embodiments, isolation structure 14 is formed by depositing a dielectric material over the sidewalls of the semiconductor fins without completely filling the trenches located between the semiconductor fins. In other words, isolation structure 14 is formed as a fin sidewall spacer. Isolation structure 14 may include, for example, a multilayer structure having one or more thermal oxide liner layers.

[0066] As discussed above, some embodiments of the IC structure 10 may include dielectric fins disposed between semiconductor fins, such as dielectric fins 160-164 located in the SRAM cell 101 and dielectric fins 260 and 262 located in the STD cell 201, and the dielectric fins may each include a single dielectric material or multiple dielectric materials, such as silicon oxide, silicon oxycarbide, silicon oxynitride, carbon-containing silicon oxide, nitrogen-containing silicon oxide, dielectric-based nitrides, dielectric-based metal oxides, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, yttrium oxide, other suitable dielectric materials, or combinations thereof.

[0067] The dielectric fins may be formed by any suitable method. For example, the dielectric fins may be formed before forming the isolation structure 14, which is deposited as a spacer layer located on the sidewalls of the semiconductor fins as discussed above. Before the spacer layer is recessed below the semiconductor fins to form the isolation structure 14, a groove is formed in the spacer layer by a patterning and etching process. Thereafter, a dielectric material is deposited in the groove using CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), flowable CVD (FCVD) and / or other suitable methods to form the dielectric fins. The spacer layer is then planarized (e.g., by one or more CMP processes) to expose the top surface of each of the semiconductor fins and the dielectric fins. Thereafter, the spacer layer is recessed or etched back (e.g., by a chemical etching process) to be lower than the top surface of each of the semiconductor fins and the dielectric fins, thereby forming the isolation structure 16.

[0068] In operation 410, method 400 forms one or more dummy gate stacks (not depicted) over semiconductor fins (and dielectric fins, if present). The dummy gate stacks may include, for example, an interface layer (including, for example, silicon oxide) and a dummy gate electrode layer (including, for example, polysilicon) formed over the interface layer. After forming other components (e.g., S / D features 114N, 114P, 214N, and 214P), portions of each dummy gate stack (e.g., the dummy gate electrode layer) are removed to form gate trenches, wherein at least a high-k gate dielectric layer (e.g., high-k gate dielectric layer 132 or 232) and a metal gate electrode (e.g., metal gate electrodes 134 and 234) are subsequently formed to complete the fabrication of each of gate stacks 130A-130D and gate stacks 230A-230C. The various material layers of the dummy gate stack may be first deposited as a blanket layer over the semiconductor fins and then patterned, followed by one or more etching processes, to form the dummy gate stack in the desired configuration in the SRAM cell 101 and the STD cell 201 .

[0069] In operation 410, top gate spacers of the GAA FET, such as top spacers 116A and 216A, may be formed on the sidewalls of the dummy gate stack. The top spacers may include silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, silicon carbon oxynitride, low-k dielectric materials, other materials, or combinations thereof. The top spacers may be formed by first depositing a spacer layer over the dummy gate stack and then performing an anisotropic etching process on the spacer layer, thereby leaving the top spacers on the sidewalls of the dummy gate stack.

[0070] In operation 412, method 400 forms various S / D components, such as n-type S / D components 114N and 214N and p-type S / D components 114P and 214P, in the S / D region of each semiconductor fin. The n-type S / D components may include epitaxially grown semiconductor materials, such as epitaxially grown Si or SiC configured to form a GAAN NFET, and may additionally include one or more n-type dopants, such as phosphorus or arsenic. The p-type S / D epitaxial components may include epitaxially grown semiconductor materials, such as epitaxially grown SiGe configured to form a GAAPFET, and may additionally include one or more p-type dopants, such as boron or indium. Each S / D component may include one or more epitaxially grown semiconductor layers. The n-type S / D components may be grown in p-type fins (such as p-type fins 106 and 206), while the p-type S / D components may be grown in n-type fins (such as n-type fins 108 and 208). Forming the S / D features may include removing portions of each semiconductor fin in its S / D region to form an S / D recess, and then performing a suitable epitaxial process (discussed in detail above with reference to the multilayer stack) to form the S / D features. In some embodiments, an annealing process is performed to activate dopants located in the S / D features and / or other S / D regions (such as the HDD region and / or the LDD region).

[0071] In some embodiments, before forming the S / D features in the S / D recesses, portions of the non-channel layers of the multilayer stack exposed in the S / D recesses (e.g., SiGe layers) are selectively removed to form openings, and then a dielectric layer is deposited in the openings to form internal spacers, such as internal spacers 116B and 216B. The internal spacers may include silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride carbon, low-k dielectric materials, other materials, or combinations thereof. The internal spacers may include a single-layer structure or a multilayer structure. The composition of the internal spacers may be similar to or different from the composition of the top spacers, which have been discussed in detail above.

[0072] In operation 414, method 400 removes the dummy gate stack to form a plurality of gate trenches. Forming the gate trenches may include forming an ILD layer (eg, Figure 5 , Fig.10 , Fig.17 , Fig. 20 and Fig.21The ILD layer 18 described in ). The ILD layer may include any suitable dielectric material that is generally different from the composition of the ESL. For example, the ILD layer may include a low-k dielectric material, silicon oxide, doped silicate glass, other suitable materials, or combinations thereof, and may be formed by any suitable method, such as spin-on glass or flowable CVD. One or more CMP processes may be used to planarize the top surface of the ILD layer.

[0073] In operation 416, method 400 implements one or more etching processes, such as a dry etching process and / or a wet etching process, to remove the non-channel layer (e.g., SiGe layer) from the multilayer stack, leaving the channel layer (e.g., Si layer) in the suspended structure. In other words, after removing the non-channel layer, a plurality of openings are inserted into the stack of the channel layer. In this embodiment, the one or more etching processes selectively remove the non-channel layer without removing or substantially removing the channel layer. In one such example, the one or more etching processes include applying a fluorine-containing etching gas.

[0074] Compared to FinFETs whose channel regions include a single-layer fin structure, forming the channel regions of GAA NFETs and GAA PFETs to different widths presents many challenges. For example, forming suspended stacks of channel layers (such as channel layers 105, 107, 207, and 209) to different widths may result in uneven etching of the multilayer stacks during the sheet release process. In some cases, non-channel layers located in narrower stacks (e.g., in n-type fins 108 or p-type fins 206) may be more easily removed than non-channel layers located in wider stacks (e.g., p-type fins 106 or n-type fins 208). As a result, in order to remove the non-channel layers of the wider stacks, the channel layers of the narrower stacks may be unintentionally etched. Therefore, the ratio of W1 to W2 and the ratio of W4 to W3 discussed in detail above may be adjusted to ensure that unintentional damage to the channel layers of the narrower stacks is maintained at an acceptable level to maintain proper performance of the IC structure 10. For example, while a ratio of W1 to W2 greater than about 4 may be suitable for some embodiments of the present invention, adjusting the ratio to between about 1.1 and about 4 may ensure that the degree of unintentional etching of the channel layer 107 is controlled within conventional IC design requirements. Similarly, the ratio of W4 to W3 may be adjusted to between about 1.1 and about 2 to ensure that the degree of unintentional etching of the channel layer 207 is maintained at an acceptable level. Alternatively or additionally, unintentional damage to the channel layer may be mitigated by adjusting the etching conditions of the sheet release process (e.g., duration of the etching process, choice of etchant, pressure of the etchant, etc.).

[0075] In operation 418, method 400 forms a gate stack (e.g., gate stacks 130A-130D, gate stacks 230A-230C, and isolation gate structure 240B) in the gate trenches and in the openings formed between the channel layers. In the present embodiment, each gate stack includes at least a high-k gate dielectric layer (e.g., high-k gate dielectric layers 132 and 232) and a metal gate electrode (e.g., metal gate electrodes 134 and 234). In the present embodiment, a portion of the high-k gate dielectric layer 132 wraps around each channel layer, so that the gate stack is bonded to multiple channel layers located in each GAA FET. The high-k gate dielectric layer may include silicon oxide, silicon oxynitride, aluminum silicon oxide, high-k dielectric materials (such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), other suitable dielectric materials, or combinations thereof. Although not described, each metal gate electrode may also include a bulk conductive layer disposed above at least one work function metal layer. The bulk conductive layer may include Cu, W, Ru, Co, Al, other suitable metals, or combinations thereof. In some instances, each gate stack may include one or more work function metal layers of the same conductivity type or different conductivity types. Examples of work function metal layers may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. Each work function metal layer may be deposited first and then patterned to meet different requirements for threshold voltages in different GAA FETs. Additional material layers may also be included in each gate stack, such as an interface layer, a barrier layer, a cap layer, other suitable material layers, or combinations thereof. Each layer of the gate stack may be deposited by any suitable method (such as chemical oxidation, thermal oxidation, ALD, CVD, PVD, plating, other suitable methods, or combinations thereof).

[0076] In some embodiments, the dielectric gate structures 240A (see FIG. Figure 8 and Fig.18) includes a dielectric gate structure that is not configured to provide any functional device. The dielectric gate structure 240A may include a single layer structure or a multilayer structure having one or more dielectric materials (such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric materials, other suitable dielectric materials, or combinations thereof). In the present embodiment, in operation 414, the dielectric gate structure is formed by removing portions of the dummy gate stack to form a gate trench, and in operation 418, one or more dielectric materials discussed above are subsequently deposited in the gate trench before or after forming the gate stack (e.g., gate stacks 130A-130D and gate stacks 230A-230C).

[0077] In some embodiments, dielectric fins (e.g., dielectric fins 160-164, 260, and 262) can facilitate the fabrication of individual conductive (or functional) gate stacks. For example, because patterning the work function metal layer as discussed above can include isotropically etching portions of the work function metal layer disposed between stacks of channel layers, work function metal layers disposed between stacks of adjacent channel layers can be unintentionally etched. The presence of dielectric lines between individual semiconductor fins (i.e., stacks of channel layers) can therefore serve as a "blocking layer" for preventing unintentional etching of one or more work function metal layers during such a patterning process.

[0078] In operation 420, method 400 forms S / D contacts (e.g., S / D contacts 120A-120D and 220A-220E) to interconnect various S / D components with subsequently formed MLI structures. In the present embodiment, the S / D contacts are disposed in an ILD layer (such as ILD layer 20). The S / D contacts may include any suitable conductive material, such as Cu, W, Ru, Co, Al, other suitable metals, or combinations thereof. Each S / D contact may further include a barrier layer, which includes any suitable material, such as Ti, Ta, TiN, and / or TaN. Forming the S / D contacts may include implementing a photolithography process and / or an etching process to form an opening (groove) in the ILD layer, such as a contact opening. Thereafter, the opening is filled with one or more conductive materials by PVD, CVD, ALD, plating, other suitable deposition processes, or combinations thereof. Thereafter, any excess conductive material may be removed by a CMP process, thereby flattening the top surface of the ILD layer and the top surface of the S / D contacts.

[0079] In some embodiments, before forming the S / D contacts, a silicide layer (e.g., silicide layers 123 and 223) is formed over the S / D components located in the contact openings. The silicide layer may be formed by first depositing a metal layer on the S / D components, performing an annealing process to allow the metal layer to react with the material of the S / D components, and then removing the unreacted portion of the metal layer to leave the silicide layer. The silicide layer may include nickel silicide, titanium silicide, cobalt silicide, other suitable silicides, or combinations thereof.

[0080] In operation 422, method 400 implements additional processing steps, including, for example, forming an MLI structure above IC structure 10. As provided herein, the MLI structure may include a plurality of conductive components configured to interconnect various devices (e.g., GAA FETs, other transistors, resistors, capacitors, and / or inductors, etc.) and / or components (e.g., gate stacks, S / D components, etc.) of SRAM cell 101 and STD cell 201 with additional devices and components to ensure proper performance of IC structure 10. The MLI structure may include various conductive layers and dielectric layers (e.g., ILD layer 20 and ESL 133) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components, such as vertical interconnect structures (e.g., vias 126A-126C, 226A, and 226B) and / or horizontal interconnect structures (e.g., wires). Each horizontal interconnect component disposed in a dielectric layer may be referred to as a "metal layer", and two different metal layers may be electrically coupled by one or more vertical interconnect structures. In some embodiments, an ESL is formed between metal layers to accommodate the manufacture of various interconnect structures. Each interconnect structure may include Cu, W, Ru, Co, Al, other suitable metals, or combinations thereof, and may further include a barrier layer including Ti, Ta, TiN, and / or TaN. Each dielectric layer may include a low-k dielectric material, silicon oxide, other suitable dielectric materials, or combinations thereof, and may be formed by spin-on glass, FCVD, other suitable methods, or combinations thereof. The method of forming each interconnect structure may be similar to the method of forming the S / D contacts as discussed above.

[0081] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. For example, the present embodiment provides a memory cell array (such as an SRAM cell) and a standard logic cell array or STD cell array in the same IC structure, wherein the memory and STD cells each include at least one GAA NFET and at least one GAA PFET, and each of the GAA FETs includes a gate structure (e.g., a high-k metal gate structure) configured to engage with a stack of channel layers. In some embodiments of the SRAM cell, the width W1 of the stack of channel layers in the GAA NFET is greater than the width W2 of the stack of channel layers in the GAA PFET. In some embodiments of the STD cell, the width W3 of the stack of channel layers in the GAA NFET is less than the width W4 of the stack of channel layers in the GAA PFET. In some embodiments of the STD cell, W3 is substantially the same as W4. In some embodiments, the ratio of W1 to W2 and the ratio of W4 to W3 are adjusted to ensure that when forming the channel region of each GAA FET, the channel layer with a narrower width is not etched or substantially not etched. Embodiments of the present invention ensure that the performance of SRAM cells and STD cells can be independently optimized for their respective applications, thereby improving the overall performance of the IC structure.

[0082] In one aspect, the present embodiment provides an integrated circuit (IC) structure, including: a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region, which are longitudinally arranged along a first direction and spaced apart from each other in a second direction perpendicular to the first direction. In some embodiments, each of the first p-type active region and the second p-type active region includes a first set of vertically stacked channel layers having a width W1 measured along the second direction, and each of the first n-type active region and the second n-type active region includes a second set of vertically stacked channel layers having a width W2 measured along the second direction, wherein the width W2 is less than the width W1, and in some embodiments, each of the first p-type active region, the first n-type active region, the second n-type active region, and the second p-type active region extends across a boundary of the memory cell along the first direction.

[0083] On the other hand, the present embodiment provides an IC structure, including: a logic standard cell having an n-type active region and a p-type active region, longitudinally oriented along a first direction and spaced apart from each other along a second direction substantially perpendicular to the first direction. In some embodiments, the n-type active region includes a first set of vertically stacked channel layers having a width W1 measured along the second direction, and the p-type active region includes a second set of vertically stacked channel layers having a width W2 measured along the second direction, wherein the width W1 is greater than or equal to the width W2. The IC also includes: a metal gate structure, longitudinally oriented along the second direction, and configured to be bonded to the first plurality of vertically stacked channel layers to form a p-type device, and bonded to the second plurality of vertically stacked channel layers to form an n-type device.

[0084] On the other hand, the present embodiment provides an IC structure, including: a memory cell having a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin, arranged longitudinally along a first direction, and spaced apart from each other along a second direction perpendicular to the first direction. In some embodiments, each of the first p-type fin and the second p-type fin includes a first set of vertically stacked channel layers having a width W1 measured along the second direction, and each of the first n-type fin and the second n-type fin includes a second set of vertically stacked channel layers having a width W2 measured along the second direction, wherein the width W2 is less than the width W1. In a further embodiment, each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin continuously crosses the boundary of the memory cell. The IC structure also includes: a standard logic cell having a third n-type fin and a third p-type fin, oriented longitudinally along the first direction and spaced apart from each other along the second direction. In some embodiments, the third n-type fin includes a third set of vertically stacked channel layers having a width W3 measured along the second direction, and the third p-type fin includes a fourth set of vertically stacked channel layers having a width W4 measured along the second direction, wherein the width W3 is greater than or equal to the width W4. Further, the IC structure includes: a metal gate structure disposed over the first n-type fin, the second n-type fin, and the third n-type fin to form a p-type device, and disposed over the first p-type active region, the second p-type active region, and the third p-type active region to form an n-type device.

[0085] Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: a memory cell, comprising: a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region, which are longitudinally arranged along a first direction and spaced apart from each other in the above order along a second direction substantially perpendicular to the first direction, wherein each of the first p-type active region and the second p-type active region comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, wherein each of the first n-type active region and the second n-type active region comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type active region, the first n-type active region, the second n-type active region, and the second p-type active region extends across a boundary of the memory cell along the first direction.

[0086] In some embodiments, the ratio of the width W1 to the width W2 is 1.1 to 4. In some embodiments, the memory cell further comprises: a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack, oriented longitudinally along the second direction, the first gate stack and the second gate stack being spaced apart from the third gate stack and the fourth gate stack along the first direction, wherein the first gate stack is disposed over the first p-type active region to provide a first n-type device, wherein the second gate stack is disposed over the first n-type active region, the second n-type active region, and the second p-type active region to provide a first p-type device, a second p-type device, and a second n-type device, respectively, wherein the third gate stack is disposed over the first p-type active region, the first n-type active region, and the second n-type active region to provide a third n-type device, a third p-type device, and a fourth p-type device, respectively, and wherein the fourth gate stack is disposed over the second p-type active region to provide a fourth n-type device. In some embodiments, each of the first n-type device and the fourth n-type device is a transmission gate (PG) device, wherein each of the first p-type device and the fourth p-type device is an isolation (IS) device, wherein each of the second p-type device and the third p-type device is a pull-up (PU) device, and wherein each of the second n-type device and the third n-type device is a pull-down (PD) device. In some embodiments, each isolation device includes a drain terminal, a source terminal, and a gate terminal electrically coupled to the source terminal or to the drain terminal. In some embodiments, the memory cell is a first memory cell, and the integrated circuit structure further includes: a second memory cell, which is disposed adjacent to the first memory cell along the first direction, so that the first p-type active region and the second p-type active region and the first n-type active region and the second n-type active region extend across the first memory cell and the second memory cell along the first direction. In some embodiments, the memory cell further includes a first dielectric structure, a second dielectric structure, a third dielectric structure, a fourth dielectric structure, and a fifth dielectric structure, which are longitudinally arranged along the first direction and spaced apart from each other in the above order along the second direction, wherein each of the first dielectric structure and the fifth dielectric structure is arranged on a boundary of the memory cell, wherein the second dielectric structure is arranged between the first p-type active region and the first n-type active region, wherein the third dielectric structure is arranged between the first n-type active region and the second n-type active region, and wherein the fourth dielectric structure is arranged between the second n-type active region and the second p-type active region.In some embodiments, each of the first dielectric structure and the fifth dielectric structure is defined as a width D1 along the second direction, wherein each of the second dielectric structure and the fourth dielectric structure is defined as a width D2 along the second direction, and wherein the third dielectric structure is defined as a width D3 along the second direction, and the width D1, width D2, and width D3 are different. In some embodiments, the width D1 is greater than the width D2, and wherein the width D2 is greater than the width D3.

[0087] Still other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a logic standard cell, comprising: an n-type active region and a p-type active region, longitudinally oriented along a first direction and spaced apart from each other along a second direction substantially perpendicular to the first direction, wherein the n-type active region comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, and wherein the p-type active region comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W1 being greater than or equal to the width W2; and a metal gate structure, longitudinally oriented along the second direction, wherein the metal gate structure is bonded to the first plurality of vertically stacked channel layers to form a p-type device, and is bonded to the second plurality of vertically stacked channel layers to form an n-type device.

[0088] In some embodiments, the ratio of the width W1 to the width W2 is 1.1 to 2. In some embodiments, the logic standard cell is a first logic standard cell, the n-type active region is a first n-type active region, the p-type active region is a first p-type active region, and the integrated circuit structure further comprises: a second logic standard cell disposed adjacent to the first logic standard cell along the first direction, wherein the second standard logic cell comprises a second n-type active region and a second p-type active region oriented along the first direction, and wherein a boundary between the first logic standard cell and the second logic standard cell is defined by a dielectric gate structure oriented longitudinally along the second direction, such that the dielectric gate structure physically separates the first n-type active region and the first p-type active region from the second n-type active region and the second p-type active region, respectively. In some embodiments, the first n-type active region and the second n-type active region have different lengths measured along the first direction, and wherein the first p-type active region and the second p-type active region have different lengths measured along the first direction. In some embodiments, the logic standard cell is a first logic standard cell, and the integrated circuit structure further comprises: a second logic standard cell disposed adjacent to the first logic standard cell along the first direction, wherein the n-type active region and the p-type active region extend across a boundary between the first logic standard cell and the second logic standard cell along the first direction. In some embodiments, the metal gate structure is a first metal gate structure, the p-type device is a first p-type device, and the n-type device is a first n-type device, wherein the boundary is defined by a second metal gate structure, and wherein the second metal gate structure forms a second p-type isolation device having the n-type active region and a second n-type isolation device having the p-type active region. In some embodiments, the logic standard cell further includes: a first dielectric structure and a second dielectric structure, the first dielectric structure being disposed at a first boundary of the logic standard cell, the second dielectric structure being disposed at a second boundary of the logic standard cell and being longitudinally oriented along the first direction, wherein each of the first dielectric structure and the second dielectric structure has a width D4 measured along the second direction, and a third dielectric structure being disposed between the n-type active region and the p-type active region and being longitudinally oriented along the first direction, wherein the third dielectric structure has a width D5 measured along the second direction, and the width D5 is less than or equal to the width D4.In some embodiments, the n-type active region is a first n-type active region, and the p-type active region is a first p-type active region, the integrated circuit structure also includes a memory cell, including: a second p-type active region, a second n-type active region, a third n-type active region and a third p-type active region, which are longitudinally arranged along the first direction and spaced apart from each other in the above order along the second direction, wherein each of the second p-type active region and the third p-type active region includes a third plurality of vertically stacked channel layers, and the third plurality of vertically stacked channel layers have a width W3 measured along the second direction, wherein each of the second n-type active region and the third n-type active region includes a fourth plurality of vertically stacked channel layers, and the fourth plurality of vertically stacked channel layers have a width W4 measured along the second direction, and the width W4 is less than the width W3, and wherein each of the second p-type active region, the second n-type active region, the third n-type active region and the third p-type active region extends across the boundary of the memory cell along the first direction.

[0089] Some further embodiments of the present application provide an integrated circuit (IC) structure, comprising: a memory cell, comprising: a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin, which are longitudinally arranged along a first direction and spaced apart from each other in the above order along a second direction substantially perpendicular to the first direction, wherein each of the first p-type fin and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, wherein each of the first n-type fin and the second n-type fin comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first ... second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W2 measured along the each continuously straddling a boundary of the memory cell; a standard logic cell comprising a third n-type fin and a third p-type fin, longitudinally oriented along the first direction and spaced apart from each other along the second direction, wherein the third n-type fin comprises a third plurality of vertically stacked channel layers, the third plurality of vertically stacked channel layers having a width W3 measured along the second direction, and wherein the third p-type fin comprises a fourth plurality of vertically stacked channel layers, the fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W3 being greater than or equal to the width W4; and a plurality of metal gate structures disposed over the first n-type fin, the second n-type fin, and the third n-type fin to form a p-type device, and disposed over the first p-type active region, the second p-type active region, and the third p-type active region to form an n-type device.

[0090] In some embodiments, the standard logic cell further comprises an isolation gate structure disposed at a boundary of the standard logic cell, the isolation gate structure being configured to form a p-type isolation device having the third n-type fin and an n-type isolation device having the third p-type fin. In some embodiments, each of the third n-type fin and the third p-type fin is interrupted by a dielectric gate structure at a boundary of the standard logic cell.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit structure, comprising: A memory cell comprising: a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region, arranged longitudinally along a first direction and spaced apart from each other in the above order along a second direction substantially perpendicular to the first direction, wherein each of the first p-type active region and the second p-type active region comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, wherein each of the first n-type active region and the second n-type active region comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and Each of the first p-type active region, the first n-type active region, the second n-type active region, and the second p-type active region extends across a boundary of the memory cell along the first direction.

2. The integrated circuit structure according to claim 1, wherein: A ratio of the width W1 to the width W2 is 1.1 to 4.

3. The integrated circuit structure according to claim 1, wherein: The storage unit also includes: a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack, which are longitudinally oriented along the second direction, the first gate stack and the second gate stack being spaced apart from the third gate stack and the fourth gate stack along the first direction, wherein the first gate stack is disposed above the first p-type active region to provide a first n-type device, wherein the second gate stack is disposed above the first n-type active region, the second n-type active region, and the second p-type active region to provide a first p-type device, a second p-type device, and a second n-type device, respectively; wherein the third gate stack is disposed above the first p-type active region, the first n-type active region, and the second n-type active region to provide a third n-type device, a third p-type device, and a fourth p-type device, respectively; and The fourth gate stack is disposed above the second p-type active region to provide a fourth n-type device.

4. The integrated circuit structure according to claim 3, wherein: Each of the first n-type device and the fourth n-type device is a pass-gate device, wherein each of the first p-type device and the fourth p-type device is an isolation device, wherein each of the second p-type device and the third p-type device is a pull-up device, and wherein each of the second n-type device and the third n-type device is a pull-down device.

5. The integrated circuit structure according to claim 4, wherein: Each isolation device includes a drain terminal, a source terminal, and a gate terminal electrically coupled to the source terminal or to the drain terminal.

6. The integrated circuit structure according to claim 1, wherein: The memory cell is a first memory cell, and the integrated circuit structure further includes: a second memory cell, which is arranged adjacent to the first memory cell along the first direction, so that the first p-type active region and the second p-type active region and the first n-type active region and the second n-type active region extend across the first memory cell and the second memory cell along the first direction.

7. The integrated circuit structure according to claim 1, wherein: The memory cell further includes a first dielectric structure, a second dielectric structure, a third dielectric structure, a fourth dielectric structure, and a fifth dielectric structure, which are longitudinally arranged along the first direction and spaced apart from each other in the above order along the second direction, Wherein, each of the first dielectric structure and the fifth dielectric structure is arranged on a boundary of the memory cell, The second dielectric structure is disposed between the first p-type active region and the first n-type active region. The third dielectric structure is disposed between the first n-type active region and the second n-type active region, and The fourth dielectric structure is disposed between the second n-type active region and the second p-type active region.

8. The integrated circuit structure according to claim 7, wherein: Each of the first dielectric structure and the fifth dielectric structure is defined as a width D1 along the second direction, wherein the second dielectric structure and the fourth dielectric structure are each defined as a width D2 along the second direction, and wherein the third dielectric structure is defined as a width D3 along the second direction, and the width D1, width D2 and width D3 are different.

9. The integrated circuit structure according to claim 8, wherein: The width D1 is greater than the width D2, and wherein the width D2 is greater than the width D3.

10. An integrated circuit structure comprising: A logic standard cell, comprising: an n-type active region disposed in an n-well and a p-type active region disposed in a p-well, longitudinally oriented along a first direction and spaced apart from each other along a second direction substantially perpendicular to the first direction, wherein the n-type active region comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, and wherein the p-type active region comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W1 being greater than the width W2; and A metal gate structure is longitudinally oriented along the second direction, wherein the metal gate structure is bonded to the first plurality of vertically stacked channel layers to form a p-type device and is bonded to the second plurality of vertically stacked channel layers to form an n-type device.

11. The integrated circuit structure according to claim 10, wherein: A ratio of the width W1 to the width W2 is 1.1 to 2.

12. The integrated circuit structure according to claim 10, wherein: The logic standard cell is a first logic standard cell, the n-type active region is a first n-type active region, and the p-type active region is a first p-type active region. The integrated circuit structure further includes: a second logic standard cell, which is arranged adjacent to the first logic standard cell along the first direction. The second logic standard cell includes a second n-type active region and a second p-type active region oriented along the first direction, and The boundary between the first logic standard cell and the second logic standard cell is defined by a dielectric gate structure longitudinally oriented along the second direction, so that the dielectric gate structure physically separates the first n-type active region and the first p-type active region from the second n-type active region and the second p-type active region, respectively.

13. The integrated circuit structure according to claim 12, wherein: The first n-type active region and the second n-type active region have different lengths measured along the first direction, and wherein the first p-type active region and the second p-type active region have different lengths measured along the first direction.

14. The integrated circuit structure according to claim 10, wherein: The logic standard cell is a first logic standard cell, and the integrated circuit structure further includes: a second logic standard cell, which is arranged adjacent to the first logic standard cell along the first direction, wherein the n-type active region and the p-type active region extend along the first direction across a boundary between the first logic standard cell and the second logic standard cell.

15. The integrated circuit structure according to claim 14, wherein: The metal gate structure is a first metal gate structure, the p-type device is a first p-type device, and the n-type device is a first n-type device, wherein the boundary is defined by a second metal gate structure, and wherein the second metal gate structure forms a second p-type isolation device having the n-type active region and a second n-type isolation device having the p-type active region.

16. The integrated circuit structure according to claim 10, wherein: The logic standard unit also includes: a first dielectric structure and a second dielectric structure, the first dielectric structure being disposed at a first boundary of the logic standard cell, the second dielectric structure being disposed at a second boundary of the logic standard cell and being longitudinally oriented along the first direction, wherein each of the first dielectric structure and the second dielectric structure has a width D4 measured along the second direction, and A third dielectric structure is disposed between the n-type active region and the p-type active region and is longitudinally oriented along the first direction, wherein the third dielectric structure has a width D5 measured along the second direction, and the width D5 is less than or equal to the width D4.

17. The integrated circuit structure according to claim 10, wherein: The n-type active region is a first n-type active region, and the p-type active region is a first p-type active region, and the integrated circuit structure further includes a memory cell, including: a second p-type active region, a second n-type active region, a third n-type active region, and a third p-type active region, which are longitudinally arranged along the first direction and spaced apart from each other in the above order along the second direction, wherein each of the second p-type active region and the third p-type active region comprises a third plurality of vertically stacked channel layers, the third plurality of vertically stacked channel layers having a width W3 measured along the second direction, wherein each of the second n-type active region and the third n-type active region comprises a fourth plurality of vertically stacked channel layers, the fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W4 being smaller than the width W3, and Each of the second p-type active region, the second n-type active region, the third n-type active region, and the third p-type active region extends across a boundary of the memory cell along the first direction.

18. An integrated circuit structure comprising: A memory cell comprising: a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin, which are longitudinally arranged along a first direction and spaced apart from each other in the above order along a second direction substantially perpendicular to the first direction, wherein each of the first p-type fin and the second p-type fin comprises a first plurality of vertically stacked channel layers, the first plurality of vertically stacked channel layers having a width W1 measured along the second direction, wherein each of the first n-type fin and the second n-type fin comprises a second plurality of vertically stacked channel layers, the second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being smaller than the width W1, and wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin continuously crosses a boundary of the memory cell; a standard logic cell, comprising a third n-type fin and a third p-type fin, longitudinally oriented along the first direction and spaced apart from each other along the second direction, wherein the third n-type fin comprises a third plurality of vertically stacked channel layers, the third plurality of vertically stacked channel layers having a width W3 measured along the second direction, and wherein the third p-type fin comprises a fourth plurality of vertically stacked channel layers, the fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W3 being greater than or equal to the width W4; and A plurality of metal gate structures are disposed over the first n-type fin, the second n-type fin, and the third n-type fin to form a p-type device, and disposed over the first p-type fin, the second p-type fin, and the third p-type fin to form an n-type device.

19. The integrated circuit structure according to claim 18, wherein: The standard logic cell further includes an isolation gate structure disposed at a boundary of the standard logic cell, the isolation gate structure being configured to form a p-type isolation device having the third n-type fin and an n-type isolation device having the third p-type fin.

20. The integrated circuit structure of claim 18, wherein: Each of the third n-type fin and the third p-type fin is interrupted by a dielectric gate structure at a boundary of the standard logic cell.

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