Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate; forming a dielectric layer on the substrate; forming a conductive via penetrating through the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the dielectric layer, the protective layer covering the conductive plug; forming an alignment trench in the protective layer and the dielectric layer, the alignment trench being isolated from the conductive plug; after forming the alignment trench, removing the protective layer to expose the top of the conductive plug; after removing the protective layer, forming a magnetic tunnel junction stack structure on the conductive plug. The protective layer formed in the embodiment of the present invention can protect the conductive plug, thereby preventing the conductive plug from being oxidized to form metal oxides, which is beneficial to directly contacting the MTJ stack structure with the conductive plug, correspondingly beneficial to improving the contact performance between the MTJ stack structure and the conductive plug, and the performance of the MRAM device is also improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory. MRAM devices have the high-speed read and write capabilities of Static Random Access Memory (SRAM), the high integration of Dynamic Random Access Memory (DRAM), and can basically be written repeatedly infinitely. MRAM devices are a kind of "fully functional" solid-state memory. Therefore, its application prospects are very promising and are expected to dominate the next-generation memory market.

[0003] In an MRAM device, data is stored by the magnetic state of a storage element. An MRAM cell usually consists of a transistor and a Magnetic Tunnel Junction (MTJ) together to form a storage cell. The MTJ structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. The two electromagnetic layers can maintain two magnetic polarization fields separated by the insulating layer. One of them is a fixed magnetic layer with a fixed polarization direction, and the other is a free-rotating magnetic layer whose polarization direction can be changed by the change of an external field. When the polarization directions of the two electromagnetic layers are parallel, the tunneling current flowing through the MTJ structure has a maximum value, and the resistance of the MTJ structure unit is relatively low. When the polarization directions of the two magnetic layers are anti-parallel, the tunneling current flowing through the MTJ structure has a minimum value, and the resistance of the MTJ structure unit is relatively high. Information is read by measuring the resistance of the MRAM cell, and this is the working principle of the MTJ structure.

[0004] In addition, in order to be compatible with the CMOS integrated circuit manufacturing process, generally speaking, the MTJ is inserted between two metal layers of the CMOS integrated circuit, for example, between the first metal layer and the second metal layer, and the two metal layers are connected by a via interconnect structure. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of MRAM devices.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dielectric layer on the substrate; forming a conductive via penetrating the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the dielectric layer, the protective layer covering the conductive plug; forming an alignment trench in the protective layer and the dielectric layer, the alignment trench being isolated from the conductive plug; after forming the alignment trench, removing the protective layer to expose the top of the conductive plug; after removing the protective layer, forming a magnetic tunnel junction stack structure on the conductive plug.

[0007] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a dielectric layer located on the substrate; a conductive plug penetrating the dielectric layer; a protective layer located on the dielectric layer and covering the conductive plug; an alignment trench located in the dielectric layer and the protective layer and isolated from the conductive plug.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure according to the embodiment of the present invention, before forming the alignment trench, a protective layer is further formed on the conductive plug. Forming the alignment trench generally includes steps of etching the dielectric layer using a mask layer as a mask and then removing the mask layer, and in the semiconductor field, an oxygen-containing gas is usually used to remove the mask layer. The protective layer formed in the embodiment of the present invention can play a role in protecting the conductive plug during the process of removing the mask layer, preventing the problem that the conductive plug is oxidized to form metal oxides due to exposure to the oxygen-containing gas. Thus, after forming a magnetic tunnel junction (MTJ) stack structure on the conductive plug, it is beneficial to make the MTJ stack structure in direct contact with the conductive plug, which is correspondingly beneficial to reducing the contact resistance between the MTJ stack structure and the conductive plug and improving the contact performance between the MTJ stack structure and the conductive plug, and further beneficial to improving the performance of a magnetic random access memory (MRAM) device.

[0010] In an alternative embodiment, after forming the dielectric layer on the substrate, the method for forming the semiconductor structure further includes: forming an etch stop layer on the dielectric layer; during the subsequent process of removing the protective layer, the protective layer and the etch stop layer have a large etch selectivity, and the etch stop layer can define the stop position of the etching during the process of removing the protective layer, which is beneficial to preventing damage to the dielectric layer caused by the process of removing the protective layer, improving the top surface flatness and height consistency of the dielectric layer, and further facilitating the provision of a flat and highly consistent interface for the subsequent formation of the MTJ stack structure; in addition, forming the conductive plug usually includes a step of planarization processing, and the etch stop layer can also define the stop position during the planarization processing step of forming the conductive plug, thereby facilitating the reduction of the difficulty of the planarization processing, improving the top surface flatness and height consistency of the conductive plug, and further providing a good interface for the formation of the magnetic tunnel junction stack structure. Description of the Drawings

[0011] Figures 1 to 7 are schematic diagrams of the structures corresponding to the respective steps in a method for forming a semiconductor structure;

[0012] Figures 8 to 20 are schematic diagrams of the structures corresponding to the respective steps in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Description of the Invention

[0013] Currently, the performance of the formed MRAM devices is not good. The reasons for the poor performance of the MRAM devices are analyzed in combination with a method for forming a semiconductor structure.

[0014] Figures 1 to 7 Illustrate schematic diagrams of the structures corresponding to the respective steps in a method for forming a semiconductor structure.

[0015] Refer to Figure 1 , provide a substrate 1; form a dielectric layer 2 on the substrate 1.

[0016] Refer to Figure 2 , form a conductive via 3 penetrating the dielectric layer 2.

[0017] Refer to Figure 3 , form a conductive plug 4 in the conductive via 3.

[0018] Refer to Figures 4 to 6 , form an alignment trench 5 in the dielectric layer 2, and the alignment trench 5 is isolated from the conductive plug 4.

[0019] Refer to Figure 7 , form a magnetic tunnel junction (MTJ) stack structure 8 on the conductive plug 4.

[0020] The inventors found that the performance of the MTJ stack structure 8 formed by the described forming method is poor. Specifically, the contact performance between the MTJ stack structure 8 and the conductive plug 4 is poor, resulting in a large contact resistance between the MTJ stack structure 8 and the conductive plug 4, reducing the TMR (magnetic flux ratio) of the MTJ stack structure 8, and further affecting the performance of the MRAM device.

[0021] The inventors further studied and found that the reasons for the poor contact performance between the MTJ stack structure 8 and the conductive plug 4 are as follows:

[0022] The step of forming the alignment trench 5 generally includes: as Figure 4 shown, forming a mask layer 6 on the conductive plug 4 and the dielectric layer 2; as Figure 5 shown, using the mask layer 5 as a mask to etch the dielectric layer 2 to form the alignment trench 5; as Figure 6 shown, after forming the alignment trench 5, removing the mask layer 6.

[0023] Among them, the material of the mask layer 6 is usually an organic material, and the removal of the mask layer 6 usually adopts an ashing process, which is usually carried out in an oxygen-containing gas atmosphere. Therefore, when removing the mask layer 6, the conductive plug 4 is exposed to the oxygen-containing gas atmosphere, and the conductive plug 4 is easily oxidized by the oxygen-containing gas, so that the material of the part of the conductive plug 4 in contact with the oxygen-containing gas is converted into a metal oxide 7, and the metal oxide 7 is located on the surface of the conductive plug 4. Therefore, after forming the MTJ stack structure 8, the metal oxide 7 is located between the conductive plug 4 and the MTJ stack structure 8, and the MTJ stack structure 8 cannot directly contact the conductive plug 4, and the resistivity of the metal oxide 7 is usually high, which results in a large contact resistance between the MTJ stack structure 8 and the conductive plug 4, reducing the contact performance between the MTJ stack structure 8 and the conductive plug 4, and further easily reducing the TMR of the magnetic tunnel junction, resulting in poor performance of the formed MRAM device.

[0024] To solve the above technical problems, in the forming method of the semiconductor structure according to the embodiments of the present invention, before forming the alignment trench, a protective layer is further formed on the conductive plug. The formation of the alignment trench generally includes the steps of etching the dielectric layer using a mask layer as a mask and then removing the mask layer, and in the semiconductor field, an oxygen-containing gas is usually used to remove the mask layer. The protective layer formed by the embodiments of the present invention can protect the conductive plug during the process of removing the mask layer, preventing the problem that the conductive plug is oxidized to form a metal oxide due to exposure to the oxygen-containing gas. After forming the MTJ stack structure on the conductive plug, it is beneficial to directly contact the MTJ stack structure with the conductive plug, which is correspondingly beneficial to reducing the contact resistance between the MTJ stack structure and the conductive plug and improving the contact performance between the MTJ stack structure and the conductive plug, and further beneficial to improving the performance of the MRAM device.

[0025] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following provides a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

[0026] Figures 8 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0027] Refer to Figure 8 , and provide a substrate 101.

[0028] The substrate 101 is used to provide a process platform for subsequent process steps.

[0029] In this embodiment, the substrate 101 provides a process platform for forming MRAM devices.

[0030] In this embodiment, transistors are formed in the substrate 101. Among them, the transistors can be one or both of NMOS transistors and PMOS transistors. Specifically, the transistors can include a gate structure, source-drain doping regions in the substrate 101 on both sides of the gate structure. In this embodiment, an interlayer dielectric layer and contact hole plugs penetrating the interlayer dielectric layer and contacting the source-drain doping regions are also formed in the substrate 101. The interlayer dielectric layer covers the surfaces of the source-drain doping regions and the sidewalls of the gate structure. Other types of semiconductor devices can also be formed in the substrate 101, and functional structures such as resistor structures and conductive structures can also be formed in the substrate 101.

[0031] In this embodiment, a first metal interlayer dielectric layer 100 is also formed in the substrate 101.

[0032] The first metal interlayer dielectric layer 100 is used to achieve electrical isolation between metal interconnects in the back-end process.

[0033] In this embodiment, the first metal interlayer dielectric layer 100 is located on the interlayer dielectric layer and covers the contact hole plugs. In this embodiment, the material of the first metal interlayer dielectric layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc. Specifically, the material of the first metal interlayer dielectric layer 100 is a low-k dielectric material, which is beneficial to reducing the parasitic capacitance between the back-end interconnect structures, and thus beneficial to reducing the back-end RC delay.

[0034] Correspondingly, in this embodiment, interconnects 105 are formed in the first metal interlayer dielectric layer 100.

[0035] The interconnecting line 105 is electrically connected to the contact plug, thereby realizing the electrical connection between the source / drain doped regions and the external circuit or other interconnecting structures and components. Specifically, the interconnecting line 105 can be any metal layer (Mx). The electrical connection between the interconnecting line 105 and the contact plug can be realized through the interconnecting structure.

[0036] In this embodiment, the material of the interconnecting line 105 is copper.

[0037] Continue to refer to Figure 8 , a dielectric layer 120 is formed on the substrate 101.

[0038] The subsequent steps further include: forming a conductive plug penetrating the dielectric layer 120, and the dielectric layer 120 is used to realize the electrical isolation between adjacent conductive plugs. The dielectric layer 120 is also used to realize the electrical isolation between the interconnecting line 110 and the subsequent magnetic tunnel junction stack structure.

[0039] Specifically, the dielectric layer 120 is formed on the first intermetal dielectric layer 100 and covers the interconnecting line 105.

[0040] In this embodiment, the material of the dielectric layer 120 is a dielectric material such as a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the dielectric layer 120 is silicon oxide.

[0041] In this embodiment, the thickness of the dielectric layer 120 is

[0042] It should be noted that in this embodiment, after providing the substrate 101 and before forming the dielectric layer 120, the method for forming the semiconductor structure further includes: forming a barrier layer 110 on the substrate 101.

[0043] Specifically, the barrier layer 110 is located on the first intermetal dielectric layer 100 and covers the interconnecting line 105.

[0044] The barrier layer 110 is used to define the etching stop position during the subsequent etching of the dielectric layer 120 to form a conductive via, thereby preventing the etching process for forming the conductive via from damaging the substrate 101. In particular, it prevents the etching process from damaging the interconnecting line 105.

[0045] Therefore, the barrier layer 110 is selected to have a material with a large etching selectivity with respect to the dielectric layer 120, so that the barrier layer 110 can define the etching stop position in the subsequent etching process for forming the conductive via. In this embodiment, the material of the barrier layer 110 is a compound material containing one or more of carbon, nitrogen, and oxygen. Specifically, in this embodiment, the material of the barrier layer 110 is silicon nitride.

[0046] In other embodiments, the material of the barrier layer may also be silicon oxynitride, silicon carbide, NDC (Nitride doped Carbon), aluminum oxide, aluminum nitride or other materials.

[0047] In this embodiment, the thickness of the barrier layer 110 is

[0048] With reference to Figure 9 , it should be noted that in this embodiment, after forming the dielectric layer 120 on the substrate 101, the method for forming the semiconductor structure further includes: forming an etch stop layer 130 on the dielectric layer 120.

[0049] In the subsequent step of forming a conductive via penetrating the dielectric layer 120, the conductive via also penetrates the etch stop layer 130. Subsequently, a conductive plug is formed in the conductive via. The process of forming the conductive plug usually includes a step of planarizing the conductive material layer. The etch stop layer 130 formed in this embodiment can define the position of the planarization process, which is beneficial to reducing the process difficulty of the planarization process and improving the top surface flatness and height consistency of the conductive plug.

[0050] In addition, a protective layer is further formed on the dielectric layer 120 and the conductive plug, and a step of removing the protective layer is further included. In this embodiment, by forming the etch stop layer 130, during the subsequent process of removing the protective layer, the protective layer and the etch stop layer 130 have a large etch selectivity, so that the etch stop layer 130 can define the position of etch stop, which is beneficial to preventing the process of removing the protective layer from damaging the top of the dielectric layer 120 and improving the top surface flatness and height consistency of the dielectric layer 120.

[0051] The material of the etch stop layer 130 may be one or more of silicon nitride, silicon oxynitride, silicon carbide and silicon carbonitride. The material of the etch stop layer 130 is a carbon-containing, nitrogen-containing, or carbon- and nitrogen-containing material. The carbon-containing or carbon-containing material has a high etch selectivity with silicon oxide, which is beneficial to ensuring that the etch stop layer 130 can define the position of etch stop during the subsequent process of removing the protective layer.

[0052] In this embodiment, the material of the etch stop layer 130 is silicon nitride. The silicon nitride material has a high density and hardness, which is beneficial to ensuring that during the subsequent process of removing the protective layer, the protective layer and the etch stop layer 130 have a high etch selectivity, so that the etch stop layer 130 can define the position of etch stop.

[0053] In the step of forming the etch stop layer 130, the thickness of the etch stop layer 130 should not be too small. Otherwise, during the subsequent planarization process of forming the conductive plug, the etch stop layer 130 is likely to be removed prematurely, or the remaining etch stop layer 130 is too thin, which is likely to reduce the effect of the etch stop layer 130 in defining the etch stop position during the subsequent removal of the protective layer. The thickness of the etch stop layer 130 should not be too large either, otherwise it is likely to cause waste of process time and process materials, and it will also take more time to etch the etch stop layer 130 subsequently, which is likely to reduce the process compatibility. Therefore, in this embodiment, the thickness of the etch stop layer 130 is to For example: etc.

[0054] In this embodiment, the etch stop layer 130 is formed by a deposition process. The process temperature of the deposition process should not be too low, otherwise it is likely to affect the formation quality of the etch stop layer 130. For example, it is likely to cause a decrease in the density and hardness of the etch stop layer 130, and further likely to reduce the effect of the etch stop layer 130 in defining the stop position during the subsequent planarization process and the removal of the protective layer. The process temperature of the deposition process should not be too high either, otherwise it is likely to affect the performance of the devices formed in the previous process. Therefore, in this embodiment, the deposition process is from 500°C to 700°C, for example: 550°C, 560°C, 670°C, etc.

[0055] In this embodiment, the etch stop layer 130 is formed by a chemical vapor deposition process. The chemical vapor deposition process is a relatively mature deposition process with high process compatibility and is conducive to saving process costs.

[0056] Refer to Figures 10 to 11 , a conductive via 200 penetrating the dielectric layer 120 is formed (as Figure 11 shown).

[0057] The conductive via 200 is used to provide a spatial position for the subsequent formation of the conductive plug.

[0058] In this embodiment, the bottom of the conductive via 200 exposes the interconnect line 105, so that the subsequent conductive plug can be in contact with the interconnect line 105, thereby realizing the electrical connection between the conductive plug and the interconnect line 105.

[0059] In this embodiment, the conductive via 200 penetrates the etch stop layer 130 and the dielectric layer 120.

[0060] The following will detail the specific steps of forming the conductive via 200 in this embodiment with reference to the accompanying drawings.

[0061] As Figure 10As shown, a first mask layer is formed on the etch stop layer 130. The first mask layer is used as a mask for etching the etch stop layer 130 and the dielectric layer 120 to form the conductive via 200.

[0062] In this embodiment, the first mask layer includes a first planar layer 111, a first anti-reflection layer 112 located on the first planar layer 111, and a first photoresist layer 113 located on the first anti-reflection layer 112. A first pattern opening (not labeled) is formed in the first photoresist layer 113.

[0063] The top surface of the first planar layer 111 is a flat surface, which is used to improve the surface flatness of the first anti-reflection coating 112, thereby improving the topography quality and dimensional accuracy of the first photoresist layer 113. In this embodiment, the material of the first planar layer 111 is spin on carbon (SOC).

[0064] In this embodiment, the thickness of the first planar layer 111 is

[0065] The first anti-reflection layer 112 is used to reduce the reflection effect during exposure, thereby improving the pattern transfer accuracy, and further improving the topography quality and dimensional accuracy of the first photoresist layer 113. In this embodiment, the material of the first anti-reflection layer 112 is Si-ARC (Silicon anti-reflective-coating).

[0066] In this embodiment, the thickness of the first anti-reflection layer 112 is

[0067] In this embodiment, the first photoresist layer 113 is formed by an exposure and development process.

[0068] As Figure 11 shown, along the first pattern opening, the etch stop layer 130 and the dielectric layer 120 are etched in sequence to form a conductive via 120 that penetrates the etch stop layer 130 and the dielectric layer 120.

[0069] In this embodiment, a dry etching process is used to etch the etch stop layer 130 and the dielectric layer 120 in sequence. The dry etching process has high etching profile controllability, which is beneficial to improving the profile quality of the conductive via 200.

[0070] Specifically, during the dry etching process, by switching the type of etching gas and adjusting the etching parameters, the etch stop layer 130 and the dielectric layer 120 can be etched in sequence in the same etching reaction chamber.

[0071] It should be noted that in this embodiment, during the formation of the conductive via 120, the barrier layer 110 at the bottom of the dielectric layer 120 is also etched, thereby exposing the interconnect line 105.

[0072] In this embodiment, during the formation of the conductive via 120, the first mask layer is gradually consumed, so that after the conductive via 120 is formed, the first mask layer has been removed.

[0073] Refer to Figures 12 to 13 , a conductive plug 140 is formed in the conductive via 200 (as Figure 13 shown).

[0074] The conductive plug 140 is used to achieve electrical connection between the substrate 101 and an external circuit or other interconnect structures.

[0075] Specifically, the conductive plug 140 is in contact with the interconnect line 105, and the conductive plug 140 is used to achieve electrical connection between the interconnect line 105 and the subsequent MTJ stack structure.

[0076] The material of the conductive plug 140 can be one or more of Cu, W, Al, TiN, TaN, and Ti. In this embodiment, the material of the conductive plug 140 is Cu.

[0077] In this embodiment, the steps of forming the conductive plug 140 include:

[0078] As Figure 12 shown, a conductive material layer 135 filling the conductive via 200 is formed, and the conductive material layer 135 also covers the etch stop layer 130. The conductive material layer 135 is used to form the conductive plug.

[0079] As Figure 13 shown, using the etch stop layer 130 as the stop layer, the conductive material layer 135 is planarized, and the remaining conductive material layer 135 in the conductive via 200 is used as the conductive plug 140.

[0080] The etch stop layer 130 can be used as a stop layer during the planarization process to define the stop position of the planarization process. This not only helps to reduce the process difficulty of the planarization process, but also helps to prevent damage to the top of the dielectric layer 120 during the planarization process, improves the top surface flatness and height consistency of the dielectric layer 120, and also improves the height consistency of the conductive plug 140. Specifically, the mechanical strength and hardness of the etch stop layer 130 are relatively large, so that the planarization process is easily stopped on the etch stop layer 130.

[0081] In this embodiment, a chemical mechanical polishing process is used for planarization.

[0082] Refer to Figure 14, a protective layer 150 is formed on the dielectric layer 120, and the protective layer 150 covers the conductive plug 140.

[0083] Subsequent steps further include: forming alignment trenches in the protective layer 150 and the dielectric layer 120, and the alignment trenches are isolated from the conductive plug 140.

[0084] In the embodiment of the present invention, before forming the alignment trenches, a protective layer 150 is formed on the conductive plug 140. Forming the alignment trenches generally includes the steps of etching the dielectric layer 120 using a mask layer as a mask and then removing the mask layer. In the semiconductor field, an oxygen-containing gas is usually used to remove the mask layer. The protective layer 150 formed in the embodiment of the present invention can protect the conductive plug 140 during the process of removing the mask layer, preventing the problem that the conductive plug 140 is oxidized to form metal oxides due to exposure to the oxygen-containing gas. Thus, after forming the MTJ stack structure on the conductive plug 140, it is beneficial to directly contact the MTJ stack structure with the conductive plug 140, which is correspondingly beneficial to reducing the contact resistance between the MTJ stack structure and the conductive plug 140 and improving the contact performance between the MTJ stack structure and the conductive plug 140, thereby improving the performance of the MRAM device.

[0085] In this embodiment, the protective layer 150 is made of a material with good density, so that the protective layer 150 can block the oxygen-containing gas during the subsequent process of removing the mask layer, preventing the oxygen-containing gas from contacting the conductive plug 140, and thus playing a role in protecting the conductive plug 140.

[0086] In this embodiment, the material of the protective layer 150 is silicon oxide. By selecting silicon oxide, the material of the protective layer 150 is the same as that of the dielectric layer 120, which is beneficial to improving process compatibility. Moreover, silicon oxide is a commonly used material in semiconductor processes, which is beneficial to improving the compatibility of the process of forming the protective layer 150 and the subsequent process of removing the protective layer 150 with the existing processes, reducing process variations and process risks. In addition, the silicon oxide material is easy to remove, which is beneficial to reducing the difficulty of removing the protective layer 150 subsequently. Moreover, the silicon oxide material has a high etching selectivity with respect to the aforementioned etch stop layer 130 material, which is beneficial to ensuring that the subsequent removal of the protective layer 150 can stop on the etch stop layer 130. In other embodiments, according to the actual process and the material of the etch stop layer, the material of the protective layer may also be silicon carbide or silicon oxycarbide.

[0087] The thickness of the protective layer 150 should not be too small, otherwise it is easy to reduce the protection effect of the protective layer 150 on the conductive plug 140 during the subsequent removal of the mask layer; subsequent steps also include removing the protective layer 150, and the thickness of the protective layer 150 should not be too large, otherwise it is easy to increase the difficulty of removing the protective layer 150 subsequently. Therefore, in this embodiment, the thickness of the protective layer 150 is to For example: etc.

[0088] In this embodiment, the protective layer 150 is formed by a deposition process. The process temperature of the deposition process should not be too low, otherwise it is easy to increase the implementation difficulty of the deposition process, resulting in difficulty in forming the protective layer 150; the process temperature of the deposition process should not be too high, otherwise it is easy to increase the risk of oxidation of the conductive plug 140 and also easy to affect the performance of the device. For this reason, in this embodiment, the process temperature of the deposition process for forming the protective layer 150 is 50°C to 100°C, for example: 60°C, 75°C, 80°C, 95°C, etc.

[0089] In this embodiment, the protective layer 150 is formed by an atomic layer deposition process. The atomic layer deposition process is a self-limiting reaction process based on the atomic layer deposition process. The deposited thin film can reach the thickness of a single atomic layer, which is beneficial to improving the thickness consistency of the protective layer 150 and precisely controlling the thickness of the protective layer 150. Moreover, the thin film prepared by the atomic layer deposition process also has the characteristics of good bonding strength, good compositional uniformity, good conformality, etc., which is beneficial to improving the density of the protective layer 150, thereby improving the blocking effect of the protective layer 150 on the oxygen-containing gas during the subsequent removal of the mask layer, and further improving the protection effect of the protective layer 150 on the conductive plug 140.

[0090] Refer to Figures 15 to 17 , an alignment trench 200 is formed in the protective layer 150 and the dielectric layer 120, and the alignment trench 200 is isolated from the conductive plug 140.

[0091] By forming the alignment trench 200, after the initial magnetic tunnel junction stack structure is formed subsequently, the initial magnetic tunnel junction stack structure formed on the bottom and side walls of the alignment trench 200 also encloses a groove corresponding to the alignment trench 200, and the groove can be used as an alignment mark (Aligner mark) for subsequent patterning of the initial magnetic tunnel junction stack structure. Specifically, the light transmittance of the subsequently formed initial MTJ stack structure is relatively low. After the initial MTJ structure is formed, the alignment marks formed in the previous process (for example: the alignment marks formed in the dielectric layer 120) are covered by the initial MTJ stack structure, so it is difficult to be used as a lithography alignment mark during the subsequent patterning of the initial MTJ stack structure.

[0092] In this embodiment, the alignment trench 200 is a deep trench structure (Isolation Deep Trench, IDT).

[0093] To prevent contact with the initial MTJ stack structure formed on the sidewalls of the alignment trench 200 subsequently, and to ensure that the initial MTJ stack structure formed in the alignment trench 200 can also enclose a groove as an alignment mark, the opening width of the alignment trench 200 should not be too small. For this reason, in this embodiment, the opening width of the alignment trench 200 is greater than or equal to 1 μm. Specifically, the opening width of the alignment trench 200 is 1 μm to 2 μm.

[0094] To ensure that the depth of the groove enclosed by the initial MTJ stack structure formed in the alignment trench 200 is not too shallow, so as to ensure that the groove can serve as an alignment mark for the photolithography process, the depth of the alignment trench 200 should not be too small. For this reason, in this embodiment, the depth of the alignment trench 200 is greater than or equal to

[0095] Specifically, in this embodiment, the depth of the alignment trench 200 is

[0096] The steps of forming the alignment trench 200 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0097] As Figure 15 shown, a mask layer is formed on the protective layer 150, and the mask layer covers the protective layer 150 located on the conductive plug 140. In this embodiment, the mask layer is the second mask layer, and the second mask layer is used as an etching mask for forming the alignment trench subsequently.

[0098] The second mask layer includes a second planarization layer 121 located on the protective layer 150, a second anti-reflection layer 122 located on the second planarization layer 121, and a second photoresist layer 123 located on the second anti-reflection layer 122. A second pattern opening (not labeled) is formed in the second photoresist layer 123, and the second pattern opening exposes a part of the second anti-reflection layer 122 located on the dielectric layer 120.

[0099] For a detailed description of the second planarization layer 121, the second anti-reflection layer 122, and the second photoresist layer 123, reference can be made to the relevant descriptions of the first planarization layer 111, the first anti-reflection layer 112, and the first photoresist layer 113 above, and this embodiment will not be elaborated here.

[0100] As Figure 16 shown, using the mask layer as a mask, the protective layer 150 and the dielectric layer 120 are etched.

[0101] In this embodiment, using the barrier layer 110 as a stop layer to etch the protective layer 150 and the dielectric layer 120 is beneficial to reducing the probability of accidentally etching the first inter-metal dielectric layer 100 when forming the alignment trench 200, and improving the depth consistency of the alignment trench 200 and precisely controlling the depth of the alignment trench 200.

[0102] In this embodiment, an etch stop layer 130 is further formed on the dielectric layer 120. Therefore, using the mask layer as a mask, the protective layer 150, the etch stop layer 130, and the dielectric layer 120 are etched. In this embodiment, a dry etching process is used to etch the protective layer 150, the etch stop layer 130, and the dielectric layer 120.

[0103] As Figure 17 shown, the mask layer is removed.

[0104] The material of the mask layer is an organic material. Therefore, in this embodiment, an ashing process is used to remove the mask layer. Specifically, in this embodiment, a plasma ashing process is used to remove the mask layer.

[0105] The ashing process usually uses an oxygen-containing gas. In this embodiment, a protective layer 150 is formed on the conductive plug 140. The protective layer 150 can protect the conductive plug 140, thereby preventing the oxygen-containing gas from contacting the conductive plug 140, and further preventing the problem that the conductive plug 140 is oxidized to form metal oxides. Furthermore, the subsequent MTJ stack structure can be directly in contact with the conductive plug 140, improving the contact performance between the subsequent MTJ stack structure and the conductive plug 140.

[0106] Referring to Figure 18 , after forming the alignment trench 200, the protective layer 150 is removed, exposing the top of the conductive plug 140. Removing the protective layer 150 prepares for the subsequent formation of the magnetic tunnel junction stack structure.

[0107] In this embodiment, with the top surface of the etch stop layer 130 as the stop position, the protective layer 150 is removed.

[0108] In the step of removing the protective layer 150, the top surface of the etch stop layer 130 can define the etch stop position, thereby preventing the process of removing the protective layer 150 from damaging the dielectric layer 120, which is beneficial to ensuring the flatness and morphology quality of the top surface of the dielectric layer 120 and providing a good interface for the subsequent formation of the MTJ stack structure.

[0109] Specifically, in the step of removing the protective layer 150, the etch selectivity between the protective layer 150 and the etch stop layer 130 is relatively large, so that the etch stop layer 130 can define the etch stop position.

[0110] In this embodiment, in the step of removing the protective layer 150, the etch selectivity ratio between the protective layer 150 and the etch stop layer 130 is greater than or equal to 10:1, for example: 15:1, 20:1, etc.

[0111] In the step of removing the protective layer 150, the etching selectivity between the protective layer 150 and the conductive plug 140 should not be too small, otherwise it is easy to damage the top surface of the conductive plug 140, which is likely to reduce the interface quality of the surface of the conductive plug 140 and increase the surface roughness of the conductive plug 140. Therefore, in this embodiment, in the step of removing the protective layer 150, the etching selectivity between the protective layer 150 and the conductive plug 140 is greater than or equal to 10:1, for example: 15:1, 20:1, etc.

[0112] In this embodiment, a wet etching process is used to remove the protective layer 150. The wet etching process is easy to achieve a large etching selectivity, and the process operation steps of the wet etching process are simple and the process cost is low.

[0113] In this embodiment, the material of the protective layer 150 is silicon oxide, and the etching solution of the wet etching process is a hydrofluoric acid solution. The hydrofluoric acid solution is a solution commonly used in semiconductor processes for etching silicon oxide, which is beneficial to improving process compatibility, and the etching selectivity of the hydrofluoric acid solution for silicon oxide and silicon nitride is relatively high, which is beneficial to improving the effect of the etching stop layer 130 for defining the etching stop position.

[0114] In the step of performing the wet etching process, the volume percentage concentration of the hydrofluoric acid solution should not be too small, otherwise it is easy to reduce the etching rate, and thus it is easy to reduce the production capacity; if the volume percentage concentration of the hydrofluoric acid solution is also not too large, otherwise it is easy to reduce the etching stability and etching uniformity, and thus it is easy to produce side effects. Therefore, in this embodiment, the volume percentage concentration of the hydrofluoric acid solution is 0.3% to 0.5%.

[0115] The etching time of the wet etching process should not be too short, otherwise it is easy to increase the risk that the protective layer 150 is not completely removed; the etching time of the wet etching process should not be too long, otherwise it is easy to increase the probability of damaging other film layers, and thus it is easy to reduce the process stability, and a too long etching time is also easy to waste production capacity. Therefore, in this embodiment, the etching time of the wet etching process is 50 seconds to 60 seconds.

[0116] In this embodiment, the solution temperature of the wet etching process is 15°C to 25°C, so as to cooperate with the volume percentage concentration of the etching solution, improve the removal efficiency of removing the protective layer 150, and reduce the probability of mis-etching other film layers, which is beneficial to improving the process stability and reducing the process risk.

[0117] Specifically, in this embodiment, the wet etching process is carried out at room temperature.

[0118] In this embodiment, 300:1 diluted HF (DHF) is used, and the etching rate of the protective layer 150 is The etching rate for the etching stop layer 130 and the conductive plug 140 is less than The etching amount of the etch stop layer 130 and the conductive plug 140 is less than The lateral etching amount of the dielectric layer 120 is less than

[0119] Reference Figures 19 to 20 , after removing the protective layer 150, a magnetic tunnel junction (MTJ) stack structure 160 is formed on the conductive plug 140 (as Figure 20 shown).

[0120] The protective layer 150 formed in this embodiment can protect the conductive plug 140 during the formation of the alignment trench 200, preventing the problem that the surface of the conductive plug 140 generates metal oxides due to oxidation. Therefore, the MTJ stack structure 160 can be in direct contact with the conductive plug 140, which is beneficial to reducing the contact resistance between the conductive plug 140 and the MTJ stack structure 160, and improving the contact performance between the conductive plug 140 and the MTJ stack structure 160. Furthermore, the magnetic flux ratio (TMR) of the MTJ stack structure 160 is improved, correspondingly enhancing the performance of the MRAM device.

[0121] The MTJ stack structure 160 includes a reference layer (not shown in the figure), a tunneling layer (not shown in the figure) located on the reference layer, and a free layer (not shown in the figure) located on the tunneling layer. The magnetization direction of the reference layer is fixed, so that it can be used as a reference layer for the magnetization direction of the free layer. The material of the reference layer is a ferromagnetic metal material, for example: CoFeB or CoFe.

[0122] The tunneling layer is used to isolate the reference layer and the free layer. The materials of the tunneling layer include MgO, SrO, BaO, RaO, SiO 2 , Al 2 O 3 , HfO 2 , NiO, GdO, Ta 2 O 5 , MoO 2 , TiO 2 or WO 2 .

[0123] The magnetization direction of the free layer has two stable orientations, which are parallel or opposite to the magnetization direction of the reference layer respectively, so that the magnetic tunnel junction can be in a low-resistance state or a high-resistance state.

[0124] The material of the free layer is also a ferromagnetic metal material, for example: CoFeB or CoFe.

[0125] The magnetic tunnel junction stack structure 160 may further include an electrode layer located at the bottom of the reference layer. The material of the electrode layer may be one or more of tantalum nitride, tantalum, titanium, and titanium nitride.

[0126] In this embodiment, the steps of forming the magnetic tunnel junction stack structure 160 include:

[0127] As Figure 19 shown, an initial MTJ stack structure 155 is formed on the etch stop layer 130, and the initial MTJ stack structure 155 is also formed on the bottom and side walls of the alignment trench 200.

[0128] The initial MTJ stack structure 155 is used to form the MTJ stack structure through subsequent patterning processes.

[0129] In this embodiment, after the initial MTJ stack structure 155 is formed, the initial MTJ stack structure 155 located in the alignment trench 200 and on the etch stop layer 130 encloses a groove 300, and the groove 300 is used as an alignment mark for the photolithography process when patterning the initial MTJ stack structure 155 subsequently.

[0130] As Figure 20 shown, the initial MTJ stack structure 155 is patterned (as Figure 19 shown), and the remaining initial MTJ stack structure 155 located on the conductive plug 140 is retained as the magnetic tunnel junction stack structure 160.

[0131] In this embodiment, the steps of patterning the initial MTJ stack structure 155 include: forming a pattern layer (not shown in the figure) on the initial MTJ stack structure 155, and the pattern layer exposes a part of the initial MTJ stack structure 155; using the pattern layer as a mask to etch the initial MTJ stack structure 155.

[0132] In this embodiment, the pattern layer includes a photoresist layer. The pattern layer can be formed through photolithography processes such as photoresist coating, development, and exposure. Among them, the groove 300 is used as an alignment mark for the exposure and development process.

[0133] In this embodiment, a dry etching process is used to pattern the initial MTJ stack structure 155.

[0134] In this embodiment, in the step of patterning the initial MTJ stack structure 155, the pattern layer is also gradually consumed, and after the MTJ stack structure 160 is formed, the pattern layer has been removed.

[0135] Continuing to refer to Figure 20 , after the magnetic tunnel junction stack structure 160 is formed, in this embodiment, the method for forming the semiconductor structure further includes: removing the etch stop layer 130 exposed by the magnetic tunnel junction stack structure 160.

[0136] Specifically, after patterning the initial MTJ stack structure 155 using a dry etching process, the etch stop layer 130 is etched in the same etch reaction chamber by converting the type of etch gas and adjusting the etch parameters.

[0137] In this embodiment, removing the etch stop layer 130 exposed by the MTJ stack structure 160 is taken as an example for illustration. In other embodiments, according to the actual process, the etch stop layer can also be retained. In this embodiment, the etch stop layer can also be used as a stop layer when patterning the initial MTJ stack structure.

[0138] Correspondingly, the present invention also provides a semiconductor structure. Referring to Figure 17 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

[0139] The semiconductor structure includes: a substrate 101; a dielectric layer 120 located on the substrate 101; a conductive plug 140 penetrating the dielectric layer 120; a protective layer 150 located on the dielectric layer 120 and covering the conductive plug 140; an alignment trench 200 located in the dielectric layer 120 and the protective layer 150 and isolated from the conductive plug 140.

[0140] In the semiconductor structure of this embodiment, a protective layer 150 is also provided. The protective layer 150 can protect the conductive plug 140 during the formation of the alignment trench 200, preventing the problem of metal oxide formation due to oxidation on the surface of the conductive plug 140, so that the subsequent magnetic tunnel junction (MTJ) stack structure can directly contact the conductive plug 140, which is beneficial to reducing the contact resistance between the MTJ stack structure and the conductive plug 140, improving the contact performance between the MTJ stack structure and the conductive plug 140, and further beneficial to increasing the tunneling magnetoresistance (TMR) of the MTJ stack structure and improving the performance of the MRAM device.

[0141] The substrate 101 is used to provide a process platform for the process. In this embodiment, transistors are formed in the substrate 101. Among them, the transistors can be one or both of NMOS transistors and PMOS transistors. In this embodiment, an interlayer dielectric layer and contact hole plugs penetrating the interlayer dielectric layer and contacting the source / drain doping regions are also formed in the substrate 101. Other types of semiconductor devices can also be formed in the substrate 101, and functional structures such as a resistance structure and a conductive structure can also be formed in the substrate 101.

[0142] In this embodiment, a first metal interlayer dielectric layer 100 is also formed in the substrate 101.

[0143] The first metal interlayer dielectric layer 100 is used to achieve electrical isolation between metal interconnects in the back-end process.

[0144] In this embodiment, the first inter-metal dielectric layer 100 is located on the inter-layer dielectric layer and covers the contact hole plug. In this embodiment, the material of the first inter-metal dielectric layer 100 is a low-k dielectric material.

[0145] In this embodiment, the substrate 101 further includes an interconnecting line 105 located in the first inter-metal dielectric layer 100. The interconnecting line 105 is electrically connected to the contact hole plug, thereby realizing the electrical connection between the source / drain doping region and an external circuit or other interconnecting structures and components. Specifically, the interconnecting line 105 can be any metal layer (Mx). The interconnecting line 105 can be electrically connected to the contact hole plug through an interconnecting structure.

[0146] In this embodiment, the material of the interconnecting line 105 is copper.

[0147] The dielectric layer 120 is used to achieve electrical isolation between adjacent conductive plugs 140, and the dielectric layer 120 is also used to achieve electrical isolation between the interconnecting line 110 and a subsequent magnetic tunnel junction stack structure.

[0148] In this embodiment, the dielectric layer 120 is located on the first inter-metal dielectric layer 100 and covers the interconnecting line 105. In this embodiment, the material of the dielectric layer 120 is silicon oxide.

[0149] In this embodiment, the thickness of the dielectric layer 120 is

[0150] The semiconductor structure further includes a barrier layer 110 located between the substrate 101 and the dielectric layer 120. In this embodiment, the barrier layer 110 is located on the first inter-metal dielectric layer 100 and covers the interconnecting line 105.

[0151] The process of forming the conductive plug 140 generally includes the step of etching the dielectric layer 120 to form a conductive via hole. The barrier layer 110 is used to define the position where etching stops during the process of etching the dielectric layer 120 to form a conductive via hole, thereby preventing the etching process of forming the conductive via hole from damaging the substrate 101.

[0152] In this embodiment, the material of the barrier layer 110 is silicon nitride.

[0153] In this embodiment, the thickness of the barrier layer 110 is

[0154] The conductive plug 140 is used to achieve the electrical connection between the substrate 101 and an external circuit or other interconnecting structures. Specifically, the conductive plug 140 is in contact with the interconnecting line 105, and the conductive plug 140 is used to achieve the electrical connection between the interconnecting line 105 and a subsequent MTJ structure. In this embodiment, the material of the conductive plug 130 is Cu.

[0155] The semiconductor structure further includes an etch stop layer 130 located between the dielectric layer 120 and the protective layer 150, and the conductive plug 140 also penetrates through the etch stop layer 130.

[0156] Subsequently, it further includes the step of removing the protective layer 150. In this embodiment, by providing the etch stop layer 130, during the process of removing the protective layer 150, the protective layer 150 and the etch stop layer 130 have a large etch selectivity, so that the etch stop layer 130 can define the etch stop position, which is beneficial to preventing damage to the top of the dielectric layer 120 during the process of removing the protective layer 150, improving the top surface flatness and height consistency of the dielectric layer 120, and thus providing a flat surface and a good interface for the subsequent formation of the MTJ stack structure.

[0157] In addition, forming the conductive plug 140 generally includes the step of planarizing the conductive material layer. The etch stop layer 130 can also serve as a stop layer to define the stop position of the planarization process, thereby reducing the process difficulty of the planarization process and improving the top surface flatness and height consistency of the conductive plug 140, and thus providing a flat surface and a good interface for the subsequent formation of the magnetic tunnel junction stack structure.

[0158] The material of the etch stop layer 130 can be one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride. The material of the etch stop layer 130 is a carbon-containing, nitrogen-containing, or carbon- and nitrogen-containing material. The carbon-containing or carbon-containing material has a high etch selectivity with silicon oxide, which is beneficial to ensuring that the etch stop layer 130 can define the etch stop position during the subsequent process of removing the protective layer 150.

[0159] In this embodiment, the material of the etch stop layer 130 is silicon nitride. The silicon nitride material has a high density and hardness. In this embodiment, the thickness of the etch stop layer 130 is to For example: etc.

[0160] The protective layer 150 is used to protect the conductive plug 140 during the formation of the alignment trench 200.

[0161] Specifically, forming the alignment trench 200 generally includes the step of removing the mask layer using an oxygen-containing gas. The protective layer 150 can isolate the conductive plug 140 and the oxygen-containing gas during the process of removing the mask layer, preventing the problem that the conductive plug 140 is oxidized to form metal oxides due to exposure to the oxygen-containing gas, so that the subsequent MTJ stack structure can directly contact the conductive plug 140, which is beneficial to improving the contact performance between the magnetic tunnel junction and the conductive plug 140.

[0162] In this embodiment, the material of the protective layer 150 is silicon oxide, which is beneficial to improving the process compatibility, reducing process variations and process risks. In addition, the silicon oxide material is easy to remove, which is beneficial to reducing the difficulty of removing the protective layer 150 subsequently. Moreover, the silicon oxide material has a high etching selectivity with respect to the material of the etch stop layer 130, which is beneficial to ensuring that the removal of the protective layer 150 can be stopped on the etch stop layer 130 subsequently. In other embodiments, the material of the protective layer may also be silicon carbide or silicon oxycarbide.

[0163] The thickness of the protective layer 150 should not be too small or too large. If the thickness of the protective layer 150 is too small, during the formation of the alignment trench 200, it is easy to reduce the protection effect of the protective layer 150 on the conductive plug 140 in the step of removing the mask layer; subsequently, there is also a step of removing the protective layer 150. If the thickness of the protective layer 150 is too large, it is easy to increase the difficulty of removing the protective layer 150 subsequently. Therefore, in this embodiment, the thickness of the protective layer is to For example: etc.

[0164] By providing the alignment trench 200 in the semiconductor structure, after the initial MTJ stack structure is formed subsequently, the initial MTJ stack structure formed on the bottom and sidewalls of the alignment trench 200 also encloses a groove corresponding to the alignment trench 200, and the groove is used as an alignment mark for patterning the initial MTJ stack structure subsequently.

[0165] In this embodiment, the alignment trench 200 is a deep trench structure. In this embodiment, the alignment trench 200 is located in the dielectric layer 120, the protective layer 150, and the etch stop layer 130.

[0166] In this embodiment, the opening width of the alignment trench 200 is 1 micron to 2 microns.

[0167] In this embodiment, the depth of the alignment trench 200

[0168] The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and this embodiment will not be elaborated herein.

[0169] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate; forming a dielectric layer on the substrate; forming an etch stop layer on the dielectric layer; forming a conductive via penetrating through the etch stop layer and the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the etch stop layer, the protective layer covering the conductive plug, the material of the protective layer being the same as the material of the dielectric layer, and the materials of both the protective layer and the dielectric layer being silicon oxide; forming alignment trenches in the protective layer and the dielectric layer, the alignment trenches being isolated from the conductive plug; after forming the alignment trenches, using the top surface of the etch stop layer as a stop position, removing the protective layer to expose the top of the conductive plug; after removing the protective layer, forming a magnetic tunnel junction stack structure on the conductive plug, the magnetic tunnel junction stack structure covering a part of the etch stop layer on the side of the conductive plug.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, after forming the magnetic tunnel junction stack structure, the method for forming the semiconductor structure further comprises: removing the etch stop layer exposed by the magnetic tunnel junction stack structure.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, the step of forming the conductive plug includes: forming a conductive material layer filling the conductive via, the conductive material layer also covering the etch stop layer; using the etch stop layer as a stop layer, performing planarization treatment on the conductive material layer, and the remaining conductive material layer in the conductive via is used as the conductive plug.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, the process for forming the protective layer includes atomic layer deposition process.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, the protective layer is formed by a deposition process, and the process temperature of the deposition process is 50°C to 100°C.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, the protective layer is removed by a wet etching process.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, the etching solution of the wet etching process is a hydrofluoric acid solution, and the process parameters of the wet etching process include: the volume percentage concentration of the hydrofluoric acid solution is 0.3% to 0.5%, the solution temperature is 15°C to 25°C, and the etching time is 50 seconds to 60 seconds.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of removing the protective layer, the etching selectivity between the protective layer and the conductive plug is greater than or equal to 10:

1.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming the protective layer, the thickness of the protective layer is to 10. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of removing the protective layer, the etching selectivity between the protective layer and the etch stop layer is greater than or equal to 10:

1.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The etch stop layer is formed by a chemical vapor deposition process.

12. The method for forming a semiconductor structure according to claim 1, wherein, the etch stop layer is formed by a deposition process, and the process temperature of the deposition process is 500°C to 700°C.

13. The method for forming a semiconductor structure according to claim 1, wherein, the material of the etch stop layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride.

14. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the etch stop layer, the thickness of the etch stop layer is to 15. A semiconductor structure, wherein, comprising: a substrate; a dielectric layer located on the substrate; a conductive plug penetrating the dielectric layer; a protective layer located on the dielectric layer and covering the conductive plug, the material of the protective layer is the same as the material of the dielectric layer, and the materials of the protective layer and the dielectric layer are both silicon oxide; an alignment trench located in the dielectric layer and the protective layer and isolated from the conductive plug; the semiconductor structure further includes: an etch stop layer located between the dielectric layer and the protective layer, and the conductive plug also penetrates the etch stop layer.

16. The semiconductor structure according to claim 15, wherein, The thickness of the protective layer is to 17. The semiconductor structure according to claim 15, wherein, the material of the etch stop layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride.

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