Thin film device

Abstract

A thin film device is provided, comprising: a first oxide semiconductor thin film transistor, comprising a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide film; a second oxide semiconductor thin film transistor, comprising a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide film; a bottom gate insulating layer, comprising the bottom gate insulating film; and a storage capacitor configured to store a signal voltage applied to the bottom gate electrode.

Description

Technical Field

[0001] The present disclosure relates to a thin film device. Background Art

[0002] Organic light emitting diode (OLED) devices are increasingly being used in display devices. OLED devices are current-driven light emitting devices that do not require a backlight and offer low power consumption, a wide viewing angle, and high contrast.

[0003] An active-matrix OLED display device includes pixel circuits, each of which includes a switching thin-film transistor (TFT) for selecting a pixel (sub-pixel) and a driving TFT for supplying current to the OLED element that produces the pixel's display. The pixel circuits can be made of amorphous silicon TFTs, polycrystalline silicon TFTs, or oxide semiconductor TFTs.

[0004] Oxide semiconductor TFTs are increasingly being used in pixel circuits of display devices due to their characteristics, such as low leakage current and relatively high electron mobility. Oxide semiconductor TFTs are used in various fields other than display devices. Summary of the Invention

[0005] Oxide semiconductor TFTs in circuits are required to have different characteristics to meet their functional requirements. For example, in a circuit for controlling a current-driven light-emitting element, the switching TFT used to select the light-emitting element is required to have a characteristic in which the drain current rises sharply relative to the gate voltage (low S value). Conversely, the driving TFT is required to have a characteristic in which the drain current rises gently (high S value). In addition to including oxide semiconductor TFTs with different characteristics, the circuit is also required to be reduced in size.

[0006] One aspect of the present disclosure is a thin film device comprising: a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide film; a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide film; a bottom gate insulating layer including the bottom gate insulating film; and a storage capacitor configured to store a signal voltage applied to the bottom gate electrode. The first metal oxide film includes a first source / drain region, a second source / drain region, and a first channel region located between the first source / drain region and the second source / drain region. The second metal oxide film includes a third source / drain region, a fourth source / drain region, and a second channel region located between the third source / drain region and the fourth source / drain region. The first electrode of the storage capacitor includes a portion of the bottom gate electrode. The second source / drain region contacts the bottom gate electrode in a contact hole in the bottom gate insulating layer. The capacitance per unit area of ​​the bottom gate insulating film is smaller than the capacitance per unit area of ​​the top gate insulating film.

[0007] Another aspect of the present disclosure is a thin film device comprising: a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide film; a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide film; a bottom gate insulating layer including the bottom gate insulating film; and a storage capacitor configured to store a signal voltage applied to the bottom gate electrode. The first metal oxide thin film includes a first source / drain region, a second source / drain region, and a first channel region located between the first source / drain region and the second source / drain region. The second metal oxide thin film includes a third source / drain region, a fourth source / drain region, and a second channel region located between the third source / drain region and the fourth source / drain region. The first electrode of the storage capacitor includes a portion of the bottom gate electrode. The second source / drain region contacts the bottom gate electrode in a contact hole in the bottom gate insulating layer. Each of the first channel region and the second channel region comprises a lower layer having lower electron mobility and an upper layer having higher electron mobility.

[0008] Another aspect of the present disclosure is a thin film device comprising: a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide film; a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide film; a bottom gate insulating layer including the bottom gate insulating film; and a storage capacitor configured to store a signal voltage applied to the bottom gate electrode. The first metal oxide thin film includes a first source / drain region, a second source / drain region, and a first channel region located between the first source / drain region and the second source / drain region. The second metal oxide thin film includes a third source / drain region, a fourth source / drain region, and a second channel region located between the third source / drain region and the fourth source / drain region. The first electrode of the storage capacitor includes a portion of the bottom gate electrode. The second source / drain region contacts the bottom gate electrode in a contact hole in the bottom gate insulating layer. Each of the first and second channel regions comprises a lower layer and an upper layer, the lower layer and the upper layer having different composition ratios or different constituent elements.

[0009] One aspect of the present disclosure provides a downsized circuit including oxide semiconductor TFTs having different characteristics.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1Schematically shows an example of the configuration of an OLED display device;

[0012] Figure 2A shows a configuration example of a pixel circuit;

[0013] Figure 2B Another configuration example of a pixel circuit is shown;

[0014] Figure 2C Still another configuration example of a pixel circuit is shown;

[0015] Figure 3A The current-voltage characteristics of a switching transistor are schematically shown;

[0016] Figure 3B The current-voltage characteristics of the driving transistor are schematically shown;

[0017] Figure 4A shows the current-voltage characteristics of an oxide semiconductor TFT including a gate insulating film having a thickness of 200 nm;

[0018] Figure 4B shows the current-voltage characteristics of an oxide semiconductor TFT including a gate insulating film having a thickness of 350 nm;

[0019] Figure 5A shows a relatively high mobility (mobility: μ to 30 cm 2 Current-voltage characteristics of IGZTO TFT with 100 nm / Vs;

[0020] Figure 5B shows a relatively low mobility (mobility: μ to 10 cm 2 Current-voltage characteristics of IGZO TFT with 100 nm / Vs;

[0021] Figure 6A schematically illustrates an example of a cross-sectional structure of a switching oxide semiconductor TFT and a driving oxide semiconductor TFT;

[0022] Figure 6B Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT;

[0023] Figure 6C Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT;

[0024] Figure 7 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT;

[0025] Figure 8 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT;

[0026] Figure 9 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT;

[0027] Figure 10 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT;

[0028] Figure 11A shows example steps of a method of manufacturing a TFT substrate;

[0029] Figure 11B shows example steps of a method of manufacturing a TFT substrate;

[0030] Figure 11C shows example steps of a method of manufacturing a TFT substrate;

[0031] Figure 11D shows example steps of a method of manufacturing a TFT substrate;

[0032] Figure 11E shows example steps of a method of manufacturing a TFT substrate;

[0033] Figure 11F shows example steps of a method of manufacturing a TFT substrate; and

[0034] Figure 11G Exemplary steps of a method of manufacturing a TFT substrate are shown. DETAILED DESCRIPTION

[0035] The following describes embodiments of the present disclosure with reference to the accompanying drawings. It should be noted that the embodiments are merely examples of implementing the concepts of the present disclosure and are not intended to limit the technical scope of the present disclosure. Common elements in the figures are represented by the same reference symbols, and the size and / or shape of each element in the figures may be exaggerated to facilitate a clear understanding of the description.

[0036] Overview

[0037] The following describes an example of an organic light-emitting diode (OLED) display device as a thin film device. The OLED display device in the present disclosure includes oxide semiconductor thin film transistors (TFTs) with different characteristics in a pixel circuit. The first oxide semiconductor TFT includes a top gate electrode, and the second oxide semiconductor TFT includes a bottom gate electrode. The first oxide semiconductor TFT can be a switching TFT, and the second oxide semiconductor TFT can be a driving TFT.

[0038] The difference in gate structure between the first oxide semiconductor TFT and the second oxide semiconductor TFT allows each TFT to have characteristics suitable for this purpose. In addition, the structure in which the source / drain region of the first oxide semiconductor TFT contacts the bottom gate of the second oxide semiconductor TFT in a contact hole in the bottom gate insulating layer reduces the number of contact holes, thereby contributing to circuit size reduction.

[0039] The characteristic configuration of the pixel circuit including the oxide semiconductor TFT disclosed herein can be applied to other circuits in a display device or circuits in a thin film device other than a display device.

[0040] Display device configuration:

[0041] Figure 1 The following schematically illustrates an example configuration of an OLED display device 1. The OLED display device 1 includes a thin film transistor (TFT) substrate 10 on which an OLED element is formed, an encapsulation substrate 20 for encapsulating the OLED element, and a bonding member (glass frit seal) 30 for bonding the TFT substrate 10 to the encapsulation substrate 20. The space between the TFT substrate 10 and the encapsulation substrate 20 is filled with dry nitrogen and sealed with the bonding member 30. The encapsulation substrate 20 and the bonding member 30 constitute a structural encapsulation unit. The structural encapsulation unit may have a thin film encapsulation (TFE) structure.

[0042] A scan driver 31, an emission driver 32, a driver IC 34, and a demultiplexer 36 are provided on the periphery of the cathode electrode region 14, which is located outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via a flexible printed circuit (FPC) 35. The scan driver 31 and the emission driver 32 are peripheral circuits fabricated on the TFT substrate 10.

[0043] The scan driver 31 drives the scan lines on the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emission period of the pixels. For example, the driver IC 34 is mounted with an anisotropic conductive film (ACF).

[0044] The drive IC 34 supplies power and timing signals (control signals) to the scan driver 31 and the emission driver 32 , and further supplies power and data signals to the demultiplexer 36 .

[0045] The demultiplexer 36 outputs the output of one pin of the driver IC 34 to d data lines connected in series (d is an integer greater than 1). The demultiplexer 36 changes the output data line (for the data signal from the driver IC 34) d times per scanning cycle to drive d times as many data lines as the output pins of the driver IC 34.

[0046] Pixel circuit configuration:

[0047] A plurality of pixel circuits are formed on the TFT substrate 10 to control current supplied to anodes of sub-pixels (also simply referred to as pixels). Figure 2A 1 shows an example configuration of a pixel circuit. Each pixel circuit includes a drive transistor T1, a select transistor T2, an emission transistor T3, and a storage capacitor C1. The storage capacitor C1 is used to store the signal voltage applied to the gate of the drive transistor T1. The pixel circuit controls the light emission of the OLED element E1.

[0048] The selection transistor T2 is a switch (switching transistor) for selecting a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate is connected to the scan line 16. One source / drain is connected to the data line 15. The other source / drain is connected to the gate of the drive transistor T1.

[0049] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is an n-channel oxide semiconductor TFT, and its gate is connected to the source / drain of the selection transistor T2. One source / drain of the driving transistor T1 is connected to the source / drain of the emission transistor T3. The other source / drain is connected to the OLED element E1 and the storage capacitor C1. The storage capacitor C1 is located between the gate and the source / drain (source) of the driving transistor T1.

[0050] Emission transistor T3 is a switch for controlling the supply and stop of drive current to OLED element E1. Emission transistor T3 is an n-channel oxide semiconductor TFT, and its gate is connected to emission control line 17. One source / drain of emission transistor T3 is connected to the source / drain of drive transistor T1. The other source / drain is connected to power supply line 18. Emission transistor T3 can be located between OLED element E1 and drive transistor T1.

[0051] Next, the operation of the pixel circuit is described. Scan driver 31 outputs a select pulse to scan line 16 to turn on select transistor T2. The data voltage provided by driver IC 34 via data line 15 is stored in storage capacitor C1. Storage capacitor C1 maintains the stored voltage during a frame. The conductance of drive transistor T1 changes in an analog manner according to the stored voltage, causing it to provide a forward bias current corresponding to the light emission level to OLED element E1.

[0052] Emission transistor T3 is located in the drive current supply path. Emission driver 32 outputs a control signal to emission control line 17 to control the on / off switching of emission transistor T3. When emission transistor T3 is on, drive current is supplied to OLED element E1. When emission transistor T3 is off, this supply of drive current ceases. By controlling the on / off switching of transistor T3, the illumination period (duty cycle) within a frame period can be controlled.

[0053] Figure 2B Another configuration example of a pixel circuit is shown. The pixel circuit includes replacing Figure 2A The reset transistor T4 is connected to the emitting transistor T3 in the OLED. The reset transistor T4 is an n-channel oxide semiconductor TFT. The reset transistor T4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. This control is performed based on a reset control signal supplied to the gate of the reset transistor T4 from the reset control line 19. The reset transistor T4 can be used for various purposes.

[0054] Figure 2C Another configuration example of a pixel circuit is shown. The pixel circuit includes n-channel transistors T1 to T6. The gate of transistor T2 provides the Vscan2 signal, and the gates of transistors T4 and T6 provide the Vscan1 signal. A data signal (voltage) is provided to storage capacitor C1 via transistors T2, T1, and T6 to correct the threshold voltage of transistor T1. Transistor T4 provides Vref to the anode of OLED element E1. Transistors T3 and T5 are connected in series with drive transistor T1, and their gates are provided with signals Vem1 and Vem2 to control the light emission of OLED element E1.

[0055] exist Figure 2C In the circuit configuration, the gate of the driving transistor T1 is connected to the source / drain of the switching transistor T6. The storage capacitor C1 is connected to the node between the gate of the driving transistor T1 and the source / drain of the switching transistor T3 and the OLED element E1. The storage capacitor C1 stores the gate voltage (gate-source voltage) that determines the amount of drive current provided by the driving transistor T1.

[0056] The pixel circuit includes a driving TFT (T1), a storage capacitor (C1) for storing a signal voltage between the source / drain and gate of the driving TFT, and a switching TFT (T2 or T6) whose source / drain is connected to the gate of the driving TFT. Figure 2C The circuit shown further includes a transistor T3 connected in series with the driving transistor T1. The pixel circuit structure described in the present disclosure enables the driving TFT and the switching TFT to each have specific characteristics and the pixel circuit to have a smaller size, which helps to achieve higher resolution. Figure 2A 、 2BThe pixel circuit configurations in 2C and 2C are merely examples; the pixel circuit may have other circuit configurations.

[0057] Characteristics of switching TFT and driving TFT:

[0058] Figure 3A The current-voltage characteristics of the switching TFT are schematically shown. The horizontal axis represents the gate voltage (gate

[0059] -source voltage), while the vertical axis represents the drain current. Figure 3B The current-voltage characteristics of the driving TFT are schematically shown. The horizontal axis represents the gate voltage (gate-source voltage), and the vertical axis represents the drain current.

[0060] The switching TFT is turned on / off by the gate signal, so it is required to have a characteristic that the drain current increases sharply with respect to the gate voltage (low S value [V / dec]). Figure 3A When the switching TFT has a lower S value, the amplitude of the allowed operating voltage (gate voltage) becomes smaller. Therefore, the voltage applied to the gate of the TFT (stress to the TFT through the gate voltage) can be reduced, which can reduce the change in threshold voltage.

[0061] In contrast, the driver TFT used to control the amount of current flowing into the OLED element requires a characteristic in which the drain current rises slowly (a high S value). When the driver TFT has a high S value, it can use a wide range of data signals (Vdata); at lower emission levels (lower gate voltages), the impact of threshold voltage variations can be reduced.

[0062] Two factors determine the S value of a TFT. One factor is the capacitance of the gate insulating film. The S value can be increased by increasing the capacitance of the gate insulating film. The other factor is the interface trap density between the semiconductor film (channel region) and the gate insulating film. The S value can be increased by increasing the interface trap density.

[0063] Figure 4A and 4B Examples of current-voltage characteristics measured by oxide semiconductor TFTs having gate insulating films of different thicknesses are provided. Figure 4A The current-voltage characteristics of an oxide semiconductor TFT having a gate insulating film with a thickness of 200 nm are shown. Figure 4B The current-voltage characteristics of an oxide semiconductor TFT having a gate insulating film with a thickness of 350 nm are shown.

[0064] like Figure 4A As shown in FIG, the S value of an oxide semiconductor TFT having a (relatively) thin gate insulating film is 0.2 V / dec. Figure 4B As shown, the S value of an oxide semiconductor TFT with a (relatively) thick gate insulating film is 0.3 V / dec. Thickening the gate insulating film increases the capacitance of the gate insulating film. These measurement results show that the S value of an oxide semiconductor TFT can be increased by increasing the capacitance of the gate insulating film.

[0065] Figure 5A and 5B Examples of current-voltage characteristics measured using oxide semiconductor TFTs having different mobilities are provided. Figure 5A shows a relatively high mobility (mobility: μ to 30 cm 2 Current-voltage characteristics of IGZTO TFT with 100 nm CMOS / Vs). Figure 5B shows a relatively low mobility (mobility: μ to 10 cm 2 Current-voltage characteristics of IGZO TFT with 100 nm CMOS and 0.1 nm CMOS.

[0066] Figure 5B The S value of the oxide semiconductor TFT with relatively low mobility is greater than Figure 5A The S value of an oxide semiconductor TFT with relatively high mobility is shown in Figure 2. Low mobility means that the interface trap density of the oxide semiconductor film is large. Therefore, the S value of an oxide semiconductor TFT can be increased by reducing the mobility of the oxide semiconductor TFT or increasing the interface trap density.

[0067] Device structure

[0068] Based on the above knowledge, an example of a pixel circuit structure with different characteristics is described below, which includes a switching oxide semiconductor TFT (also referred to as a switching TFT) and a driving oxide semiconductor TFT (also referred to as a driving TFT).

[0069] Figure 6A Schematic diagram of an example of a cross-sectional structure of a switching oxide semiconductor TFT (first oxide semiconductor TFT) and a driving oxide semiconductor TFT (second oxide semiconductor TFT). The switching TFT 210, the driving TFT 220, and the storage capacitor 230 are fabricated on a flexible or rigid insulating substrate (not shown) made of resin or glass.

[0070] The switching TFT 210, the driving TFT 220 and the storage capacitor 230 correspond to Figure 2A and Figure 2B The selection transistor T2, the driving transistor T1 and the storage capacitor C1 in.

[0071] The driving TFT 220 includes a bottom gate electrode 153 and a bottom gate insulating layer (G insulating layer) 155 between the bottom gate electrode 153 and the metal oxide film (second metal oxide film). The metal oxide film includes source / drain regions (S / D regions) 111 and 113, and a channel region 109 between the source / drain regions 111 and 113 in the same plane. The bottom gate insulating layer 155 can be a silicon oxide layer or a laminate of a silicon oxide layer (upper layer) and a silicon nitride layer (lower layer).

[0072] The metal oxide film is directly located on (in contact with) the gate insulating layer 155. The metal oxide may be indium gallium zinc oxide (IGZO). The source / drain regions 111 and 113 are formed of a metal oxide that reduces resistance. The channel region 109 is formed of a metal oxide (semiconductor) that does not reduce resistance.

[0073] The bottom gate electrode 153 (a portion thereof) faces the channel region 109 on the bottom gate insulating layer 155. The bottom gate electrode 153, the bottom gate insulating layer 155, and the channel region 109 are arranged one above the other in this order from the bottom (the layer closer to the substrate). The gate insulating layer 155 is in contact with the channel region 109 and the bottom gate electrode 153. The portion of the bottom gate insulating layer 155 that is in contact with the bottom gate electrode 153 and the channel region 109 corresponds to the bottom gate insulating film of the driving TFT 220.

[0074] A data signal (signal voltage) is supplied to the bottom gate electrode 153 to control the driving current of the OLED element. Another portion of the bottom gate electrode 153 also faces at least a portion of the source / drain region 113 on the bottom gate insulating layer 155. A storage capacitor 230 is disposed between the source / drain region 113 and the bottom gate electrode 153. Another portion of the bottom gate electrode 153 corresponds to the lower electrode (first electrode) of the storage capacitor. The portion of the source / drain region 113 facing the lower electrode corresponds to the upper electrode (second electrode) of the storage capacitor. The storage capacitor 230 stores the signal voltage to be supplied to the bottom gate electrode 153.

[0075] The driving TFT 220 further includes a top gate electrode 125 and a gate insulating film 117 located between the top gate electrode 125 and the channel region 109 in the layered direction. The gate insulating film 117 may be a silicon oxide film, a silicon nitride film, or a laminate of these films. The channel region 109, the gate insulating film 117, and the top gate electrode 125 are arranged one above the other in this order from the bottom (the layer closer to the substrate); the gate insulating film 117 is in contact with the channel region 109 and the top gate electrode 125.

[0076] The top gate electrode 125 may be electrically floating. The top gate electrode 125 may be used as a mask (for self-alignment) when forming the source / drain regions 111 and 113. In addition, the top gate electrode 125 shields the channel 109 from external light.

[0077] The switching TFT 210 includes a metal oxide film (first metal oxide film) on the gate insulating layer 155. Figure 6A In the example of FIG, the metal oxide film is directly located on the gate insulating layer 155. The metal oxide film includes source / drain regions 105 and 107, and a channel region 103 between the source / drain regions 105 and 107 in the same plane. The metal oxide may be IGZO.

[0078] The source / drain regions 105 and 107 are formed of a metal oxide that reduces resistance. The channel region 103 is formed of a metal oxide that does not reduce resistance (high-resistance metal oxide). The metal oxide film of the switching TFT 210 is contained in the same metal oxide layer as the metal oxide film of the driving TFT 220 and is formed together.

[0079] The switching TFT 210 further includes a top gate electrode 123 and a gate insulating film 115 located between the top gate electrode 123 and the channel region 103 in the layered direction. The gate insulating film 115 may be a silicon oxide film, a silicon nitride film, or a laminate of these films. The channel region 103, the gate insulating film 115, and the top gate electrode 123 are arranged one above the other in this order from the bottom (the layer closer to the substrate); the gate insulating film 115 is in contact with the channel region 103 and the top gate electrode 123.

[0080] The gate insulating film 115 of the switching TFT 210 is included in the same insulating layer as the gate insulating film 117 of the driving TFT 220, and they are formed together. The top gate electrode 123 is included in the same metal layer as the top gate electrode 125 of the driving TFT 220, and they are formed together. Although the switching TFT 210 does not have a bottom gate electrode like the driving TFT 220, it can include a bottom gate electrode. In addition, the bottom gate electrode and the top gate electrode can be electrically connected to have the same potential.

[0081] The source / drain region 105 includes a contact 151 within a contact hole opened by the gate insulating layer 155 ; the source / drain region 105 is in contact with (directly connected to) the bottom gate electrode 153 at the contact 151 .

[0082] An interlayer insulating layer 121 is formed to cover the switching TFT 210 and the driving TFT 220. Source / drain electrodes 127, 128, and 129 are in contact with the source / drain regions 111, 113, and 107, respectively, in contact holes opened through the interlayer insulating layer 121. The source / drain electrodes 127, 128, and 129 are included in the same metal layer and are formed together.

[0083] for Figure 6AIn the configuration example shown, the characteristics of the switching TFT 210 and the driving TFT 220 can be controlled by adjusting the thickness d1 of the gate insulating film 115 of the switching TFT 210 (top) and the thickness d2 of the bottom gate insulating layer 155 of the driving TFT 220. Figure 6A As shown, the thickness d1 of the (top) gate insulating film 115 is thinner than the thickness d2 of the bottom gate insulating film 155 .

[0084] This means that the capacitance per unit area of ​​the top gate insulating film of the switching TFT 210 is greater than the capacitance per unit area of ​​the bottom gate insulating film (included in the bottom gate insulating layer 155) of the driving TFT 220. Therefore, the s value of the switching TFT 210 can be made smaller than the s value of the driving TFT 220.

[0085] Furthermore, by connecting the source / drain regions 105 of the TFT 210 and the bottom gate electrode 153 through the contact holes in the gate insulating layer 155 , the number of contact holes for connecting the switching TFT 210 and the driving TFT 220 can be reduced.

[0086] Figure 6B Another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT is schematically shown. Figure 6B The driving TFT 223 shown in FIG does not include Figure 6A The top gate electrode 125 of the driving TFT 220 is shown in FIG. 223. Similar to the driving TFT 223, the top gate electrode of the driving TFT may be omitted. Figure 6B The other components in the configuration example are the same as Figure 6A The components are the same as those in the configuration example in .

[0087] Figure 6C Another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT is schematically shown. Figure 6C The driving TFT 226 shown in FIG includes source / drain electrodes 131 connecting the top gate electrode 125 and the source / drain regions 113. The source / drain electrodes 131 maintain the top gate electrode 125 and the source / drain regions 113 at the same potential. Maintaining the top gate electrode 125 and the source / drain regions 113 at the same potential stabilizes the potential in the upper region of the channel, thereby achieving saturation characteristics more suitable for the driving TFT. Figure 6C The other components in the configuration example are the same as Figure 6A The components are the same as those in the configuration example in .

[0088] exist Figures 6A to 6C In the configuration example shown in , a portion of the bottom gate electrode 153 becomes the lower electrode of the storage capacitor, and a portion of the source / drain region 113 opposite to the lower electrode becomes the upper electrode of the storage capacitor. Figure 2CIn the pixel circuit described, the storage capacitor is located between the gate of the driving transistor T1 and the source / drain of the switching transistor T3 (the third oxide semiconductor thin film transistor). The upper electrode of the storage capacitor in this circuit configuration may include at least a portion of the source / drain region of the switching transistor T3. For example, a portion of the source / drain of the switching transistor T3 opposite to the lower electrode may become the upper electrode. The same applies to Figure 8 and 10 The configuration example shown in .

[0089] Figure 7 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT. Figure 6A The differences are mainly described as follows. Figure 7 The configuration examples in include one with Figure 6A The structure of the storage capacitor 230 in the configuration example is different from the structure of the storage capacitor 250. Figure 7 Contact 151 and Figure 6A The contacts 151 in FIG. 1 are different in appearance, but this is only a difference in the way they are drawn; the structure is the same.

[0090] Figure 7 The storage capacitor 250 in the configuration example is located between the top gate electrode 167 (a portion thereof) and the bottom gate electrode 168 (a portion thereof) of the driving TFT 240. Each curved line with filled circles at both ends thereof connects two independent bottom gate electrodes 168 or two independent top gate electrodes 167, meaning that one end is physically continued to the other end in one plane, in other words, both ends are included in one inseparable thin film.

[0091] exist Figure 7 In the illustrated configuration example, the storage capacitor 250 is composed of thin films stacked in the hole of the gate insulating layer 155. Specifically, the bottom gate electrode 168 (part thereof), the oxide semiconductor film 163, the insulating film 165, and the top gate electrode 167 (part thereof) are arranged one above the other in this order from the bottom (the layer closer to the substrate). The oxide semiconductor film 163 is in contact with the bottom gate electrode 168 and the insulating film 165. The insulating film 165 is in contact with the top gate electrode 167.

[0092] This structure of the storage capacitor 250 allows for a smaller distance between electrodes to achieve a desired capacitance in a smaller area, thereby making it possible to shrink the pixel circuit.

[0093] The oxide semiconductor film 163 is included in the same layer as the metal semiconductor film of the switching TFT 210 and the metal semiconductor film of the driving TFT 240, and these films are formed together. The insulating film 165 is included in the same layer as the (top) gate insulating film 115 of the switching TFT 210 and the (top) gate insulating film 117 of the driving TFT 240, and these films are formed together.

[0094] Figure 7 The storage capacitor 250 in this configuration example includes an oxide semiconductor film 163 formed to cover a portion of the bottom gate electrode 168. As described below, the oxide semiconductor film 163 prevents a portion of the bottom gate electrode 168 included in the storage capacitor 250 from being etched or damaged by an etchant for the oxide semiconductor film when manufacturing an OLED display device.

[0095] Figure 7 The configuration example further includes a source / drain electrode 161 connecting the top gate electrode 167 of the driving TFT 240 and the source / drain region 113. The source / drain electrode 161 maintains the top gate electrode 167 and the source / drain region 113 at the same potential. Maintaining the top gate electrode 167 and the source / drain region 113 at the same potential stabilizes the potential of the upper region of the channel to obtain a saturation characteristic more suitable for the driving TFT. The source / drain electrode 161 is optional. The same applies to Figure 9 and 10 The configuration example shown in .

[0096] Figure 8 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT. Figure 6A The differences are mainly described as follows. Figure 8 In the configuration example in , the switching TFT and the driving TFT each include a laminate of metal oxide thin films having different characteristics to achieve characteristics suitable for functions specific to the switching TFT or the driving TFT.

[0097] Figure 8 The driving TFT 270 in the configuration example includes a laminate of two metal oxide films. The lower metal oxide film includes source / drain regions (S / D regions) 311 and 313, and a channel region 309 between the source / drain regions 311 and 313 in the same plane.

[0098] The two stacked metal oxide semiconductor films in the laminate have different composition ratios. For example, the upper layer is InGaZnO with a composition ratio of In:Ga:Zn of 2:1:1, and the lower layer is InGaZnO with a composition ratio of In:Ga:Zn of 1:1:1. Their respective composition ratios are different. In this case, InGaZnO with a higher In composition ratio of 2:1:1 has higher electron mobility than InGaZnO with a lower In composition ratio of 1:1:1. This configuration allows Figure 3A and 3B Two different properties are shown.

[0099] Alternatively, the two stacked metal oxide semiconductor films may have different composition elements from each other. For example, the upper layer may be InGaZnO, and the lower layer may be ZnO. In this case, the electron mobility of InGaZnO is higher than that of ZnO. IGZTO, IGO, and IZO may also be used as the upper layer. This configuration allows Figure 3A and B show two different properties.

[0100] In these configuration examples, the lower metal oxide semiconductor film is connected to the bottom gate electrode 153. The lower metal oxide film is made of a material having (relatively) low mobility (high trap density), such as IGZO.

[0101] The upper metal oxide film includes source / drain regions (S / D regions) 411 and 413 and a channel region 409 between the source / drain regions 411 and 413 in the same plane. The upper metal oxide film is made of a material with (relatively) high mobility (low trap density), such as indium gallium zinc tin oxide (IGZTO). Metal oxides with a high indium density exhibit higher electron mobility or lower trap density. Examples of materials with high mobility include indium gallium oxide (IGO) and indium zinc oxide (IZO), and examples of materials with low mobility include zinc oxide (ZnO).

[0102] exist Figure 8 In the configuration example, the lower channel region 309 and the upper channel region 409 of the driver TFT 270 have the same planar shape. The same applies to the source / drain regions. The source / drain electrodes 127 and 128 are in contact with the source / drain regions 411 and 413 of the upper metal oxide film, respectively, in contact holes opened through the interlayer insulating layer 121.

[0103] Figure 8The switching TFT 260 in the configuration example includes a laminate of two metal oxide films. The lower metal oxide film includes source / drain regions (S / D regions) 305 and 307 and a channel region 303 between the source / drain regions 305 and 307 in the same plane. The lower metal oxide film is made of a material with (relatively) low mobility (high trap density), such as IGZO. The source / drain region 305 includes a contact 351 in a contact hole opened through the gate insulating layer 355; the source / drain region 305 is in contact with (directly connected to) the bottom gate electrode 153 at the contact 351.

[0104] The upper metal oxide film includes source / drain regions (S / D regions) 405 and 407 and a channel region 403 in the same plane between the source / drain regions 405 and 407. The upper metal oxide film is made of a material with (relatively) high mobility (low trap density), such as IGZTO.

[0105] exist Figure 8 In the configuration example of FIG, the lower channel region 303 and the upper channel region 403 of the switching TFT 260 have the same planar shape. The same applies to the source / drain regions. The source / drain electrode 129 contacts the source / drain region 407 of the upper metal oxide film in a contact hole opened through the interlayer insulating layer 121.

[0106] exist Figure 8 In the configuration example, the lower metal oxide films of the switching TFT 260 and the driving TFT 270 are included in the same metal oxide layer and are formed together. The upper metal oxide films of the switching TFT 260 and the driving TFT 270 are included in the same metal oxide layer and are formed together. The upper and lower metal oxide films of the switching TFT 260 and the driving TFT 270 are etched together to form source / drain regions together.

[0107] In the switching TFT 260, the upper channel region 403 has an interface with the (top) gate insulating film 115. The upper channel region 403 of the switching TFT 260 is made of a material having high mobility and exhibits a low s value. This interface provides the switching TFT 260 with characteristics more suitable for a switching TFT.

[0108] In the driving TFT 270, the lower channel region 309 has an interface with the bottom gate insulating layer 355. The lower channel region 309 of the driving TFT 270 is made of a material having low mobility and exhibits a high s value. This interface provides the driving TFT 270 with characteristics more suitable for a driving TFT.

[0109] Since the driving TFT 270 has a high S value in the channel region, the bottom gate insulating layer 355 can be made thinner. Therefore, the storage capacitor 280 formed between the bottom gate electrode 153 and the source / drain region 313 can have a smaller area. The channels of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT can be made of different metal oxides.

[0110] Figure 9 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT. Figure 7 The main differences are as follows. Figure 9 The storage capacitor 290 in the configuration example does not include Figure 7 The oxide semiconductor film 163 in the storage capacitor 250 is removed. Therefore, the capacitor insulating film of the storage capacitor 290 can be made thinner, thereby reducing the area of ​​the storage capacitor 290. In addition, since there is no oxide semiconductor film, the storage capacitor 290 can be stabilized.

[0111] As described above, the oxide semiconductor film 163 serves to prevent the bottom gate electrode 168 from being etched. Figure 9 In the configuration example, an OLED display device is manufactured by adjusting the amount of the bottom gate electrode 168 to be etched by the etching solution, or using a selective etching solution when etching the metal oxide layer.

[0112] Figure 10 Schematically shows another example of the cross-sectional structure of the switching oxide semiconductor TFT and the driving oxide semiconductor TFT. Figure 7 The main differences are as follows. Figure 10 The configuration example in includes a switching TFT 510 , a driving TFT 520 , and a storage capacitor 530 .

[0113] Figure 10 The configuration example in includes a bottom gate insulating film 540 including a plurality of insulating layers provided one over another. Figure 10 The gate insulating film 540 in the configuration example is composed of two insulating films, a lower insulating layer 541 and an upper insulating layer 543. The lower insulating layer 541 and the upper insulating layer 543 are located between the bottom gate electrode 168 and the channel region 109 of the driving TFT 520. Another insulating film may be included between the lower insulating layer 541 and the upper insulating layer 543.

[0114] The upper insulating layer 543 may be made of silicon oxide. The metal oxide thin films of the switching TFT 510 and the driving TFT 520 are formed directly on the upper insulating layer 543. Silicon oxide is one of the materials of the upper insulating layer 543 used to enhance the characteristics of the metal oxide thin film (oxide semiconductor). The lower insulating layer 541 is made of a material having a higher relative dielectric constant than the upper insulating layer 543. The lower insulating layer 541 may be made of silicon nitride or aluminum oxide.

[0115] The storage capacitor 530 is arranged between a portion of the bottom gate electrode 168 and a portion of the source / drain region 551 of the driver TFT 520. The upper insulating layer 543 has a hole; a portion 553 of the source / drain region 551 contacts the lower insulating layer 541 in the hole. The storage capacitor 530 is composed of a portion 553 of the source / drain region 551 (the second electrode or upper electrode), a portion of the lower insulating layer 541, and a portion of the bottom gate electrode 168 (the first electrode or lower electrode). The capacitive insulating film of the storage capacitor 530 is a layer of the lower insulating layer 541 and is made of a material with a high relative dielectric constant; thus, the storage capacitor 530 can have a smaller area.

[0116] refer to Figure 6A 、 6B , 6C, 8 and 10 include a storage capacitor between the source / drain region and the bottom gate electrode of the driving TFT. Figure 2C As shown in the circuit configuration example in FIG, the storage capacitor can be configured between the gate of the driving TFT and the source / drain region of the switching TFT directly connected to the driving TFT. Figure 6A 、 6B In the configuration examples of , 6C, 8 or 10, a portion of the bottom gate electrode is opposite to at least a portion of the source / drain region of the switching TFT on the insulating layer 155, 355 or 541.

[0117] In reference Figures 6A to 10 In the configuration examples described, some elements shown in one diagram may be applied to the configuration examples in other diagrams. Figure 7 or Figure 9 The storage capacitor structure in Figure 8 Configuration examples in . Figure 7 or Figure 9 The element shown for equalizing the potential of the top gate electrode to the potential of the source / drain region can be applied to Figure 8 Configuration examples in .

[0118] Manufacturing method

[0119] Describes a method for making Figure 7 The configuration example method is shown. Figures 11A to 11G An example of this manufacturing method is shown. For ease of understanding, Figures 11A to 11G Each of the arrowed lines indicates a range of the switching TFT 210, the contact 151, the storage capacitor 250, and the driving TFT 240 to be manufactured.

[0120] like Figure 11A As shown, the method deposits a metal layer by sputtering on an insulating substrate (not shown), and forms the bottom gate electrode 168 by photolithography and etching. A desired metal material such as Mo, W, Nb, or Al can be used.

[0121] Next, if Figure 11B As shown, the method deposits an insulating layer (e.g., a silicon oxide layer) by CVD, and forms a (bottom) gate insulating layer 155 by photolithography and etching. A hole 561 for forming the contact 151 and a hole 562 for forming the storage capacitor 250 are opened through the gate insulating layer 155.

[0122] Next, if Figure 11C As shown, this method deposits an oxide semiconductor layer (metal oxide layer) by sputtering, and forms a pattern of an oxide semiconductor 565 by photolithography and etching. A portion of the oxide semiconductor layer (oxide semiconductor film) is formed in the hole 561 and the hole 562 of the bottom gate insulating layer 155. As described above, the oxide semiconductor film 163 in the hole 562 covers the bottom gate electrode 168 to prevent the bottom gate electrode 168 from being exposed to the etching solution.

[0123] Next, if Figure 11D As shown, the method deposits an insulating layer (e.g., a silicon oxide layer) by CVD, and forms the top gate insulating films 115 and 117 and the insulating film 165 of the storage capacitor by photolithography and etching. In addition, the method deposits a metal layer by sputtering, and forms the top gate electrodes 123 and 167 by photolithography and etching. A desired metal material such as Mo, W, Nb, or Al can be used.

[0124] Next, if Figure 11E As shown, this method uses the top gate electrodes 123 and 167 as masks to reduce the resistance of the source / drain regions of the oxide semiconductor layer. The resistance is reduced by exposing the source / drain regions of the oxide semiconductor layer to helium plasma. Alternatively, the resistance can be reduced by implanting boron, argon, or hydrogen ions.

[0125] Next, if Figure 11F As shown, the method deposits an insulating layer (eg, a silicon oxide layer) by CVD, and forms an interlayer insulating layer 121 by photolithography and etching.

[0126] Next, if Figure 11GAs shown, the method deposits a metal layer by sputtering and forms a metal layer including source / drain electrodes 161 by photolithography and etching. The metal layer includes the source / drain electrodes of the TFTs in the pixel circuit and the data line. The material and layer structure of the metal layer can be selected as desired; for example, the metal layer is formed by depositing a Ti / Al / Ti conductive film and patterning the conductive film.

[0127] The method further deposits an insulating layer (e.g., a silicon oxide layer) by CVD, forms a passivation layer 571 by photolithography and etching, and further forms an overcoat layer 573 of an organic material. An anode 577 is formed on the overcoat layer 573 and contacts the source / drain 161 through a contact hole opened through the passivation layer 571 and the overcoat layer 573.

[0128] The anode 577 may include three thin films: a transparent conductive film, a reflective metal film, and another transparent conductive film. The transparent conductive material may be ITO or IZO. The reflective metal material may be Ag, Mg, or Al. The anode 577 may be formed by sputtering and etching.

[0129] This method further deposits a photosensitive organic resin film by spin coating and patterns the photosensitive organic resin film to form a pixel defining layer 579. Apertures are formed in the pixel defining layer 579, exposing the anode 577 at the bottom of the openings. The pixel defining layer 579 separates the light-emitting regions of the sub-pixels. The TFT substrate 10 is manufactured by depositing organic light-emitting materials of R, G, and B colors, respectively, to form an organic light-emitting film (not shown) on the anode, and further forming a cathode (not shown) over the entire substrate area.

[0130] The embodiments of the present disclosure have been described above; however, the present disclosure is not limited to the above embodiments. Those skilled in the art can easily modify, add, or convert each element in the above embodiments within the scope of the present disclosure. Part of the configuration of one embodiment can be replaced with the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A thin film device comprising: a first oxide semiconductor thin film transistor comprising a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide thin film; a second oxide semiconductor thin film transistor comprising a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide thin film; a bottom gate insulating layer, comprising the bottom gate insulating film; as well as a storage capacitor configured to store a signal voltage applied to the bottom gate electrode, Wherein, the first metal oxide film includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region; Wherein, the second metal oxide film includes a second source region, a second drain region and a second channel region located between the second source region and the second drain region; wherein the first electrode of the storage capacitor includes a portion of the bottom gate electrode; wherein one of the first source region and the first drain region is in direct contact with the bottom gate electrode in the contact hole of the bottom gate insulating layer; Among them, the unit area capacitance of the bottom gate insulating film is smaller than the unit area capacitance of the top gate insulating film. wherein the bottom gate insulating film is thicker than the top gate insulating film, Wherein, the second oxide semiconductor thin film transistor further includes a top gate electrode; The top gate electrode of the second oxide semiconductor thin film transistor is connected to one of the second source region and the second drain region of the second oxide semiconductor thin film transistor, so that the top gate electrode and the one of the second source region and the second drain region connected thereto have the same potential, and The storage capacitor comprises the following structure, wherein: a metal oxide thin film included in the same layer as the first metal oxide thin film and the second metal oxide thin film and located over and in contact with a portion of the bottom gate electrode; an insulating film included in the same layer as the top gate insulating film and located above and in contact with the metal oxide film; and A portion of the top gate electrode of the second oxide semiconductor thin film transistor that is located above and in contact with the insulating film.

2. The thin film device according to claim 1, wherein Each of the first source region, the first drain region, the second source region, and the second drain region is a metal oxide that reduces resistance.

3. A thin film device comprising: a first oxide semiconductor thin film transistor comprising a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide thin film; a second oxide semiconductor thin film transistor comprising a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide thin film; a bottom gate insulating layer, comprising the bottom gate insulating film; as well as a storage capacitor configured to store a signal voltage applied to the bottom gate electrode, Wherein, the first metal oxide film includes a first source region, a first drain region and a first channel region located between the first source region and the first drain region; Wherein, the second metal oxide film includes a second source region, a second drain region and a second channel region located between the second source region and the second drain region; wherein the first electrode of the storage capacitor includes a portion of the bottom gate electrode; wherein one of the first source region and the first drain region is in direct contact with the bottom gate electrode in the contact hole of the bottom gate insulating layer; Among them, the unit area capacitance of the bottom gate insulating film is smaller than the unit area capacitance of the top gate insulating film. wherein the bottom gate insulating film is thicker than the top gate insulating film, Wherein, the second oxide semiconductor thin film transistor further includes a top gate electrode; The top gate electrode of the second oxide semiconductor thin film transistor is connected to one of the second source region and the second drain region of the second oxide semiconductor thin film transistor, so that the top gate electrode and the one of the second source region and the second drain region connected thereto have the same potential, and The storage capacitor comprises the following structure, wherein: an insulating film included in the same layer as the top gate insulating film of the first oxide semiconductor thin film transistor and located over and in contact with a portion of the bottom gate electrode; and A portion of the top gate electrode of the second oxide semiconductor thin film transistor that is located above and in contact with the insulating film.

4. A thin film device comprising: a first oxide semiconductor thin film transistor comprising a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide thin film; a second oxide semiconductor thin film transistor comprising a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide thin film; a bottom gate insulating layer, comprising the bottom gate insulating film; as well as a storage capacitor configured to store a signal voltage applied to the bottom gate electrode, Wherein, the first metal oxide film includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region; Wherein, the second metal oxide film includes a second source region, a second drain region and a second channel region located between the second source region and the second drain region; wherein the first electrode of the storage capacitor includes a portion of the bottom gate electrode; wherein one of the first source region and the first drain region is in direct contact with the bottom gate electrode in the contact hole of the bottom gate insulating layer; Among them, the unit area capacitance of the bottom gate insulating film is smaller than the unit area capacitance of the top gate insulating film. wherein the bottom gate insulating film is thicker than the top gate insulating film, Wherein, the second oxide semiconductor thin film transistor further includes a top gate electrode; The top gate electrode of the second oxide semiconductor thin film transistor is connected to one of the second source region and the second drain region of the second oxide semiconductor thin film transistor, so that the top gate electrode and the one of the second source region and the second drain region connected thereto have the same potential, and Wherein, the bottom gate insulating layer includes a lower insulating layer and an upper insulating layer; Wherein, the bottom gate insulating film includes a portion of the upper insulating layer and a portion of the lower insulating layer; wherein the relative dielectric constant of the lower insulating layer is higher than the relative dielectric constant of the upper insulating layer; and The storage capacitor includes a structure comprising a portion of the lower insulating layer located above and in contact with a portion of the bottom gate electrode and a second electrode located above and in contact with a portion of the lower insulating layer.

5. The thin film device according to claim 4, wherein: The second electrode of the storage capacitor includes at least a portion of one of the second source region and the second drain region.

6. The thin film device according to claim 4, wherein: The second electrode of the storage capacitor includes at least a portion of one of a third source region and a third drain region of a third oxide semiconductor thin film transistor connected in series with the first oxide semiconductor thin film transistor.

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