Method and structure for integrating dual-gate JFET device in bipolar junction transistor process

Abstract

The invention discloses a method and a structure for integrating a double-gate JFET (junction field effect transistor) device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming a buried layer structure, an epitaxial layer and an isolation structure of the bipolar junction transistor and the JFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, etching to form a base region window, and forming a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region through the base region window; s500, forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes of the bipolar junction transistor and the JFET device on the dielectric layer. According to the invention, the high-speed bipolar junction transistor and the JFET device can be integrated in a single manufacturing process under the condition that a large amount of process complexity is not increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and structure for integrating a dual-gate JFET device in a bipolar junction transistor process. Background Technology

[0002] High-precision JFET operational amplifiers manufactured using modern BiFET bipolar technology feature low noise, high input impedance, low temperature drift, and low input bias current, making them suitable for signal amplification in electronic systems. Currently, domestic bipolar technology platforms offering JFET operational amplifiers with polysilicon resistors (≤100ppm), low bias current (≤50pA), and low offset voltage (≤1mV) all utilize BiFET bipolar technology with polysilicon resistors and JFETs, which lags behind international standards. Whether it's the urgent need for independent and controllable manufacturing and safe production of components in next-generation weaponry, or the civilian market sectors such as automotive electronics, medical electronics, and instrumentation, JFET operational amplifiers have a vast market potential. Currently, the industrial-grade market is mainly monopolized by large international companies such as TI and ADI, with a global market share exceeding $1 billion and annual domestic procurement of approximately 500 million yuan. Therefore, there is a broad market demand for this series of high-precision JFET op-amp products.

[0003] The manufacturing process of these products integrates high-performance characteristics such as high voltage, high speed, high precision, and low bias. Specifically, it requires the simultaneous integration of multiple high-performance special process devices such as JFET devices and bipolar junction transistors in a single manufacturing process, which places extremely high demands on the manufacturing technology and poses a huge challenge to the integration of process devices. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method and structure for simultaneously integrating high-speed bipolar junction transistors and JFET devices in a single manufacturing process without increasing the complexity of the process.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a method for integrating a dual-gate JFET device in a bipolar junction transistor process, comprising the following steps: S100. Provide a substrate and form a buried layer structure, an epitaxial layer, and an isolation structure for the bipolar junction transistor and JFET device on the substrate. S200, Penetration doping and well region doping are performed in the epitaxial layer, and a field oxygen layer is selectively formed above the epitaxial layer to define the active region and the field region; S300, A collector crystal region and a base crystal region of a bipolar junction transistor, as well as a bottom gate crystal region, a top gate crystal region, a source crystal layer, and a drain crystal region of a JFET device are formed above the epitaxial layer. S400, a dielectric layer is deposited above the epitaxial layer, and a base region window is etched to form it; a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, and a source region and a drain region are formed by implantation and annealing of the base region window. S500: Form an emitter window and form an emitter crystal region of a bipolar junction transistor in the emitter window; S600, forming electrodes for bipolar junction transistors and JFET devices on the dielectric layer.

[0006] Furthermore, step S100 includes the following sub-steps: A substrate is provided, the substrate including a lower silicon layer, a first oxide layer and an upper silicon layer; a bipolar device region for forming a bipolar junction transistor and a JFET device region for forming a JFET device are defined on the substrate; A first buried layer of the first doping type is formed in the bipolar device region corresponding to the upper silicon layer, and a second buried layer of the first doping type is formed in the JFET device region corresponding to the JFET device region. An epitaxial layer is formed on the upper end of the upper silicon layer; A fully dielectric island isolation is formed between the bipolar device region and the JFET device region. The fully dielectric island isolation penetrates the epitaxial layer and the upper silicon layer and is connected to the first oxide layer.

[0007] Furthermore, step S200 includes the following sub-steps: A pre-oxidized layer is grown above the epitaxial layer, and a mask layer is deposited above the pre-oxidized layer; In the epitaxial layer, a bipolar device penetration doping region of the first doping type connected to the first buried layer and a JFET device penetration doping region of the first doping type connected to the second buried layer are formed by ion implantation and annealing processes. A second-doped well region is formed in the JFET device region; A field oxide layer is formed on the epitaxial layer through a local oxidation process, thereby simultaneously defining the active region and the field region in the bipolar device region and the JFET device region.

[0008] Furthermore, step S300 includes the following sub-steps: A first crystalline layer is deposited on the upper surface of the field oxide layer and the pre-oxidation layer, and a first type of doping is implanted on the first crystalline layer to form a collector crystalline region in the bipolar device region and a bottom gate crystalline region and a top gate crystalline region in the JFET device region. A second type of doping is performed on the first crystal layer to form a base crystal region in the bipolar device region and a source crystal region and a drain crystal region in the JFET device region. The excess first crystal layer is removed by etching.

[0009] Furthermore, step S400 includes the following sub-steps: A dielectric layer is deposited above the epitaxial layer, and the base region window of the bipolar junction transistor is formed by etching. A second oxide layer is grown on the surface of the base region window; A second-type doped inner base region is formed by implantation at the bottom of the base region window using an implantation process; Annealing allows the two types of dopants in the first crystalline layer to diffuse into the substrate, forming a heavily doped outer base region of the second doping type on both sides of the inner base region, and forming a heavily doped collector region, a heavily doped bottom gate, a heavily doped top gate of the first doping type, and a source region and a drain region of the second doping type.

[0010] Furthermore, step S500 includes the following sub-steps: An L-shaped sidewall structure is formed by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and an emission region window is obtained by etching the second oxide layer. A second crystalline layer is deposited within the emitter window to form the emitter region of a bipolar junction transistor through an implantation process; The emitter crystal region is formed through an etching process; The heavily doped emitter region of the first doping type is formed by annealing.

[0011] Furthermore, step S600 includes the following sub-steps: Holes are made on the dielectric layer at positions corresponding to the collector crystal region, base crystal region, source crystal region, drain crystal region, bottom gate crystal region, and top gate crystal region to obtain collector contact holes, base contact holes, source contact holes, drain contact holes, bottom gate contact holes, and top gate contact holes. A collector contact is formed in the collector contact hole, a base contact is formed in the base contact hole, an emitter contact is formed in the emitter contact hole, a source contact is formed in the source contact hole, a drain contact is formed in the drain contact hole, a bottom gate contact is formed in the bottom gate contact hole, a top gate contact is formed in the top gate contact hole, and an emitter contact is formed on the emitter crystal region. A metal layer is deposited to form a collector electrode that is in contact with the collector electrode, a base electrode that is in contact with the base electrode, an emitter electrode that is in contact with the emitter electrode, a source electrode that is in contact with the source electrode, a drain electrode that is in contact with the drain electrode, a bottom gate electrode that is in contact with the bottom gate electrode, and a top gate electrode that is in contact with the top gate electrode.

[0012] Furthermore, the step of forming an L-shaped sidewall structure by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and obtaining the emission region window by etching the second oxide layer, includes the following sub-steps: Silicon nitride is deposited on the inner surface of the second oxide layer to form a silicon nitride layer, and an amorphous deposition is performed on the surface of the silicon nitride layer to form a sacrificial layer; The sacrificial layer at the bottom of the base window is removed by dry etching of polysilicon, the silicon nitride layer at the bottom of the base window is removed by dry etching of silicon nitride, and the sacrificial layer on the sidewall of the base window is removed by wet etching of polysilicon, forming two symmetrical L-shaped sidewall structures. The exposed second oxide layer at the bottom of the two sidewall structures is etched to obtain the emission area window.

[0013] Furthermore, the first doping type and the second doping type refer to opposite doping types, where the first doping type is N-type doping and the second doping type is P-type doping; or The first doping type is P-type doping, and the second doping type is N-type doping.

[0014] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a structure for integrating a dual-gate JFET device in a bipolar junction transistor process, which is fabricated using the method described above for integrating a dual-gate JFET device in a bipolar junction transistor process.

[0015] The method and structure for integrating dual-gate JFET devices in a bipolar junction transistor (BJT) process of the present invention have at least the following beneficial effects: The present invention innovatively integrates the BJT process and the JFET process to form a unified and concise process flow. Compared with the traditional separate fabrication and integration scheme, the number of process steps is reduced, the number of photomasks is decreased, significantly improving manufacturing efficiency and reducing process complexity. Two types of high-performance semiconductor devices, BJTs and dual-gate JFETs, are simultaneously integrated in a single manufacturing process, overcoming the technical bottleneck of difficulty in achieving high speed, high precision, and low noise characteristics in traditional processes. Through innovative process sequence design, while maintaining the high transconductance and high speed advantages of BJTs, the excellent characteristics of high input impedance and low bias current of JFETs are incorporated, providing an ideal device foundation for high-end analog integrated circuit design. The heavily doped collector region of the BJT and the heavily doped gate region of the JFET can be formed simultaneously, with small deviations in doping uniformity, significantly improving device parameter consistency. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a process flow diagram of one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0017] Figure 2 This is a cross-sectional schematic diagram of the substrate after pretreatment in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0018] Figure 3 This is a cross-sectional schematic diagram after the formation of the well region in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0019] Figure 4 This is a cross-sectional schematic diagram after the formation of the field oxide layer in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0020] Figure 5 This is a cross-sectional schematic diagram after the formation of the first crystallization layer in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0021] Figure 6 This is a cross-sectional schematic diagram of the electrode crystal regions obtained by doping and implanting on the first crystal layer in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0022] Figure 7 This is a cross-sectional schematic diagram after removing excess first crystal layer in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0023] Figure 8 This is a cross-sectional schematic diagram after forming the base region window in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0024] Figure 9 This is a cross-sectional schematic diagram of a method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention, after forming a heavily doped outer base region, a heavily doped collector region, a heavily doped bottom gate, a heavily doped top gate, a source region, and a drain region.

[0025] Figure 10 This is a cross-sectional schematic diagram after forming the emitter window in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0026] Figure 11 This is a cross-sectional schematic diagram after the formation of the heavily doped emitter region in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0027] Figure 12 This is a cross-sectional schematic diagram after the formation of each electrode structure in one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor process according to the present invention.

[0028] The meanings of the labels in the attached diagram are as follows: Lower silicon layer 100; First oxide layer 101; Upper silicon layer 102; First buried layer 103; Second buried layer 104; Epitaxial layer 105; Trench isolation oxide layer 106; Trench isolation polysilicon 107; Bipolar device through-doped region 108; JFET device through-doped region 109; Pre-oxide layer 110; Mask layer 111; Well region 112; Field oxide layer 113; Collector crystal region 114; Base crystal region 117; Bottom gate crystal region 115; Top gate crystal region 116; Source crystal region 118; Drain crystal region 119; dielectric layer 120; second oxide layer 121; heavily doped collector region 122; heavily doped outer base region 123; heavily doped bottom gate 124; heavily doped top gate 126; source region 125; drain region 127; inner base region 128; sidewall structure 129; emitter crystal region 130; heavily doped emitter region 131; collector electrode 132; base electrode 133; emitter electrode 134; bottom gate electrode 135; top gate electrode 137; source electrode 136; drain electrode 138; and first crystal layer 139. Detailed Implementation

[0029] The invention will now be further described with reference to the accompanying drawings.

[0030] Please see Figure 1 This is a flowchart of one embodiment of the method for integrating a dual-gate JFET device in a bipolar junction transistor (BJT) process according to the present invention. This embodiment includes the following steps: S100. Provide a substrate and perform pretreatment. Provide a substrate, and form on the substrate a buried layer structure for a bipolar junction transistor and a JFET device, an epitaxial layer 105, and an isolation structure for the bipolar junction transistor and the JFET device. For details, please refer to [link to relevant documentation]. Figure 2 This step may include the following sub-steps: S101. A substrate is provided. Specifically, the substrate includes a lower silicon layer 100, a first oxide layer 101, and an upper silicon layer 102. A bipolar device region for forming a bipolar junction transistor and a JFET device region for forming a JFET device are defined on the substrate. In this embodiment, the materials of the lower silicon layer 100 and the upper silicon layer 102 are preferably SOI silicon, and the material of the SOI silicon substrate may include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0031] S102, Forming a first buried layer 103 and a second buried layer 104. Specifically, using a photomask, a first buried layer 103 of a first doping type is formed in the bipolar device region corresponding to the upper silicon layer 102, and a second buried layer 104 of a first doping type is formed in the JFET device region. When the formed bipolar junction transistor is an NPN transistor, the formed JFET device is a PJFET device, and the first doping type is N-type; when the formed bipolar junction transistor is a PNP transistor, the formed JFET device is an NJFET device, and the first doping type is P-type.

[0032] S103. Form an epitaxial layer 105. Specifically, an epitaxial layer 105 is formed on the upper end of the upper silicon layer 102.

[0033] S104. Forming a full dielectric island isolation. Specifically, a photomask is used to form a full dielectric island isolation between the isolation bipolar device region and the JFET device region. The full dielectric island isolation penetrates the epitaxial layer 105 and the upper silicon layer 102 and is connected to the first oxide layer 101. The full dielectric island isolation includes a trench isolation oxide layer 106 and trench isolation polysilicon 107 filled in the trenches formed by the trench isolation oxide layer 106. The trench isolation oxide layer 106 is connected to the first oxide layer 101.

[0034] S200: Complete penetration doping and well doping, and distinguish between the active region and the field region. Penetration doping and well doping are performed in the epitaxial layer 105, and a field oxide layer 113 is selectively formed above the epitaxial layer 105 to define the active region and the field region. For details, please refer to... Figure 3 and Figure 4 This step may include the following sub-steps: S201. Grow a pre-oxide layer 110 and deposit a mask layer 111. Specifically, a pre-oxide layer 110 is grown above the epitaxial layer 105, and a mask layer 111 is deposited above the pre-oxide layer 110. First, a pre-oxide layer 110 is grown on the epitaxial layer 105 by thermo-oxidation, and then a mask layer 111 is deposited on the pre-oxide layer 110. The material of the mask layer 111 is preferably silicon nitride.

[0035] S202, Forming a bipolar device through-doped region 108 and a JFET device through-doped region 109. Specifically, using a photomask, a first-doped bipolar device through-doped region 108 connected to the first buried layer 103 and a first-doped JFET device through-doped region 109 connected to the second buried layer 104 are formed in the epitaxial layer 105 by ion implantation and annealing processes.

[0036] S203. Forming well region 112. Specifically, using a photomask, a well region 112 of a second doping type is formed in the JFET device region. The first doping type is opposite to the second doping type; when the first doping type is N-type, the second doping type is P-type; when the first doping type is P-type, the second doping type is N-type.

[0037] S204. Forming the field oxide layer 113. Specifically, using a photomask, a selectively oxidized field oxide layer 113 is formed on the epitaxial layer 105 through a local oxidation process. Excess mask layer 111 and pre-oxidized layer 110 are removed; the specific removal process can be rinsing. Based on the field oxide layer 113, active and field regions are simultaneously defined in the bipolar device region and the JFET device region. The area covered by the field oxide layer 113 is the field region, and the area not covered by the field oxide layer 113 is the active region.

[0038] S300: Crystallization regions are formed for the electrodes of the bipolar junction transistor (BJT) and the JFET device. Above the epitaxial layer 105, a collector crystallization region 114 and a base crystallization region 117 for the BJT are formed, as well as a bottom gate crystallization region 115, a top gate crystallization region 116, a source crystallization layer, and a drain crystallization region 119 for the JFET device. For details, please refer to [link to documentation]. Figures 5 to 7 This step may include the following sub-steps: S301. Forming the collector crystal region 114, the bottom gate crystal region 115, and the top gate crystal region 116. Specifically, a first crystal layer 139 is deposited on the upper surface of the field oxide layer 113 and the pre-oxidation layer 110. A first doping type is then performed on the first crystal layer 139 to form the collector crystal region 114 in the bipolar device region and the bottom gate crystal region 115 and the top gate crystal region 116 in the JFET device region. The first crystal layer 139 can be a novel semiconductor conductive material such as polysilicon or germanium-silicon. In this embodiment, the first crystal layer 139 is polysilicon, the collector crystal region 114 is a polysilicon collector, the bottom gate crystal region 115 is a polysilicon bottom gate, and the top gate crystal region 116 is a polysilicon top gate. In this embodiment, general doping is performed before using a photomask for the first doping type.

[0039] S302. Forming a base crystal region 117, a source crystal region 118, and a drain crystal region 119. Specifically, a second type of doping is performed on the first crystal layer 139 using a photomask to form the base crystal region 117 in the bipolar device region, and the source crystal region 118 and the drain crystal region 119 in the JFET device region. In this embodiment, the base crystal region 117 is a polysilicon base, the source crystal region 118 is a polysilicon source, and the drain crystal region 119 is a polysilicon drain.

[0040] S303. Remove excess first crystalline layer 139 by etching. In this embodiment, the etching process is preferably dry etching.

[0041] S400, Doping is advanced through the base region window. A dielectric layer 120 is deposited above the epitaxial layer 105, and a base region window is etched to form it. Through implantation and annealing of the base region window, a heavily doped collector region 122, a heavily doped outer base region 123, a heavily doped bottom gate 124, a heavily doped top gate 126, and a source region 125 and a drain region 127 are formed. For details, please refer to [link to relevant documentation]. Figure 8 and Figure 9 This step may include the following sub-steps: S401. Forming the base region window. Specifically, a dielectric layer 120 is deposited above the epitaxial layer 105, and the base region window of the bipolar junction transistor is formed by etching. In this embodiment, the dielectric layer 120 can be USG or TEOS. The pre-oxide layer 110 and the polycrystalline base crystal region 117 are removed by dry etching using a photomask to form the base region window of the bipolar junction transistor, and two base crystal regions 117 are formed on both sides of the base region window.

[0042] S402. Grow a second oxide layer 121. Specifically, a second oxide layer 121 is grown on the surface of the base region window. The second oxide layer 121 is a thin sidewall oxide layer.

[0043] S403, Forming the inner base region 128. Specifically, a second-doped inner base region 128 is formed at the bottom of the base region window using a photomask implantation process.

[0044] S404, Doping Diffusion. Specifically, through base region annealing, the two types of dopants in the first crystal layer 139 diffuse into the substrate; that is, the N / P type dopants previously implanted by the polycrystalline silicon diffuse into the single-crystal silicon. A heavily doped outer base region 123 of the second doping type is formed on both sides of the inner base region 128. The outer base region is connected to the inner base region 128 through polycrystalline silicon to form a dual base region. Simultaneously, a heavily doped collector region 122, a heavily doped bottom gate 124, and a heavily doped top gate 126 of the first doping type, as well as a source region 125 and a drain region 127 of the second doping type are also formed.

[0045] S500, Forming the emitter crystal region 130. An emitter window is formed, and the emitter crystal region 130 of the bipolar junction transistor is formed within the emitter window. For details, please refer to [link to relevant documentation]. Figure 10 and Figure 11 This step may include the following sub-steps: S501. An L-shaped sidewall structure 129 is formed by performing multiple deposition, etching, and etching processes on the inner surface of the second oxide layer 121. The emitter window is obtained by etching the second oxide layer 121. Specifically, silicon nitride is deposited on the inner surface of the second oxide layer 121 to form a silicon nitride layer. An amorphous deposition is performed on the surface of the silicon nitride layer to form a sacrificial layer (not shown in the figure). The sacrificial layer at the bottom of the base window is removed by polysilicon dry etching, the silicon nitride layer at the bottom of the base window is removed by silicon nitride dry etching, and the sacrificial layer on the sidewall of the base window is removed by polysilicon wet etching, forming two symmetrical L-shaped sidewall structures 129. The exposed second oxide layer 121 at the bottom of the two sidewall structures 129 is etched to obtain the emitter window.

[0046] S502. A second crystalline layer is deposited within the emitter window, and the emitter region of the bipolar junction transistor is formed by implantation. In this embodiment, the material of the second crystalline layer is preferably polycrystalline silicon, and the emitter region of the bipolar junction transistor is formed by implantation on the second crystalline layer using a photomask.

[0047] S503. The emitter crystal region 130 is formed by etching. Specifically, a photomask is used to perform dry etching on the emitter region to etch out excess polysilicon to form a polysilicon emitter (i.e., emitter crystal region 130) of a bipolar junction transistor.

[0048] S504, The first type of heavily doped emitter region 131 is formed by annealing.

[0049] S600: Forming the electrode structures for the bipolar junction transistor and JFET device. Electrodes for the bipolar junction transistor and JFET device are formed on the dielectric layer 120. For details, please refer to... Figure 12 This step may include the following sub-steps: S601. Holes are drilled on the dielectric layer 120 at positions corresponding to the collector crystal region 114, base crystal region 117, source crystal region 118, drain crystal region 119, bottom gate crystal region 115, and top gate crystal region 116, respectively, to obtain collector contact holes, base contact holes, source contact holes, drain contact holes, bottom gate contact holes, and top gate contact holes. It should be noted that since there are two base crystal regions 117, holes are drilled corresponding to the two base crystal regions 117 to obtain two base contact holes, and correspondingly, two base contacts and two base electrodes 133 are formed in steps S602 and S603, respectively.

[0050] S602. A collector contact is formed in the collector contact hole, a base contact is formed in the base contact hole, an emitter contact is formed in the emitter contact hole, a source contact is formed in the source contact hole, a drain contact is formed in the drain contact hole, a bottom gate contact is formed in the bottom gate contact hole, a top gate contact is formed in the top gate contact hole, and an emitter contact is formed on the emitter crystal region 130.

[0051] Electrode contact structures can be formed using different processes. For example, this embodiment uses a tungsten plug process to form ohmic contacts. Specifically: First, a titanium metal adhesion layer is deposited on the surface of the dielectric layer 120 after the contact hole etching has been completed using a physical vapor deposition process; then, a titanium nitride barrier layer is deposited; rapid thermal annealing is performed to form titanium silicide on the silicon or polysilicon surface at the bottom of the contact hole, effectively reducing contact resistance; isotropic deposition is performed using a tungsten chemical vapor deposition process to completely fill the contact hole; excess metal layers outside the contact hole are removed by chemical mechanical polishing or dry etching processes to form a complete tungsten plug structure within the contact hole.

[0052] S603, depositing a metal layer and etching to form a collector electrode 132, a base electrode 133, an emitter electrode 134, a source electrode 136, a drain electrode 138, a bottom gate electrode 135, and a top gate electrode 137.

[0053] The present invention also discloses a structure for integrating a dual-gate JFET device in a bipolar junction transistor process. The structure for integrating a dual-gate JFET device in a bipolar junction transistor process can be fabricated using the method for integrating a dual-gate JFET device in a bipolar junction transistor process described in the above embodiments.

[0054] This invention innovatively integrates bipolar junction transistor (BJT) and JFET (Jet Electron Field Test) processes to form a unified and streamlined process flow. Compared to traditional separate fabrication and integration schemes, this reduces the number of process steps and photomasks, significantly improving manufacturing efficiency and reducing process complexity. It integrates two high-performance semiconductor devices—BJTs and dual-gate JFETs—in a single manufacturing process, overcoming the technical bottleneck of traditional processes that struggle to balance high speed, high precision, and low noise. Through innovative process sequence design, it maintains the high transconductance and high speed advantages of BJTs while incorporating the high input impedance and low bias current characteristics of JFETs, providing an ideal device foundation for high-end analog integrated circuit design. The heavily doped collector region of the BJT and the heavily doped gate region of the JFET can be formed simultaneously, resulting in minimal doping uniformity deviation and significantly improving device parameter consistency.

[0055] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A method for integrating a dual-gate JFET device in a bipolar junction transistor process, characterized in that, Includes the following steps: S100. Provide a substrate and form a buried layer structure, an epitaxial layer, and an isolation structure for the bipolar junction transistor and JFET device on the substrate. S200, Penetration doping and well region doping are performed in the epitaxial layer, and a field oxygen layer is selectively formed above the epitaxial layer to define the active region and the field region; S300, A collector crystal region and a base crystal region of a bipolar junction transistor, as well as a bottom gate crystal region, a top gate crystal region, a source crystal layer, and a drain crystal region of a JFET device are formed above the epitaxial layer. S400, a dielectric layer is deposited above the epitaxial layer, and a base region window is etched to form it; a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, and a source region and a drain region are formed by implantation and annealing of the base region window. S500: Form an emitter window and form an emitter crystal region of a bipolar junction transistor in the emitter window; S600, forming electrodes for bipolar junction transistors and JFET devices on the dielectric layer.

2. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 1, characterized in that, Step S100 includes the following sub-steps: A substrate is provided, the substrate including a lower silicon layer, a first oxide layer and an upper silicon layer; a bipolar device region for forming a bipolar junction transistor and a JFET device region for forming a JFET device are defined on the substrate; A first buried layer of the first doping type is formed in the bipolar device region corresponding to the upper silicon layer, and a second buried layer of the first doping type is formed in the JFET device region corresponding to the JFET device region. An epitaxial layer is formed on the upper end of the upper silicon layer; A fully dielectric island isolation is formed between the bipolar device region and the JFET device region. The fully dielectric island isolation penetrates the epitaxial layer and the upper silicon layer and is connected to the first oxide layer.

3. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 2, characterized in that, Step S200 includes the following sub-steps: A pre-oxidized layer is grown above the epitaxial layer, and a mask layer is deposited above the pre-oxidized layer; In the epitaxial layer, a bipolar device penetration doping region of the first doping type connected to the first buried layer and a JFET device penetration doping region of the first doping type connected to the second buried layer are formed by ion implantation and annealing processes. A second-doped well region is formed in the JFET device region; A field oxide layer is formed on the epitaxial layer through a local oxidation process, thereby simultaneously defining the active region and the field region in the bipolar device region and the JFET device region.

4. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 3, characterized in that, The S300 step includes the following sub-steps: A first crystalline layer is deposited on the upper surface of the field oxide layer and the pre-oxidation layer, and a first type of doping is implanted on the first crystalline layer to form a collector crystalline region in the bipolar device region and a bottom gate crystalline region and a top gate crystalline region in the JFET device region. A second type of doping is performed on the first crystal layer to form a base crystal region in the bipolar device region and a source crystal region and a drain crystal region in the JFET device region. The excess first crystal layer is removed by etching.

5. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 1, characterized in that, The S400 step includes the following sub-steps: A dielectric layer is deposited above the epitaxial layer, and the base region window of the bipolar junction transistor is formed by etching. A second oxide layer is grown on the surface of the base region window; A second-type doped inner base region is formed by implantation at the bottom of the base region window using an implantation process; Annealing allows the two types of dopants in the first crystalline layer to diffuse into the substrate, forming a heavily doped outer base region of the second doping type on both sides of the inner base region, and forming a heavily doped collector region, a heavily doped bottom gate, a heavily doped top gate of the first doping type, and a source region and a drain region of the second doping type.

6. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 5, characterized in that, The S500 step includes the following sub-steps: An L-shaped sidewall structure is formed by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and an emission region window is obtained by etching the second oxide layer. A second crystalline layer is deposited within the emitter window to form the emitter region of a bipolar junction transistor through an implantation process; The emitter crystal region is formed through an etching process; The heavily doped emitter region of the first doping type is formed by annealing.

7. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 5, characterized in that, The S600 step includes the following sub-steps: Holes are made on the dielectric layer at positions corresponding to the collector crystal region, base crystal region, source crystal region, drain crystal region, bottom gate crystal region, and top gate crystal region to obtain collector contact holes, base contact holes, source contact holes, drain contact holes, bottom gate contact holes, and top gate contact holes. A collector contact is formed in the collector contact hole, a base contact is formed in the base contact hole, an emitter contact is formed in the emitter contact hole, a source contact is formed in the source contact hole, a drain contact is formed in the drain contact hole, a bottom gate contact is formed in the bottom gate contact hole, a top gate contact is formed in the top gate contact hole, and an emitter contact is formed on the emitter crystal region. A metal layer is deposited to form a collector electrode that is in contact with the collector electrode, a base electrode that is in contact with the base electrode, an emitter electrode that is in contact with the emitter electrode, a source electrode that is in contact with the source electrode, a drain electrode that is in contact with the drain electrode, a bottom gate electrode that is in contact with the bottom gate electrode, and a top gate electrode that is in contact with the top gate electrode.

8. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 6, characterized in that, The step of forming an L-shaped sidewall structure by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and obtaining the emission region window by etching the second oxide layer, includes the following sub-steps: Silicon nitride is deposited on the inner surface of the second oxide layer to form a silicon nitride layer, and an amorphous deposition is performed on the surface of the silicon nitride layer to form a sacrificial layer; The sacrificial layer at the bottom of the base window is removed by dry etching of polysilicon, the silicon nitride layer at the bottom of the base window is removed by dry etching of silicon nitride, and the sacrificial layer on the sidewall of the base window is removed by wet etching of polysilicon, forming two symmetrical L-shaped sidewall structures. The exposed second oxide layer at the bottom of the two sidewall structures is etched to obtain the emission area window.

9. The method for integrating a dual-gate JFET device in a bipolar junction transistor process as described in claim 3, characterized in that: The first doping type and the second doping type refer to opposite doping types, where the first doping type is N-type doping and the second doping type is P-type doping. or The first doping type is P-type doping, and the second doping type is N-type doping.

10. A structure for integrating a dual-gate JFET device in a bipolar junction transistor process, characterized in that: It is manufactured using the method described in any one of claims 1 to 9 for integrating a dual-gate JFET device in a bipolar junction transistor process.

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