Preparation method of silicon carbide step groove and groove type silicon carbide device
By fabricating stepped trenches on a silicon carbide substrate, the problems of electric field concentration and low breakdown voltage in traditional silicon carbide MOSFETs in high-voltage applications are solved, realizing the fabrication of high-performance silicon carbide devices suitable for high-frequency switching circuits in new energy vehicles.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-04-14
AI Technical Summary
Traditional trench silicon carbide MOSFETs suffer from localized electric field concentration, low breakdown voltage, and excessively high electric field in the bottom gate oxide layer due to the simple trench structure design in high-voltage applications, making them unsuitable for high-frequency switching circuits in new energy vehicles.
The silicon carbide stepped trench fabrication method involves growing an etching mask layer on a SiC substrate and performing photolithography to form a patterned photoresist. Dry etching forms the first-level trench, and wet oxidation and wet etching are used to form a stepped trench, reducing the number of photolithography processes, adjusting the shape of the etching mask, and improving the electric field of the bottom gate oxide layer.
It improves the manufacturability and reliability of the device, reduces switching losses, avoids electric field concentration at sharp points, and is suitable for high-frequency switching circuits in new energy vehicles.
Smart Images
Figure CN121865648A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon carbide device fabrication technology, and in particular to a method for fabricating silicon carbide stepped trenches and a trench-type silicon carbide device. Background Technology
[0002] Silicon carbide (SiC) is a wide bandgap semiconductor material that can be used to fabricate power devices. SiC power devices are suitable for high-frequency, high-voltage, and high-temperature applications and help improve the efficiency and power density of power electronic systems.
[0003] Silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) come in two common types: planar and trench. Trench MOSFETs are widely studied and applied due to their smaller cell area and higher channel mobility. However, traditional trench silicon carbide MOSFETs suffer from limitations in trench structure design. For example, the trench bottom has a sharp geometry, which can lead to localized electric field concentration in high-voltage applications. In particular, the curvature effect at the trench bottom causes the electric field peak to multiply, resulting in a lower breakdown voltage and an excessively high electric field in the bottom gate oxide layer. At the same time, interface defects on the trench sidewalls and carrier scattering increase the on-resistance. These defects exacerbate switching losses and reliability risks under high-frequency switching, making them unsuitable for the high-frequency switching circuit requirements of new energy vehicles. Summary of the Invention
[0004] The purpose of this invention is to provide a method for preparing silicon carbide stepped trenches and a trench-type silicon carbide device, which solves the problems of low breakdown voltage and excessively high electric field of the bottom gate oxide layer in existing devices, making them unsuitable for the high-frequency switching circuit requirements of new energy vehicles.
[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: The first aspect of this invention provides a method for preparing silicon carbide stepped trenches, comprising: An etching mask layer is grown on the epitaxial layer on the upper surface of a SiC substrate; Photolithography is performed on the etched mask layer to generate patterned photoresist; Using patterned photoresist as a mask, the patterned etching mask layer is dry etched to the upper surface of the epitaxial layer to form a patterned etching mask layer. The epitaxial layer is then etched using the patterned etching mask layer as a mask to form a first-level trench. The depth of the first-level trench is less than the thickness of the epitaxial layer. Using a wet oxidation process, part of the etching mask layer is oxidized to silicon dioxide, and then the silicon dioxide is removed using a wet etching process to form a treated etching mask layer. The silicon dioxide is formed on the upper surface of the etching mask layer and on the sidewalls near the first-level trench. Using the processed etching mask layer as the etching mask, the epitaxial layer is etched close to the two side walls of the first trench, and a second trench is formed based on the first trench to obtain a stepped trench.
[0006] In some embodiments, before growing an etching mask layer on the epitaxial layer on the upper surface of the SiC substrate, the method further includes: The SiC substrate and epitaxial layer were cleaned sequentially using a first cleaning solution, a second cleaning solution, and a BOE cleaning solution. The first cleaning solution was prepared with ammonia water: hydrogen peroxide: pure water in a ratio of 1:1:5 and the cleaning temperature was 70°C. The second cleaning solution was prepared with hydrochloric acid: hydrogen peroxide: pure water in a ratio of 1:1:5 and the cleaning temperature was 70°C. The BOE cleaning solution was prepared with hydrofluoric acid: ammonium fluoride in a ratio of 1:20 and the cleaning temperature was room temperature. The cleaned SiC substrate and epitaxial layer were subjected to acetone ultrasonication, isopropanol ultrasonication, DI water rinsing and drying treatment in sequence to obtain a dried SiC substrate and epitaxial layer.
[0007] In some embodiments, the material of the etch mask layer is polycrystalline silicon.
[0008] In some embodiments, during the growth of the etched mask layer, an ionization enhanced chemical vapor deposition (IECVD) process or a low-pressure chemical vapor deposition (LPCVD) process under room temperature conditions is employed.
[0009] In some embodiments, the photolithography process includes coating, pre-baking, exposure, post-baking, development, and hardening processes.
[0010] In some embodiments, the process temperature of the wet oxidation process is 900°C-1100°C.
[0011] In some embodiments, the etchant used in the wet etching process is BOE.
[0012] A second aspect of the present invention provides a trench-type silicon carbide device, comprising a SiC substrate and an epitaxial layer disposed sequentially from bottom to top; The stepped trenches are formed within the epitaxial layer and include a first-level trench and a second-level trench arranged sequentially from bottom to top.
[0013] In some embodiments, the depth of the first-level trench is greater than the depth of the second-level trench.
[0014] In some embodiments, trench-type silicon carbide devices are suitable for high-frequency switching circuits in new energy vehicles.
[0015] Compared to existing technologies, this invention provides a method for fabricating a silicon carbide stepped trench and a trench-type silicon carbide device. An etching mask layer is grown on an epitaxial layer on the upper surface of a SiC substrate. A photolithography process is performed on the etching mask layer to generate a patterned photoresist. Using the patterned photoresist as a mask, the patterned etching mask layer is dry-etched to the upper surface of the epitaxial layer to form a patterned etching mask layer. The epitaxial layer is then etched using the patterned etching mask layer as a mask to form a first-level trench. A wet oxidation process is used to oxidize a portion of the etching mask layer to silicon dioxide, and a wet etching process is used to remove the silicon dioxide, forming a treated etching mask layer. Silicon dioxide is formed on the upper surface of the etching mask layer and on the sidewalls near the first-level trench. Using the treated etching mask layer as an etching mask, a portion of the epitaxial layer is etched near the sidewalls of the first trench, forming a second-level trench based on the first-level trench, thus obtaining a stepped trench. In this way, by using the wet oxidation process of the etched mask layer to adjust the shape of the etched mask and etch a silicon carbide trench with a stepped shape, it helps to improve the situation of excessive electric field in the bottom gate oxide layer, enhance the manufacturability and reliability of the device, and reduce switching losses. The volume expansion caused by wet oxidation and the isotropic rounding of wet etching synergistically round the mask edge, which is then transmitted to the trench junction through etching, making the junction of the first-level trench and the second-level trench smoother and avoiding breakdown caused by concentrated electric field at the tip. Through the thermal oxidation and wet etching processes of the etched mask layer, the self-adjustment of the mask pattern is realized, replacing the traditional two photolithography processes, reducing the number of photolithography processes, and the fabrication method is simple and easy to apply to the high-frequency switching circuit requirements of new energy vehicles. Attached Figure Description
[0016] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1 A schematic flowchart of the method for preparing silicon carbide stepped trenches is shown. Figure 2 A schematic diagram of the structure of the SiC substrate and the epitaxial layer is shown. Figure 3 A schematic diagram of the structure for growing and etching the mask layer is shown. Figure 4 A schematic diagram of the structure after photoresist coating is shown. Figure 5 A schematic diagram of the structure for generating patterned photoresist is shown. Figure 6 A schematic diagram illustrating the structure of the patterned etching mask layer is shown. Figure 7 A schematic diagram of the structure forming the first-stage trench is shown. Figure 8 A schematic diagram illustrating the structure for forming silicon dioxide is shown. Figure 9 A schematic diagram of the structure after removing silica is shown. Figure 10 A schematic diagram of the structure that yields a stepped groove is shown. Figure 11 A schematic diagram of the structure of a trench-type silicon carbide device is shown.
[0017] Explanation of reference numerals in the attached figures: 1. SiC substrate; 2. Epitaxial layer; 3. Etching mask layer; 4. Patterned photoresist; 5. Silicon dioxide; 6. Stepped trench; 61. First-level trench; 62. Second-level trench. Detailed Implementation
[0018] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present invention by way of example, but should not be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
[0019] The following is a detailed description of a method for preparing a silicon carbide stepped trench according to an embodiment of the present invention.
[0020] See Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating silicon carbide stepped trenches is shown. This invention provides a method for fabricating silicon carbide stepped trenches, comprising: S101. An etching mask layer 3 is grown on the epitaxial layer 2 on the upper surface of the SiC substrate 1.
[0021] The material of the etching mask layer 3 is polycrystalline silicon. During the growth of the etching mask layer 3, either plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) at room temperature is used.
[0022] Figure 2 A schematic diagram of the structure of SiC substrate 1 and epitaxial layer 2 is shown. (See attached diagram) Figure 2 As shown, the epitaxial layer 2 is disposed on the upper surface of the SiC substrate 1.
[0023] Before growing the etching mask layer 3 on the epitaxial layer 2 on the upper surface of the SiC substrate 1, the method further includes: Step A1: The SiC substrate 1 and the epitaxial layer 2 are cleaned sequentially using the first cleaning solution, the second cleaning solution and the BOE cleaning solution.
[0024] The first cleaning solution has a ratio of ammonia:hydrogen peroxide:pure water = 1:1:5 and a cleaning temperature of 70°C. The second cleaning solution has a ratio of hydrochloric acid:hydrogen peroxide:pure water = 1:1:5 and a cleaning temperature of 70°C. The BOE cleaning solution has a ratio of hydrofluoric acid:ammonium fluoride = 1:20 and a cleaning temperature of room temperature.
[0025] Step A2: After cleaning, the SiC substrate 1 and epitaxial layer 2 are subjected to acetone ultrasonication, isopropanol ultrasonication, DI water rinsing and drying treatment in sequence to obtain dried SiC substrate 1 and epitaxial layer 2.
[0026] Figure 3 A schematic diagram of the structure of the growth etching mask layer 3 is shown. (See attached image) Figure 3 As shown, PECVD or LPCVD is used to grow an etching mask layer 3 on the upper surface of the dried SiC substrate 1 and the epitaxial layer 2.
[0027] S102. Perform photolithography on the etched mask layer 3 to generate patterned photoresist 4.
[0028] The photolithography process includes coating, pre-baking, exposure, post-baking, development, and hardening.
[0029] Specifically, step S102 includes: Photoresist coating: Photoresist is uniformly coated onto the upper surface of the etching mask layer 3. The structure after photoresist coating is as follows. Figure 4 As shown, Figure 4 A schematic diagram of the structure after photoresist coating is shown.
[0030] Pre-baking: The coated photoresist is pre-baked to cure it.
[0031] Exposure: Selective exposure of the photoresist after pre-baking to form a latent image pattern.
[0032] Post-baking: Post-baking is performed on the exposed photoresist.
[0033] Development: The photoresist is treated with a developer and then baked to form the developed photoresist.
[0034] Hardening: The developed photoresist undergoes a hardening process to generate patterned photoresist 4, enhancing its adhesion and stability. See [link to diagram for patterned photoresist 4] for details. Figure 5 As shown, Figure 5 A schematic diagram of the structure for generating patterned photoresist 4 is shown.
[0035] S103. Using patterned photoresist 4 as a mask, dry etch the patterned etching mask layer 3 to the upper surface of the epitaxial layer 2 to form a patterned etching mask layer 3, and use the patterned etching mask layer 3 as a mask to etch the epitaxial layer 2 to form the first-level trench 61.
[0036] The depth of the first-level trench 61 is less than the thickness of the epitaxial layer 2.
[0037] Specifically, Figure 6 A schematic diagram illustrating the structure of the patterned etching mask layer 3 is shown below. Figure 6 As shown, using patterned photoresist 4 as a mask, polysilicon is dry etched (i.e., the mask layer 3 is etched) until the upper surface of the epitaxial layer 2 is exposed, forming the patterned etch mask layer 3.
[0038] Figure 7 A schematic diagram of the structure forming the first-stage trench 61 is shown. See [link / reference] Figure 7 As shown, using the patterned polysilicon (i.e. the patterned etching mask layer 3) as a mask, the epitaxial layer 2 is etched until the depth of the first-level trench 61 is reached, forming the first-level trench 61. The depth of the first-level trench 61 is less than the thickness of the epitaxial layer 2.
[0039] S104. Using a wet oxidation process, a portion of the etching mask layer 3 is oxidized to silicon dioxide 5, and then the silicon dioxide 5 is removed using a wet etching process to form the treated etching mask layer 3.
[0040] Silicon dioxide 5 is formed on the upper surface of the etch mask layer 3 and on the sidewalls near the first-level trench 61.
[0041] The process temperature for wet oxidation is 900°C-1100°C. The etchant used in the wet etching process is a buffered oxide etchant (BOE).
[0042] Specifically, Figure 8 A schematic diagram illustrating the structure forming silicon dioxide 5 is shown below. Figure 8 As shown, the surface polycrystalline silicon is oxidized into silicon dioxide 5 using a wet oxygen oxidation process at a temperature of 900°C-1100°C. Figure 9 A schematic diagram of the structure after removing silica 5 is shown. See [link / reference]. Figure 9 As shown, silicon dioxide 5 is removed using a wet etching process with BOE.
[0043] S105. Using the processed etching mask layer 3 as an etching mask, the epitaxial layer 2 is etched to the sidewalls of the first trench, and a second trench 62 is formed based on the first trench 61 to obtain a stepped trench 6.
[0044] Specifically, Figure 10 A schematic diagram of the structure of the stepped groove 6 is shown. (See attached image) Figure 10 As shown, the etching mask layer 3, which has been treated by wet oxygen oxidation and wet etching, is used as the etching mask. The epitaxial layer 2 is etched again on the basis of the first trench 61, and finally the trench 6 with a stepped shape is formed.
[0045] This invention reduces the number of photolithography processes, simplifies the fabrication method, and significantly improves performance. The junction between the first-stage trench 61 and the second-stage trench 62 is smoother, preventing breakdown caused by concentrated electric field at the tip. This invention helps solve the problem of excessively high electric field in the bottom gate oxide layer, enhancing the manufacturability and reliability of the device and reducing switching losses. Because this invention reduces the number of photolithography processes, simplifies the fabrication method, and significantly improves performance, it enables the fabrication and production of high-performance, mass-produced trench-type silicon carbide devices, possessing enormous market potential and broad application prospects.
[0046] Based on the above Figure 1As can be seen from the implementation method, in this embodiment of the invention, an etching mask layer 3 is grown on the epitaxial layer 2 on the upper surface of the SiC substrate 1; a photolithography process is performed on the etching mask layer 3 to generate a patterned photoresist 4; using the patterned photoresist 4 as a mask, the patterned etching mask layer 3 is dry etched to the upper surface of the epitaxial layer 2 to form a patterned etching mask layer 3, and the epitaxial layer 2 is etched using the patterned etching mask layer 3 as a mask to form a first-level trench 61; using a wet oxidation process, part of the etching mask layer 3 is oxidized to silicon dioxide 5, and the silicon dioxide 5 is removed using a wet etching process to form a processed etching mask layer 3, where silicon dioxide 5 is formed in the upper surface of the etching mask layer 3 and on the sidewalls near the first-level trench 61; using the processed etching mask layer 3 as an etching mask, part of the epitaxial layer 2 is etched near the sidewalls of the first trench, and a second-level trench 62 is formed based on the first-level trench 61 to obtain a stepped trench 6. In this way, by using the wet oxidation process of the etched mask layer 3 to adjust the shape of the etched mask and etch a silicon carbide trench with a stepped shape, it helps to improve the situation of excessive electric field in the bottom gate oxide layer, enhance the manufacturability and reliability of the device, and reduce switching losses. The volume expansion caused by wet oxidation and the isotropic rounding of wet etching synergistically round the mask edge, which is then transmitted to the trench junction through etching, making the junction of the first-level trench 61 and the second-level trench 62 smoother and avoiding breakdown caused by concentrated electric field at the tip. Through the thermal oxidation and wet etching processes of the etched mask layer 3, the self-adjustment of the mask pattern is realized, replacing the traditional two photolithography processes, reducing the number of photolithography processes, and the fabrication method is simple and easy to apply to the high-frequency switching circuit requirements of new energy vehicles.
[0047] Based on the same inventive concept, this invention also provides a trench-type silicon carbide device. Figure 11 This is a schematic diagram of the structure of a trench-type silicon carbide device in an embodiment of the present invention. The trench-type silicon carbide device may include a SiC substrate 1 and an epitaxial layer 2 arranged sequentially from bottom to top. A stepped groove 6 is formed within the epitaxial layer 2. The stepped groove 6 includes a first-level groove 61 and a second-level groove 62 arranged sequentially from bottom to top.
[0048] The depth of the first-stage trench 61 is greater than the depth of the second-stage trench 62. Trench-type silicon carbide devices are suitable for high-frequency switching circuits in new energy vehicles.
[0049] While specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of the invention. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any manner.
[0050] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for preparing silicon carbide stepped trenches, characterized in that, include: An etching mask layer is grown on the epitaxial layer on the upper surface of a SiC substrate; A photolithography process is performed on the etched mask layer to generate a patterned photoresist; Using the patterned photoresist as a mask, the patterned etching mask layer is dry etched to the upper surface of the epitaxial layer to form a patterned etching mask layer, and the epitaxial layer is etched using the patterned etching mask layer as a mask to form a first-level trench, wherein the depth of the first-level trench is less than the thickness of the epitaxial layer. Using a wet oxidation process, a portion of the etching mask layer is oxidized to silicon dioxide, and then the silicon dioxide is removed using a wet etching process to form a treated etching mask layer. The silicon dioxide is formed on the upper surface of the etching mask layer and on the sidewalls near the first-level trench. Using the processed etching mask layer as an etching mask, the epitaxial layer is etched close to the two sidewalls of the first trench, and a second trench is formed based on the first trench to obtain a stepped trench.
2. The method for preparing silicon carbide stepped trenches according to claim 1, characterized in that, Before growing an etching mask layer on the epitaxial layer on the upper surface of the SiC substrate, the method further includes: The SiC substrate and the epitaxial layer are cleaned sequentially using a first cleaning solution, a second cleaning solution, and a BOE cleaning solution. The first cleaning solution has a ratio of ammonia:hydrogen peroxide:pure water = 1:1:5 and a cleaning temperature of 70°C. The second cleaning solution has a ratio of hydrochloric acid:hydrogen peroxide:pure water = 1:1:5 and a cleaning temperature of 70°C. The BOE cleaning solution has a ratio of hydrofluoric acid:ammonium fluoride = 1:20 and a cleaning temperature of room temperature. The cleaned SiC substrate and epitaxial layer were subjected to acetone ultrasonication, isopropanol ultrasonication, DI water rinsing and drying treatment in sequence to obtain a dried SiC substrate and epitaxial layer.
3. The method for preparing silicon carbide stepped trenches according to claim 1, characterized in that, The material of the etching mask layer is polycrystalline silicon.
4. The method for preparing silicon carbide stepped trenches according to claim 1, characterized in that, During the growth and etching of the mask layer, either ionization enhanced chemical vapor deposition (IECVD) or low-pressure chemical vapor deposition (LPCVD) is used at room temperature.
5. The method for preparing silicon carbide stepped trenches according to claim 1, characterized in that, The photolithography process includes coating, pre-baking, exposure, post-baking, development, and hardening processes.
6. The method for preparing silicon carbide stepped trenches according to claim 1, characterized in that, The process temperature for the wet oxidation process is 900°C-1100°C.
7. The method for preparing silicon carbide stepped trenches according to claim 1, characterized in that, The wet etching process uses BOE as the etching solution.
8. A trench-type silicon carbide device, characterized in that, The method for fabricating silicon carbide stepped trenches according to any one of claims 1-7, wherein the trench-type silicon carbide device comprises a SiC substrate and an epitaxial layer arranged sequentially from bottom to top; A stepped groove is formed within the epitaxial layer, the stepped groove comprising a first-level groove and a second-level groove arranged sequentially from bottom to top.
9. The trench-type silicon carbide device according to claim 8, characterized in that, The depth of the first-level trench is greater than the depth of the second-level trench.
10. The trench-type silicon carbide device according to claim 8, characterized in that, The trench-type silicon carbide device is suitable for high-frequency switching circuits in new energy vehicles.