Method and structure for integrating pjfet and njfet devices in a bipolar junction transistor process

Abstract

The invention discloses a method and a structure for integrating a PJFET device and an NJFET device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming buried layer structures, isolation structures and epitaxial layers of a bipolar junction transistor, the PJFET device and the NJFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region of the PJFET device and the NJFET device above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, and etching to form a base region window; forming a heavily-doped collector region, a heavily-doped outer base region, and heavily-doped bottom gates, heavily-doped top gates, source regions and drain regions of the PJFET device and the NJFET device through injection and annealing of a base region window; forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes on the dielectric layer. According to the invention, the bipolar junction transistor, the PJFET device and the NJFET device are simultaneously integrated in a single manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and structure for integrating PJFET and NJFET devices in a bipolar junction transistor process. Background Technology

[0002] High-precision JFET operational amplifiers manufactured using modern BiFET bipolar technology feature low noise, high input impedance, low temperature drift, and low input bias current, making them suitable for signal amplification in electronic systems. Currently, domestic bipolar technology platforms offering JFET operational amplifiers with polysilicon resistors (≤100ppm), low bias current (≤50pA), and low offset voltage (≤1mV) all utilize BiFET bipolar technology with polysilicon resistors and JFETs, which lags behind international standards. Whether it's the urgent need for independent and controllable manufacturing and safe production of components in next-generation weaponry, or the civilian market sectors such as automotive electronics, medical electronics, and instrumentation, JFET operational amplifiers have a vast market potential. Currently, the industrial-grade market is mainly monopolized by large international companies such as TI and ADI, with a global market share exceeding $1 billion and annual domestic procurement of approximately 500 million yuan. Therefore, there is a broad market demand for this series of high-precision JFET op-amp products.

[0003] The manufacturing process of these products integrates high-performance characteristics such as high voltage, high speed, high precision, and low bias. Specifically, it requires the simultaneous integration of multiple high-performance special process devices such as PJFET devices, NJFET devices, and bipolar junction transistors in a single manufacturing process. This places extremely high demands on the manufacturing technology and presents a huge challenge to the integration of process devices. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method and structure for simultaneously integrating high-speed bipolar junction transistors, PJFET devices and NJFET devices in a single manufacturing process without increasing the complexity of the process.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a method for integrating PJFET devices and NJFET devices in a bipolar junction transistor process, comprising the following steps: S100. Provide a substrate and form a buried layer structure, an epitaxial layer, and an isolation structure for the bipolar junction transistor, PJFET device, and NJFET device on the substrate. S200, Penetration doping and well region doping are performed in the epitaxial layer, and a field oxygen layer is selectively formed above the epitaxial layer to define the active region and the field region; S300, A collector crystal region and a base crystal region of a bipolar junction transistor, as well as a bottom gate crystal region, a top gate crystal region, a source crystal layer, and a drain crystal region of a PJFET device and an NJFET device are formed above the epitaxial layer. S400, deposit a dielectric layer above the epitaxial layer and etch to form a base region window; through the implantation and annealing of the base region window, form a heavily doped collector region and a heavily doped outer base region of a bipolar junction transistor, as well as a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region of a PJFET device and an NJFET device. S500: Form an emitter window and form an emitter crystal region of a bipolar junction transistor in the emitter window; S600, forming electrodes for bipolar junction transistors, PJFET devices, and NJFET devices on the dielectric layer.

[0006] Furthermore, step S100 includes the following sub-steps: A substrate is provided, the substrate including a lower silicon layer, a first oxide layer and an upper silicon layer; a bipolar device region for forming a bipolar junction transistor, a first JFET device region for forming a PJFET device and an NJFET device are defined on the substrate; A first buried layer of the first doping type is formed in the bipolar device region corresponding to the upper silicon layer, a second buried layer of the first doping type is formed in the region corresponding to the first JFET device, and a third buried layer of the second doping type is formed in the region corresponding to the second JFET device in the upper silicon layer. An epitaxial layer is formed on the upper end of the upper silicon layer; A fully dielectric island isolation is formed, comprising an isolated bipolar device region, a first JFET device region, and a second JFET device region. The fully dielectric island isolation penetrates the epitaxial layer and the upper silicon layer and is connected to the first oxide layer.

[0007] Furthermore, step S200 includes the following sub-steps: A pre-oxidized layer is grown above the epitaxial layer, and a mask layer is deposited above the pre-oxidized layer; A second doped outer well region is formed in the second device region, and the outer well region is connected to the third buried layer; In the epitaxial layer, a first doped bipolar device penetration doping region of the first doped type connected to the first buried layer, a first JFET device penetration doping region of the first doped type connected to the second buried layer, and a second JFET device penetration doping region of the second doped type connected to the third buried layer are formed by ion implantation and annealing processes. A second-doped well region is formed in the first JFET device region; A first-doped inner well region is formed within the outer well region; A field oxide layer is formed on the epitaxial layer through a local oxidation process, thereby simultaneously defining the active region and the field region in the bipolar device region, the first JFET device region, and the second JFET device region.

[0008] Furthermore, step S300 includes the following sub-steps: A first crystalline layer is deposited on the upper surface of the field oxide layer and the pre-oxidation layer, and a first type of doping is implanted on the first crystalline layer to form a collector crystalline region in the bipolar device region, a first bottom gate crystalline region and a first top gate crystalline region in the first JFET device region, and a second source crystalline region and a second drain crystalline region in the second device region. A second type of doping is performed on the first crystal layer to form a base crystal region in the bipolar device region, a first source crystal region and a first drain crystal region in the first JFET device region, and a second bottom gate crystal region and a second top gate crystal region in the second JFET device region. The excess first crystal layer is removed by etching.

[0009] Furthermore, step S400 includes the following sub-steps: A dielectric layer is deposited above the epitaxial layer, and the base region window of the bipolar junction transistor is formed by etching. A second oxide layer is grown on the surface of the base region window; A second-type doped inner base region is formed by implantation at the bottom of the base region window using an implantation process; Annealing allows the two types of dopants in the first crystalline layer to diffuse into the substrate, forming a heavily doped outer base region of the second doping type on both sides of the inner base region. It also forms a heavily doped collector region, a heavily doped first bottom gate, a heavily doped first top gate, a second source region, and a second drain region of the first doping type, as well as a heavily doped second bottom gate, a heavily doped second top gate, a first source region, and a first drain region of the second doping type.

[0010] Furthermore, step S500 includes the following sub-steps: An L-shaped sidewall structure is formed by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and an emission region window is obtained by etching the second oxide layer. A second crystalline layer is deposited within the emitter window to form the emitter region of a bipolar junction transistor through an implantation process; The emitter crystal region is formed through an etching process; The heavily doped emitter region of the first doping type is formed by annealing.

[0011] Furthermore, step S600 includes the following sub-steps: Holes are made on the dielectric layer at positions corresponding to the collector crystal region, base crystal region, first source crystal region, first drain crystal region, first bottom gate crystal region, first top gate crystal region, second source crystal region, second drain crystal region, second bottom gate crystal region, and second top gate crystal region, respectively, to obtain collector contact holes, base contact holes, first source contact holes, first drain contact holes, first bottom gate contact holes, first top gate contact holes, second source contact holes, second drain contact holes, second bottom gate contact holes, and second top gate contact holes; A collector contact is formed in the collector contact hole, a base contact is formed in the base contact hole, an emitter contact is formed in the emitter contact hole, a first source contact is formed in the first source contact hole, a first drain contact is formed in the first drain contact hole, a first bottom gate contact is formed in the first bottom gate contact hole, a first top gate contact is formed in the first top gate contact hole, a second source contact is formed in the second source contact hole, a second drain contact is formed in the second drain contact hole, a second bottom gate contact is formed in the second bottom gate contact hole, a second top gate contact is formed in the second top gate contact hole, and an emitter contact is formed on the emitter crystal region. A metal layer is deposited to form a collector electrode that is in contact with the collector electrode, a base electrode that is in contact with the base electrode, an emitter electrode that is in contact with the emitter electrode, a first source electrode that is in contact with the first source electrode, a first drain electrode that is in contact with the first drain electrode, a first bottom gate electrode that is in contact with the first bottom gate, a first top gate electrode that is in contact with the first top gate, a second source electrode that is in contact with the second source electrode, a second drain electrode that is in contact with the second drain electrode, a second bottom gate electrode that is in contact with the second bottom gate, and a second top gate electrode that is in contact with the second top gate.

[0012] Furthermore, the step of forming an L-shaped sidewall structure by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and obtaining the emission region window by etching the second oxide layer, includes the following sub-steps: Silicon nitride is deposited on the inner surface of the second oxide layer to form a silicon nitride layer, and an amorphous deposition is performed on the surface of the silicon nitride layer to form a sacrificial layer; The sacrificial layer at the bottom of the base window is removed by dry etching of polysilicon, the silicon nitride layer at the bottom of the base window is removed by dry etching of silicon nitride, and the sacrificial layer on the sidewall of the base window is removed by wet etching of polysilicon, forming two symmetrical L-shaped sidewall structures. The exposed second oxide layer at the bottom of the two sidewall structures is etched to obtain the emission area window.

[0013] Furthermore, the first doping type and the second doping type are opposite doping types, with the first doping type being N-type doping and the second doping type being P-type doping; or The first doping type is P-type doping, and the second doping type is N-type doping.

[0014] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a structure that integrates PJFET devices and NJFET devices in a bipolar junction transistor process, which is fabricated using the method described above for integrating PJFET devices and NJFET devices in a bipolar junction transistor process.

[0015] The structure of integrating PJFET and NJFET devices in a bipolar junction transistor (BJT) process of the present invention has at least the following beneficial effects: For the first time, the present invention successfully integrates three types of high-performance semiconductor devices—bipolar junction transistors, PJFET devices, and NJFET devices—in a single process flow, overcoming the technical bottleneck of the traditional BiFET process's difficulty in simultaneously integrating complementary JFET devices; the number of process steps is reduced, the number of photomasks is decreased, significantly improving manufacturing efficiency and reducing process complexity; through innovative process design, while maintaining the high transconductance and high speed advantages of bipolar transistors, the complementary characteristics of PJFETs and NJFETs are perfectly integrated; through the design of three buried layers, optimized isolation and electrical connection between the bipolar devices and complementary JFET devices are achieved. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0017] Figure 2 This is a cross-sectional schematic diagram of the substrate after pretreatment in one embodiment of the method for integrating PJFET and NJFET devices in bipolar junction transistor technology according to the present invention.

[0018] Figure 3 This is a cross-sectional schematic diagram after the formation of the inner well region in one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0019] Figure 4 This is a cross-sectional schematic diagram after the formation of the field oxide layer in one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0020] Figure 5 This is a schematic diagram of the interface after the formation of the first crystallization layer in one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0021] Figure 6 This is a schematic cross-sectional view of the electrode crystal regions obtained by doping and implanting on the first crystal layer in one embodiment of the method for integrating PJFET and NJFET devices in bipolar junction transistor technology according to the present invention.

[0022] Figure 7 This is a cross-sectional schematic diagram after removing excess first crystal layer in one embodiment of the method for integrating PJFET and NJFET devices in bipolar junction transistor technology according to the present invention.

[0023] Figure 8 This is a cross-sectional schematic diagram after forming the base region window in one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0024] Figure 9 This is a cross-sectional schematic diagram of a method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention, after forming a heavily doped outer base region, a heavily doped collector region, and heavily doped bottom gate, heavily doped top gate, source region, and drain region of the PJFET and NJFET devices.

[0025] Figure 10 This is a cross-sectional schematic diagram after forming the emitter window in one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0026] Figure 11 This is a cross-sectional schematic diagram after the formation of the heavily doped emitter region in one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process according to the present invention.

[0027] Figure 12 This is a cross-sectional schematic diagram after the electrode structures are formed, according to one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor process of the present invention.

[0028] The meanings of the labels in the attached diagram are as follows: Lower silicon layer 100, first oxide layer 101, upper silicon layer 102, first buried layer 103, second buried layer 104, third buried layer 105, epitaxial layer 106, trench isolation oxide layer 107, trench isolation polysilicon 108, bipolar device through-doped region 110, first JFET device through-doped region 111, second JFET device through-doped region 112, outer well region 109, well region 113, inner well region 114, field oxide layer 116, first crystal layer 117, collector crystal region 118, base crystal region 119, first bottom gate crystal region 120, first top gate crystal region 122, first source crystal region 121, first drain crystal region 123, second bottom gate crystal region 124, second top gate crystal region 126, second source crystal region 125, second drain crystal region 127, dielectric. Layer 128, second oxide layer 129, heavily doped collector region 130, heavily doped outer base region 131, heavily doped first bottom gate 132, heavily doped first top gate 134, first source region 133, first drain region 135, heavily doped second bottom gate 136, heavily doped second top gate 138, second source region 137, second drain region 139, inner base region 140, sidewall structure 141, emitter crystal region 143, heavily doped emitter region 144, collector electrode 145, base electrode 146, emitter electrode 147, first bottom gate electrode 148, first top gate electrode 150, first source electrode 149, first drain electrode 151, second bottom gate electrode 152, second top gate electrode 154, second source electrode 153, second drain electrode 155, pre-oxidation layer 156, mask layer 157. Detailed Implementation

[0029] The invention will now be further described with reference to the accompanying drawings.

[0030] Please see Figure 1 This is a flowchart of one embodiment of the method for integrating PJFET and NJFET devices in a bipolar junction transistor (BJT) process according to the present invention. This embodiment may include the following steps: S100. Provide a substrate and perform pretreatment. Provide a substrate, and form on the substrate a buried layer structure for a bipolar junction transistor, a PJFET device, and an NJFET device, an epitaxial layer 106, and an isolation structure for the bipolar junction transistor, PJFET device, and NJFET device. For details, please refer to [link to relevant documentation]. Figure 2 This step may include the following sub-steps: S101. A substrate is provided. Specifically, the substrate includes a lower silicon layer 100, a first oxide layer 101, and an upper silicon layer 102. A bipolar device region for forming a bipolar junction transistor (BJFET), a first JFET device region for forming a PJFET device, and a second JFET device region for forming an NJFET device are defined on the substrate. When the first JFET device region is used to form a PJFET device, the second JFET device region is used to form an NJFET device; when the first JFET device region is used to form an NJFET device, the second JFET device region is used to form a PJFET device. In this embodiment, the materials of the lower silicon layer 100 and the upper silicon layer 102 are preferably SOI silicon, and the material of the SOI silicon substrate may include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0031] S102, forming a first buried layer 103, a second buried layer 104, and a third buried layer 105. Specifically, using a photomask, a first buried layer 103 of a first doping type is formed in the bipolar device region corresponding to the upper silicon layer 102, a second buried layer 104 of a first doping type is formed in the region corresponding to the first JFET device, and a third buried layer 105 of a second doping type is formed in the region corresponding to the second JFET device on the upper silicon layer 102. The first doping type and the second doping type are opposite doping types. When the formed bipolar junction transistor is an NPN transistor, a PJFET device is formed in the first device region, and an NJFET device is formed in the second device region. The first doping type is N-type, and the second doping type is P-type. When the formed bipolar junction transistor is a PNP transistor, an NJFET device is formed in the first device region, and a PJFET device is formed in the second device region. The first doping type is P-type, and the second doping type is N-type.

[0032] S103. Form an epitaxial layer 106. Specifically, an epitaxial layer 106 is formed on the upper end of the upper silicon layer 102.

[0033] S104. Forming a full dielectric island isolation. Specifically, a photomask is used to form a full dielectric island isolation for the isolation bipolar device region, the first JFET device region, and the second JFET device region. The full dielectric island isolation penetrates the epitaxial layer 106 and the upper silicon layer 102 and is connected to the first oxide layer 101. The full dielectric island isolation includes a trench isolation oxide layer 107 and trench isolation polysilicon 108 filled in the trenches formed by the trench isolation oxide layer 107. The trench isolation oxide layer 107 is connected to the first oxide layer 101.

[0034] S200: Complete penetration doping and well doping, and distinguish between the active region and the field region. Penetration doping and well doping are performed in the epitaxial layer 106, and a field oxide layer 116 is selectively formed above the epitaxial layer 106 to define the active region and the field region. For details, please refer to... Figure 3 and Figure 4 This step may include the following sub-steps: S201. Grow a pre-oxide layer 156 and deposit a mask layer 157. Specifically, a pre-oxide layer 156 is grown above the epitaxial layer 106, and a mask layer 157 is deposited above the pre-oxide layer 156. First, a pre-oxide layer 156 is grown on the epitaxial layer 106 by thermo-oxidation, and then a mask layer 157 is deposited on the pre-oxide layer 156. The material of the mask layer 157 is preferably silicon nitride.

[0035] S202, Forming the outer well region 109. Specifically, using a photomask, ion implantation is performed to form a second-doped outer well region 109 in the second device region. After high-temperature annealing, the outer well region 109 is connected to the third buried layer 105.

[0036] S203, forming a bipolar device through-doped region 110, a first JFET device through-doped region 111, and a second JFET device through-doped region 112. Specifically, using a photomask, a first-doped bipolar device through-doped region 110 connected to the first buried layer 103, a first-doped JFET device through-doped region 111 connected to the second buried layer 104, and a second-doped JFET device through-doped region 112 connected to the third buried layer 105 are formed in the epitaxial layer 106 through ion implantation and annealing processes.

[0037] S204. Forming well region 113. Specifically, using a photomask, a second-doped well region 113 is formed in the first JFET device region by ion implantation.

[0038] S205. Forming the inner well region 114. Specifically, using a photomask, the first doped inner well region 114 is formed within the outer well region 109 by ion implantation.

[0039] 206. Forming the field oxide layer 116. Specifically, using a photomask, a field oxide layer 116 is formed on the epitaxial layer 106 through a local oxidation process. Excess mask layer 157 and pre-oxidized layer 156 are removed; the preferred removal process is rinsing. Based on the field oxide layer 116, active and field regions are simultaneously defined in the bipolar device region, the first JFET device region, and the second JFET device region. The region covered by the field oxide layer 116 is the field region, and the region not covered by the field oxide layer 116 is the active region.

[0040] S300: Forming crystalline regions for each electrode of the bipolar junction transistor, PJFET device, and NJFET device. Above the epitaxial layer 106, a collector crystalline region 118 and a base crystalline region 119 for the bipolar junction transistor, as well as a bottom gate crystalline region, top gate crystalline region, source crystalline layer, and drain crystalline region for the PJFET device and NJFET device, are formed. For details, please refer to [link to documentation]. Figures 5 to 7 This step may include the following sub-steps: S301, forming a collector crystal region 118, a first bottom gate crystal region 120, a first top gate crystal region 122, a second source crystal region 125, and a second drain crystal region 127. Specifically, a first crystal layer 117 is deposited on the upper surface of the field oxide layer 116 and the pre-oxidation layer 156, and a first doping type is performed on the first crystal layer 117 to form a collector crystal region 118 in the bipolar device region, a first bottom gate crystal region 120 and a first top gate crystal region 122 in the first JFET device region, and a second source crystal region 125 and a second drain crystal region 127 in the second device region. In this embodiment, general doping is performed before using a photomask for the first doping type. The first crystal layer 117 can be a novel semiconductor conductive material such as polycrystalline silicon or germanium silicon. In this embodiment, the first crystal layer 117 is preferably polycrystalline silicon. The collector crystal region 118 is a polycrystalline silicon collector, the first bottom gate crystal region 120 is a first polycrystalline silicon bottom gate, the first top gate crystal region 122 is a first polycrystalline silicon top gate, the second source crystal region 125 is a second polycrystalline silicon source, and the second drain crystal region 127 is a second polycrystalline silicon drain.

[0041] S302, forming a base crystal region 119, a first source crystal region 121, a first drain crystal region 123, a second bottom gate crystal region 124, and a second top gate crystal region 126. Specifically, a photomask performs a second type of doping implantation on the first crystal layer 117 to form the base crystal region 119 in the bipolar device region, the first source crystal region 121 and the first drain crystal region 123 in the first JFET device region, and the second bottom gate crystal region 124 and the second top gate crystal region 126 in the second JFET device region. In this embodiment, the base crystal region 119 is a polysilicon base, the first source crystal region 121 is a first polysilicon source, the first drain crystal region 123 is a first polysilicon drain, the second bottom gate crystal region 124 is a second polysilicon bottom gate, and the second top gate crystal region 126 is a second polysilicon top gate.

[0042] When the first doping type is N-type and the second doping type is P-type, the bottom gate crystal region, top gate crystal region, source crystal layer, and drain crystal region of the PJFET device are the first bottom gate crystal region 120, the first top gate crystal region 122, the first source crystal region 121, and the first drain crystal region 123, respectively. The bottom gate crystal region, top gate crystal region, source crystal layer, and drain crystal region of the NJFET device are the second bottom gate crystal region 124, the second top gate crystal region 126, the second source crystal region 125, and the second drain crystal region 127, respectively. When the first doping type is P-type and the second doping type is N-type, the bottom gate crystal region, top gate crystal region, source crystal layer, and drain crystal region of the PJFET device are the second bottom gate crystal region 124, the second top gate crystal region 126, the second source crystal region 125, and the second drain crystal region 127, respectively. The bottom gate crystal region, top gate crystal region, source crystal layer, and drain crystal region of the NJFET device are the first bottom gate crystal region 120, the first top gate crystal region 122, the first source crystal region 121, and the first drain crystal region 123, respectively.

[0043] S303. Remove excess first crystalline layer 117 by etching. In this embodiment, the etching process is preferably dry etching.

[0044] S400, Doping is advanced through the base region window. A dielectric layer 128 is deposited above the epitaxial layer 106, and a base region window is etched to form it. Through implantation and annealing of the base region window, a heavily doped collector region 130 and a heavily doped outer base region 131 of a bipolar junction transistor are formed, as well as the heavily doped bottom gate, heavily doped top gate, source region, and drain region of a PJFET device and an NJFET device. For details, please refer to [link to relevant documentation]. Figure 8 and Figure 9 This step may include the following sub-steps: S401. Forming the base region window. Specifically, a dielectric layer 128 is deposited above the epitaxial layer 106, and the base region window of the bipolar junction transistor is formed by etching. In this embodiment, the dielectric layer 128 can be USG or TEOS. The pre-oxide layer 156 and the polycrystalline base crystal region 119 are removed by dry etching using a photomask to form the base region window of the bipolar junction transistor, and two base crystal regions 119 are formed on both sides of the base region window.

[0045] S402. Grow a second oxide layer 129. Specifically, a second oxide layer 129 is grown on the surface of the base region window. The second oxide layer 129 is a thin sidewall oxide layer.

[0046] S403, Forming the inner base region 140. Specifically, a second-doped inner base region 140 is formed at the bottom of the base region window using a photomask implantation process.

[0047] S404, Doping Diffusion. Specifically, through annealing, the two types of dopants in the first crystal layer 117 diffuse into the substrate; that is, the N / P type dopants previously implanted by the polycrystalline silicon diffuse into the single-crystal silicon, forming a heavily doped outer base region 131 of the second doping type on both sides of the inner base region 140. The outer base region is connected to the inner base region 140 through the polycrystalline silicon to form a dual base region. At the same time, a heavily doped collector region 130 of the first doping type, a heavily doped first bottom gate 132, a heavily doped first top gate 134, a second source region 137, and a second drain region 139, as well as a heavily doped second bottom gate 136, a heavily doped second top gate 138, a first source region 133, and a first drain region 135 of the second doping type are also formed.

[0048] When the first doping type is N-type and the second doping type is P-type, the heavily doped bottom gate, heavily doped top gate, source region, and drain region of the PJFET device are respectively heavily doped first bottom gate 132, heavily doped first top gate 134, first source region 133, and first drain region 135. The heavily doped bottom gate, heavily doped top gate, source region, and drain region of the NJFET device are respectively heavily doped second bottom gate 136, heavily doped second top gate 138, second source region 137, and second drain region 139. When the first doping type is P-type and the second doping type is N-type, the heavily doped bottom gate, heavily doped top gate, source region, and drain region of the PJFET device are respectively heavily doped second bottom gate 136, heavily doped second top gate 138, second source region 137, and second drain region 139. The heavily doped bottom gate, heavily doped top gate, source region, and drain region of the NJFET device are respectively heavily doped first bottom gate 132, heavily doped first top gate 134, first source region 133, and first drain region 135.

[0049] S500, Forming the emitter crystal region 143. An emitter window is formed, and the emitter crystal region 143 of the bipolar junction transistor is formed within the emitter window. For details, please refer to [link to relevant documentation]. Figure 10 and Figure 11 This step may include the following sub-steps: S501. An L-shaped sidewall structure 141 is formed by performing multiple deposition, etching, and etching processes on the inner surface of the second oxide layer 129. The emitter window is obtained by etching the second oxide layer 129. Specifically, silicon nitride is deposited on the inner surface of the second oxide layer 129 to form a silicon nitride layer. An amorphous deposition is performed on the surface of the silicon nitride layer to form a sacrificial layer (not shown in the figure). The sacrificial layer at the bottom of the base region window is removed by polysilicon dry etching, the silicon nitride layer at the bottom of the base region window is removed by silicon nitride dry etching, and the sacrificial layer on the sidewall of the base region window is removed by polysilicon wet etching, forming two symmetrical L-shaped sidewall structures 141. The exposed second oxide layer 129 at the bottom of the two sidewall structures 141 is etched to obtain the emitter window.

[0050] S502. A second crystalline layer is deposited within the emitter window, and the emitter region of the bipolar junction transistor is formed by implantation. In this embodiment, the material of the second crystalline layer is preferably polycrystalline silicon, and the emitter region of the bipolar junction transistor is formed by implantation on the second crystalline layer using a photomask.

[0051] S503. The emitter crystal region 143 is formed by etching. Specifically, a photomask is used to perform dry etching on the emitter region to etch out excess polysilicon to form a polysilicon emitter (i.e., emitter crystal region 143) of a bipolar junction transistor.

[0052] S504, The first type of heavily doped emitter region 144 is formed by annealing.

[0053] S600: Forming the electrode structures for a bipolar junction transistor, a PJFET device, and an NJFET device. Electrodes for the bipolar junction transistor, PJFET device, and NJFET device are formed on the dielectric layer 128. For details, please refer to [link to documentation]. Figure 12 This step may include the following sub-steps: S601 makes holes on the dielectric layer 128 at the positions corresponding to the collector crystal region 118, base crystal region 119, first source crystal region 121, first drain crystal region 123, first bottom gate crystal region 120, first top gate crystal region 122, second source crystal region 125, second drain crystal region 127, second bottom gate crystal region 124, and second top gate crystal region 126, respectively, to obtain collector contact holes, base contact holes, first source contact holes, first drain contact holes, first bottom gate contact holes, first top gate contact holes, second source contact holes, second drain contact holes, second bottom gate contact holes, and second top gate contact holes.

[0054] S602. A collector contact is formed in the collector contact hole, a base contact is formed in the base contact hole, an emitter contact is formed in the emitter contact hole, a first source contact is formed in the first source contact hole, a first drain contact is formed in the first drain contact hole, a first bottom gate contact is formed in the first bottom gate contact hole, a first top gate contact is formed in the first top gate contact hole, a second source contact is formed in the second source contact hole, a second drain contact is formed in the second drain contact hole, a second bottom gate contact is formed in the second bottom gate contact hole, a second top gate contact is formed in the second top gate contact hole, and an emitter contact is formed on the emitter crystal region 143.

[0055] Electrode contact structures can be formed using different processes. For example, this embodiment uses a tungsten plug process to form ohmic contacts. Specifically: First, a titanium metal adhesion layer is deposited on the surface of the dielectric layer 128 after the contact hole etching has been completed using a physical vapor deposition process; then, a titanium nitride barrier layer is deposited; rapid thermal annealing is performed to form titanium silicide on the silicon or polysilicon surface at the bottom of the contact hole, effectively reducing contact resistance; isotropic deposition is performed using a tungsten chemical vapor deposition process to completely fill the contact hole; excess metal layers outside the contact hole are removed by chemical mechanical polishing or dry etching processes to form a complete tungsten plug structure within the contact hole.

[0056] S603, depositing a metal layer to form a collector electrode 145 connected to the collector electrode, a base electrode 146 connected to the base electrode, an emitter electrode 147 connected to the emitter electrode, a first source electrode 149 connected to the first source electrode, a first drain electrode 151 connected to the first drain electrode, a first bottom gate electrode 148 connected to the first bottom gate, a first top gate electrode 150 connected to the first top gate, a second source electrode 153 connected to the second source electrode, a second drain electrode 155 connected to the second drain electrode, a second bottom gate electrode 152 connected to the second bottom gate, and a second top gate electrode 154 connected to the second top gate.

[0057] When the first doping type is N-type and the second doping type is P-type, the electrodes of the PJFET device are the first bottom gate electrode 148, the first top gate electrode 150, the first drain electrode 151, and the first source electrode 149, respectively. The electrodes of the NJFET device are the second bottom gate electrode 152, the second top gate electrode 154, the second source electrode 153, and the second drain electrode 155, respectively. When the first doping type is P-type and the second doping type is N-type, the electrodes of the PJFET device are the second bottom gate electrode 152, the second top gate electrode 154, the second source electrode 153, and the second drain electrode 155, respectively. The electrodes of the NJFET device are the first bottom gate electrode 148, the first top gate electrode 150, the first drain electrode 151, and the first source electrode 149, respectively.

[0058] The present invention also discloses a structure for integrating PJFET devices and NJFET devices in a bipolar junction transistor process. The structure for integrating PJFET devices and NJFET devices in a bipolar junction transistor process can be fabricated using the method for integrating PJFET devices and NJFET devices in a bipolar junction transistor process described in the above embodiments.

[0059] This invention is the first to successfully integrate three types of high-performance semiconductor devices—bipolar junction transistors (BJFETs), PJFETs, and NJFETs—in a single process flow, overcoming the technical bottleneck of integrating complementary JFET devices simultaneously in traditional BiFET processes. The reduced number of process steps and photomasks significantly improves manufacturing efficiency and reduces process complexity. Through innovative process design, it perfectly integrates the complementary characteristics of PJFETs and NJFETs while maintaining the high transconductance and high speed advantages of bipolar transistors. The design of three buried layers achieves optimized isolation and electrical connection between the bipolar devices and the complementary JFET devices.

[0060] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A method for integrating PJFET and NJFET devices in a bipolar junction transistor process, characterized in that, Includes the following steps: S100. Provide a substrate and form a buried layer structure, an epitaxial layer, and an isolation structure for the bipolar junction transistor, PJFET device, and NJFET device on the substrate. S200, Penetration doping and well region doping are performed in the epitaxial layer, and a field oxygen layer is selectively formed above the epitaxial layer to define the active region and the field region; S300, A collector crystal region and a base crystal region of a bipolar junction transistor, as well as a bottom gate crystal region, a top gate crystal region, a source crystal layer, and a drain crystal region of a PJFET device and an NJFET device are formed above the epitaxial layer. S400, deposit a dielectric layer above the epitaxial layer and etch to form a base region window; through the implantation and annealing of the base region window, form a heavily doped collector region and a heavily doped outer base region of a bipolar junction transistor, as well as a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region of a PJFET device and an NJFET device. S500: Form an emitter window and form an emitter crystal region of a bipolar junction transistor in the emitter window; S600, forming electrodes for bipolar junction transistors, PJFET devices, and NJFET devices on the dielectric layer.

2. The method for integrating PJFET and NJFET devices in the bipolar junction transistor process as described in claim 1, characterized in that, Step S100 includes the following sub-steps: A substrate is provided, the substrate including a lower silicon layer, a first oxide layer and an upper silicon layer; a bipolar device region for forming a bipolar junction transistor, a first JFET device region for forming a PJFET device and an NJFET device are defined on the substrate; A first buried layer of the first doping type is formed in the bipolar device region corresponding to the upper silicon layer, a second buried layer of the first doping type is formed in the region corresponding to the first JFET device, and a third buried layer of the second doping type is formed in the region corresponding to the second JFET device in the upper silicon layer. An epitaxial layer is formed on the upper end of the upper silicon layer; A fully dielectric island isolation is formed, comprising an isolated bipolar device region, a first JFET device region, and a second JFET device region. The fully dielectric island isolation penetrates the epitaxial layer and the upper silicon layer and is connected to the first oxide layer.

3. The method for integrating PJFET and NJFET devices in the bipolar junction transistor process as described in claim 1, characterized in that, Step S200 includes the following sub-steps: A pre-oxidized layer is grown above the epitaxial layer, and a mask layer is deposited above the pre-oxidized layer; A second doped outer well region is formed in the second device region, and the outer well region is connected to the third buried layer; In the epitaxial layer, a first doped bipolar device penetration doping region of the first doped type connected to the first buried layer, a first JFET device penetration doping region of the first doped type connected to the second buried layer, and a second JFET device penetration doping region of the second doped type connected to the third buried layer are formed by ion implantation and annealing processes. A second-doped well region is formed in the first JFET device region; A first-doped inner well region is formed within the outer well region; A field oxide layer is formed on the epitaxial layer through a local oxidation process, thereby simultaneously defining the active region and the field region in the bipolar device region, the first JFET device region, and the second JFET device region.

4. The method for integrating PJFET and NJFET devices in the bipolar junction transistor process as described in claim 3, characterized in that, Step S300 includes the following sub-steps: A first crystalline layer is deposited on the upper surface of the field oxide layer and the pre-oxidation layer, and a first type of doping is implanted on the first crystalline layer to form a collector crystalline region in the bipolar device region, a first bottom gate crystalline region and a first top gate crystalline region in the first JFET device region, and a second source crystalline region and a second drain crystalline region in the second device region. A second type of doping is performed on the first crystal layer to form a base crystal region in the bipolar device region, a first source crystal region and a first drain crystal region in the first JFET device region, and a second bottom gate crystal region and a second top gate crystal region in the second JFET device region. The excess first crystal layer is removed by etching.

5. The method for integrating PJFET and NJFET devices in the bipolar junction transistor process as described in claim 1, characterized in that, Step S400 includes the following sub-steps: A dielectric layer is deposited above the epitaxial layer, and the base region window of the bipolar junction transistor is formed by etching. A second oxide layer is grown on the surface of the base region window; A second-type doped inner base region is formed by implantation at the bottom of the base region window using an implantation process; Annealing allows the two types of dopants in the first crystalline layer to diffuse into the substrate, forming a heavily doped outer base region of the second doping type on both sides of the inner base region. It also forms a heavily doped collector region, a heavily doped first bottom gate, a heavily doped first top gate, a second source region, and a second drain region of the first doping type, as well as a heavily doped second bottom gate, a heavily doped second top gate, a first source region, and a first drain region of the second doping type.

6. The method for integrating PJFET and NJFET devices in a bipolar junction transistor process as described in claim 5, characterized in that, The S500 step includes the following sub-steps: An L-shaped sidewall structure is formed by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and an emission region window is obtained by etching the second oxide layer. A second crystalline layer is deposited within the emitter window to form the emitter region of a bipolar junction transistor through an implantation process; The emitter crystal region is formed through an etching process; The heavily doped emitter region of the first doping type is formed by annealing.

7. The method for integrating PJFET and NJFET devices in a bipolar junction transistor process as described in claim 5, characterized in that, The S600 step includes the following sub-steps: Holes are made on the dielectric layer at positions corresponding to the collector crystal region, base crystal region, first source crystal region, first drain crystal region, first bottom gate crystal region, first top gate crystal region, second source crystal region, second drain crystal region, second bottom gate crystal region, and second top gate crystal region, respectively, to obtain collector contact holes, base contact holes, first source contact holes, first drain contact holes, first bottom gate contact holes, first top gate contact holes, second source contact holes, second drain contact holes, second bottom gate contact holes, and second top gate contact holes; A collector contact is formed in the collector contact hole, a base contact is formed in the base contact hole, an emitter contact is formed in the emitter contact hole, a first source contact is formed in the first source contact hole, a first drain contact is formed in the first drain contact hole, a first bottom gate contact is formed in the first bottom gate contact hole, a first top gate contact is formed in the first top gate contact hole, a second source contact is formed in the second source contact hole, a second drain contact is formed in the second drain contact hole, a second bottom gate contact is formed in the second bottom gate contact hole, a second top gate contact is formed in the second top gate contact hole, and an emitter contact is formed on the emitter crystal region. A metal layer is deposited to form a collector electrode that is in contact with the collector electrode, a base electrode that is in contact with the base electrode, an emitter electrode that is in contact with the emitter electrode, a first source electrode that is in contact with the first source electrode, a first drain electrode that is in contact with the first drain electrode, a first bottom gate electrode that is in contact with the first bottom gate, a first top gate electrode that is in contact with the first top gate, a second source electrode that is in contact with the second source electrode, a second drain electrode that is in contact with the second drain electrode, a second bottom gate electrode that is in contact with the second bottom gate, and a second top gate electrode that is in contact with the second top gate.

8. The method for integrating PJFET and NJFET devices in a bipolar junction transistor process as described in claim 6, characterized in that, The step of forming an L-shaped sidewall structure by performing multiple deposition, etching, and corrosion processes on the inner surface of the second oxide layer, and obtaining the emission region window by etching the second oxide layer, includes the following sub-steps: Silicon nitride is deposited on the inner surface of the second oxide layer to form a silicon nitride layer, and an amorphous deposition is performed on the surface of the silicon nitride layer to form a sacrificial layer; The sacrificial layer at the bottom of the base window is removed by dry etching of polysilicon, the silicon nitride layer at the bottom of the base window is removed by dry etching of silicon nitride, and the sacrificial layer on the sidewall of the base window is removed by wet etching of polysilicon, forming two symmetrical L-shaped sidewall structures. The exposed second oxide layer at the bottom of the two sidewall structures is etched to obtain the emission area window.

9. The method for integrating PJFET and NJFET devices in the bipolar junction transistor process as described in claim 3, characterized in that: The first doping type is the opposite of the second doping type; the first doping type is N-type doping, and the second doping type is P-type doping. or The first doping type is P-type doping, and the second doping type is N-type doping.

10. A structure for integrating PJFET and NJFET devices in a bipolar junction transistor process, characterized in that: It is manufactured using the method described in any one of claims 1 to 9 for integrating PJFET and NJFET devices in a bipolar junction transistor process.

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