Display driving circuit and display panel

Abstract

The application discloses a display driving circuit and a display panel, which at least comprise a double-gate structure and a gate selection unit connected with the gate of the double-gate structure; the double-gate structure comprises a bottom gate, a top gate, a source and a drain controlled to be turned on by the bottom gate and / or the top gate; the bottom gate is connected with a first gate driving module through the gate selection unit, the top gate is connected with a second gate driving module through the gate selection unit, the source is connected with a data line, and the drain is connected with a pixel electrode, so as to control the working voltage of the gate of the double-gate structure through the gate selection unit, and then the display gray scale of the pixel electrode is controlled. Through the above structure, the gray scale number of picture display is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display panel, in particular to a display driving circuit and a display panel. BACKGROUND

[0002] With the development of technology, the display color of LCD display screen is more and more rich, and the wide display color is usually combined with color filter (three primary colors RGB) and gray scale display (gray scale)

[0003] The implementation is realized. By controlling the brightness of RGB three sub-pixels on the liquid crystal screen respectively, the display with different colors is adjusted, and the more rich the level of intermediate brightness is, the more delicate the picture effect is. The gray between white and black can be distinguished into different levels according to the brightness (brightness level)

[0004] The performance of the difference in brightness level is called gray scale display (gray scale). According to the difference of the applied voltage, the transmittance of the LCD display screen is different, from

[0005] The gray scale display is realized. The domestic LCD display screen mainly adopts 8-bit processing system, that is, 256

[0006] (28) gray scale. Simply speaking, there are 256 kinds of brightness changes from black to white. 256x256x256=16777216 colors can be composed by using RGB three primary colors, that is, 16 million colors commonly known as.

[0007] Generally speaking, the higher the gray scale is, the more rich the display color is, and the more delicate the picture is, and it is easier to express rich details.

[0008] The gray scale of the LCD display screen refers to the number of brightness levels that can be distinguished between the darkest and the brightest in the same level of brightness. The gray scale mainly depends on the number of digital-to-analog (A / D) conversion bits of the system. Of course, the video processing chip, memory and transmission system of the system should provide corresponding

[0009] Bit support. Generally no gray, 8, 16, 32, 64, 128, 5 256, 1024, etc., the higher the gray level of the LCD display screen, the richer the color, the more colorful; on the contrary, the display color is simple and the change is simple. Through the combination of RGB color blocking material corresponding to the change of backlight source transmittance, different color display pictures can be obtained. Good purity color blocking material and new color block (RGBW) can increase the color gamut of the display, making the display picture more realistic. The transmittance of the pixel unit of the liquid crystal screen is controlled by the gray voltage to rotate the liquid crystal. The more the controllable gray voltage, the more the controllable transmittance, and the more the fusion color in a single pixel, making the display picture more delicate.

[0010] The input of gray voltage is controlled by IC output and transmitted to each pixel electrode through data line, and the actual voltage of liquid crystal rotation is determined by the final holding voltage transmitted to the pixel electrode by TFT device. When charging, TFT device cannot transmit gray voltage to pixel electrode with 100%, and there will be a certain loss. Therefore, in order to obtain ideal gray voltage, corresponding voltage compensation will be carried out on gray voltage, so that the final pixel holding voltage reaches the design value. The charging rate difference of different TFT devices will affect the difference of pixel transmittance. Without increasing the number of gray scale, using TFT devices with different charging rates can show more gray voltage values on the pixel unit, thereby improving the number of controllable transmittance and making the display picture more rich. SUMMARY

[0011] The technical problem solved by the present application is to provide a display driving circuit and a display panel to improve the gray scale number of picture display.

[0012] To solve the above problems, the present application provides a display driving circuit, which at least comprises a double gate structure and a gate selection unit connected with the gate of the double gate structure; the double gate structure comprises a bottom gate and a top gate, and a source and a drain controlled by the bottom gate and / or the top gate; the bottom gate is connected with a first gate drive module through the gate selection unit, the top gate is connected with a second gate drive module through the gate selection unit, the source is connected with a data line, and the drain is connected with a pixel electrode, so as to control the working mode of the double gate structure through the gate selection unit, and then control the display gray scale of the pixel electrode.

[0013] Wherein, the working voltage of the first gate drive module and the second gate drive module is different.

[0014] The gate selection unit at least comprises a first transistor and a second transistor; a gate of the first transistor is connected with a first control line, a source is connected with the first gate drive module, and a drain is connected with the bottom gate; a gate of the second transistor is connected with a second control line, a source is connected with the second gate drive module, and a drain is connected with the top gate.

[0015] The first control line outputs a first level signal to control the first transistor to be turned on, and the second control line outputs a second level signal to control the second transistor to be turned off, so as to obtain a first working mode in which the bottom gate controls the source and the drain to be turned on; the first control line outputs a second level signal to control the first transistor to be turned off, and the second control line outputs a first level signal to control the second transistor to be turned on, so as to obtain a second working mode in which the top gate controls the source and the drain to be turned on; the first control line outputs a first level signal to control the first transistor to be turned on, and the second control line outputs a first level signal to control the second transistor to be turned on, so as to obtain a third working mode in which the top gate and the bottom gate control the source and the drain to be turned on at the same time.

[0016] The gate selection unit further comprises a third transistor; a gate of the third transistor is connected with a third control line, a source is connected with one of the bottom gate and the top gate, and a drain is connected with the other one of the bottom gate and the top gate.

[0017] The first control line outputs a first level signal to control the first transistor to be turned on, the second control line outputs a second level signal to control the second transistor to be turned off, and the third control line outputs a second level signal to control the bottom gate to be disconnected from the top gate, so that the bottom gate controls the source and the drain to be turned on under the first gate voltage output by the first gate drive module, thereby obtaining a first working mode; the first control line outputs a second level signal to control the first transistor to be turned off, the second control line outputs a first level signal to control the second transistor to be turned on, and the third control line outputs a second level signal to control the bottom gate to be disconnected from the top gate, so that the top gate controls the source and the drain to be turned on under the second gate voltage output by the second gate drive module, thereby obtaining a second working mode; the first control line outputs a first level signal to control the first transistor to be turned on, the second control line outputs a second level signal to control the second transistor to be turned off, and the third control line outputs a first level signal to control the bottom gate to be connected to the top gate, so that the bottom gate and the top gate control the source and the drain to be turned on under the first gate voltage output by the first gate drive module, thereby obtaining a third working mode; and the first control line outputs a second level signal to control the first transistor to be turned off, the second control line outputs a first level signal to control the second transistor to be turned on, and the third control line outputs a first level signal to control the bottom gate to be connected to the top gate, so that the bottom gate and the top gate control the source and the drain to be turned on under the second gate voltage output by the second gate drive module, thereby obtaining a fourth working mode.

[0018] The charging rate of the double-gate structure in the third working mode is greater than the charging rate in the first working mode, the charging rate in the first working mode is greater than the charging rate in the fourth working mode, and the charging rate in the fourth working mode is greater than the charging rate in the second working mode.

[0019] The display drive circuit further comprises a reset unit, one end of the reset unit is grounded, and the other end is connected to the gate of the double-gate structure, so as to reset the potential of the other gate when one of the gates is working.

[0020] The reset unit comprises a fourth transistor, a fifth transistor and a sixth transistor; the gate of the fourth transistor is connected to the second gate drive module, the source of the fourth transistor is connected to the drain of the sixth transistor, and the drain of the fourth transistor is connected to the bottom gate; the gate of the fifth transistor is connected to the first gate drive module, the source of the fifth transistor is connected to the drain of the sixth transistor, and the drain of the fifth transistor is connected to the top gate; the gate of the sixth transistor is connected to a fourth control line, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the sources of the fourth transistor and the fifth transistor.

[0021] The application further provides a display panel, wherein the display panel comprises a plurality of pixel units arranged in an array, and each pixel unit comprises the display driving circuit of the first embodiment.

[0022] The application has the following beneficial effects: the bottom gate and / or the top gate in the double-gate structure are controlled to work under the voltage of the first gate driving module or the second gate driving module by the gate selection unit, so that the working voltages of the gates of the double-gate structure are different, the charging rate of the source electrode to the drain electrode of the double-gate structure is different, and the pixel electrode has different display gray scales under the conditions of different gates and different voltages of the gates. The application improves the number of gray scales of picture display by switching the working state of the TFT in the double-gate structure, and further improves the picture display quality. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0024] Figure 1 FIG. 1 is a structural schematic diagram of a display driving circuit of a first embodiment of the application;

[0025] Figure 2 FIG. 2 is a structural schematic diagram of a display driving circuit of a second embodiment of the application;

[0026] Figure 3 FIG. 3 is a structural schematic diagram of a display driving circuit of a third embodiment of the application;

[0027] Figure 4 FIG. 4 is a structural schematic diagram of a display driving circuit of a fourth embodiment of the application;

[0028] Figure 5 FIG. 5 is a sectional structural schematic diagram of a double-gate structure of an embodiment of the application;

[0029] Figure 6 FIG. 6 is a structural schematic diagram of a display panel of a first embodiment of the application;

[0030] Figure 7 FIG. 7 is a structural schematic diagram of a display panel of a second embodiment of the application;

[0031] Figure 8 FIG. 8 is a schematic diagram of the relationship between the transmittance and the applied voltage in a TFT-LCD.

[0032] 10 double gate structure; 101 bottom gate layer; 102 first gate insulating layer; 103 semiconductor layer; 1041 source layer; 1042 drain layer; 105 second gate insulating layer; 106 top gate layer; 11 bottom gate; 12 top gate; T1 first transistor; T2 second transistor; T3 third transistor; T4 fourth transistor; T5 fifth transistor; T6 sixth transistor; GOA1 first gate driving module; GOA2 second gate driving module; L1 first control line; L2 second control line; L3 third control line; L4 fourth control line; 20 gate selection unit; 30 reset unit; 601 pixel unit. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0034] The terms used in the embodiments of the present application are merely for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0035] It should be understood that the term "and / or" used herein is merely an association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present application specification and claims and the above-mentioned drawings generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0036] It should be understood that the terms "include", "contain" or any other variation used herein are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0037] It should be noted that if the application embodiments involve directionality indication (such as up, down, left, right, front, back, …), the directionality indication is only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indication also changes accordingly.

[0038] Reference herein to "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive or alternative embodiments. It is explicitly contemplated that embodiments described herein can be combined with other embodiments.

[0039] The design idea of the application is: a combination structure of switchable TFT working state is designed by using a dual-gate transistor. By switching different TFT devices for work in display, more actual gray scale voltage values can be obtained, thereby increasing the display gray scale number, providing display picture quality, and making the display panel more abundant.

[0040] The application provides a first display driving circuit, please refer to Figure 1 , Figure 1 The structure diagram of the first embodiment of the display driving circuit of the application is shown in the figure. Figure 1 As shown in the figure, the display driving circuit includes a dual-gate structure 10 and a gate selection unit 20 connected with the dual-gate structure 10.

[0041] The dual-gate structure 10 includes a bottom gate 11, a top gate 12, and a source and a drain controlled by the bottom gate 11 and / or the top gate 12 to be turned on, the source is connected with a data line data, and the drain is connected with a pixel electrode pxl. The bottom gate 11 is connected with a first gate drive module GOA1 through the gate selection unit 20, and the top gate 12 is connected with a second gate drive module GOA2 through the gate selection unit 20. The first gate drive module GOA1 and / or the second gate drive module GOA2 are selected by the gate selection unit 20 to control the working mode and working voltage of the gate of the dual-gate structure 10.

[0042] The dual-gate structure 10 has different charging rates under different working voltages and working modes. Different display gray scales are realized by matching the TFT devices with different charging rates with the gray scale voltages, thereby improving the display quality of the display picture.

[0043] It should be noted that the gate of the double-gate structure 10 includes two gates, i.e., the bottom gate 11 and the top gate 12. The double-gate structure 10 works under the control of the separate bottom gate 11 to form a bottom-gate TFT, works under the control of the separate top gate 12 to form a top-gate TFT, and works under the simultaneous control of the bottom gate 11 and the top gate 12 to form a bottom-gate TFT+top-gate TFT.

[0044] Generally, the bottom gate 11 and the top gate 12 have different working voltages. In order to make the bottom gate 11 and the top gate 12 work normally, in the embodiment, the working voltages of the first gate drive module GOA1 and the second gate drive module GOA2 are different, so that the bottom gate 11 and the top gate 12 work at different working voltages. The working voltage refers to the working voltage at which the first gate drive module GOA1 controls the bottom gate 11 to be turned on / normal working, and the working voltage at which the second gate drive module GOA2 controls the top gate 12 to be turned on / normal working. When the bottom gate 11 and the top gate 12 are N-type transistors turned on at a high level, the working voltage generally refers to the high-level voltage.

[0045] In the first embodiment, the gate gating unit 20 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected with the first control line L1, the source is connected with the first gate drive module GOA1, and the drain is connected with the bottom gate 11, so as to control the conduction of the bottom gate 11 and the first gate drive module GOA1 through the first transistor T1. The gate of the second transistor T2 is connected with the second control line L2, the source is connected with the second gate drive module GOA2, and the drain is connected with the top gate 12, so as to control the conduction of the top gate 12 and the second gate drive module GOA2 through the second transistor T2.

[0046] In the first embodiment, the gate gating unit 20 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected with the first control line L1, the source is connected with the first gate drive module GOA1, and the drain is connected with the bottom gate 11, so as to control the conduction of the bottom gate 11 and the first gate drive module GOA1 through the first transistor T1. The gate of the second transistor T2 is connected with the second control line L2, the source is connected with the second gate drive module GOA2, and the drain is connected with the top gate 12, so as to control the conduction of the top gate 12 and the second gate drive module GOA2 through the second transistor T2.

[0047] In the first embodiment, the double-gate structure 10 includes three working modes.

[0048] The first control line L1 outputs a first-level signal to control the first transistor T1 to be turned on, and the second control line L2 outputs a second-level signal to control the second transistor T2 to be turned off, so as to obtain a first working mode in which the bottom gate 11 controls the source and the drain to be turned on. Specifically, the first working mode is that the bottom gate 11 controls the source and the drain to be turned on at the first gate voltage output by the first gate drive module GOA1, so that the data line data charges the pixel electrode pxl, that is, the bottom-gate TFT works.

[0049] The first control line L1 outputs a second level signal to control the first transistor T1 to be off, and the second control line L2 outputs a first level signal to control the second transistor T2 to be on, so as to obtain the second working mode in which the top gate 12 controls the source and drain to be on. Specifically, the second working mode refers to that the top gate TFT is controlled by the second gate voltage output by the second gate driving module GOA2 to be on, so that the data line data charges the pixel electrode pxl, that is, the top gate TFT is on.

[0050] .

[0051] The first control line L1 outputs a first level signal to control the first transistor T1 to be on, and the second control line L2 outputs a first level signal to control the second transistor T2 to be on, so as to obtain the third working mode in which the bottom gate 11 and the top gate 12 control the source and drain to be on. Specifically, the third working mode refers to that the bottom gate TFT is controlled by the first gate voltage output by the first gate driving module GOA1 to be on, and at the same time, the top gate TFT is controlled by the second gate voltage output by the second gate driving module GOA2 to be on, so as to charge the data line data to the pixel electrode pxl. The third working mode refers to that the bottom gate TFT and the top gate TFT work.

[0052]

[0053] In a specific embodiment, the first transistor T1 and the second transistor T2 are N-type transistors, and the first level signal is a high level signal, and the second level signal is a low level signal. In another specific embodiment, the first transistor T1 and the second transistor T2 are P-type transistors, and at this time, the on-off of the first transistor T1 and the second transistor T2 is controlled by a low level signal, and the first level signal is a low level signal, and the second level signal is a high level signal. In other embodiments, the first transistor T1 and the second transistor T2 can be one N-type transistor and the other P-type transistor, and the driving method and working mode are similar to the above, which will not be described herein.

[0054] In another driving mode, in the first working mode, the second transistor T2 can also be on, and at the same time, the second gate driving module GOA2 outputs a low level voltage or a zero potential voltage,

[0055]

[0056] ​​Thus, the top gate 12 is discharged using the zero-potential voltage of the second gate drive module GOA2 to prevent the residual induced charge on the top gate 12 from affecting the bottom gate 11. Similarly, in the second operating mode, the first transistor T1 is turned on, and at the same time, the first gate drive module GOA1 outputs a second-level signal or a zero-potential voltage to discharge the bottom gate 11, thereby preventing the residual induced charge on the bottom gate 11 from affecting the top gate 12.

[0057] In another embodiment, the bottom gate 11 or the top gate 12 can also be discharged via a reset unit 30. For details, please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the display driving circuit of this application. Figure 2 As shown, the display driving circuit also includes a reset unit 30. One end of the reset unit 30 is grounded, and the other end is connected to the bottom gate 11 and / or the top gate 12 of the dual-gate structure 10, so as to reset the potential of the other gate when one gate is working. Specifically, when the bottom gate 11 is working, the top gate 12 is grounded to reset the potential of the top gate 12, thereby preventing the residual induced charge on the top gate 12 from affecting the bottom gate 11, or when the top gate 12 is working, the bottom gate 11 is grounded to reset the potential of the bottom gate 11, thereby preventing the residual induced charge on the bottom gate 11 from affecting the top gate 12.

[0058] In one specific embodiment, the reset unit 30 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The gate of the fourth transistor T4 is connected to the second gate driving module GOA2, its source is connected to the drain of the sixth transistor T6, and its drain is connected to the bottom gate 11. The gate of the fifth transistor T5 is connected to the first gate driving module GOA1, its source is connected to the drain of the sixth transistor T6, and its drain is connected to the top gate 12. The gate of the sixth transistor T6 is connected to the fourth control line L4, its source is grounded, and its drain is connected to the sources of both the fourth transistor T4 and the fifth transistor T5. This allows the sixth transistor T6 to control the conduction of the fourth transistor T4 and the fifth transistor T5 to ground, making it easier to control the conduction of the fourth transistor T4 and the fifth transistor T5 to ground.

[0059] In other embodiments, the reset unit 30 may also be other circuit structures, such as a single-pole double-throw switch circuit, which is not limited here.

[0060] Specifically, the driving mode of the reset unit 30 in the second embodiment includes: in the first working mode of the bottom-gate TFT, the bottom gate 11 is at a high level under the driving of the first gate driving module GOA1, the fifth transistor T5 is in an open state, at this time, the sixth transistor T6 is opened by the first level signal of the fourth control line L4, so that the top gate 12 is grounded through T5 and T6, thereby resetting the potential of the top gate 12. In the second working mode of the top-gate TFT, the top gate 12 is at a high level under the driving of the second gate driving module GOA2, the fourth transistor T4 is in an open state, at this time, the sixth transistor T6 is opened by the first level signal of the fourth control line L4, so that the bottom gate 11 is grounded through T4 and T6, thereby resetting the potential of the bottom gate 11. In the third working mode of the bottom-gate TFT+top-gate TFT, the fourth control line L4 outputs the second level signal to control the sixth transistor T6 to be closed, preventing the bottom gate 11 and the top gate 12 from being grounded, thereby ensuring the normal work of the bottom-gate TFT+top-gate TFT.

[0061] In a specific embodiment, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be N-type transistors, and the first level signal is a high level signal, and the second level signal is a low level signal. In another specific embodiment, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are P-type transistors, at this time, the conduction of the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 is controlled by a low level signal, and the first level signal is a low level signal, and the second level signal is a high level signal.

[0062] The application also provides another gate gating unit structure, specifically, please refer to Figure 3 , Figure 3 The application provides a structure schematic diagram of a third embodiment of the display driving circuit. As shown in the figure, the display driving circuit includes a double-gate structure 10 and a gate gating unit 20 connected with the double-gate structure 10. Figure 3

[0063] The double-gate structure 10 is as described in the first embodiment, which is not repeated here.

[0064] In the embodiment, the gate gating unit 20 includes a first transistor T1, a second transistor T2 and a third transistor T3.

[0065] ​The gate of the first transistor T1 is connected to the first control line L1, the source is connected to the first gate drive module GOA1, and the drain is connected to the bottom gate 11. The conduction of the bottom gate 11 and the first gate drive module GOA1 is controlled by the first transistor T1. The gate of the second transistor T2 is connected to the second control line L2, the source is connected to the second gate drive module GOA2, and the drain is connected to the top gate 12. The conduction of the top gate 12 and the second gate drive module GOA2 is controlled by the second transistor T2. The gate of the third transistor T3 is connected to the third control line L3, the source is connected to one of the bottom gate 11 and the top gate 12, and the drain is connected to the other of the bottom gate 11 and the top gate 12.

[0066] In the embodiment, the dual-gate structure 10 includes four working modes.

[0067] The first control line L1 outputs a first level signal to control the first transistor T1 to be turned on, the second control line L2 outputs a second level signal to control the second transistor T2 to be turned off, and the third control line L3 outputs a second level signal to control the third transistor T3 to be turned off, thereby controlling the bottom gate 11 and the top gate 12 to be disconnected, so as to obtain the first working mode in which the bottom gate 11 controls the source and the drain to be turned on under the first gate voltage output by the first gate drive module GOA1. Specifically, the first working mode is that the bottom gate 11 controls the source and the drain to be turned on under the first gate voltage, so that the data line data charges the pixel electrode pxl. That is, the first working mode refers to the bottom gate TFT+GOA1 working.

[0068] The first control line L1 outputs a second level signal to control the first transistor T1 to be turned off, the second control line L2 outputs a first level signal to control the second transistor T2 to be turned on, and the third control line L3 outputs a second level signal to control the third transistor T3 to be turned off, thereby controlling the bottom gate 11 and the top gate 12 to be disconnected, so as to obtain the second working mode in which the top gate 12 controls the source and the drain to be turned on under the second gate voltage output by the second gate drive module GOA2. Specifically, the second working mode is that the top gate 12 controls the source and the drain to be turned on under the second gate voltage, so that the data line data charges the pixel electrode pxl. That is, the second working mode refers to the top gate TFT+GOA2 working.

[0069] The first control line L1 outputs a first level signal to control the first transistor T1 to be turned on, the second control line L2 outputs a second level signal to control the second transistor T2 to be turned off, and the third control line L3 outputs a first level signal to control the third transistor T3 to be turned on, thereby controlling the bottom gate 11 and the top gate 12 to be turned on, so that the third working mode is obtained in which the bottom gate 11 and the top gate 12 control the source and the drain to be turned on under the first gate voltage output by the first gate driving module GOA1. Specifically, the third working mode is that the bottom gate 11 and the top gate 12 control the source and the drain to be turned on under the first gate voltage, so that the data line data charges the pixel electrode pxl. That is, the third working mode refers to the bottom gate TFT + the top gate TFT + the GOA1 working. In the third working mode, the bottom gate 11 plays a main role, and the top gate 12 plays a promoting role.

[0070] The first control line L1 outputs a second level signal to control the first transistor T1 to be turned off, the second control line L2 outputs a first level signal to control the second transistor T2 to be turned on, and the third control line L3 outputs a first level signal to control the third transistor T3 to be turned on, thereby controlling the bottom gate 11 and the top gate 12 to be turned on, so that the fourth working mode is obtained in which the bottom gate 11 and the top gate 12 control the source and the drain to be turned on under the second gate voltage output by the second gate driving module GOA2. Specifically, the fourth working mode is that the bottom gate 11 and the top gate 12 control the source and the drain to be turned on under the second gate voltage, so that the data line data charges the pixel electrode pxl. That is, the fourth working mode refers to the bottom gate TFT + the top gate TFT + the GOA2 working. In the fourth working mode, the top gate 12 plays a main role, and the bottom gate 11 plays a promoting role.

[0071] In the embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 are all N-type transistors, the first level signal is a high-level voltage, and the second level signal is a low-level voltage. In another specific embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors, at this time, the turning on of the first transistor T1, the second transistor T2, and the third transistor T3 is controlled by a low-level signal, then the first level signal is a low-level voltage, and the second level signal is a high-level voltage. In other embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 can be partially N-type transistors and partially P-type transistors, which are not limited herein.

[0072] In the embodiment, the bottom gate TFT and the top gate TFT of the double-gate structure 10 are both N-type transistors, then the first gate voltage at which the first gate driving module GOA1 works and the second gate voltage at which the second gate driving module GOA2 works are both high-level voltages. In other embodiments, they can also be P-type transistors, which are not limited herein.

[0073] In another embodiment, to prevent residual charge on the voltage of the other gate in the dual-gate structure 10 from affecting the gate in operation when the single-bottom-gate TFT or single-top-gate TFT is working, this application also provides a fourth display driving circuit, please refer to [reference needed]. Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the display driving circuit of this application. Figure 4 As shown, based on the third embodiment, the display driving circuit further includes a reset unit 30. One end of the reset unit 30 is grounded, and the other end is connected to the bottom gate 11 and / or the top gate 12 of the dual-gate structure 10, so as to reset the potential of the other gate when one gate is working. Specifically, when the bottom gate 11 is working, the top gate 12 is grounded to reset the potential of the top gate 12, thereby preventing the residual induced charge on the top gate 12 from affecting the bottom gate 11, or when the top gate 12 is working, the bottom gate 11 is grounded to reset the potential of the bottom gate 11, thereby preventing the residual induced charge on the bottom gate 11 from affecting the top gate 12.

[0074] In one specific embodiment, the reset unit 30 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The gate of the fourth transistor T4 is connected to the second gate driving module GOA2, its source is connected to the drain of the sixth transistor T6, and its drain is connected to the bottom gate 11. The gate of the fifth transistor T5 is connected to the first gate driving module GOA1, its source is connected to the drain of the sixth transistor T6, and its drain is connected to the top gate 12. The gate of the sixth transistor T6 is connected to the fourth control line L4, its source is grounded, and its drain is connected to the sources of both the fourth transistor T4 and the fifth transistor T5. This allows the sixth transistor T6 to control the conduction of the fourth transistor T4 and the fifth transistor T5 to ground, making it easier to control the conduction of the fourth transistor T4 and the fifth transistor T5 to ground.

[0075] In other embodiments, the reset unit 30 can also not be provided, and the bottom gate 11 or the top gate 12 can be discharged directly by the low voltage of the first gate drive module GOA1 and the second gate drive module GOA2. Specifically, in the first working mode of the bottom gate TFT+GOA1, the second transistor T2 is controlled to be turned on by the second control line L2, and at the same time, the second gate drive module GOA2 outputs a low voltage or a zero potential voltage, so that the top gate 12 is discharged by the low voltage of the second gate drive module GOA2, to avoid the influence of the residual induced charge on the top gate 12 on the bottom gate 11. Similarly, in the second working mode of the top gate TFT+GOA2, the first transistor T1 is controlled to be turned on by the first control line L1, and at the same time, the first gate drive module GOA1 outputs a low voltage or a zero potential voltage, so that the first gate drive module GOA1 discharges the bottom gate 11, to avoid the influence of the residual induced charge on the bottom gate 11 on the top gate 12. In the third and fourth working modes, the bottom gate 11 or the top gate 12 does not need to be reset, and the first gate drive module GOA1 and the second gate drive module GOA2 can normally work. This is not limited here.

[0076] In other embodiments, the gate selection unit 20 can also be other circuit structures, which are not limited here. Compared with the structure of the gate selection unit 20 in the first and second embodiments, the gate selection unit 20 in the third and fourth embodiments can achieve more gray scales.

[0077] It should be noted that the "first", "second", and the like in the present application do not limit the order of the transistors.

[0078] Generally, the on-state current of the dual-gate TFT is higher than that of the single-gate TFT, and the charging rate of the dual-gate TFT is better than that of the single-gate TFT. The charging rate of the TFT is different, and the display gray scale of the pixel electrode controlled thereby is also different. Therefore, in actual application, different types of TFTs can be designed to have a certain gradient change according to the charging rate, to achieve the charging rate of different working modes, thereby improving the display gray scale of the display picture.

[0079] In the first and second embodiments, the charging rate of the dual-gate structure 10 in the third working mode of the bottom gate TFT+top gate TFT can be designed to be greater than that in the first working mode of the bottom gate TFT, and greater than that in the second working mode of the top gate TFT. That is, the charging rate of the bottom gate TFT+top gate TFT is greater than that of the bottom gate TFT, and greater than that of the top gate TFT, so as to realize three different display gray scales under the same gray scale voltage, and further increase the display gray scale.

[0080] In the third embodiment and the fourth embodiment, the charging rate of the dual-gate structure 10 in the third working mode is greater than the charging rate in the first working mode, the charging rate in the first working mode is greater than the charging rate in the fourth working mode, and the charging rate in the fourth working mode is greater than the charging rate in the second working mode. That is, the charging rate of the bottom-gate TFT + top-gate TFT + GOA1 working mode > the charging rate of the bottom-gate TFT + GOA1 working mode > the charging rate of the bottom-gate TFT + top-gate TFT + GOA2 working mode > the charging rate of the top-gate TFT + GOA2 working mode. In a specific embodiment, different charging rates can be achieved by designing the areas of the top-gate layer and the bottom-gate layer of the dual-gate structure, which is not limited herein. Specifically, the charging rate of the bottom-gate TFT + GOA1 working mode > the charging rate of the bottom-gate TFT + top-gate TFT + GOA2 working mode can be achieved by increasing the area of the bottom-gate layer, which is not limited herein, or can also be achieved by setting the voltages on the first gate drive module GOA1 and the second gate drive module GOA2, which is not limited herein.

[0081] In other specific embodiments, the bottom gate 11 and the top gate 12 can also be connected to the same gate control module through different transistors, that is, the working modes of the bottom gate 11 and the top gate 12 are controlled by the same gate control module. However, in general, there is a difference between the working voltages of the bottom gate 11 and the top gate 12. In this embodiment, in order to ensure the normal working of the bottom gate 11 and the top gate 12, the working voltages of the bottom gate 11 and the top gate 12 are controlled by the first gate drive module GOA1 and the second gate drive module GOA2, respectively, which is not limited herein.

[0082] It should be noted that the present embodiment is a preferred embodiment, but is not limited to the specific implementation in the present embodiment, and the implementation in other embodiments also belongs to the protection scope of the present application.

[0083] The present application also provides a specific dual-gate structure, which is described in detail in the following. Figure 5 , Figure 5 is a cross-sectional structure diagram of an embodiment of the dual-gate structure of the present application. As shown in Figure 5 , the dual-gate structure 10 includes a bottom-gate layer 101, the surface of the bottom-gate layer 101 is provided with a first gate insulating layer 102, the surface of the first gate insulating layer 102 is provided with a semiconductor layer 103, the surface of the semiconductor layer 103 is provided with a spaced source layer 1041 and a drain layer 1042, the surface of the source layer 1041 and the drain layer 1042 and the middle thereof are provided with a second gate insulating layer 105, and the surface of the second gate insulating layer 105 is provided with a top-gate layer 106.

[0084] The present application also provides a display panel, which is described in detail in the following. Figure 6 , Figure 6Fig. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application. Figure 6 As shown in Fig. 1, the display panel comprises a plurality of pixel units 601 arranged in an array, each of which comprises a display driving circuit as described in the above embodiments.

[0085] In the second embodiment, in order to improve the utilization of the display panel, the bottom gate 11 of the double-gate structure 10 of the pixel unit 601 in the same row is connected to the same first gate driving module GOA1 through the same first transistor T1, and the top gate 12 of the double-gate structure 10 of the pixel unit 601 in the same row is connected to the same second gate driving module GOA2 through the same second transistor T2. Meanwhile, the bottom gate 11 and the top gate 12 of the double-gate structure are connected through a third transistor T3. For details, please refer to Fig. 2. Figure 7 , Figure 7 Fig. 2 is a structural schematic diagram of a display panel according to a second embodiment of the present application.

[0086] In the second embodiment, each pixel unit 601 comprises a double-gate structure 10, and the double-gate structures 10 in the pixel units 601 in the same row are connected to the first gate driving module GOA1 and the second gate driving module GOA2 through a gate selection unit 20.

[0087] In the second embodiment, the double-gate structures 10 in the same row are also connected to the ground through a reset unit 30. The double-gate structures 10 in the pixel units 601 in the same row are controlled through the reset unit 30, so that the pixel units 601 in the same row display the same gray scale display screen.

[0088] In the second embodiment, the gate selection units 20 and the reset units 30 connected to the pixel units 601 in adjacent two rows are staggered. That is, one side of the pixel unit 301 in the current row is connected to the gate selection unit 20, and the other side is connected to the reset unit 30, and one side of the pixel unit 601 in the next row is connected to the reset unit 30, and the other side is connected to the gate selection unit 20. In other embodiments, the gate selection units 20 and the reset units 30 can also be not staggered, that is, one side of the pixel unit 601 in each row is connected to the gate selection unit 20, and the other side is connected to the reset unit 30, which is not limited herein.

[0089] The present application also provides a graph showing the relationship between the transmittance and the applied voltage, for details, please refer to Fig. 3. Figure 8 , Figure 8 Fig. 3 is a schematic diagram showing the relationship between the transmittance and the applied voltage in a TFT-LCD. As shown in Fig. 3, the gray area is the part that needs to be controlled by selecting the gray scale voltage to change the transmittance of the liquid crystal. Figure 8 Figure 8 ​As can be seen, in the gray scale voltage selection range, the change of the applied voltage causes the transmittance of the light in the liquid crystal screen to also present a continuous change, and thus the display of the light and dark change can be replaced by the change of the gray scale voltage. The specific steps of increasing the display gray scale number are as follows:

[0090] First, the VT curve of the product liquid crystal in operation is determined, and then the selectable gray scale voltage range is determined.

[0091] Second, four TFTs with different charging rates under the control of GOA1 and GOA2 respectively are simulated and designed, and the charging rates are: bottom gate + top gate + GOA1 work > bottom gate + GOA1 work > bottom gate + top gate + GOA2 work > top gate + GOA2 work.

[0092] Third, different TFTs are switched. The actual value of the gray scale voltage is composed of the gray scale voltage setting value and the compensation value, which is caused by the characteristics of the TFT device itself. The loss of the charging rate will cause the actual pixel voltage to deviate from the gray scale setting value, so the compensation value is needed to make up for it. When the same actual gray scale voltage value is input, the actual voltage transmitted to the pixel electrode by the TFTs with different charging rates will be different, thereby increasing the number of actual pixel electrode voltages, enriching the display picture in actual display, and being conducive to improving the display quality.

[0093] In actual application, if the gray scale compensation value can be controllably adjusted, the driving IC can perform controllable changes of the gray scale compensation value according to the picture display, so that theoretically more refined gray scale segmentation can be realized without increasing the gray scale number.

[0094] In the embodiment, the conversion of the light and dark effect of the display picture can also be realized by switching the working mode of the TFT. Specifically, the display is equipped with a corresponding sensor to perceive the change of the external light intensity. When the external light intensity is high (daytime) or dark (night), the sensor feeds back to the driving IC end (control end), the driving IC sends a control signal, and the TFT is selected and switched to work, thereby reducing the light intensity ratio of the display area to the environment light and reducing visual fatigue. The change of the screen brightness can also be realized by directly adjusting the change of the backlight brightness.

[0095] The beneficial effects of the embodiment are: the working mode of the TFT in the double-gate structure is selected by selecting the first transistor, the second transistor and the third transistor in the selection circuit, the picture display of different gray scales is realized by designing the charging rate under different working modes, the gray scale number of the picture display is increased by switching the working mode of the TFT, and the picture display quality is improved.

[0096] The above merely illustrates the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display driving circuit, characterized in that, It includes at least a dual-gate structure and a gate selection unit connected to the gate of the dual-gate structure; The dual-gate structure includes a bottom gate and a top gate, as well as a source and a drain that are controlled to be turned on by the bottom gate and / or the top gate; the bottom gate is connected to a first gate driving module through the gate selection unit, the top gate is connected to a second gate driving module through the gate selection unit, the source is connected to a data line, and the drain is connected to a pixel electrode, so as to control the working mode of the dual-gate structure through the gate selection unit, thereby controlling the display grayscale of the pixel electrode; The gate selection unit includes a first transistor, a second transistor, and a third transistor. The gate of the first transistor is connected to a first control line, the source is connected to the first gate driving module, and the drain is connected to the bottom gate. The gate of the second transistor is connected to a second control line, the source is connected to the second gate driving module, and the drain is connected to the top gate. The gate of the third transistor is connected to a third control line, the source is connected to one of the bottom gate and the top gate, and the drain is connected to the other of the bottom gate and the top gate.

2. The display driving circuit according to claim 1, characterized in that, The first gate drive module and the second gate drive module operate at different voltages.

3. The display driving circuit according to claim 1, characterized in that, The first control line outputs a first level signal to control the first transistor to be turned on, the second control line outputs a second level signal to control the second transistor to be turned off, and the third control line outputs a second level signal to control the bottom gate to be disconnected from the top gate, thereby obtaining a first working mode in which the bottom gate controls the source and the drain to be turned on under the first gate voltage output by the first gate driving module. The first control line outputs a second level signal to control the first transistor to be turned off, the second control line outputs a first level signal to control the second transistor to be turned on, and the third control line outputs a second level signal to control the bottom gate and the top gate to be disconnected, thereby obtaining a second working mode in which the top gate controls the source and the drain to be turned on under the second gate voltage output by the second gate driving module. The first control line outputs a first level signal to control the first transistor to be turned on, the second control line outputs a second level signal to control the second transistor to be turned off, and the third control line outputs a first level signal to control the bottom gate and the top gate to be turned on, thereby obtaining a third working mode in which the bottom gate and the top gate simultaneously control the source and the drain to be turned on under the first gate voltage output by the first gate driving module. The first control line outputs a second level signal to control the first transistor to be turned off, the second control line outputs a first level signal to control the second transistor to be turned on, and the third control line outputs a first level signal to control the bottom gate and the top gate to be turned on, thereby obtaining a fourth operating mode in which the bottom gate and the top gate simultaneously control the source and the drain to be turned on under the second gate voltage output by the second gate driving module.

4. The display driving circuit according to claim 3, characterized in that, The charging rate of the dual-gate structure in the third operating mode is greater than that in the first operating mode, the charging rate in the first operating mode is greater than that in the fourth operating mode, and the charging rate in the fourth operating mode is greater than that in the second operating mode.

5. The display driving circuit according to claim 1, characterized in that, The display driving circuit also includes a reset unit, one end of which is grounded and the other end is connected to the gate of the dual-gate structure, so as to reset the potential of the other gate when one gate is working.

6. The display driving circuit according to claim 5, characterized in that, The reset unit includes a fourth transistor, a fifth transistor, and a sixth transistor; The gate of the fourth transistor is connected to the second gate driving module, the source is connected to the drain of the sixth transistor, and the drain is connected to the bottom gate. The gate of the fifth transistor is connected to the first gate driving module, the source is connected to the drain of the sixth transistor, and the drain is connected to the top gate. The gate of the sixth transistor is connected to the fourth control line, the source is grounded, and the drain is connected to the source of the fourth transistor and the fifth transistor.

7. A display panel, characterized in that, The display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a display driving circuit as described in any one of claims 1 to 6.

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