Integrated Chip and Its Forming Method

Abstract

An integrated chip has a memory cell comprising a magnetic tunnel junction (MTJ) device and an access selector device. The MTJ device includes a free layer and a fixed layer. The access selector device includes a first metal structure and a second metal structure spaced apart by one or more non-metallic layers. The first metal structure includes a polarized magnetic layer. The polarized magnetic layer generates a magnetic field extending through the free layer, tilting its magnetic field to significantly reduce the switching time for the MTJ device. The access selector device may be a bipolar selector. The polarized magnetic layer may be incorporated into the electrodes of the bipolar selector. Both the access selector device and the MTJ device can be formed from a stack of material layers. The resulting memory cell can be compact and has good write speeds. Embodiments of the invention also relate to a method of forming an integrated chip.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated chips and methods for forming the same. Background Technology

[0002] Many electronic devices contain electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile electronic memory uses power to maintain data, while non-volatile memory can store data without power. Magnetoresistive random access memory (MRAM) is a type of non-volatile memory that has long attracted attention. Summary of the Invention

[0003] According to one aspect of the present invention, an integrated chip is provided, comprising: a magnetic tunnel junction (MTJ) device having a first electrode and a second electrode; and an access selector device for the MTJ device, comprising a first metal structure and a second metal structure spaced apart by one or more non-metallic layers; wherein one of the first metal structure and the second metal structure is connected to the second electrode, and the first metal structure includes a polarized ferromagnetic layer.

[0004] According to another aspect of the present invention, an integrated chip is provided, comprising: a magnetic tunnel junction (MTJ) device disposed within a dielectric structure above a substrate, the MTJ device including a magnetic tunnel junction disposed between a first MTJ electrode and a second MTJ electrode; and a bipolar selector (BS) including an intermediate structure disposed between a first BS electrode and a second BS electrode; wherein the second BS electrode is connected to or integral with the first MTJ electrode; the intermediate structure is one or more layers of an insulator and / or a semiconductor; and one of the first BS electrode and the second BS electrode includes a polarizing magnetic layer.

[0005] According to another aspect of the present invention, a method for forming an integrated chip is provided, comprising: forming a magnetic tunnel junction (MTJ) device over a semiconductor substrate, the MTJ device having a magnetic tunnel junction disposed between a first electrode and a second electrode; and forming a bipolar selector for the MTJ device; wherein the bipolar selector includes a ferromagnetic material layer having a fixed polarization; and the bipolar selector is connected to the second electrode. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A schematic diagram of a memory circuit with a memory cell according to some embodiments of the present invention is shown. The memory cell includes a magnetic tunnel junction (MTJ) device and an access selector device having a polarized magnetic layer configured to substantially reduce the switching time for the MTJ device.

[0008] Figure 2A The traces of the magnetic field direction vector of the free layer of the MTJ device during switching are shown;

[0009] Figure 2B Another trace of the magnetic field direction vector of the free layer of the MTJ device during switching is shown, compared with Figure 2A In contrast, it demonstrates how the initial tilt angle reduces the number of precession cycles during the switching operation;

[0010] Figures 3A to 3D Cross-sectional views of some embodiments of an integrated circuit with a memory cell according to the present invention are shown. The memory cell includes an MTJ device and an access selector device having a polarized magnetic layer configured to substantially reduce the switching time for the MTJ device.

[0011] Figure 4 A block diagram of a memory circuit is shown, comprising a memory array having multiple memory cells, each memory cell including an access selector device with a bipolar selector.

[0012] Figure 5 Cross-sectional views of some embodiments of an integrated chip with memory cells are shown. The memory cells include magnetic tunnel junction (MTJ) devices and access selector devices having polarized magnetic layers configured to substantially reduce the switching time for the MTJ devices.

[0013] Figures 6-14 Some embodiments of a method for forming an integrated chip with memory cells are shown, the memory cells including magnetic tunnel junction (MTJ) devices and access selector devices having polarized magnetic layers configured to substantially reduce the switching time for the MTJ devices.

[0014] Figures 15-16 Some other embodiments of a method for forming an integrated chip with memory cells are shown, the memory cells including magnetic tunnel junction (MTJ) devices and access selector devices having polarized magnetic layers configured to substantially reduce the switching time for the MTJ devices.

[0015] Figure 17 Flowcharts are provided for some embodiments of a method for forming an integrated chip with memory cells, the memory cells including magnetic tunnel junction (MTJ) devices and access selector devices having polarized magnetic layers configured to substantially reduce switching time for the MTJ devices. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] A magnetic tunnel junction (MTJ) device is an MRAM device comprising an MTJ arranged vertically between conductive electrodes. The MTJ includes a fixed layer spaced from a free layer by a tunnel barrier layer. The fixed layer has static (i.e., fixed) magnetic orientation, while the free layer has magnetic orientation that can switch between a parallel configuration relative to the fixed layer's orientation and an anti-parallel configuration relative to the fixed layer's orientation. The parallel configuration provides a low-resistance state that digitally stores data as a first data state (e.g., logic "1"). The anti-parallel configuration provides a high-resistance state that digitally stores data as a second data state (e.g., logic "0").

[0019] Typically, MTJ devices are arranged in rows and columns within a memory array. Read or write operations are performed on the MTJ devices within the memory array by activating word lines and bit lines to provide voltage and / or current to the selected MTJ devices. Access selector devices for the MTJ devices allow current to flow selectively through the selected MTJ device in either of two opposite directions. This is because the polarization orientation of the free layers in the MTJ device switches between an anti-parallel configuration and a parallel configuration, providing either a high-resistance state or a low-resistance state, depending on the direction of the applied current. For example, current flow from the bottom electrode to the top electrode can provide an anti-parallel configuration for the MTJ device, resulting in a high-resistance state, while current flow from the top electrode to the bottom electrode can provide a parallel configuration for the MTJ device, resulting in a low-resistance state.

[0020] One type of access selector device used in MTJ devices is the MOSFET transistor. While MOSFET transistors offer good performance, the relatively high voltage and / or current used during write operations in MTJ devices results in a relatively large size for MOSFET transistors relative to the MTJ device. The large size of MOSFET transistors limits the size of memory cells in memory arrays. Another type of access selector device comprises two unipolar selectors (i.e., each device carries current in only one direction during normal operation). Yet another type of access selector device is the bipolar selector. Bipolar selectors, formed from stacked thin films, can have a much smaller size than MOSFETs.

[0021] The integrated chip according to the present invention has a memory cell comprising a magnetic tunnel junction (MTJ) device and an access selector device. The MTJ device comprises a free layer and a fixed layer. The access selector device comprises a first metal structure and a second metal structure spaced apart by one or more non-metallic layers. According to the present teachings, the first metal structure comprises a polarized magnetic layer. Similar to the fixed layer, the polarized magnetic layer has a static or fixed magnetic orientation. The magnetic orientation of the polarized magnetic layer is generally different from the magnetic orientation of the fixed layer. In some embodiments, the magnetic orientation of the polarized magnetic layer is almost orthogonal to the magnetic orientation of the fixed layer. The magnetic field generated by the polarized magnetic layer extends through the free layer, tilting its magnetic orientation away from the direction of current, thereby significantly reducing the switching time of the MTJ device. In some of these teachings, the access selector device is a bipolar selector. In some of these teachings, the polarized magnetic layer is incorporated into the electrodes of the bipolar selector. In some of these teachings, the bipolar selector comprises a dielectric layer formed by oxidizing a portion of the polarized magnetic layer. Forming the dielectric layer by oxidizing the polarized magnetic layer provides a simplified process and facilitates the integration of the bipolar selector with the MTJ device. In some of these teachings, both the access selector device and the MTJ device are formed from a stack of material layers. The memory cells in the integrated chip according to this teaching can be manufactured efficiently, can be compact, and can have good write speeds.

[0022] Figure 1 A schematic diagram of a memory cell 100 having an access selector device 101 and a magnetic tunnel junction (MTJ) device 109 according to some embodiments of the present invention is shown. The access selector device 101 includes a polarized magnetic layer 104a configured to substantially reduce the switching time for the MTJ device.

[0023] MTJ device 109 includes MTJ 107 disposed between a first electrode 108 and a second electrode 105. The first electrode 108 is connected to a word line WL, and the second electrode 105 is connected to an access selector device 101 that modulates access to MTJ device 109 (e.g., read access and / or write access). Access selector device 101 is also connected to a bit line BL. In some embodiments, access selector device 101 is located between BL and MTJ device 109. In some alternative embodiments, access selector device 101 is located between WL and MTJ device 109.

[0024] In some embodiments, the MTJ107 includes a fixed layer 107c spaced apart from a free layer 107a by a dielectric tunnel barrier 107b. The fixed layer 107c has a fixed magnetic polarization, while the free layer 107a has a magnetic polarization relative to the fixed layer 107c that can be changed to parallel (i.e., "P" state) or anti-parallel (i.e., "AP" state) magnetic polarization by a switching operation. The switching operation can be performed using the tunnel magnetoresistance (TMR) effect. The relationship between the magnetic polarizations of the fixed layer 107c and the free layer 107a defines the resistive state of the MTJ107, thereby enabling the MTJ107 to store data states.

[0025] In some embodiments, the polarization of the fixed layer 107c is vertical (along the first direction 110 or the second direction 112). In some embodiments, the fixed layer 107c includes cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), etc. In some embodiments, the dielectric tunnel barrier 107b includes magnesium oxide (MgO), aluminum oxide (Al2O3), etc. In some embodiments, the free layer 107a includes cobalt (Co), iron (Fe), boron (B), etc. In some embodiments, the first electrode 108 and the second electrode 105 include one or more of titanium, tantalum, tungsten, titanium nitride, tantalum nitride, etc.

[0026] Access selector device 101 may be a bipolar selector, comprising a first electrode 104 and a second electrode 102 spaced apart by a non-metallic structure 103, wherein the first electrode 104 is a metallic structure and the second electrode 102 is another metallic structure. The non-metallic structure 103 may be one or more suitable insulators and / or semiconductors. In some embodiments, the non-metallic structure 103 comprises an insulator, which is an oxide of a ferromagnetic metal, such as cobalt oxide (CoOx), nickel oxide (NiOx), iron oxide (FeOx), etc. In some embodiments, the non-metallic structure 103 comprises an insulator, which is an inherent oxide, such as hafnium oxide (HfO2), titanium oxide (TiO2), aluminum oxide (Al2O3), etc. In some embodiments, the non-metallic structure 103 comprises a single layer that is an insulator; and the access selector device 101 is a metal-insulator-metal (MIM) bipolar selector. In some embodiments, the non-metallic structure 103 includes a first insulator 103a and a second insulator 103b, and the access selector device 101 is a (MIIM) bipolar selector. In some embodiments, the first insulator 103a has a first bandgap energy, and the second insulator 103b has a second bandgap energy different from the first bandgap energy. In some of these embodiments, the first insulator 103a is titanium oxide (TiO2) or the like. In some of these embodiments, the second insulator 103b is an oxide of a magnetic metal. In some of these embodiments, the oxide of the magnetic metal is cobalt oxide (CoOx), iron oxide (FeOx), nickel oxide (NiOx), etc. For example, the oxide of the magnetic metal may be Co3O4.

[0027] In some embodiments, the non-metallic structure 103 includes a semiconductor layer; and the access selector device 101 is a metal-semiconductor-metal (MSM) bipolar selector. Suitable semiconductors for the access selector device 101 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), oxide semiconductors such as indium gallium zinc oxide (IGZO), group III-V materials such as indium gallium arsenide (InGaAs), etc. In some embodiments, the non-metallic structure 103 includes multiple semiconductor layers. In some embodiments, the non-metallic structure 103 includes a mixture of insulator and semiconductor layers. Multilayering of different materials can help provide the desired rectification characteristics for the access selector device 101.

[0028] During operation, the access selector device 101 allows current to be driven by a relatively large voltage difference, thus passing through with a relatively small resistance. Current can flow through the MTJ device 109 along a first direction 110 (e.g., from word line WL to bit line BL) or a second direction 112 opposite to the first direction 110 (e.g., from bit line BL to word line WL). Current flowing through the MTJ device 109 along the first direction 110 is used to write a first data state (e.g., logic "0") to the MTJ device 109. Current flowing through the MTJ device 109 along the second direction 112 is used to write a second data state (e.g., logic "1") to the MTJ device 109. The access selector device 101 exhibits significantly greater resistance for current driven by a small voltage difference. Therefore, when memory cell 100 is not selected, the access selector device 101 can reduce leakage current through the MTJ device 109.

[0029] The first electrode 104 and the second electrode 102 of the access selector device 101 may comprise one or more metals, such as titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), and copper (Cu). According to some aspects of this teaching, one of the first electrode 104 and the second electrode 102 includes a polarized magnetic layer. The polarized magnetic layer may be a ferromagnetic layer. The ferromagnetic layer may be cobalt (Co), iron (Fe), nickel (Ni), or an alloy such as cobalt-iron-boron (CoFeB), or a multilayer ferromagnetic structure such as cobalt-iron / nickel-iron (CoFe / NiFe). In some embodiments, the polarized magnetic layer has in-plane polarization, which is perpendicular to both the first direction 110 and the second direction 112. In some embodiments, one of the first electrode 104 and the second electrode 102 of the access selector device 101 includes a polarized ferromagnetic layer and a metal. For example, the first electrode 104 may include a polarized magnetic layer 104a and a nonmagnetic layer 104b, which is metallic. In a more specific example, the polarized magnetic layer 104a can be cobalt (Co) or the like, while the non-magnetic layer 104b can be titanium (Ti) or the like.

[0030] The polarized magnetic layer 104a generates a magnetic field 114, which is operable to tilt the magnetic field in the free layer 107a away from the direction of the current, thereby reducing the write time (switching time) for the MTJ device 109. Figure 2A and Figure 2B This effect is explained. For example... Figure 2AAs shown in curve 200a, the polarization direction 201a of the magnetic field in the free layer 107a does not move along a direct path when transitioning from the first direction 203a to the second direction 205a, but precesses around axis 209 to form a spiral. The axis 209 of this spiral is oriented along the current direction, which can be either the first direction 110 or the second direction 112. The time during which this precession occurs is called the latency of the write operation. For example, the latency can range from approximately 5 nanoseconds to approximately 10 nanoseconds. Figure 2B As shown, if the initial direction of polarization is slightly tilted away from the axis, the number of precessions and the resulting latency can be greatly reduced.

[0031] In practice, without the polarized magnetic layer 104a, the magnetic field of the free layer 107a is approximately parallel to the axis 209, and the initial movement away from the axis 209 is very slow and has many precessions. The polarized magnetic layer 104a initially tilts the magnetic field of the free layer 107a, which can significantly reduce the latency. In some embodiments, the polarized magnetic layer 104a tilts the magnetic field of the free layer 107a by about one to about five degrees. In some embodiments, the polarized magnetic layer 104a tilts the magnetic field of the free layer 107a sufficiently to reduce the latency by half or more. In some embodiments, the tilt reduces the latency by eight times or more. Smaller tilt angles may be sufficient to achieve these results.

[0032] Figures 3A to 3D Cross-sectional views 300, 320, 340, and 360 of an integrated chip according to various embodiments of the present invention are shown. Each cross-sectional view is characterized by a memory cell comprising an MTJ device and an access selector device having an intermediate structure disposed between two metal structures. One of the metal structures includes a polarized magnetic layer, the magnetic field generated by which the magnetic field can effectively reduce the number of precession cycles experienced by the free layer of the MTJ device during switching.

[0033] Figure 3AA cross-sectional view 300 of an integrated chip having a dielectric structure 304 disposed above a substrate 302 is shown. The dielectric structure 304 includes multiple stacked interlayer dielectric (ILD) layers and surrounds a first memory cell 305a and a second memory cell 305b, the second memory cell 305b being laterally adjacent to the first memory cell 305a. Both the first memory cell 305a and the second memory cell 305b include an access selector device 101 and an MTJ device 109 configured to store data states. In each of the first memory cell 305a and the second memory cell 305b, the access selector device 101 and the MTJ device 109 are formed by separate vertical stacks of thin films or layers. The access selector device 101 is a bipolar selector that includes a polarized magnetic layer 104a that generates a magnetic field 114a, which effectively tilts the polarization of a free layer 107a away from the direction of current (either a first direction 110 or a second direction 112). This effect can occur regardless of whether the free layer 107a is in a parallel or anti-parallel configuration. The nonmagnetic layer 104b of the first electrode 104 is adjacent to the second electrode 105 of the MTJ device 109. These adjacent layers can be formed from a single layer of a material.

[0034] The dielectric structure 304 further surrounds a plurality of metal interconnect layers, including adjacent interconnect layers 306a and 306b. A first memory cell 305a and a second memory cell 305b are disposed between interconnect layers 306a and 306b. Interconnect layers 306a and 306b may include interconnect lines and interconnect vias. The interconnect lines and interconnect vias include conductive materials (e.g., copper, aluminum, tungsten, etc.). The interconnect lines and interconnect vias may further include a diffusion barrier layer and / or an adhesive layer surrounding the conductive material.

[0035] Figure 3B A cross-sectional view 320 of an integrated chip according to some other embodiments of the present invention is shown. In cross-sectional view 320, a first memory cell 305c and a second memory cell 305d are disposed within a dielectric structure 304. Each memory cell includes an access selector device 101 and an MTJ device 109. The polarized magnetic layer 104a of the access selector device 101 generates a magnetic field 114b capable of effectively tilting the polarization of the free layer 107a away from the current direction, regardless of whether the free layer 107a is in a parallel or anti-parallel configuration. The first memory cell 305c and the second memory cell 305d are... Figure 3AThe difference between the first memory cell 305a and the second memory cell 305b in cross-sectional view 300 is that the MTJ device 109 is positioned above the access selector device 101. In the device shown in cross-sectional view 320, the second electrode 102 of the MTJ device 109 is adjacent to the first electrode 108 of the access selector device 101. These electrodes can be formed from a single layer of a material. In other words, the top electrode for one device can provide the bottom electrode for another device.

[0036] As shown in the comparison of cross-sectional views 300 and 320, the layers of the access selector device 101 can be formed on top of or below the layers of the MTJ device 109. The polarized magnetic layer 104a of the access selector device 101 can be located on the MTJ device 109 side of the non-metallic structure 103 or on the opposite side. The free layer 107a of the MTJ device 109 can be closer to or further away from the access selector device 101 than the fixed layer 107c. Despite these alternatives, the effectiveness of the polarized magnetic layer 104a in improving write speed can be increased by placing it closer to the free layer 107a.

[0037] Figure 3C A cross-sectional view 340 shows another integrated chip with laterally arranged memory cells 305e and 305f, each memory cell including an MTJ device 109 and an access selector device 101. In each of the memory cells 305e and 305f, the access selector device 101 can be laterally offset from the MTJ device 109. Additionally, given that the MTJ device 109 is disposed between interconnect layers 306a and 306b, in this embodiment, the access selector device 101 is disposed between interconnect layers 306b and 306c. The access selector device 101 is a bipolar selector that includes a polarized magnetic layer 104a that generates a magnetic field 114c capable of effectively tilting the polarization of the free layer 107a away from the direction of the current (either a first direction 110 or a second direction 112).

[0038] Figure 3DA cross-sectional view 360 of another integrated chip with laterally arranged memory cells 305g and 305h is shown, each memory cell including an MTJ device 109 and an access selector device 361. The access selector device 361 includes a first unipolar selector 377 and a second unipolar selector 365. The first unipolar selector 377 and the second unipolar selector 365 are respectively configured to allow current to flow in a single direction during normal operation (e.g., except in the event of a breakdown). For example, the first unipolar selector 377 is configured to allow current to flow through the MTJ device 109 along a first direction 110 (e.g., from the first word line WL1 to the bit line BL1), while the second unipolar selector 365 is configured to allow current to flow through the MTJ device 109 along a second direction 112 opposite to the first direction 110 (e.g., from the bit line BL1 to the second word line WL2). When current flows through the MTJ device 109 along the first direction 110, a first data state (e.g., logic "0") can be written to the MTJ device 109. When current flows through MTJ device 109 in the second direction 112, a second data state (e.g., logic "1") can be written into MTJ device 109.

[0039] In some embodiments, the first single-pole selector 377 and the second single-pole selector 365 are diodes (e.g., PN diodes, PiN diodes, Schottky diodes, oxide-semiconductor-oxide diodes, etc.). In such embodiments, an applied voltage difference greater than the diode's threshold is used to access the MTJ device 109 for read and write operations. In other embodiments, one or both of the first single-pole selector 377 and the second single-pole selector 365 are based on filament selectors, rectifiers, varistor-type selectors, electronic threshold switches (OTS), chalcogenide-based selectors, Mott effect-based selectors, mixed-ion electronic conductivity (MIEC)-based selectors, field-assisted superlinear threshold (FAST) selectors, etc. In some embodiments, the first single-pole selector 377 and the second single-pole selector 365 are single-pole selectors of the same type. In other embodiments, the first single-pole selector 377 and the second single-pole selector 365 are single-pole selectors of different types. For example, in some embodiments, the first unipolar selector 377 may be a diode, while the second unipolar selector may be a filament-based selector.

[0040] The electrode for the first singlet selector 377 includes an electrode having a magnetic layer 375 that generates a magnetic field 114d capable of effectively tilting the polarization of the free layer 107a away from the direction of the current (first direction 110 or second direction 112), thereby reducing the latency of writing to the MTJ device 109. In other embodiments, the magnetic layer 375 is disposed at other locations within the access selector device 361. For example, the magnetic layer 375 may be all or part of the bottom electrode 379 of the first singlet selector 377, the crossbar 371, the via 373 connecting the MTJ device 109 to the crossbar 371, the via 369 connecting the second singlet selector 365 to the crossbar 371, the bottom electrode 367 for the second singlet selector 365, or the top electrode 363 for the second singlet selector 365.

[0041] Figure 4 Block diagrams of some embodiments of a memory circuit 400 are shown, the memory circuit 400 including a memory array having a plurality of memory cells, each memory cell including an access selector device having a plurality of bipolar selectors.

[0042] The memory circuit 400 includes a plurality of memory cells 404 a,1 -404 c,4 Memory array 402. Multiple memory cells 404 a,1 -404 c,4 The memory cells are arranged in rows and / or columns within the memory array 402. For example, the first row of memory cells includes memory cells 404. a,1 -404 c,1 The first column of memory cells includes memory cell 404. a,1 -404 a,4 Multiple memory cells 404 a,1 -404 c,4 Each includes an MTJ device 109 connected to an access selector device 101, which has a polarized magnetic layer 104a that reduces the write time for each MTJ device 109. The access selector device 101 is configured to allow current to flow through the selected memory cell 404. a,1 -404 c,4 Simultaneously suppress flow through unselected memory cells 404 a,1 -404 c,4 The leakage current is selectively supplied to multiple memory cells 404. a,1 -404 c,4 Access to one or more MTJ devices 109.

[0043] The memory array 402 is connected to a control circuit via multiple bit lines BL1-BL4 and multiple word lines WL1-WL3. In some embodiments, the control circuit includes a bit line decoder 406 connected to the multiple bit lines BL1-BL4 and a word line decoder 408 connected to the multiple word lines WL1-WL3. In some embodiments, the control circuit may further include a sense amplifier 410 connected to the memory array 402 via multiple word lines WL1-WL3. The sense amplifier 410 is configured to receive signals from multiple memory cells 404. a,1 -404 c,4 Read data.

[0044] In order to access memory cell 404 a,1 -404 c,4 The MTJ device 109, bit line decoder 406 is configured to be based on the first address S received from the control circuit 412. ADDR1 The first voltage is selectively applied to one or more bit lines BL1-BL4, while the word line decoder 408 is configured to apply a second address S received from the control circuit 412. ADDR2 A second voltage is selectively applied to one or more word lines WL1-WL3. The applied voltage will cause current to flow through the selected memory cell 404. a,1 -404 c,4 Access selector device 101 and MTJ device 109.

[0045] Figure 5 A cross-sectional view of an integrated chip 500 having a memory array comprising multiple memory cells is shown, according to some other aspects of this teaching. Each memory cell includes an MTJ device and an access selector device having a polarized magnetic layer that reduces the write time for the MTJ. The polarized magnetic layer of any memory cell can also help reduce the write time for the MTJ of one or more adjacent cells. This can be combined with information regarding... Figure 3A Cross-sectional view 300 Figure 3B Cross-sectional view 320 Figure 3C Cross-sectional view 340, and Figure 3D The concept described in any of the cross-sectional diagrams 360 modifies the integrated chip 500.

[0046] The integrated chip 500 includes a substrate 202, which includes an embedded memory region 508 and a logic region 510. A dielectric structure 204 is disposed above the substrate 202. The dielectric structure 204 includes a plurality of stacked interlayer dielectric (ILD) layers 512a-512f vertically spaced apart by etch stop layers 513a-513e. In some embodiments, the plurality of stacked ILD layers 512a-512f include one or more of silicon dioxide, SiCOH, fluorosilicate glass, phosphate glass (e.g., borosilicate glass), etc. In some embodiments, the etch stop layers 513a-513e include nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), etc.

[0047] Multiple memory cells 305i are disposed within an embedded memory region 508, each memory cell 305i including an access selector device 505 connected to an MTJ device 109. The access selector device 505 includes a first metal structure 509 and a top electrode 501 spaced apart by one or more non-metallic layers 506. The first metal structure 509 includes a polarized magnetic layer 504 having in-plane polarization. In some embodiments, the one or more non-metallic layers 506 include a first dielectric layer 503 adjacent to the polarized magnetic layer 504 and being an oxide product of the polarized magnetic layer 504. In some embodiments, the one or more non-metallic layers 506 further include a second dielectric layer 502 having a different bandgap energy than the first dielectric layer 503. In some embodiments, the access selector device 505 is a bipolar selector.

[0048] MTJ device 109 has MTJ107 disposed between a first electrode 511 and a second electrode 507. In some embodiments, sidewall spacers 530 are disposed along opposite sides of MTJ107. In some embodiments, sidewall spacers 530 extend to a side of the sidewall of access selector device 505. Sidewall spacers 530 may have an outermost curved sidewall facing away from MTJ107. In various embodiments, sidewall spacers 530 include silicon nitride, silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), etc. In some embodiments, an encapsulation layer 534 is disposed over sidewall spacers 530. In some embodiments, encapsulation layer 534 includes oxides (e.g., silicon-rich oxides), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), etc.

[0049] In some embodiments, a top electrode via 536 extends through the encapsulation layer 534 to contact the top electrode 501 of the memory cell 305i. The top electrode via 536 connects the second electrode 105 to the interconnect 514c. In some embodiments, the top electrode via 536 comprises aluminum, copper, tungsten, or the like. In some embodiments, the second interconnect 514b is disposed below the memory cell 305i and spaced apart from the memory cell 305i by a lower insulating structure 520 and a fourth etch stop layer 513d. A bottom electrode via 524 may extend through the lower insulating structure 520 to connect the first electrode 511 to the second interconnect 514b.

[0050] The lower insulating structure 520 may include one or more layers of various insulators. In some embodiments, the lower insulating structure 520 includes a silicon-rich oxide layer, etc. In some embodiments, the lower insulating structure 520 has a greater (i.e., thicker) thickness in the logic region 510 than in the embedded memory region 508. In some embodiments, the lower insulating structure 520 includes layers of silicon carbide, silicon nitride, etc. In some embodiments, the lower insulating structure 520 includes an encapsulation layer 534. In some embodiments, the lower insulating structure 520 includes a layer of tetraethyl orthosilicate (TEOS), etc.

[0051] In some embodiments, the second interconnect 514b is connected to the word line WL. Alternatively, the second interconnect 514b may be a word line. In some embodiments, the second interconnect 514c is connected to the bit line BL1 or BL2. In some embodiments, the second interconnect 514c itself provides a bit line. The memory cell 305i is formed within the fifth ILD layer 512e. Alternatively, the memory cell 305i may be formed within another ILD layer above or below the fifth ILD layer 512e.

[0052] Within the logic region 510, one or more additional interconnect layers are disposed within the dielectric structure 204. These additional interconnect layers include conductive contacts 540, interconnect lines 542, and interconnect vias 544. The additional interconnect layers are connected to a logic device 538 disposed within the substrate 202. In some embodiments, the logic device 538 may include a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), etc.).

[0053] Figures 6-14 Cross-sectional views 600-1400 are shown, illustrating a method for forming an integrated chip with an access selector device according to some embodiments of the invention. The access selector device includes a bipolar selector comprising a polarized magnetic layer for reducing the associated write time for MTJ devices. While described relative to the method... Figures 6 to 14 However, it should be understood that Figures 6 to 14 The structure disclosed herein is not limited to this method, but can be used independently as a structure independent of this method. Furthermore, although Figures 6 to 14 Specific structures and compositions for MTJ devices and access selector devices are shown, but the method can be readily extended to other structures and compositions within the scope of this disclosure.

[0054] like Figure 6 As shown in cross-sectional view 600, a lower insulating structure 605 is formed above a metal interconnect structure 601, which itself is formed above a substrate 220. In various embodiments, the substrate 202 can be any type of semiconductor host (e.g., silicon, SiGe, SOI), such as a semiconductor wafer and / or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. The metal interconnect structure 601 may include one or more ILD layers, which are spaced apart by etch stop layers and surrounding conductors, vias, etc. The ILD layers may include one or more dielectric materials, such as silicon dioxide (SiO2), SiCOH, fluorosilicate glass, phosphate glass (e.g., borosilicate glass), etc. The conductive material forming conductors, vias, etc. within the metal interconnect structure 601 may include metals (e.g., aluminum, copper, tungsten) formed by deposition processes (e.g., CVD, PVD, PE-CVD, ALD).

[0055] In some embodiments, a lower insulating structure 605 is formed and selectively patterned to define a bottom electrode via opening 602 above a similar conductive component within the interconnect 514b or metal interconnect structure 601. In some embodiments, the lower insulating structure 605 includes a fourth etch stop layer 513d or some other etch stop layer, and a first dielectric layer 522 disposed above the etch stop layer. The first dielectric layer 522 may include one or more of silicon carbide, silicon-rich oxide, TEOS (tetraethyl orthosilicate), etc.

[0056] like Figure 7As shown in cross-sectional view 700, an MTJ device stack 717 may be formed above a lower insulating structure 605. The MTJ device stack 717 may include a bottom electrode structure 715, an MTJ stack 709, and a top electrode 701. In some embodiments, the bottom electrode structure 715 includes a bottom electrode layer 711 covering a bottom electrode via layer 713. The bottom electrode via layer 713 may cover the lower insulating structure 605 and fill the opening 602. The MTJ stack 709 may include a fixing layer 707, a dielectric barrier tunnel layer 705, and a free layer 703. In some embodiments, the fixing layer 707 is disposed between the free layer 703 and the bottom electrode structure 715. In other embodiments (not shown), the free layer 703 is disposed between the fixing layer 707 and the bottom electrode structure 715. The top electrode layer 701 is formed above the MTJ stack 709.

[0057] like Figure 8 As shown in cross-sectional view 800, a ferromagnetic layer 801 may be deposited over the MTJ device stack 717. In some embodiments, the thickness of the ferromagnetic layer 801 is between about 5 nm and about 200 nm. In some embodiments, the thickness of the ferromagnetic layer 801 is between about 15 nm and about 50 nm. In some embodiments, the ferromagnetic layer 801 is formed by polarization using a crystal growth process or the like. In other embodiments, the ferromagnetic layer 801 is polarized after formation. In some embodiments, the ferromagnetic layer 801 has high coercivity to facilitate making it a static layer that maintains its polarization throughout the entire lifetime of any resulting device.

[0058] like Figure 9 As shown in cross-sectional view 900, the ferromagnetic layer 801 may be partially oxidized to form a first dielectric layer 901. In some embodiments, the first dielectric layer 901 has a thickness between about 2 nm and about 40 nm. In some embodiments, the first dielectric layer 901 has a thickness between about 5 nm and about 20 nm. In some embodiments, the oxidation process reduces the ferromagnetic layer 801 to a thickness between about 5 nm and about 60 nm. In some embodiments, the oxidation process reduces the ferromagnetic layer 801 to a thickness between about 10 nm and about 30 nm. Any suitable oxidation process can be used. In some embodiments, oxidation is performed by exposing the ferromagnetic layer 801 to oxygen. In some embodiments, oxidation is performed by exposing the ferromagnetic layer 801 to a plasma comprising oxygen-containing ions or molecules. In some embodiments, oxidation is performed by allowing the ferromagnetic layer 801 to scavenge oxygen from an oxide layer disposed above the ferromagnetic layer 801.

[0059] like Figure 10 As shown in the cross-sectional diagram 1000, it can be seen that... Figure 9An additional layer is deposited over the structure shown in cross-sectional view 900 to form a bipolar selector stack 1007. The bipolar selector stack 1007 may include a ferromagnetic layer 801, a non-metallic layer 1005, and a top electrode layer 1003. The non-metallic layer 1005 may include a first dielectric layer 901 and a second dielectric layer 1001, wherein the second dielectric layer has a bandgap energy different from that of the first dielectric layer 901. In some embodiments, the second dielectric layer 1001 has a thickness between about 2 nm and about 40 nm. In some embodiments, the second dielectric layer 1001 has a thickness between about 5 nm and about 20 nm. In some embodiments, the top electrode layer 1003 has a thickness between about 5 nm and about 60 nm. In some embodiments, the top electrode layer 1003 has a thickness between about 10 nm and about 30 nm.

[0060] like Figure 11 As shown in cross-sectional view 1100, a mask layer 1101 can be formed, and a bipolar selector stack 1007 can be selectively etched according to the mask layer 1101 to define memory cells 305i. The mask layer 1101 can be silicon nitride, silicon carbide, etc. Etching can define access selector devices 505 from the bipolar selector stack 1007. Patterning to define access selector devices 505 includes defining a top electrode 501 from a top electrode layer 1003, a second dielectric layer 502 from a second dielectric layer 1001, and a first dielectric layer 503 from a first dielectric layer 901. Access selector devices 505 also include a first metal structure 509, which includes a polarized magnetic layer 504 defined from a ferromagnetic layer 801. The first metal structure 509 can also be considered to include all or part of a second electrode 507 defined from the top electrode layer 701. Etching with mask layer 1101 can further define portions of the MTJ device 109, including defining the second electrode 507 from the top electrode layer 701, and defining all or part of the MTJ 107 from the MTJ stack 709. Figure 11 The portion of MTJ107 formed by etching the MTJ stack 709 may include a free layer 107a, a dielectric tunnel barrier 107b, and / or a fixed layer 107c.

[0061] like Figure 12 As shown in the cross-sectional view 1200, the sidewall spacer 530 is formed adjacent to the memory cell 305i, as... Figure 11 The cross-sectional view 1100 is shown. The sidewall spacer 530 is located on the side of the access selector device 505 and extends to the side portion of the MTJ107, which includes at least the dielectric tunnel barrier 107b. Also as... Figure 12As shown in cross-sectional view 1200, the sidewall spacer 530 provides a mask function for selective etching, which completes the definition of MTJ device 109 from MTJ stack 709. Selective etching defines a first electrode 511 from bottom electrode layer 711 and a bottom electrode via 524 from bottom electrode via layer 713. As a result, the edge of the first electrode 511 can be aligned with the sidewall spacer 530. Etching removes the mask layer 1101.

[0062] like Figure 13 As shown in cross-sectional view 1300, a package layer 534 is formed above the memory cell 305i and the sidewall spacer 530. The package layer 534 is located on the sides of both the MTJ device 109 and the access selector device 505. Figure 14 As shown in the cross-sectional view 1400, a fourth ILD layer 512d can be formed above the package layer 534. The fourth ILD layer 512d can be patterned to define openings, which are then filled with metal to define electrode vias 536 and interconnect wires 514c. The resulting structure can be formed... Figure 5 This is a portion of the integrated chip 500 shown.

[0063] In the example of integrated chip 500, memory cell 305i is shown as having a single set of sidewall spacers 530 and a single encapsulation layer 534. In various embodiments, additional sidewall spacers, additional encapsulation layers, and one or more overlay layers may be used to: prevent cross-contamination between layers of bipolar selector stack 1007 and / or MTJ device stack 717 during patterning, facilitate patterning of bipolar selector stack 1007 and / or MTJ device stack 717, and ensure that via 536 falls on top electrode 501 without causing a short circuit.

[0064] Figures 15-16 Cross-sectional views 1500-1600 illustrate some embodiments of another method for forming an integrated chip with an access selector device, the access selector device including a bipolar selector comprising a polarized magnetic layer for reducing write time for the associated MTJ device. Figure 15 As shown in cross-sectional view 1500, the formation of the bipolar selector can begin with the formation of a third dielectric layer 1501 and a ferromagnetic layer 1503 over the MTJ device stack 717. The third dielectric layer 1501 comprises an oxide layer. Figure 16As shown in the cross-sectional view 1600, the fourth dielectric layer 1601 can then be formed by partially oxidizing the ferromagnetic layer 1503. Oxidation can occur by removing oxygen from the third dielectric layer 1501. In the resulting bipolar selector stack 1605, the top electrode layer 701 of the MTJ stack 709 can be used as the bottom electrode, the ferromagnetic layer 1503 can be used as the top electrode, and the third dielectric layer 1501 and the fourth dielectric layer 1601 can be non-metallic layers 1005 that space the top electrode from the bottom electrode.

[0065] Figure 17 Flowcharts are provided for some embodiments of a method 1700 for forming an integrated chip with memory cells, the memory cells including MTJ devices and access selector means, wherein the access selector means includes a polarized magnetic layer for reducing the write time of the associated memory cells. Although method 1700 is illustrated and described below as a series of actions or events, it will be understood that the illustrated order of such actions or events should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events in addition to those illustrated and / or described herein. Furthermore, implementing one or more aspects or embodiments described herein may not require all the actions shown. Additionally, one or more actions described herein may be performed in one or more independent actions and / or stages.

[0066] Action 1701 forms an MTJ device stack on the substrate. Figure 7 Cross-sectional view 700 shows an embodiment corresponding to action 1701, wherein an MTJ device stack 717 is formed over substrate 220.

[0067] Action 1703 forms an electrode layer for a bipolar selector stack including a magnetic layer. Figure 8 Cross-sectional view 800 shows an embodiment corresponding to action 1703, wherein the magnetic layer is a ferromagnetic layer 801. Figure 15 Cross-sectional view 1500 shows another example where the magnetic layer is a ferromagnetic layer 1503. The layers of the bipolar selector stack can be formed directly above the layers of the MTJ device stack 717, as shown below. Figures 8-10 and Figures 15-16 The cross-sectional views are shown at 800-1000 and 1500-1600. In some alternative embodiments, the layers of the MTJ device stack 717 are formed above the layers of the bipolar selector. In other embodiments, the MTJ device stack and the access selector device may have different spatial relationships.

[0068] Action 1705 is part of an oxidized magnetic layer to form a dielectric layer for bipolar selector stacks. Figure 9Cross-sectional view 900 shows an example where a first dielectric layer 901 has been formed by partially oxidizing a ferromagnetic layer 801. Figure 16 Cross-sectional view 1600 shows another example, in which a fourth dielectric layer 1601 has been formed by partially oxidizing the ferromagnetic layer 1503.

[0069] Action 1707 forms any remaining layers of the bipolar selector stack. Figure 10 Cross-sectional view 1000 shows an example in which the bipolar selector stack 1007 is completed by forming a second dielectric layer 1001 and a top electrode layer 1003 over a first dielectric layer 901. Figure 16 Cross-sectional view 1600 shows another example in which a portion of the ferromagnetic layer 1503 is oxidized to form a fourth dielectric layer 1601 to complete the bipolar selector stack 1007.

[0070] Action 1709 performs patterning to form individual devices from bipolar selector stacks and MTJ device stacks. Figure 11 Cross-sectional view 1100 shows an example where patterning has defined the access selector device 505 and partially defined the MTJ device 109 for each memory cell 305i.

[0071] Action 1711 forms sidewall spacers in the vicinity of the various devices patterned by action 1709. Figure 12 Cross-sectional view 1200 shows an example in which the sidewall spacer 530 has been formed adjacent to the access selector device 505 and the portion of the MTJ device 109 including the dielectric tunnel barrier 107b for each memory cell 305i.

[0072] Action 1713 uses the sidewall spacers formed by action 1711 to pattern the bottom electrode layer for the memory cell. Figure 12 Cross-sectional view 1200 shows an example in which sidewall spacers 530 have been used to pattern the first electrode 511 and bottom electrode via 524 for each memory cell 305i.

[0073] Action 1715 forms a package layer that covers the bipolar selector of each memory cell and the sides of the MTJ device. Figure 13 Cross-sectional view 1300 shows an example where the encapsulation layer 534 covers the sides of the access selector device 505 and the MTJ device 109 of each memory cell 305i.

[0074] Action 1717 forms a via that connects to the top electrode of the memory cell. Figure 14 Cross-sectional view 1400 shows an example where vias 536 have been made to contact the top electrode 501 in each memory cell 305i.

[0075] Some aspects of this teaching relate to an integrated chip including a magnetic tunnel junction (MTJ) device and an access selector device. The device has a first electrode and a second electrode. The access selector device includes a first metallic structure and a second metallic structure spaced apart by one or more non-metallic layers. One of the first metallic structure and the second metallic structure is connected to the second electrode. According to this teaching, the first metallic structure of the access selector device includes a polarized ferromagnetic layer.

[0076] In some of these teachings, the first metallic structure is an electrode for an access selector device. In some of these teachings, the access selector device is a bipolar selector. In some of these teachings, one or more non-metallic layers comprise two insulators with different bandgap energies. In some of these teachings, one of the two insulators with different bandgap energies is an oxide of a metal of a polarized ferromagnetic layer. In some of these teachings, the MTJ and the access selector device are formed by a stack of material layers. In some of these teachings, one or more non-metallic layers is an oxide of a polarized ferromagnetic layer. In some of these teachings, the polarized ferromagnetic layer has in-plane polarization. In some of these teachings, the MTJ device may include a fixed layer with perpendicular magnetic polarization. In some of these teachings, the first metallic structure comprises an electrode layer different from the polarized ferromagnetic layer. The MTJ device includes a free layer and a fixed layer. The polarized ferromagnetic layer generates a magnetic field that passes through the free layer. The magnetic field tilts the polarization direction of the free layer of the MTJ device, thereby reducing the switching time for the MTJ device.

[0077] Some aspects of this teaching relate to an integrated chip having a magnetic tunnel junction (MTJ) device disposed within a dielectric structure above a substrate. The MTJ device includes an MTJ disposed between a first MTJ electrode and a second electrode. The integrated chip also has a bipolar selector (BS) including an intermediate structure disposed between a first BS electrode and a second BS electrode. The second BS electrode is connected to or integrated with the first MTJ electrode. The intermediate structure is one or more layers of an insulator and / or semiconductor. One of the first and second BS electrodes includes a polarizing magnetic layer.

[0078] In some of these teachings, the polarization magnetic layer has in-plane polarization. In some of these teachings, the first BS electrode provides the polarization magnetic layer. In some of these teachings, the MTJ device includes a free layer and a fixed layer, and the polarization magnetic layer has a magnetic field that effectively reduces the number of precession cycles experienced by the free layer during switching of the MTJ device.

[0079] Some aspects of this teaching relate to a method for forming an integrated chip. The method includes forming a magnetic tunnel junction (MTJ) device over a semiconductor substrate and forming a bipolar selector for the MTJ device. The MTJ device has an MTJ disposed between a first electrode and a second electrode. The bipolar selector includes a ferromagnetic material layer with in-plane polarization located over the semiconductor substrate and connected to the second electrode.

[0080] In some of these teachings, the bipolar selector is formed directly above or below the MTJ device. In some of these teachings, the ferromagnetic material layer is configured to reduce the write voltage of the MTJ device. In some of these teachings, the bipolar selector (BS) includes one or more non-metallic layers disposed between a first BS electrode and a second BS electrode. In some of these teachings, the bipolar selector is formed in part by oxidizing a portion of the ferromagnetic material layer to form one or more non-metallic layers.

[0081] Some aspects of this teaching relate to a method for switching the polarization of a free layer in a magnetic tunnel junction (MTJ) device. The method includes forming a magnetic tunnel junction (MTJ) device over a semiconductor substrate, wherein the MTJ device has an MTJ disposed between a first electrode and a second electrode. The method also includes forming a bipolar selector with an in-plane polarized ferromagnetic material layer over the semiconductor substrate, configured such that the ferromagnetic material tilts the polarization direction in the free layer away from the direction of current, thereby reducing the write time for the MTJ device.

[0082] Embodiments of the present invention provide an integrated chip, comprising: a magnetic tunnel junction (MTJ) device having a first electrode and a second electrode; and an access selector device for the MTJ device, comprising a first metal structure and a second metal structure spaced apart by one or more non-metallic layers; wherein one of the first metal structure and the second metal structure is connected to the second electrode, and the first metal structure includes a polarized ferromagnetic layer.

[0083] In the aforementioned integrated chip, the first metal structure is an electrode for accessing the selector device.

[0084] In the aforementioned integrated chip, the access selector device is a bipolar selector.

[0085] In the aforementioned integrated chip, one or more non-metallic layers comprise two insulators with different bandgap energies.

[0086] In the aforementioned integrated chip, one of the two insulators with different bandgap energies is an oxide of a metal with a polarized ferromagnetic layer.

[0087] In the aforementioned integrated chip, the magnetic tunnel junction device and the access selector device are formed by stacking material layers.

[0088] In the aforementioned integrated chip, one of the one or more non-metallic layers is an oxide of a polarized ferromagnetic layer.

[0089] In the aforementioned integrated chip, the polarized ferromagnetic layer exhibits in-plane polarization.

[0090] In the aforementioned integrated chip, the magnetic tunnel junction device includes a fixed layer with vertical magnetic polarization.

[0091] In the aforementioned integrated chip, the first metal structure includes an electrode layer that is different from the polarized ferromagnetic layer.

[0092] In the aforementioned integrated chip, the polarized ferromagnetic layer tilts the polarization direction of the free layer of the magnetic tunnel junction device.

[0093] In the aforementioned integrated chip, the magnetic tunnel junction device includes a free layer and a fixed layer; and the polarized ferromagnetic layer has a magnetic field that extends through the free layer to reduce the switching time for the magnetic tunnel junction device.

[0094] Embodiments of the present invention provide an integrated chip, comprising: a magnetic tunnel junction (MTJ) device disposed within a dielectric structure above a substrate, the MTJ device including a magnetic tunnel junction disposed between a first MTJ electrode and a second MTJ electrode; and a bipolar selector (BS) including an intermediate structure disposed between a first BS electrode and a second BS electrode; wherein the second BS electrode is connected to or integral with the first MTJ electrode; the intermediate structure is one or more layers of an insulator and / or a semiconductor; and one of the first BS electrode and the second BS electrode includes a polarizing magnetic layer.

[0095] In the aforementioned integrated chip, the polarized magnetic layer exhibits in-plane polarization.

[0096] In the aforementioned integrated chip, the first bipolar selector electrode includes a polarized magnetic layer.

[0097] In the aforementioned integrated chip, the magnetic tunnel junction device includes a free layer and a fixed layer; and the polarized magnetic layer has a magnetic field that effectively reduces the number of precession cycles experienced by the free layer during the switching of the magnetic tunnel junction device.

[0098] Embodiments of the present invention provide a method for forming an integrated chip, comprising: forming a magnetic tunnel junction (MTJ) device over a semiconductor substrate, the MTJ device having a magnetic tunnel junction disposed between a first electrode and a second electrode; and forming a bipolar selector for the MTJ device; wherein the bipolar selector includes a ferromagnetic material layer having a fixed polarization; and the bipolar selector is connected to the second electrode.

[0099] In the above method, the bipolar selector is formed directly above or below the magnetic tunnel junction device.

[0100] In the above method, the magnetic tunnel junction device includes a fixed layer having a polarization substantially orthogonal to the polarization of the ferromagnetic material layer.

[0101] In the above method, the bipolar selector (BS) includes one or more non-metallic layers disposed between the first bipolar selector electrode and the second bipolar selector electrode; and forming the bipolar selector includes oxidizing a portion of the ferromagnetic material layer to form one or more non-metallic layers.

[0102] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: A magnetic tunnel junction device having a first electrode and a second electrode; as well as Access selector device for the magnetic tunnel junction device, comprising a first metal structure and a second metal structure spaced apart by one or more non-metallic layers, wherein the one or more non-metallic layers comprise two insulators with different bandgap energies; Wherein, one of the first metal structure and the second metal structure is connected to the second electrode, and The first metallic structure includes a polarized ferromagnetic layer. Wherein, one of the two insulators with different bandgap energies is an oxide of the metal of the polarized ferromagnetic layer.

2. The integrated chip according to claim 1, wherein, The first metal structure is an electrode for the access selector device.

3. The integrated chip according to claim 2, wherein, The access selector device is a bipolar selector.

4. The integrated chip according to claim 3, wherein, The access selector device is formed above or below the magnetic tunnel junction device.

5. The integrated chip according to claim 1, wherein, One of the two insulators having different bandgap energies is an oxide of cobalt, an oxide of iron, or an oxide of nickel.

6. The integrated chip according to claim 3, wherein, The magnetic tunnel junction device and the access selector device are formed by stacking material layers.

7. The integrated chip according to claim 6, wherein, One of the one or more non-metallic layers is an oxide of the polarized ferromagnetic layer.

8. The integrated chip according to claim 6, wherein, The polarized ferromagnetic layer has in-plane polarization.

9. The integrated chip according to claim 8, wherein, The magnetic tunnel junction device includes a fixed layer with vertical magnetic polarization.

10. The integrated chip according to claim 1, wherein, The first metal structure includes an electrode layer that is different from the polarized ferromagnetic layer.

11. The integrated chip according to claim 1, wherein, The polarized ferromagnetic layer tilts the polarization direction of the free layer of the magnetic tunnel junction device.

12. The integrated chip according to claim 1, wherein: The magnetic tunnel junction device includes a free layer and a fixed layer; and The polarized ferromagnetic layer has a magnetic field that extends through the free layer to reduce the switching time for the magnetic tunnel junction device.

13. An integrated chip, comprising: A magnetic tunnel junction device is disposed within a dielectric structure above a substrate, the magnetic tunnel junction device comprising a magnetic tunnel junction disposed between a first magnetic tunnel junction electrode and a second magnetic tunnel junction electrode; as well as A bipolar selector, including an intermediate structure disposed between a first bipolar selector electrode and a second bipolar selector electrode; The magnetic tunnel junction device includes a fixed layer and a free layer; The second bipolar selector electrode is connected to the first magnetic tunnel junction electrode or is integrated with the first magnetic tunnel junction electrode; The intermediate structure is one or more layers of an insulator and / or semiconductor; and One of the first bipolar selector electrode and the second bipolar selector electrode includes a polarized magnetic layer, wherein the polarized magnetic layer has a magnetic field extending through the free layer.

14. The integrated chip according to claim 13, wherein, The polarized magnetic layer has in-plane polarization.

15. The integrated chip according to claim 13, wherein, The first bipolar selector electrode includes the polarized magnetic layer.

16. The integrated chip according to claim 13, wherein, The polarized magnetic layer has a magnetic field that effectively reduces the number of precession cycles experienced by the free layer during switching of the magnetic tunnel junction device.

17. A method for forming an integrated chip, comprising: A magnetic tunnel junction device is formed over a semiconductor substrate, the magnetic tunnel junction device having a magnetic tunnel junction disposed between a first electrode and a second electrode, wherein the magnetic tunnel junction device includes a free layer and a fixed layer; and Forming a bipolar selector for the magnetic tunnel junction device; The bipolar selector includes a ferromagnetic material layer with fixed polarization, wherein the ferromagnetic material layer has a magnetic field extending through the free layer; and The bipolar selector is connected to the second electrode.

18. The method according to claim 17, wherein, The bipolar selector is formed directly above or below the magnetic tunnel junction device.

19. The method according to claim 17, wherein, The fixing layer has a polarization orthogonal to that of the ferromagnetic material layer.

20. The method of claim 17, wherein: The bipolar selector includes one or more non-metallic layers disposed between the first bipolar selector electrode and the second bipolar selector electrode; and Forming the bipolar selector includes oxidizing a portion of the ferromagnetic material layer to form one of the one or more non-metallic layers.

Images