Parallel soft-elimination decoding method and related device

Abstract

The embodiment of the present application discloses a parallel soft elimination decoding method and a related device, the method comprising: obtaining a sequence to be decoded, the bit length of the sequence to be decoded is N; determining the level range s to 0 of the log likelihood ratio LLR update mechanism of the sequence to be decoded according to N, wherein the level m to the level 0 constitutes a sub-block for parallel decoding processing of non-parity check PC bits, N=2 s+1 ; Perform LLR iteration and update of the sequence to be decoded layer by layer according to the level range s to 0 until the preset maximum number of iterations is reached, and obtain the target log-likelihood ratio LLR of the information bit direction of the sequence to be decoded, where the information bit direction is the LLR transmission direction from the high level to the low level; perform decoding according to the target LLR in the information bit direction to obtain the decoding result. The embodiment of the present application can meet the soft bit output and ensure high decoding performance requirements.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a parallel soft elimination decoding method and related devices. Background Art

[0002] In recent years, as polar codes have been included in the 5G standard for wireless communications, research on decoding of polar codes has become a hot topic in the field of communications. The current mainstream polar code decoding methods can be divided into two categories according to their decoding output, namely polar code hard bit decoding and polar code soft bit decoding. Polar code hard bit decoding refers to the decoder directly determining the transmitted information bit based on the received signal. Polar code soft bit decoding refers to the decoder calculating the soft bit value of the transmitted information (such as the log-likelihood ratio Log-Likelihood-Ratio) based on the received signal. Afterwards, the obtained soft bit value can also be finally hard-determined to achieve hard bit output. Therefore, soft bit decoding is more flexible and more adaptable than hard bit decoding. At present, the main hard bit decoding methods of Polar codes include Successive Cancellation (SC) decoding, Successive Cancellation List (SCL) decoding, and CRC-Aided Successive Cancellation List (CA-SCL) decoding with cyclic parity check. The soft bit decoding methods mainly include Belief Propagation decoding and Soft Cancellation (SCAN) decoding. In terms of decoding performance, SC decoding is the worst, and the performance of BP decoding and SCAN decoding is close, which is slightly better than SC decoding. SCL decoding is greatly improved compared with the former, and CA-SCL after CRC check can make the performance of Polar codes better than LDPC codes and Turbo codes. Therefore, SCL decoding and CA-SCL decoding are mainly used in actual systems.

[0003] However, since both SCL decoding and CA-SCL decoding are Polar hard bit decoding, they cannot directly output soft bit values, which makes these two solutions have certain limitations in application scenarios. In some specific scenarios, Polar soft bit decoding is required to match. In this case, only BP decoding or SCAN decoding with average performance can be used to achieve the purpose of soft bit output. Therefore, how to design a decoding method that can meet the soft bit output and ensure high decoding performance is a technical problem that needs to be solved at present. Summary of the invention

[0004] The embodiments of the present application provide a parallel soft elimination decoding method and related devices, which can meet the requirements of soft bit output and ensure high decoding performance.

[0005] In a first aspect, an embodiment of the present application provides a parallel soft elimination decoding method, comprising:

[0006] Obtain a sequence to be decoded, where the bit length of the sequence to be decoded is N, where N is a positive integer;

[0007] The level range s to 0 of the log-likelihood ratio (LLR) update mechanism of the sequence to be decoded is determined according to N, wherein level m to level 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, N=2 s+1 , m is an integer greater than or equal to 2, and s is an integer greater than m;

[0008] Iteratively updating the LLR of the sequence to be decoded layer by layer according to the layer range s to 0 until a preset maximum number of iterations is reached, and obtaining a target log-likelihood ratio LLR in the information bit direction of the sequence to be decoded, where the information bit direction is the LLR transmission direction from a high level to a low level;

[0009] Decoding is performed according to the target LLR in the information bit direction to obtain a decoding result.

[0010] In a second aspect, the present application provides a communication device, which may include multiple functional modules or units for correspondingly executing the method provided in the first aspect, or any method provided in any possible implementation manner of the first aspect.

[0011] In a third aspect, the present application provides a communication device for executing the method described in the first aspect. The communication device may include: a memory, a processor coupled to the memory, and a transceiver, wherein: the transceiver is used to communicate with other communication devices (such as terminals or network devices). The memory is used to store the implementation code of the method described in the first aspect, and the processor is used to execute the program code stored in the memory, that is, to execute the method provided in the first aspect, or any method provided in any possible implementation of the first aspect.

[0012] In a fourth aspect, a computer-readable storage medium is provided, wherein instructions are stored on the computer, and when the instructions are executed on a computer, the computer executes the method described in the first aspect.

[0013] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the method described in the first aspect.

[0014] In a sixth aspect, the present application provides a communication chip, which may include: a processor, and one or more interfaces coupled to the processor. The processor may be used to call the method provided in the first aspect, or an implementation program of the method provided in any one of the possible implementations of the first aspect from a memory, and execute the instructions contained in the program. The interface may be used to output the processing result of the processor.

[0015] By implementing the embodiment of the present application, the communication device first obtains a sequence to be decoded, where the bit length of the sequence to be decoded is N, where N is a positive integer; secondly, the level range s to 0 of the log-likelihood ratio LLR update mechanism of the sequence to be decoded is determined according to N, where level m to level 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, and N=2 s+1 , m is an integer greater than or equal to 2, s is an integer greater than m; again, the LLR of the sequence to be decoded is iteratively updated layer by layer according to the level range s to 0 until the preset maximum number of iterations is reached, and the target log-likelihood ratio LLR of the information bit direction of the sequence to be decoded is obtained, and the information bit direction is the LLR transmission direction from the high level to the low level; finally, decoding is performed according to the target LLR in the information bit direction to obtain the decoding result. It can be seen that compared with the current serial soft elimination decoding mechanism, the communication equipment can improve the algorithm efficiency by parallelizing the decoding process in the soft elimination decoding mechanism, so as to meet the soft bit output and ensure high decoding performance requirements, which is conducive to reducing the decoding delay and improving the decoding throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0017] Figure 1 It is a structural diagram of a communication system provided in an embodiment of the present application;

[0018] Figure 2 It is a structural diagram of a terminal device provided in an embodiment of the present application;

[0019] Figure 3 It is a structural diagram of a network device provided in an embodiment of the present application;

[0020] Figure 4 This is a schematic diagram of channel coding provided by an embodiment of the present application;

[0021] Figure 5 is a fence diagram of a Polar code with a code length N=8 provided in an embodiment of the present application;

[0022] Figure 6It is a butterfly operation graph of a "butterfly" topology provided in an embodiment of the present application;

[0023] Figure 7 It is a schematic diagram of soft information transmission of a butterfly operation graph provided in an embodiment of the present application;

[0024] Figure 8 is a decoding binary tree provided in an embodiment of the present application;

[0025] Fig. 9 It is another decoding binary tree provided in the embodiment of the present application;

[0026] Fig.10 It is a schematic diagram of the correspondence between the factor graph of the sequence to be decoded and the decoding binary tree provided in the embodiment of the present application;

[0027] Fig.11 It is a simplified decoding binary tree provided in the embodiment of the present application;

[0028] Fig.12a It is a flowchart of a parallel soft elimination decoding method provided in an embodiment of the present application;

[0029] Figure 12b It is a schematic diagram of a parallel decoding processing sub-block provided in an embodiment of the present application;

[0030] Fig.13 This is a fast soft elimination decoding flow chart provided by an embodiment of the present application;

[0031] Fig.14 It is a structural diagram of a multi-package sharing competition computing resource provided by an embodiment of the present application;

[0032] Fig.15 This is a block diagram of the functional units of a communication device provided in an embodiment of the present application;

[0033] Fig.16 It is a structural diagram of another communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0035] Figure 1A schematic diagram of a communication system provided for an embodiment of the present application. The communication system 100 may include at least one network device 101 (only one is shown) and one or more terminal devices 102 connected to the network device 101. The network device 101 may communicate wirelessly with the terminal device 102 via one or more antennas. Each network device 101 may provide communication coverage for its corresponding coverage area 104. The coverage area 104 corresponding to the network device 101 may be divided into multiple sectors, wherein one sector corresponds to a portion of the coverage area (not shown).

[0036] In the embodiment of the present application, the network device 101 may include: a base transceiver station (Base Transceiver Station), a wireless transceiver, a basic service set (Basic Service Set, BSS), an extended service set (Extended Service Set, ESS), Node B (NodeB), evolved Node B (evolved NodeB, eNB or eNodeB), or next-generation Node B (next-generation NodeB, gNB), etc. The communication system 100 may include several different types of network devices 101, such as a macro base station (macrobasestation), a micro base station (microbasestation), etc. The network device 101 may also be a small station, a transmission node (Transmission Reference Point, TRP), etc. The network device 101 can apply different wireless technologies, such as a cell wireless access technology, or a WLAN wireless access technology.

[0037] In the embodiment of the present application, the terminal device 102 is a device with wireless transceiver function that can be deployed on land, including indoors or outdoors, handheld, wearable or vehicle-mounted; it can also be deployed on the water surface (such as ships, etc.); it can also be deployed in the air (such as airplanes, balloons and satellites, etc.). The terminal device can be a mobile phone, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. The embodiment of the present application does not limit the application scenario. The terminal device may sometimes also be referred to as user equipment (UE), terminal, access terminal, UE unit, UE station, mobile device, mobile station, mobile station (mobilestation), mobile terminal, mobile client, mobile unit (mobile unit), remote station, remote terminal equipment, remote unit, wireless unit, wireless communication equipment, user agent or user device, etc.

[0038] It should be noted that the terms "system" and "network" in the embodiments of the present application can be used interchangeably. "Multiple" refers to two or more. In view of this, in the embodiments of the present application, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0039] refer to Figure 2 , Figure 2 The terminal device provided in the embodiment of the present application is shown. Figure 2 As shown, the terminal device 200 may include: an input and output module (including an audio input and output module 218, a key input module 216, and a display 220, etc.), a user interface 202, one or more processors 204, a transmitter 206, a receiver 208, a coupler 210, an antenna 214, and a memory 212. These components may be connected via a bus or other means. Figure 2 Take bus connection as an example.

[0040] The antenna 214 can be used to convert electromagnetic energy into electromagnetic waves in free space, or convert electromagnetic waves in free space into electromagnetic energy in a transmission line. The coupler 210 is used to divide the mobile communication signal received by the antenna 214 into multiple paths and distribute them to multiple receivers 208.

[0041] The transmitter 206 may be configured to perform transmission processing on the signal output by the processor 204 .

[0042] The receiver 208 may be configured to receive and process the mobile communication signal received by the antenna 214 .

[0043] In the embodiment of the present application, the transmitter 206 and the receiver 208 can be regarded as a wireless modem. In the terminal device 200, the number of the transmitter 206 and the number of the receiver 208 can be one or more.

[0044] Apart from Figure 2 In addition to the transmitter 206 and the receiver 208 shown, the terminal device 200 may also include other communication components, such as a GPS module, a Bluetooth module, a wireless high-fidelity (Wireless Fidelity, Wi-Fi) module, etc. Not limited to the wireless communication signals described above, the terminal device 200 may also support other wireless communication signals, such as satellite signals, shortwave signals, etc. Not limited to wireless communication, the terminal device 200 may also be configured with a wired network interface (such as a LAN interface) 201 to support wired communication.

[0045] The input / output module can be used to realize the interaction between the terminal device 200 and the user / external environment, and can mainly include an audio input / output module 218, a key input module 216, and a display 220. Specifically, the input / output module can also include: a camera, a touch screen, and a sensor. The input / output modules communicate with the processor 204 through the user interface 202.

[0046] The memory 212 can be coupled to the processor 204 through a bus or an input / output port, or the memory 212 can be integrated with the processor 204. The memory 212 is used to store various software programs and / or multiple sets of instructions. Specifically, the memory 212 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. The memory 212 can store an operating system (hereinafter referred to as the system), such as an embedded operating system such as ANDROID, IOS, WINDOWS, or LINUX. The memory 212 can also store a network communication program, which can be used to communicate with one or more additional devices, one or more terminal devices, and one or more network devices. The memory 212 can also store a user interface program, which can display the content of the application program vividly through a graphical operation interface, and receive user control operations on the application program through input controls such as menus, dialog boxes, and buttons.

[0047] In the embodiment of the present application, the memory 212 may be used to store an implementation program of the parallel soft elimination decoding method provided by one or more embodiments of the present application. For the implementation of the parallel soft elimination decoding method provided by one or more embodiments of the present application, please refer to the subsequent embodiments.

[0048] The processor 204 can be used to read and execute computer-readable instructions. Specifically, the processor 204 can be used to call a program stored in the memory 212, such as an implementation program of the parallel soft elimination decoding method provided by one or more embodiments of the present application on the first transfer device side, and execute the instructions contained in the program to implement the methods involved in the subsequent embodiments. The processor 204 can support: Global System for Mobile Communication (GSM) (2G) communication, Wideband Code Division Multiple Access (WCDMA) (3G) communication, and Long Term Evolution (LTE) (4G) communication, and 5G communication, etc. One or more. Optionally, when the processor 204 sends any message or data, it specifically drives or controls the transmitter 206 to do the sending.

[0049] Optionally, when the processor 204 receives any message or data, it specifically performs the reception by driving or controlling the receiver 208. Therefore, the processor 204 can be regarded as a control center for performing transmission or reception, and the transmitter 206 and the receiver 208 are specific executors of the transmission and reception operations.

[0050] It is understandable that the terminal device 200 may be Figure 1 The terminal device 102 in the communication system 100 shown can be implemented as a user equipment (UE), a terminal, an access terminal, a UE unit, a UE station, a mobile device, a mobile station, a mobile station (mobilestation), a mobile terminal, etc.

[0051] Need to explain, Figure 2 The terminal device 200 shown is only one implementation of the embodiment of the present application. In actual applications, the terminal device 200 may also include more or fewer components, which is not limited here.

[0052] refer to Figure 3 , Figure 3 The network device provided by the embodiment of the present application is shown. Figure 3 As shown, the network device 300 may include: one or more processors 301, a memory 302, a network interface 303, a transmitter 305, a receiver 306, a coupler 307 and an antenna 308. These components may be connected via a bus 304 or other means. Figure 3 Take bus connection as an example.

[0053] The network interface 303 may be used for the network device 300 to communicate with other communication devices, such as other network devices. Specifically, the network interface 303 may be a wired interface.

[0054] The transmitter 305 can be used to perform transmission processing on the signal output by the processor 301, such as signal modulation. The receiver 306 can be used to perform reception processing on the mobile communication signal received by the antenna 308. For example, signal demodulation. In some embodiments of the present application, the transmitter 305 and the receiver 306 can be regarded as a wireless modem. In the network device 300, the number of transmitters 305 and receivers 306 can be one or more. The antenna 308 can be used to convert electromagnetic energy in the transmission line into electromagnetic waves in free space, or to convert electromagnetic waves in free space into electromagnetic energy in the transmission line. The coupler 307 can be used to divide the mobile communication signal into multiple paths and distribute them to multiple receivers 306.

[0055] The memory 302 can be coupled to the processor 301 through the bus 304 or the input / output port, and the memory 302 can also be integrated with the processor 301. The memory 302 is used to store various software programs and / or multiple groups of instructions. Specifically, the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices or other non-volatile solid-state storage devices. The memory 302 can store an operating system (hereinafter referred to as system), such as embedded operating systems such as uCOS, VxWorks, RTLinux, etc. The memory 302 can also store a network communication program, which can be used to communicate with one or more additional devices, one or more terminal devices, and one or more network devices.

[0056] The processor 301 can be used to manage wireless channels, establish and remove calls and communication links, and provide cell switching control for users in the control area. Specifically, the processor 301 may include: an administration module / communication module (AM / CM) (a center for voice exchange and information exchange), a basic module (BM) (for completing call processing, signaling processing, wireless resource management, wireless link management and circuit maintenance functions), a transcoder and submultiplexer (TCSM) (for completing multiplexing, demultiplexing and code conversion functions), and the like.

[0057] In the embodiment of the present application, the processor 301 can be used to read and execute computer-readable instructions. Specifically, the processor 301 can be used to call a program stored in the memory 302, such as an implementation program of the parallel soft elimination decoding method provided in one or more embodiments of the present application, and execute the instructions contained in the program.

[0058] It is understandable that the network device 300 may be Figure 1 The network device 101 in the communication system 100 shown may be implemented as a base station, a wireless transceiver, a basic service set (BSS), an extended service set (ESS), NodeB, eNodeB, gNB, etc.

[0059] It should be noted that Figure 3 The network device 300 shown is only one implementation of the embodiment of the present application. In actual applications, the network device 300 may also include more or fewer components, which is not limited here.

[0060] It should be noted that the receiving device described in the following embodiments may be the above-mentioned terminal device, and the sending device may be the above-mentioned network device. Alternatively, the receiving device described in the following embodiments may be the above-mentioned network device, and the sending device may be the above-mentioned terminal device.

[0061] It should be noted that Figure 3 The network device 300 shown is only one implementation of the embodiment of the present application. In actual applications, the network device 300 may also include more or fewer components, which is not limited here.

[0062] It should be noted that the receiving device described in the following embodiments may be the above-mentioned terminal device, and the sending device may be the above-mentioned network device. Alternatively, the receiving device described in the following embodiments may be the above-mentioned network device, and the sending device may be the above-mentioned terminal device.

[0063] Figure 4 It is a schematic diagram of channel coding in a communication link. The transmitting device performs source coding and channel coding on the signal to be transmitted (i.e., the source) to obtain a coded signal, and then performs rate matching and digital modulation on the coded signal, and transmits the coded signal through the channel. The receiving device receives the channel output signal from the channel and performs digital demodulation, rate matching, channel decoding and source decoding, and finally restores the signal (i.e., the destination). Among them, the signal to be transmitted includes U1, U2...UN, a total of N bits, and N is the length of the signal to be transmitted, or the code length. Correspondingly, the coded signal includes X1, X2...XN, a total of N bits. The channel output signal includes Y1, Y2...YN, a total of N bits. In this application, the signal to be transmitted may also be referred to as a pre-coded signal, and the coded signal is the coded signal. The signal to be transmitted may also be referred to as a sequence to be transmitted or a sequence to be recovered, the channel output signal may also be referred to as a received sequence or a sequence to be decoded, and the coded signal may also be referred to as a coded sequence. Among them, the pre-coded signal includes fixed bits (Frozenbits) and information bits (Informationbits). In the encoding process of the Polar code, a part of the bits in are used to carry information, which is called information bits. The set of indexes of these bits can be recorded as another part of the bits is set to a fixed value pre-agreed by the transceiver, which is called a fixed bit. The set of its indexes can be represented by the complement of. The selection method of the information bit index set is not limited in this application. Among them, the information bits can also include various types of check bits.

[0064] Polar codes are the only coding method that has been theoretically proven to asymptotically reach channel capacity, and have excellent decoding performance in a wide range of operating ranges (code length, code rate, and signal-to-noise ratio).

[0065] The encoding of polar code can be expressed as follows:

[0066] x=u·Fn

[0067] Where u is an n-length binary vector (information bits), F n is the Kronecker transformation matrix. is a 2×2 matrix The K product. The code generated by this method and the bit-by-bit cancellation (SC) decoding method will produce polarization. That is, some bits in u pass through an equivalent high-reliability channel and are decoded with high probability, and the remaining bits pass through an equivalent low-reliability channel and are decoded with low probability. Accordingly, we use the high-reliability channel for information transmission, and set the bits corresponding to the low-reliability channel to zero (freeze) and do not transmit data. In some specific scenarios, such as soft decoding iteration of cascaded Polar codes, iterative decoding interference elimination in multi-user scenarios, etc., Polar soft bit decoding is required to match. In this case, BP decoding or SCAN decoding with average performance is usually used to achieve the purpose of soft bit output.

[0068] Mainstream Polar decoding algorithms such as Successive Cancellation (SC) and Successive Cancellation List (SCL) can achieve good performance when the code is short, but can only provide binary decoding results (hard bit output) and cannot provide the likelihood probability of the decoded bit (soft bit output). The disadvantages of this are: it cannot participate in the composition of various concatenated codes (such as serial concatenated codes, parallel concatenated codes, and generalized concatenated codes) as a subcode; it cannot participate in the large iterative reception algorithms of various advanced receivers (such as Multi Input Multi Output (MIMO), non-orthogonal multiple access NOMA, etc.) as a submodule and obtain gain; it has poor support for services (digital language, video transmission) that are sensitive to bit error rate (Bit Error Rate, BER) (rather than frame error rate (Block Error Rate, BLER)). At the same time, there is a serial soft cancellation (Soft Cancellation, SCAN) algorithm that avoids hard decisions on the decoded bits, but uses soft decisions and soft bits for feedback, so that even if the previous bit is decoded incorrectly, it will not have a diffuse impact on the decision of the subsequent bits. The BLER performance of the soft cancellation algorithm is better than that of the SC algorithm in a small number of iterations, but more importantly, it can provide soft bit output and has better BER performance. However, due to the serial decoding order of the soft cancellation algorithm, its decoding delay has become a bottleneck restricting its application.

[0069] The following is an introduction to the soft bit decoding algorithm. Figure 5is a fence graph (also called factor graph, coding graph, etc.) of the Polar code corresponding to the Polar code with code length N = 8. The coding process of the polar code can be represented by the connection relationship in the above figure, where the row number of the node is denoted by i, the column number is denoted by s, the node in the i-th row and s-th column is denoted by (i, s), and the leftmost node (i, s) = {(0, 0), (1, 0), (2, 0), (4, 0)} is set as a frozen bit, and the 4-bit information bit is encoded into 8-bit coded bits. After the above encoding, the coded n-length codeword (coded bit) is modulated and then passed through a noisy channel. Figure 6 for Figure 5 The butterfly operation graph of each "butterfly" topology in the butterfly operation graph represents the encoding and decoding relationship of [u(i,s),u(i+2s,s)]·F=[x(i,s+1),x(i+2s,s+1)], where u(i,s),u(i+2s,s) represent the binary values ​​of the two nodes on the left side of the butterfly operation graph respectively, and x(i,s+1),x(i+2s,s+1) represent the binary values ​​of the two nodes on the right side of the butterfly operation graph respectively. Figure 7 for Figure 6 The four nodes in the butterfly operation diagram transmit soft information to each other, and the transmission relationship and steps are shown in the figure. Among them, the soft message transmitted to the left (information bit direction) is represented by α, and the soft message transmitted to the right (codeword bit direction) is represented by β. The soft message exchange in a butterfly operation is carried out in 4 steps, and each arrow represents the message transmission of 1 bit. In traditional SC decoding, the message to the left is soft (likelihood probability) and the message to the right is hard (0 / 1 judgment). In the embodiment of the present application, both the messages to the left and the right are soft.

[0070] In the soft cancellation algorithm, the long code is recursively projected to the short code, and the decoding order can be described as follows Figure 8 The depth-first search on the binary tree shown in the figure, where the numbers ①②③④ represent the soft message transmission directions. And so on, Figure 5 The decoding binary tree corresponding to the factor graph of Fig. 9 The decoding binary tree shown in FIG. 1 is a root node, which is an N-length codeword to be decoded, corresponding to an 8-bit codeword of s=3. The child node to the lower left is an N / 2-length codeword after left projection, corresponding to a 4-bit codeword of the upper half of s=2. The child node to the lower right is an N / 2-length codeword after right projection, corresponding to a 4-bit codeword of the lower half of s=2. The decoding binary tree of the sequence to be decoded is formed by analogy. More intuitively, the corresponding relationship between the factor graph of the sequence to be decoded and the decoding binary tree is as follows: Fig.10As shown, the 8-bit codeword in the third column of the factor graph corresponds to the root node of the third layer of the decoding binary tree, the two consecutive 4-bit codewords in the second column of the factor graph (respectively the left-projected 4-bit codeword {(0,1), (1,2), (2,2), (3,2)} and the right-projected 4-bit codeword {(4,2), (5,2), (6,2), (7,2)}) correspond one-to-one to the two leaf nodes of the second layer of the decoding binary tree, the four consecutive 2-bit codewords in the first column of the factor graph (respectively the codeword {(0,1), (1,1)}, the codeword {(2,1), (3,1)}, the codeword {(4,1), (5,1)}, the codeword {(6,1), (7,1)}) correspond one-to-one to the four leaf nodes of the first layer of the decoding binary tree, and the 8 bits in the 0th column of the factor graph correspond one-to-one to the 8 leaf nodes of the 0th layer of the decoding binary tree.

[0071] The embodiment of the present application parallelizes the special sub-blocks encountered in the serial soft elimination algorithm at the mth stage (m>=2), thereby speeding up the decoder. The decoding of these sub-blocks does not need to be decoded bit by bit, but rather multiple bits are directly decoded simultaneously. Therefore, when these nodes are accessed on the decoding binary tree, there is no need to recursively go down to the leaf node, thereby reducing the steps required for decoding. Specifically, the sub-blocks that can be accelerated are:

[0072] Rate-0 sub-block: the corresponding sub-channel numbers are all frozen bits;

[0073] Rate-1 sub-block: that is, the corresponding sub-channel labels are all information bits;

[0074] REP sub-block: that is, there is only one information bit in the corresponding sub-channel label, and the rest are all frozen bits;

[0075] SPC sub-block: that is, there is only one frozen bit in the corresponding sub-channel label, and the rest are all information bits;

[0076] 4-BIT sub-block: A sub-block of any length of 4.

[0077] Through sub-block acceleration, Fig. 9 The decoding binary tree described in can be greatly simplified, and decoding can be completed without visiting the leaf nodes. The simplified decoding binary tree is as follows Fig.11 The simplified decoding binary tree shown in FIG. The simplified binary tree has only two nodes, and only two steps are needed at least in the decoder chip.

[0078] See also Fig.12a , Fig.12a is a flow chart of a parallel soft elimination decoding method provided by an embodiment of the present application, which can be based on a communication device (such as Figure 1The method is implemented by a network device or a terminal device in the communication system shown in the figure, and includes but is not limited to the following steps:

[0079] Step S1201: Obtain a sequence to be decoded, where the bit length of the sequence to be decoded is N, where N is a positive integer;

[0080] The sequence to be decoded may be any GN-Coset code (eg, RM code, Polar code, TurboProduct code, etc.), which is not limited here.

[0081] Step S1202: Determine the level range s to 0 of the log-likelihood ratio (LLR) update mechanism of the sequence to be decoded according to N, wherein level m to level 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, N=2 s+1 , m is an integer greater than or equal to 2, and s is an integer greater than m;

[0082] The sub-block supporting parallel decoding processing may be N / 2 of the reference node set according to the mth column. m The node subset obtained by performing node mapping on any codeword in the consecutive codewords, the reference node set is a set of nodes from the 0th column to the mth column in the factor graph, the N / 2 m The consecutive codewords are codewords divided according to the butterfly operation relationship, and the node mapping means that the row numbers of the nodes from the 0th column to the m-1th column correspond to the row number of the codeword currently selected in the mth column.

[0083] The sub-block supporting parallel decoding processing may also be a node subset of any sub-binary tree structure from the 0th layer to the mth layer in the decoding binary tree.

[0084] Step S1203: performing LLR iterative update on the sequence to be decoded layer by layer according to the layer range s to 0 until a preset maximum number of iterations is reached, and obtaining a target log-likelihood ratio LLR in the information bit direction of the sequence to be decoded, where the information bit direction is the LLR transmission direction from a high level to a low level;

[0085] Step S1204: Decoding is performed according to the target LLR in the information bit direction to obtain a decoding result.

[0086] It can be seen that in this example, the communication device first obtains the sequence to be decoded, the bit length of the sequence to be decoded is N, and N is a positive integer; secondly, the level range s to 0 of the log-likelihood ratio LLR update mechanism of the sequence to be decoded is determined according to N, wherein level m to level 0 constitutes a sub-block for parallel decoding processing of non-parity check PC bits, and N=2 s+1, m is an integer greater than or equal to 2, s is an integer greater than m; again, the LLR of the sequence to be decoded is iteratively updated layer by layer according to the level range s to 0 until the preset maximum number of iterations is reached, and the target log-likelihood ratio LLR of the information bit direction of the sequence to be decoded is obtained, and the information bit direction is the LLR transmission direction from the high level to the low level; finally, decoding is performed according to the target LLR in the information bit direction to obtain the decoding result. It can be seen that compared with the current serial soft elimination decoding mechanism, the communication equipment can improve the algorithm efficiency by parallelizing the decoding process in the soft elimination decoding mechanism, so as to meet the soft bit output and ensure high decoding performance requirements, which is conducive to reducing the decoding delay and improving the decoding throughput.

[0087] In a possible example, the sub-block supporting parallel decoding processing includes at least one of the following:

[0088] Rate-0 sub-block: the corresponding sub-channel numbers are all frozen bits;

[0089] Rate-1 sub-block: that is, the corresponding sub-channel labels are all information bits;

[0090] REP sub-block: that is, there is only one information bit in the corresponding sub-channel label, and the rest are all frozen bits;

[0091] SPC sub-block: that is, there is only one frozen bit in the corresponding sub-channel label, and the rest are all information bits; and,

[0092] 4-BIT sub-block: A sub-block of any length of 4.

[0093] In one possible example, Figure 12b The schematic diagram of the parallel decoding processing sub-block shown in FIG. 1 defines the row numbers of the sub-blocks supporting parallel processing as {i, i+1, ..., i+2 s -1}; i is 0 or a positive integer;

[0094] The input of the sub-block supporting parallel decoding processing is defined as follows:

[0095] The log-likelihood ratios (LLRs) of the codeword input are α(i, m), α(i+1, m), ..., α(i+2 s -1, m), where α is the LLR transmitted in the information bit direction, x in α(x, y) represents the row number in the factor graph of the sequence to be decoded, and y represents the column number in the factor graph;

[0096] The LLRs input on the information side are β(i, 0), β(i+1, 0), ..., β(i+2 s-1, 0), where β is the LLR transmitted in the codeword bit direction, x in β(x, y) represents the row number in the factor graph, y represents the column number in the factor graph, and the codeword bit direction is the LLR transmission direction from the low level to the high level;

[0097] When the jth bit is a frozen bit, the value of β(j,0) is defined as infinity, j is greater than or equal to i and less than or equal to i+2 s -1;

[0098] The output of the sub-block supporting parallel decoding processing is defined as follows:

[0099] The LLR output on the codeword side is β(i, m), β(i+1, m), ..., β(i+2 s -1, m).

[0100] In a possible example, the sub-block supporting parallel processing includes the Rate-0 sub-block, and the parallel decoding processing manner of the Rate-0 sub-block is as follows:

[0101] β(i,m)=β(i+1,m)=...=β(i+2 s -1, m)=∞.

[0102] In a possible example, the sub-block supporting parallel processing includes the Rate-1 sub-block, and the parallel decoding processing manner of the Rate-1 sub-block is as follows:

[0103] β(i,m)=β(i+1,m)=...=β(i+2 s -1, m)=0.

[0104] In a possible example, the sub-block supporting parallel processing includes the REP sub-block, and the parallel decoding processing manner of the REP sub-block is as follows:

[0105]

[0106] In a possible example, the sub-block supporting parallel processing includes the SPC sub-block, and the parallel decoding processing manner of the SPC sub-block is as follows:

[0107] β(j,m)=f1(α(i,m),α(i+1,m),…,α(j-1,m),α(j+1,m),…,α(i+2 s -1, m))

[0108]

[0109] In a possible example, the sub-block supporting parallel decoding processing includes the 4-BIT sub-block, and the parallel decoding method of the 4-BIT sub-block is as follows:

[0110] The LLRs input on the codeword side are α(i, m), α(i+1, m), α(i+2, m), α(i+3, m);

[0111] F and I represent frozen bits and information bits respectively. If the frozen / information bit mode corresponding to the information side of the sub-block supporting parallel decoding processing is [FFII], the output LLR is

[0112] β(i, m) = α(i+2, m)

[0113] β(i+1, m) = α(i+3, m)

[0114] β(i+2, m) = α(i, m)

[0115] β(i+3, m) = α(i+1, m)

[0116] If the freeze / information bit pattern corresponding to the 4 bits is [FIFI], the output LLR is

[0117] β(i, m) = α(i+1, m)

[0118] β(i+1, m) = α(i+3, m)

[0119] β(i+2, m) = α(i, m)

[0120] β(i+3,m)=α(i+2,m).

[0121] In a possible example, the sequence to be decoded includes only the non-PC bits; the iterative updating of the LLR level by level of the sequence to be decoded according to the level range s to 0 includes: iterative updating of the LLR level by level of the sequence to be decoded according to the level range s to m.

[0122] It can be seen that in this example, since level m is multi-bit parallel decoding in the decoding process of non-PC bits, the decoder speed is accelerated and the soft elimination decoding efficiency is improved.

[0123] In a possible example, the sequence to be decoded includes the non-PC bits and PC bits; the LLR iterative update of the sequence to be decoded according to the level range s to 0 includes: performing LLR iterative update of the non-PC bits according to the level range s to m; performing LLR iterative update of the PC bits according to the level range s to 0 according to the SCAN decoding algorithm.

[0124] It can be seen that in this example, since level m is multi-bit parallel decoding during the decoding process of non-PC bits, the decoder speed is accelerated, the soft elimination decoding efficiency is improved, and the accurate decoding of PC bits can be guaranteed.

[0125] In this possible example, the bits in the sequence to be decoded are classified and defined in the following manner:

[0126] The label corresponding to the definition subchannel u is denoted as l(u); the set of all information subchannels is denoted as The set of all frozen subchannels is denoted as The set of all PC subchannels is denoted as The set of all information bits verified by PC bit u is denoted as The set of all information bits verified by any PC bit is denoted as The remaining set of information bits is denoted by

[0127] The update formula of β is:

[0128]

[0129]

[0130]

[0131]

[0132] in,

[0133]

[0134] in, and is a set of constants greater than 0 and less than 1.

[0135] In this possible example, the function By replacing it with function f2,

[0136]

[0137] Among them, sign is the sign removal function, abs is the absolute value function, and min is the minimum value function;

[0138] Will If β is set to 0, the formula of β is updated as follows:

[0139]

[0140] Among them, by replacing the function f2, the update formula of the aforementioned soft message β can be replaced into a hardware-friendly form.

[0141] when hour,

[0142] when hour,

[0143] In practice, a more radical simplification approach can be adopted to achieve more efficient hardware implementation.

[0144] In the specific implementation, we can set a register array Δ, whose length is the length L of the check shift register. At the beginning of each decoding iteration, the value of the register array Δ is reset to zero. When the soft message value α u Will be accumulated into the f2 function and updated in the corresponding position of the register array:

[0145]

[0146] In this way, the value in the register array is continuously updated until the decoded node We can directly take out the value in the corresponding register to update its soft message value β u :

[0147]

[0148] The soft elimination decoding algorithm of the embodiment of the present application can not only provide soft bit output, but also has the characteristics of low latency and parallelization.

[0149] Applicable to the following scenarios:

[0150] (1) As a subcode, it provides soft output for various cascade codes;

[0151] (2) As a submodule to provide soft output for advanced receivers;

[0152] (3) Support BER-sensitive services;

[0153] (4) Support delay-sensitive services.

[0154] The simplified process of the above decoding algorithm in the "serial decoding" module can be as follows: Fig.13 The fast soft elimination decoding flow chart first sends the LLR input from the codeword side and the LLR input from the information side to the "serial decoding" module; and performs Rate-0 / REP / SPC / Rate-1 / 4-BIT sub-block judgment on the sub-code block currently processed by the module.

[0155] If the subcode block currently being processed belongs to any of the above sub-blocks, it is processed according to the parallel decoding method of the sub-block.

[0156] If the subcode block currently being processed does not belong to any of the above sub-blocks, it is recursively sub-decomposed and decoded.

[0157] If the decoding of the currently processed subcode block is completed, the subcode block is exited, and the subcode block of the previous layer is returned to be updated and decoding is continued until the number of iterations meets the preset maximum number of iterations.

[0158] Among them, j in the code decomposition step is the row number of the currently processed bit in the factor graph.

[0159] The above decoding algorithm can be implemented as follows: Fig.14 The structure of multiple packets sharing competitive computing resources is implemented, and the structure specifically includes multiple state machines, a first arbitrator, a first gate, a second arbitrator, a second gate, a third arbitrator, and a third gate;

[0160] The multiple state machines are all communicatively connected with the first gate, the second gate, and the third gate; the first arbitrator is connected to the first gate, the second arbitrator is connected to the second gate, and the third arbitrator is connected to the third gate; the first gate is connected to a first computing resource that supports the level-by-level update of the log-likelihood ratio LLR in the information bit direction, the second gate is connected to a second computing resource that supports the parallelized decoding process, and the third gate is connected to a third computing resource that supports the level-by-level update of the LLR in the codeword bit direction, the information bit direction is the LLR transmission direction from the high level to the low level, the codeword bit direction is the LLR transmission direction from the low level to the high level, and the parallelized decoding process is the parallelized decoding process as in the above method embodiment;

[0161] Each state machine in the plurality of state machines is used to schedule a packet to be decoded;

[0162] The first arbitrator is used to sequentially configure the first computing resource for at least one state machine among the multiple state machines according to a preset priority after detecting a first application of the at least one state machine among the multiple state machines;

[0163] The second arbitrator is used to sequentially configure the second computing resource for at least one state machine among the multiple state machines according to a preset priority after detecting a second application of the at least one state machine among the multiple state machines;

[0164] The third arbitrator is used to sequentially configure the third computing resource for at least one state machine among the multiple state machines according to a preset priority after detecting a third application of the at least one state machine among the multiple state machines.

[0165] Among them, N state machines jointly schedule N packets to be decoded, and the packets to be decoded may be sequences to be decoded.

[0166] In a specific implementation, the above-mentioned structure of multiple packages sharing competitive computing resources can be integrated into a communication device, or implemented using a distributed device. This application does not make a sole limitation on the hardware integration method.

[0167] It can be seen that in this example, compared with the current serial soft elimination decoding mechanism, the present application can improve the algorithm efficiency by parallelizing the decoding processing in the soft elimination decoding mechanism, thereby being able to meet the soft bit output and ensure high decoding performance requirements, which is beneficial to reducing the decoding delay and improving the decoding throughput.

[0168] The method of the embodiment of the present application is described in detail above, and the device of the embodiment of the present application is provided below.

[0169] See also Fig.15 , Fig.15 1 is a functional unit block diagram of a communication device 1500 provided in an embodiment of the present application, which specifically includes a processing unit 1501 and a communication unit 1502. The processing unit 1501 is used to control and manage the actions of the communication device. For example, the processing unit 1501 is used to support the communication device to execute Figure 4 The communication unit 1502 is used to support the communication between the communication device and other devices. The communication device may also include a storage unit 1503 for storing program codes and data of the terminal.

[0170] In specific implementation, the processing unit 1502 is used to execute any step of the above method embodiment, and when performing data transmission such as sending, the communication unit 1502 can be selectively called to complete the corresponding operation. Detailed description is given below.

[0171] The processing unit 1502 is used to obtain a sequence to be decoded through the communication unit, where the bit length of the sequence to be decoded is N, where N is a positive integer; and determine a level range s to 0 of a log-likelihood ratio (LLR) update mechanism of the sequence to be decoded according to N, where levels m to 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, and N=2 s+1 , m is an integer greater than or equal to 2, and s is an integer greater than m; and the to-be-decoded sequence is iteratively updated layer by layer by LLR according to the level range s to 0 until a preset maximum number of iterations is reached to obtain a target log-likelihood ratio LLR in the information bit direction of the to-be-decoded sequence, wherein the information bit direction is the LLR transmission direction from a high level to a low level; and decoding is performed according to the target LLR in the information bit direction to obtain a decoding result.

[0172] In a possible example, the sub-block supporting parallel decoding processing includes at least one of the following:

[0173] Rate-0 sub-block: the corresponding sub-channel numbers are all frozen bits;

[0174] Rate-1 sub-block: that is, the corresponding sub-channel labels are all information bits;

[0175] REP sub-block: that is, there is only one information bit in the corresponding sub-channel label, and the rest are all frozen bits;

[0176] SPC sub-block: that is, there is only one frozen bit in the corresponding sub-channel label, and the rest are all information bits; and,

[0177] 4-BIT sub-block: A sub-block of any length of 4.

[0178] In a possible example, the row numbers of the sub-blocks supporting parallel processing are {i, i+1, ..., i+2 s -1};

[0179] The input of the sub-block supporting parallel decoding processing is defined as follows:

[0180] The log-likelihood ratios (LLRs) of the codeword input are α(i, m), α(i+1, m), ..., α(i+2 s -1, m), where α is the LLR transmitted in the information bit direction, x in α(x, y) represents the row number in the factor graph of the sequence to be decoded, and y represents the column number in the factor graph;

[0181] The LLRs input on the information side are β(i, 0), β(i+1, 0), ..., β(i+2 s -1, 0), where β is the LLR transmitted in the codeword bit direction, x in β(x, y) represents the row number in the factor graph, y represents the column number in the factor graph, and the codeword bit direction is the LLR transmission direction from the low level to the high level;

[0182] When the jth bit is a frozen bit, the value of β(j,0) is defined as infinity, j is greater than or equal to i and less than or equal to i+2 s -1;

[0183] The output of the sub-block supporting parallel decoding processing is defined as follows:

[0184] The LLR output on the codeword side is β(i, m), β(i+1, m), ..., β(i+2 s -1, m).

[0185] In a possible example, the sub-block supporting parallel processing includes the Rate-0 sub-block, and the parallel decoding processing manner of the Rate-0 sub-block is as follows:

[0186] β(i,m)=β(i+1,m)=...=β(i+2 s -1, m)=∞.

[0187] In a possible example, the sub-block supporting parallel processing includes the Rate-1 sub-block, and the parallel decoding processing manner of the Rate-1 sub-block is as follows:

[0188] β(i,m)=β(i+1,m)=...=β(i+2 s -1, m)=0.

[0189] In a possible example, the sub-block supporting parallel processing includes the REP sub-block, and the parallel decoding processing manner of the REP sub-block is as follows:

[0190]

[0191] In a possible example, the sub-block supporting parallel processing includes the SPC sub-block, and the parallel decoding processing manner of the SPC sub-block is as follows:

[0192] β(j,m)=f1(α(i,m),α(i+1,m),…,α(j-1,m),α(j+1,m),…,α(i+2 s -1, m))

[0193]

[0194] In a possible example, the sub-block supporting parallel decoding processing includes the 4-BIT sub-block, and the parallel decoding method of the 4-BIT sub-block is as follows:

[0195] The LLRs input on the codeword side are α(i, m), α(i+1, m), α(i+2, m), α(i+3, m);

[0196] F and I represent frozen bits and information bits respectively. If the frozen / information bit mode corresponding to the information side of the sub-block supporting parallel decoding processing is [FFII], the output LLR is

[0197] β(i, m) = α(i+2, m)

[0198] β(i, 1, m) = α(i+3, m)

[0199] β(i+2, m) = α(i, m)

[0200] β(i, 3, m) = α(i+1, m)

[0201] If the freeze / information bit pattern corresponding to the 4 bits is [FIFI], the output LLR is

[0202] β(i, m) = α(i+1, m)

[0203] β(i+1, m) = α(i+3, m)

[0204] β(i+2, m) = α(i, m)

[0205] β(i+3,m)=α(i+2,m).

[0206] In one possible example, the sequence to be decoded includes only the non-PC bits; in terms of iteratively updating the LLR level by level of the sequence to be decoded according to the level range s to 0, the processing unit is specifically used to iteratively update the LLR level by level of the sequence to be decoded according to the level range s to m.

[0207] In one possible example, the sequence to be decoded includes the non-PC bits and PC bits; in terms of the LLR iterative update of the sequence to be decoded according to the level range s to 0, the processing unit is specifically used to: iteratively update the LLR of the non-PC bits according to the level range s to m; and iteratively update the LLR of the PC bits according to the level range s to 0 according to the SCAN decoding algorithm.

[0208] In a possible example, the bits in the sequence to be decoded are classified and defined in the following manner:

[0209] The label corresponding to the definition subchannel u is denoted as l(u); the set of all information subchannels is denoted as The set of all frozen subchannels is denoted as The set of all PC subchannels is denoted as The set of all information bits verified by PC bit u is denoted as The set of all information bits verified by any PC bit is denoted as The remaining set of information bits is denoted by

[0210] The update formula of β is:

[0211]

[0212]

[0213]

[0214]

[0215] in

[0216]

[0217] in, and is a set of constants greater than 0 and less than 1.

[0218] In one possible example, the function By replacing it with function f2,

[0219]

[0220] Among them, sign is the sign removal function, abs is the absolute value function, and min is the minimum value function;

[0221] Will If β is set to 0, the formula of β is updated as follows:

[0222]

[0223] It should be noted that the implementation of each unit can also refer to Fig.12a Since the method embodiment and the device embodiment are different presentation forms of the same technical concept, the content of the method embodiment part in this application should be synchronously adapted to the device embodiment part, and will not be repeated here.

[0224] See also Fig.16 , Fig.16 A communication device 1600 is provided in an embodiment of the present application. The communication device 1600 includes a processor 1601, a memory 1602, and a transceiver 1603. The processor 1601, the memory 1602, and the transceiver 1603 are interconnected via a bus.

[0225] The memory 1602 includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a portable read-only memory (CD-ROM), and is used for related instructions and data. The transceiver 1603 is used to receive and send data.

[0226] The processor 1601 may be one or more central processing units (CPUs). When the processor 701 is a CPU, the CPU may be a single-core CPU or a multi-core CPU.

[0227] The processor 1601 in the communication device 1600 is used to read the program code stored in the memory 1602 and perform the following operations:

[0228] Obtain a sequence to be decoded, where the bit length of the sequence to be decoded is N, where N is a positive integer;

[0229] The level range s to 0 of the log-likelihood ratio (LLR) update mechanism of the sequence to be decoded is determined according to N, wherein level m to level 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, N=2 s+1 , m is an integer greater than or equal to 2, and s is an integer greater than m;

[0230] Iteratively updating the LLR of the sequence to be decoded layer by layer according to the layer range s to 0 until a preset maximum number of iterations is reached, and obtaining a target log-likelihood ratio LLR in the information bit direction of the sequence to be decoded, where the information bit direction is the LLR transmission direction from a high level to a low level;

[0231] Decoding is performed according to the target LLR in the information bit direction to obtain a decoding result.

[0232] It should be noted that the implementation of each operation can also refer to Fig.12a The corresponding description of the method embodiment shown.

[0233] An embodiment of the present application also provides a chip system, wherein the chip system includes a processor for calling and running a computer program from a memory, so that a device equipped with the chip system executes part or all of the steps of any method recorded in the above method embodiments.

[0234] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps of any method described in the above method embodiments, and the above computer includes an electronic device.

[0235] The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, the computer program is operable to cause a computer to execute some or all of the steps of any method described in the method embodiment. The computer program product may be a software installation package, and the computer includes an electronic device.

[0236] Those skilled in the art can understand that to implement all or part of the processes in the above-mentioned embodiments, the processes can be completed by computer programs to instruct related hardware, and the programs can be stored in computer-readable storage media. When the programs are executed, they can include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM or random access memory RAM, magnetic disk or optical disk and other media that can store program codes.

Claims

1. A parallel soft elimination decoding method, characterized in that: include: Obtain a sequence to be decoded, where the bit length of the sequence to be decoded is N, where N is a positive integer; The level range s to 0 of the log-likelihood ratio LLR update mechanism of the sequence to be decoded is determined according to N, wherein level m to level 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, N=2 s+1 , m is an integer greater than or equal to 2, and s is an integer greater than m; Iteratively updating the LLR of the sequence to be decoded layer by layer according to the layer range s to 0 until a preset maximum number of iterations is reached, and obtaining a target log-likelihood ratio LLR in the information bit direction of the sequence to be decoded, where the information bit direction is the LLR transmission direction from a high level to a low level; Decoding is performed according to the target LLR in the information bit direction to obtain a decoding result.

2. The method according to claim 1, characterized in that The sub-blocks of the non-parity PC bit parallel decoding processing include at least one of the following: Rate-0 sub-block: the corresponding sub-channel numbers are all frozen bits; Rate-1 sub-block: that is, the corresponding sub-channel labels are all information bits; REP sub-block: that is, there is only one information bit in the corresponding sub-channel label, and the rest are all frozen bits; SPC sub-block: that is, there is only one frozen bit in the corresponding sub-channel label, and the rest are all information bits; and, 4-BIT sub-block: A sub-block of any length of 4.

3. The method according to claim 2, characterized in that The row numbers of the sub-blocks processed by the non-parity PC bit parallel decoding are {i, i+1, ..., i+2 s -1}; The input of the sub-block for the non-parity PC bit parallel decoding process is defined as follows: The log-likelihood ratios (LLRs) of the codeword input are α(i, m), α(i+1, m), ..., α(i+2 s -1, m), where α is the LLR transmitted in the information bit direction, x in α(x, y) represents the row number in the factor graph of the sequence to be decoded, and y represents the column number in the factor graph; The LLRs input on the information side are β(i, 0), β(i+1, 0), ..., β(i+2 s -1, 0), where β is the LLR transmitted in the codeword bit direction, x in β(x, y) represents the row number in the factor graph, y represents the column number in the factor graph, and the codeword bit direction is the LLR transmission direction from the low level to the high level; When the jth bit is a frozen bit, the value of β(j,0) is defined as infinity, j is greater than or equal to i and less than or equal to i+2 s -1; The output of the sub-block of the non-parity PC bit parallel decoding process is defined as follows: The LLR output on the codeword side is β(i, m), β(i+1, m), ..., β(i+2 s -1, m).

4. The method according to claim 3, characterized in that The sub-blocks for parallel decoding of non-parity PC bits include the Rate-0 sub-blocks, and the parallel decoding processing of the Rate-0 sub-blocks is as follows: β(i,m), β(i+1,m),..., β(i+2 s -1, m) = ∞.

5. The method according to claim 3, characterized in that: The sub-blocks for parallel decoding of non-parity PC bits include the Rate-1 sub-blocks, and the parallel decoding processing of the Rate-1 sub-blocks is as follows: β(i,m)=β(i+1,m)=...=β(i+2 s -1, m) = 0.

6. The method according to claim 3, characterized in that The sub-block for parallel decoding of the non-parity PC bits includes the REP sub-block, and the parallel decoding processing of the REP sub-block is as follows:

7. The method according to claim 3, characterized in that The sub-block for parallel decoding of the non-parity check PC bits includes the SPC sub-block, and the parallel decoding processing of the SPC sub-block is as follows: β(j,m)=f1(α(i,m),α(i+1,m),…,α(j-1,m),α(j+1,m),…,α(i+2 s -1,m)) 8. The method according to claim 3, characterized in that The sub-blocks processed by the non-parity PC bit parallel decoding include the 4-BIT sub-blocks, and the parallel decoding method of the 4-BIT sub-blocks is as follows: The LLRs input on the codeword side are α(i, m), α(i+1, m), α(i+2, m), α(i+3, m); Let F and I represent the frozen bit and the information bit respectively. If the frozen / information bit pattern corresponding to the information side of the sub-block processed by the non-parity PC bit parallel decoding is [FFII], the output LLR is β(i, m) = α(i+2, m) β(i+1, m) = α(i+3, m) β(i+2, m) = α(i, m) β(i+3, m) = α(i+1, m) If the frozen / information bit pattern corresponding to the information side of the sub-block processed by the non-parity PC bit parallel decoding is [FIFI], the output LLR is β(i,m)=α(i+1,m) β(i+1, m) = α(i+3, m) β(i+2, m) = α(i, m) β(i+3,m)=α(i+2,m).

9. The method according to any one of claims 1 to 8, characterized in that: The sequence to be decoded includes only the non-parity check PC bits; and performing LLR iterative level-by-level updating on the sequence to be decoded according to the level range s to 0, comprising: The to-be-decoded sequence is iteratively updated level by level by LLR according to the level range s to m.

10. The method according to any one of claims 1 to 8, characterized in that: The sequence to be decoded includes the non-parity check PC bits and the parity check PC bits; and performing LLR iterative level-by-level updating on the sequence to be decoded according to the level range s to 0, including: Performing LLR iterative level-by-level update on the non-parity check PC bits according to the level range s to m; The parity check PC bits are iteratively updated level by level according to the level range s to 0 based on the SCAN decoding algorithm.

11. The method according to claim 10, characterized in that The bits in the sequence to be decoded are classified and defined in the following manner: The label corresponding to the definition subchannel u is denoted as l(u); the set of all information subchannels is denoted as I; the set of all frozen subchannels is denoted as F; the set of all parity check PC subchannels is denoted as P; the set of all information bits checked by the parity check PC bit u is denoted as I(u), u∈P; the set of all information bits checked by any parity check PC bit is denoted as The remaining set of information bits is denoted by The update formula of β is: in, in, and is a set of constants greater than 0 and less than 1.

12. The method according to claim 11, characterized in that The function By replacing it with function f2, Among them, sign is the sign removal function, abs is the absolute value function, and min is the minimum value function; Will If β is set to 0, the formula of β is updated as follows:

13. A structure for multiple packages to share competing computing resources, characterized in that: The system comprises a plurality of state machines, a first arbitrator, a first gate, a second arbitrator, a second gate, a third arbitrator, and a third gate; The multiple state machines are all communicatively connected with the first gate, the second gate, and the third gate; the first arbitrator is connected to the first gate, the second arbitrator is connected to the second gate, and the third arbitrator is connected to the third gate; the first gate is connected to a first computing resource that supports the level-by-level update of the log-likelihood ratio LLR in the information bit direction, the second gate is connected to a second computing resource that supports the parallelized decoding process, and the third gate is connected to a third computing resource that supports the level-by-level update of the LLR in the codeword bit direction, the information bit direction is the LLR transmission direction from the high level to the low level, the codeword bit direction is the LLR transmission direction from the low level to the high level, and the parallelized decoding process is the parallelized decoding process as claimed in any one of claims 1 to 12; Each state machine in the plurality of state machines is used to schedule a packet to be decoded; The first arbitrator is used to sequentially configure the first computing resource for at least one state machine among the multiple state machines according to a preset priority after detecting a first application of the at least one state machine among the multiple state machines; The second arbitrator is used to sequentially configure the second computing resource for at least one state machine among the multiple state machines according to a preset priority after detecting a second application of the at least one state machine among the multiple state machines; The third arbitrator is used to sequentially configure the third computing resource for at least one state machine among the multiple state machines according to a preset priority after detecting a third application of the at least one state machine among the multiple state machines.

14. A communication device, characterized in that: It includes a processing unit and a communication unit, wherein: The processing unit is used to obtain a sequence to be decoded through the communication unit, wherein the bit length of the sequence to be decoded is N, where N is a positive integer; and determine a level range s to 0 of a log-likelihood ratio (LLR) update mechanism of the sequence to be decoded according to N, wherein levels m to 0 constitute a sub-block for parallel decoding processing of non-parity check PC bits, and N=2 s+1 , m is an integer greater than or equal to 2, and s is an integer greater than m; and the to-be-decoded sequence is iteratively updated layer by layer by LLR according to the level range s to 0 until a preset maximum number of iterations is reached to obtain a target log-likelihood ratio LLR in the information bit direction of the to-be-decoded sequence, wherein the information bit direction is the LLR transmission direction from a high level to a low level; and decoding is performed according to the target LLR in the information bit direction to obtain a decoding result.

15. The communication device according to claim 14, characterized in that The sub-blocks of the non-parity PC bit parallel decoding processing include at least one of the following: Rate-0 sub-block: the corresponding sub-channel numbers are all frozen bits; Rate-1 sub-block: that is, the corresponding sub-channel labels are all information bits; REP sub-block: that is, there is only one information bit in the corresponding sub-channel label, and the rest are all frozen bits; SPC sub-block: that is, there is only one frozen bit in the corresponding sub-channel label, and the rest are all information bits; and, 4-BIT sub-block: A sub-block of any length of 4.

16. The communication device according to claim 15, characterized in that The row numbers of the sub-blocks processed by the non-parity PC bit parallel decoding are {i, i+1, ..., i+2 s -1}; The input of the sub-block for the non-parity PC bit parallel decoding process is defined as follows: The log-likelihood ratio LLR of the codeword input is α(i,m)α(i+1,m),...,α(i+2 s -1,m), where α is the LLR transmitted in the information bit direction, x in α(x,y) represents the row number in the factor graph of the sequence to be decoded, and y represents the column number in the factor graph; The LLRs of the information side input are β(i,0),β(i+1,0),...,β(i+2 s -1,0), where β is the LLR transmitted in the codeword bit direction, x in β(x,y) represents the row number in the factor graph, y represents the column number in the factor graph, and the codeword bit direction is the LLR transmission direction from the low level to the high level; When the jth bit is a frozen bit, the value of β(j,0) is defined as infinity, j is greater than or equal to i and less than or equal to i+2 s -1; The output of the sub-block of the non-parity PC bit parallel decoding process is defined as follows: The LLR output on the codeword side is β(i,m),β(i+1,m),...,β(i+2 s -1m).

17. The communication device according to claim 16, characterized in that The sub-blocks for parallel decoding of non-parity PC bits include the Rate-0 sub-blocks, and the parallel decoding processing of the Rate-0 sub-blocks is as follows: β(i,m)=β(i+1,m)=…=β(i+2 s -1,m) = ∞.

18. The communication device according to claim 16, characterized in that The sub-blocks for parallel decoding of non-parity PC bits include the Rate-1 sub-blocks, and the parallel decoding processing of the Rate-1 sub-blocks is as follows: β(i,m)=β(i+1,m)...=β(i+2 s -1,m) = 0.

19. The communication device according to claim 16, characterized in that The sub-block for parallel decoding of the non-parity PC bits includes the REP sub-block, and the parallel decoding processing of the REP sub-block is as follows:

20. The communication device according to claim 16, characterized in that The sub-block for parallel decoding of the non-parity check PC bits includes the SPC sub-block, and the parallel decoding processing of the SPC sub-block is as follows: β(j,m)=f1(α(i,m),α(i+1,m),…,α(j-1,m),α(j+1,m),…,α(i+2 s -1,m)) 21. The communication device according to claim 16, characterized in that The sub-blocks processed by the non-parity PC bit parallel decoding include the 4-BIT sub-blocks, and the parallel decoding method of the 4-BIT sub-blocks is as follows: The LLRs input on the codeword side are α(i, m), α(i+1, m), α(i+2, m), α(i+3, m); Let F and I represent the frozen bit and the information bit respectively. If the frozen / information bit pattern corresponding to the information side of the sub-block processed by the non-parity PC bit parallel decoding is [FFII], the output LLR is β(i, m) = α(i+2, m) β(i+1, m) = α(i+3, m) β(i+2, m) = α(i, m) β(i+3, m) = α(i+1, m) If the frozen / information bit pattern corresponding to the information side of the sub-block processed by the non-parity PC bit parallel decoding is [FIFI], the output LLR is β(i, m) = α(i+1, m) β(i+1, m) = α(i+3, m) β(i+2, m) = α(i, m) β(i+3,m)=α(i+2,m).

22. The communication device according to any one of claims 14 to 21, characterized in that: The sequence to be decoded only includes the non-parity PC bits; in terms of iteratively updating the LLR level by level of the sequence to be decoded according to the level range s to 0, the processing unit is specifically used to: iteratively update the LLR level by level of the sequence to be decoded according to the level range s to m.

23. The communication device according to any one of claims 14 to 21, characterized in that: The sequence to be decoded includes the non-parity PC bits and parity PC bits; in terms of the LLR iterative update of the sequence to be decoded according to the level range s to 0, the processing unit is specifically used to: perform LLR iterative update of the non-parity PC bits according to the level range s to m; and perform LLR iterative update of the parity PC bits according to the level range s to 0 according to the SCAN decoding algorithm.

24. The communication device according to claim 23, characterized in that The bits in the sequence to be decoded are classified and defined in the following manner: The label corresponding to the definition subchannel u is denoted as l(u); the set of all information subchannels is denoted as I; the set of all frozen subchannels is denoted as F; the set of all parity check PC subchannels is denoted as P; the set of all information bits checked by the parity check PC bit u is denoted as I(u), u∈P; the set of all information bits checked by any parity check PC bit is denoted as The remaining set of information bits is denoted by The update formula of β is: in, in, and is a set of constants greater than 0 and less than 1.

25. The communication device according to claim 24, characterized in that The function By replacing it with function f2, Among them, sign is the sign removal function, abs is the absolute value function, and min is the minimum value function; Will If β is set to 0, the formula of β is updated as follows:

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