Integrated assembly having a semiconductor oxide channel material and method of forming the integrated assembly

Abstract

Some embodiments include an integrated assembly having a gate material, an insulating material adjacent to the gate material, and a semiconductor oxide adjacent to the insulating material. The semiconductor oxide has a channel region proximate to the gate material and separated from the gate material by the insulating material. An electric field along the gate material induces carrier flow within the channel region, wherein the carrier flow is along a first direction. The semiconductor oxide includes grain boundaries having portions extending along a second direction, the second direction intersecting the first direction of the carrier flow. In some embodiments, the semiconductor oxide has grain boundaries extending along the first direction and offset from the insulating material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundaries. Some embodiments include a method of forming an integrated assembly.

Description

[0001] Related patent data

[0002] This patent claims priority to and the benefit of U.S. Provisional Application No. 62 / 770,081, filed on November 20, 2018, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Integrated assemblies having semiconductor oxide channel materials and methods of forming the integrated assemblies. Background Art

[0004] Semiconductor oxides (e.g., oxides including one or more of indium, gallium, zinc, and tin) may be incorporated into integrated assemblies. For example, the semiconductor oxide may be used to form the channel region of a transistor. The transistor may be used as an access device in a memory array, or for other applications.

[0005] It would be desirable to develop improved semiconducting oxides suitable for use in integrated assemblies, and it would be desirable to develop integrated components utilizing the improved semiconducting oxides. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 and 2 is a diagrammatic cross-sectional side view of a region of an example integrated assembly including an example transistor.

[0007] Figure 3 is a diagrammatic schematic illustration of a region of an example memory array.

[0008] Figures 4 to 6 is a diagrammatic cross-sectional side view of a region of an example integrated assembly including an example transistor.

[0009] Figure 7 and 8 is a diagrammatic cross-sectional top-down view along line AA showing Figure 6 An example embodiment configuration of an example integrated assembly. Figure 6 A cross-sectional side view along Figure 7 and 8 Line BB. Fig. 8A As an alternative Figure 8 An example of an assembly of FIG. 1 is a diagrammatic cross-sectional top-down view of a region of an integrated assembly.

[0010] Figures 9 to 14 For use in manufacturing Figure 1 A diagrammatic cross-sectional side view of a region of an example integrated assembly shown at an example process stage of an example method of an integrated assembly. Fig. 10A As an alternative Fig.10 An example of an assembly of a diagrammatic cross-sectional side view of a region of an integrated assembly.

[0011] Figures 15 to 21 For use in manufacturing Figure 2 A diagrammatic cross-sectional side view of a region of an example integrated assembly shown at an example process stage of an example method of an integrated assembly. DETAILED DESCRIPTION

[0012] Some embodiments include a semiconductor oxide in a channel region for a transistor. The transistor may include a conductive gate material and may include an insulating gate dielectric between the gate material and the semiconductor oxide. Operation of the transistor induces carrier flow (e.g., electron flow and / or hole migration) along the channel region. The carriers flow along a first direction. The semiconductor oxide may be configured to have grain boundaries extending along the first direction and separated from the gate dielectric by an intervening region; and the current flow may be entirely within the intervening region so that the current flow does not intersect the grain boundaries (i.e., is substantially parallel to the grain boundaries). Alternatively, the semiconductor oxide may be configured to have grain boundaries that intersect the current. Reference is made below to Figures 1 to 21 Example embodiments are described.

[0013] refer to Figure 1 , this figure illustrates a region of an integrated assembly 10 that includes an example memory cell 12 with an example access device (transistor) 14. Transistor 14 is over a digit line 16, which in turn is supported by a substrate 18.

[0014] Base 18 may include semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. Base 18 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including semiconductor material, including but not limited to integral semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, base 18 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

[0015] The base 18 includes a horizontally extending upper surface 17. In some embodiments, the upper surface 17 can be considered to extend along a first direction; wherein this first direction is shown to be along the axis 5.

[0016] A gap is provided between substrate 18 and digit line 16 to indicate that there may be additional material, electrical components, etc. provided between substrate 18 and digit line 16 .

[0017] Digital line 16 includes conductive material 19. Conductive material 19 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, digital line 16 may include one or both of tungsten and ruthenium, consist essentially of one or both of tungsten and ruthenium, or consist of one or both of tungsten and ruthenium.

[0018] The access device 14 includes a pillar 20 of a semiconductor oxide 22. The semiconductor oxide may include any suitable composition; and in some embodiments, may include one or more of indium, zinc, tin, and gallium. For example, the semiconductor oxide may include, consist essentially of, or consist of a composition having oxygen and indium, zinc, and gallium. Indium, zinc, and gallium may be considered metals within such a composition. The stoichiometric content of the composition may be expressed as a metal atomic percentage. Specifically, the content of each of the metals of the semiconductor oxide may be explicit in terms of the concentration of each of the metals of the semiconductor oxide relative to the total concentration of all metals of the semiconductor oxide; and the concentration of oxygen is ignored. In some example embodiments, the semiconductor oxide 22 may include indium with a metal atomic percentage in the range of about 14 to about 24, gallium with a metal atomic percentage in the range of about 37 to about 47, and zinc with a metal atomic percentage in the range of about 35 to about 45. In some example embodiments, the metal atomic percentage of indium may be in a range of about 16 to about 22, the metal atomic percentage of gallium may be in a range of about 39 to about 45, and the metal atomic percentage of zinc may be in a range of about 37 to about 43. It should be noted that even small changes in the stoichiometry of the semiconductor oxide may substantially alter the physical properties of the semiconductor oxide. Therefore, it may be advantageous to carefully control the metal content within the semiconductor oxide.

[0019] In the illustrated embodiment, the pillars 20 of semiconductor oxide extend vertically; or in other words, extend along a second axis 7 that is substantially orthogonal to the first axis 5. The term "substantially orthogonal" means orthogonal within reasonable tolerances of manufacturing and measurement.

[0020] The semiconductor oxide pillar 20 has a Figure 1 The cross-section of FIG. 2 shows opposite sidewall surfaces 23 and 25. The sidewall surface 23 may be referred to as a first sidewall surface, and the sidewall surface 25 may be referred to as a second sidewall surface.

[0021] The access device 14 includes an insulating material 24 along (i.e., adjacent to) and directly against the semiconductor oxide 22. The insulating material 24 may include any suitable composition. For example, in some embodiments, the insulating material 24 may include one or more high-k materials, where the term high-k means that the dielectric constant is greater than the dielectric constant of silicon dioxide. For example, the insulating material 24 may include one or more metal oxides; and in some embodiments may include, consist essentially of, or consist of one or more of aluminum oxide, hafnium dioxide, zirconium oxide, titanium oxide, etc. In some embodiments, the insulating material 24 may be referred to as an insulating gate oxide or a gate dielectric.

[0022] In the illustrated embodiment, the first region 26 of insulating material 24 is along the first sidewall surface 23 of the pillar 20 , and the second region 28 of insulating material 24 is along the second sidewall surface 25 of the pillar 20 .

[0023] The access device 14 also includes a gate material 30 along and directly against the insulating material 24. The gate material 30 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the gate material 30 may include one or both of tungsten and titanium nitride.

[0024] In the embodiment shown, the first region 32 of the gate material 30 is along the first region 26 of the insulating material 24, and the second region 34 of the gate material 30 is along the second region 28 of the insulating material. In some embodiments, the gate material 30 may be considered to be separated from the semiconductor oxide 22 by the insulating material 24. In some embodiments, there may be an additional composition between the semiconductor oxide and the gate material (e.g., an additional insulating composition), and thus, the gate material may be considered to be separated from the semiconductor oxide by at least the insulating material 24.

[0025] Gate material 30 is supported over insulating material 36. Insulating material 36 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide. In some embodiments, insulating material 36 may be omitted.

[0026] Pillar 20 of semiconductor oxide 22 extends between first conductive contact 37 and second conductive contact corresponding to digit line 16. First conductive contact 37 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, first conductive contact 37 may include one or both of tungsten and ruthenium, consist essentially of one or both of tungsten and ruthenium, or consist of one or both of tungsten and ruthenium.

[0027] Conductive contact 37 is coupled to charge storage device 38; in the embodiment shown, the charge storage device is a capacitor. In other embodiments, the charge storage device may have other configurations; and may, for example, include phase change materials, conductive bridging materials, etc.

[0028] Capacitor 38 has a node coupled to a reference voltage 40. Such a reference voltage may be ground, Vcc / 2, or any other suitable reference voltage.

[0029] The gate material 30 may be coupled to the word line WL1, and the digit line 16 may correspond to the digit line DL1. In operation, a voltage is applied to the word line WL1 which establishes an electric field along the first region 32 and the second region 34 of the gate material 30. Such an electric field induces carrier flow within a channel region composed of a semiconductor oxide, wherein such carrier flow extends between the digit line 16 and the conductive contact 37. The carrier flow is illustrated by arrows 42 and 44. The carrier flow extends along the vertical direction of the pillar 20 (i.e., along the direction of the second axis 7).

[0030] In the embodiment shown, the semiconductor oxide 22 is polycrystalline. Individual grains of polycrystalline material are bounded by grain boundaries. Grain boundaries are illustrated by dashed lines 46. The grains may have any suitable grain size; and in some embodiments, the average grain size may be in the range of about 1 nanometer (nm) to about 100 nm; in the range of about 1 nm to about 50 nm; in the range of about 20 nm to about 25 nm, etc. Any suitable method may be used to determine the average grain size. The crystallinity may be cubic crystallinity (i.e., may have a cubic unit cell, may include a cubic crystal system). In some embodiments, individual crystalline grains may be referred to as being dominated by cubic crystallinity, which means that the crystallinity is substantially cubic and may or may not be completely cubic throughout the grain. The term "substantially cubic" means cubic within a reasonable tolerance. In some embodiments, a polycrystalline material may be referred to as having primarily cubic crystallinity, which means that greater than 50 volume percent of the polycrystalline material has cubic crystallinity (or at least substantially cubic crystallinity). In some embodiments, the content of cubic crystallinity (or substantially cubic crystallinity) within the polycrystalline material may be greater than 70 volume percent, greater than 90 volume percent, greater than 95 volume percent, etc.

[0031] The direction of carrier flow (indicated by arrows 42 and 44) ​​intersects the grain boundaries of the polycrystalline material 22. In other words, one or more of the grain boundaries have a portion (e.g., the illustrated portion 47) extending in a direction intersecting the direction of current flow. In some embodiments, the current flow direction may be referred to as a first direction, and the grain boundary direction may be referred to as a second direction. An advantage of having carriers flow through one or more of the grain boundaries of the semiconductor oxide 22 may be that this enables carrier flow to be modified by adjusting the number of grain boundaries per unit length of the semiconductor oxide. Thus, carrier flow may be customized for a particular application by tailoring the grain size of the semiconductor oxide 22.

[0032] refer to Figure 2 , this figure illustrates a region of an integrated assembly 10a that includes another example memory cell 12a having an example access device (transistor) 14a. Where appropriate, the same reference numerals as described above in describing Figure 1 The same reference numerals as used in describing assembly 10a are used to describe assembly 10a.

[0033] Transistor 14 a is over digit line 16 , which in turn is supported by substrate 18 .

[0034] The base 18 comprises a horizontally extending upper surface 17 , wherein the upper surface extends along a first direction of the axis 5 .

[0035] The access device 14a includes a pillar 20a of a semiconductor oxide 22a. The semiconductor oxide may include any suitable composition; and in some embodiments, may include one or more of indium, zinc, tin, and gallium. For example, the semiconductor oxide may include, consist essentially of, or consist of a composition having oxygen and indium, zinc, and gallium. In some example embodiments, the semiconductor oxide 22a may include indium having a metal atomic percentage in a range of about 16 to about 26, gallium having a metal atomic percentage in a range of about 45 to about 55, and zinc having a metal atomic percentage in a range of about 24 to about 34. In some example embodiments, the metal atomic percentage of indium may be in a range of about 18 to about 24, the metal atomic percentage of gallium may be in a range of about 47 to about 53, and the metal atomic percentage of zinc may be in a range of about 26 to about 32.

[0036] In the illustrated embodiment, the pillars 20 a of semiconductor oxide extend vertically; or in other words, along an axis 7 that is substantially orthogonal to the axis 5 .

[0037] The semiconductor oxide pillar 20a has a Figure 2 The cross section has opposite first and second side wall surfaces 23 and 25 .

[0038] Access device 14a includes insulating material 24 along and directly against semiconductor oxide 22a. A first region 26 of insulating material 24 is along first sidewall surface 23 of pillar 20a, and a second region 28 of insulating material 24 is along second sidewall surface 25 of pillar 20a.

[0039] The access device 14 also includes a gate material 30 along and directly against the insulating material 24. A first region 32 of the gate material 30 is along the first region 26 of the insulating material 24, and a second region 34 of the gate material 30 is along the second region 28 of the insulating material. In some embodiments, the gate material 30 can be considered to be separated from the semiconductor oxide 22 by the insulating material 24.

[0040] Gate material 30 is supported over insulating material 36 .

[0041] Pillar 20 a of semiconductor oxide 22 a extends between first conductive contact 37 and a second conductive contact corresponding to digit line 16 .

[0042] Conductive contact 37 is coupled to a charge storage device 38, which in the illustrated embodiment is a capacitor.

[0043] The gate material 30 is coupled to the word line WL1, and the digit line 16 corresponds to the digit line DL1. In operation, a voltage is applied to the word line WL1 which establishes an electric field along the first region 32 and the second region 34 of the gate material 30. Such an electric field induces carrier flow within the channel region composed of the semiconductor oxide 22a, wherein such carrier flow extends between the digit line 16 and the conductive contact 37. The carrier flow is illustrated by arrows 42 and 44. The carrier flow extends in the vertical direction of the pillar 20a.

[0044] In the illustrated embodiment, the semiconductor oxide 22a is configured such that the grain boundary 46a extends in the vertical direction of the axis 7 and traverses the entire length of the semiconductor oxide 22a from the digit line 16 to the conductive contact 37. The grain boundary 46a is offset from the first region 26 of the insulating material 24 by the first intervening region 50 of the semiconductor oxide 22a, and is offset from the second region 28 of the insulating material 24 by the second intervening region 52 of the semiconductor oxide 22a. Figure 2 In the embodiment of FIG. 4 , the grain boundary 46a is shown as wavy. In other embodiments, the grain boundary may be substantially straight, or may have other configurations; but in any case, will extend substantially vertically along the pillar 20a. The semiconductor oxide 22a may have cubic crystallinity.

[0045] The carrier flow within the semiconductor oxide 22a (indicated by arrows 42 and 44) ​​is within the intervening regions 50 and 52 and is primarily along (i.e., substantially parallel to) the vertical direction of the grain boundary 46a; and in some embodiments, does not intersect the grain boundary 46a. The term "substantially parallel" means along the same general direction as the grain boundary, and in some embodiments, may be parallel within a reasonable tolerance of measurement. The intervening regions 50 and 52 may be very uniform in terms of physical and chemical properties. An advantage of having the carrier flow through the intervening regions 50 and 52 of the semiconductor oxide 22a may be that this enables the carrier flow to be uniform across a large number of substantially identical access devices 14a.

[0046] In some embodiments, Figure 1 and 2 Memory cells 12 and 12a of can be representative memory cells incorporated into a memory array. All memory cells within a given memory array can be substantially identical to each other; where the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement. Figure 3A region of an example memory array 54 is shown. The memory array includes word lines WL1 and WL2, and digit lines DL1 and DL2. The memory array also includes a plurality of memory cells 12 or 12a. The word lines can be viewed as extending along the rows of the memory array, and the digit lines can be viewed as extending along the columns of the memory array. Each of the memory cells is uniquely addressed using one of the word lines and one of the digit lines. The illustrated memory array is a dynamic random access memory (DRAM) array. In other embodiments, the above reference Figure 1 and 2 Transistors 14 and 14a of the type described may be used in other types of memory arrays. Additionally or alternatively, the transistors may be used in other circuit systems; for example, logic, sensors, etc.

[0047] Figure 1 and 2 The transistors 14 and 14a are shown as having vertically extending pillars of semiconductor oxide, and having carrier flow extending vertically along such pillars. In other embodiments, similar transistors may have other configurations. For example, Figure 4 and 5 A transistor configured for horizontal carrier flow is shown.

[0048] refer to Figure 4 , a region of integrated assembly 10b is shown to include transistor 14b. Transistor 14b includes the transistor 14b described above with reference to Figure 1 Semiconductor oxide 22 of the type described. Such semiconductor oxide extends horizontally and, in particular, in the same direction as the horizontally extending upper surface 17 of the substrate 18, ie in the direction of the axis 5.

[0049] Semiconductor oxide 22 is supported by insulating material 56. Such insulating material may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of one or both of silicon dioxide and silicon nitride.

[0050] Semiconductor oxide 22 extends between first contact 58 and second contact 60. First contact 58 and second contact 60 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0051] An insulating material 24 is over the semiconductor oxide 22 , and a gate material 30 is over the insulating material 24 .

[0052] In operation, the electric field along gate material 30 induces carrier flow within the channel region of semiconductor oxide 22. The carrier flow is represented by arrows 42, and in the illustrated embodiment extends substantially parallel to horizontally extending upper surface 17 of substrate 18 (ie, along axis 5).

[0053] refer to Figure 5 , a region of integrated assembly 10c is shown to include transistor 14c. Transistor 14c includes the transistor 14c described above with reference to Figure 1 Semiconductor oxide 22a of the type described. Such semiconductor oxide extends horizontally and, in particular, in the same direction as the horizontally extending upper surface 17 of the substrate 18 (ie, in the direction of the axis 5).

[0054] The semiconductor oxide 22 a is supported by the insulating material 56 and extends between the first contact 58 and the second contact 60 .

[0055] The insulating material 24 is above and below the semiconductor oxide 22a, and the gate material 30 is above and below the insulating material 24. Figure 5 In the embodiment of FIG. 1 (i.e., assembly 10c), semiconductor oxide 22a is vertically located between the upper and lower regions of material 30. This is consistent with Figure 4 In contrast to the embodiment of (i.e., assembly 10b), which has only a single region of gate material 30 (specifically, a region of gate material 30 above the semiconductor oxide). In some embodiments, similar to Figure 4 In some embodiments, the semiconductor oxide 22a of the assembly 10c may be adjacent to only a single region of the gate material 30; and in some embodiments, similar to Figure 5 An embodiment of Figure 4 The gate dielectric material (gate oxide material) 22 of (assembly 10b) may be disposed between the upper and lower regions of the gate material.

[0056] Still refer to Figure 5 In the embodiment shown, the electric field along the gate material 30 induces carrier flow within the channel region of the semiconductor oxide 22a. The carrier flow is represented by arrows 42 and 44, and in the embodiment shown extends substantially parallel to the horizontally extending upper surface 17 of the substrate 18 (i.e., extends along the axis 5).

[0057] It should be noted that the above reference Figure 2 The depicted embodiment shows a single vertically extending grain boundary along the approximate center of the semiconductor oxide pillar 20a. In some embodiments, such a grain boundary is generated by recrystallization within the semiconductor oxide 22a and propagates inward from the sidewall surfaces 23 and 25 of the pillar 20a. Thus, a grain boundary similar to Figure 2, but in the structure, the grain boundaries extending inward from surfaces 23 and 25 have not yet merged into a single grain boundary extending downward along the center of pillar 20a. Alternatively, there may be a pair of grain boundaries extending vertically along pillar 20a, such as Figure 6 Specifically, Figure 6 An integrated assembly 10d is shown, which includes Figure 2 However, instead of including two grain boundaries 46b and 46c extending vertically along the pillar 20a, the transistor 14d includes two grain boundaries 46b and 46c extending vertically along the pillar 20a. Figure 2 4. Intermediate regions 50 and 52 are between surface 23 and grain boundary 46b and between surface 25 and grain boundary 46c, respectively. Such intermediary regions include the channel regions of the transistor, and the carrier flow (indicated by arrows 42 and 44) ​​extends vertically along such channel regions.

[0058] Figure 7 and 8 Show along Figure 6 A pair of top-down views of line AA of FIG. 14A to indicate an alternative configuration of transistor 14d. Note that Figure 6 Side view along Figure 7 and 8 Line BB.

[0059] refer to Figure 7 , gate material 30 and insulating material 24 are along two opposite sides of pillar 20a of semiconductor oxide 22a, and insulating material 62 is along the other two opposite sides of pillar 20a. Insulating material 62 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of one or both of silicon dioxide and silicon nitride. Grain boundary regions 46b and 46c are parallel to opposite sidewall surfaces 23 and 25.

[0060] refer to Figure 8 , in a gate-around configuration, the insulating material 24 and the gate material 30 completely surround the pillar 20a. Grain boundaries 46b and 46c are part of a continuous grain boundary structure within the semiconductor oxide 22a. In the embodiment shown, the grain boundary structure is polygonal (specifically, substantially square) and conformal to the configuration of the gate material 30 extending around the pillar 20a. It should be noted that there may be multiple grain boundaries or at least one grain boundary; in some embodiments, the crystallized grains may be considered columnar; and the crystallized grains may or may not extend all the way down to the underlying "substrate" corresponding to the conductive material 19.

[0061] Fig. 8A Display Alternative Figure 8 14e and shows the region of transistor 14e. Grain boundaries 46 are vertically oriented, similar to Figure 6 and 8 The boundaries 46b / 46c of the semiconductor oxide 22a and along the columnar grain structure 43. In some embodiments, there may be a plurality of vertically oriented grain boundaries 46 extending within the semiconductor oxide 22a, and in some embodiments, there may be at least one vertically oriented grain boundary 46 extending within the semiconductor oxide 22a.

[0062] The structures described above may be formed using any suitable method. Figures 9 to 21 Describes an instance method; where Figures 9 to 14 Description used to form Figure 1 An example method of transistor 14, and wherein Figures 15 to 21 Description used to form Figure 2 An example method of transistor 14a. Figures 9 to 21 The substrate 18 is not shown in order to simplify the drawing.

[0063] refer to Fig. 9 , Figure 1 The manufacture of the integrated assembly 10 begins by providing the conductive material 19 of the component 16. In some embodiments, the conductive material 19 can have an upper surface that includes, consists essentially of, or consists of one or both of tungsten and ruthenium. The remainder of the conductive material 19 can be the same composition as this upper surface, or can be a different composition relative to this upper surface.

[0064] refer to Fig.10 , the semiconductor oxide 22 is deposited over the conductive material 19; and in the embodiment shown, directly onto the conductive material 19. The semiconductor oxide 22 may be deposited under any suitable conditions utilizing any suitable process. In some embodiments, the deposition may utilize one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In an example embodiment, the deposition of the semiconductor oxide 22 may utilize PVD, and may be performed in a chamber utilizing an environment within the chamber having a temperature in a range of about 20° C. to about 500° C. and a pressure in a range of about 1 mTorr to about 9 mTorr. In some embodiments, the temperature of the environment may be in a range of about 80° C. to about 150° C.

[0065] Fig.10 The semiconductor oxide 22 may include the Figure 1 Any of the compositions described. In some embodiments, the semiconductor oxide may include indium, gallium, and zinc. In such embodiments, physical vapor deposition of the semiconductor oxide may utilize multiple targets to achieve the desired concentrations of indium, gallium, and zinc; or may utilize a single target with the desired concentrations.

[0066] The deposited semiconductor oxide 22 is polycrystalline (with grain boundaries illustrated by dashed lines 46 ).

[0067] Fig. 10A Display Alternative Fig.10 The integrated assembly 10e of the assembly 10. The assembly 10e has Fig. 8A The vertically oriented grain boundaries of the semiconductor oxide 22 are formed with a columnar grain structure 43. An amorphous region 70 of the semiconductor oxide 22 may exist below the grains 43. Such an amorphous region may have any suitable thickness; for example, about The grain 43 is along the Fig. 10A The grain 43 grows in the direction of the grain growth indicated by the arrow 73; and can be grown by annealing during and / or after the deposition of the semiconductor oxide 22. Region 71 may correspond to a crystal nucleation region. In some embodiments, the grain 43 can be considered to be produced by double-sided growth, where the thickness increases along the growth direction 73.

[0068] Fig.11 Shown in Fig.10 The semiconductor oxide 22 is patterned into a vertically extending structure corresponding to the pillars 20. Such a structure has a vertical extension along Fig.11 The cross-section of the crystal structure may include opposite sidewall surfaces 23 and 25. In some embodiments, the grain structure may include vertical columns (e.g., Fig. 10A columnar grains similar to columnar grains).

[0069] refer to Fig.12 Insulating material 24 is formed along opposite sidewalls 23 and 25 of pillar 20 and over the pillar. Insulating material 24 includes a first region 26 along sidewall surface 23 and a second region 28 along sidewall surface 25.

[0070] Insulating material 36 is formed over insulating material 24; and gate material 30 is formed over insulating material 36 and pillars 20. Gate material 30 includes first region 32 along first region 26 of insulating material 24, and includes second region 34 along second region 28 of insulating material 24. In some embodiments, insulating material 36 may be omitted.

[0071] refer to Fig.13 , materials 24, 36, and 30 are patterned. Patterning may include any suitable combination of masking and etching. Such patterning removes materials 30 and 24 from above upper surface 63 of pillar 20. Fig.13The assembly 10 may be disposed within a chamber and subjected to annealing while the upper surface 63 is exposed to a desired environment. For example, in some embodiments, the upper surface 63 may be exposed to an oxidizing environment (e.g., an environment including one or both of O2 and O3) to replenish oxygen that may have been lost from the semiconductor oxide 22 during patterning of the materials 24, 30, and 36. The annealing may be performed at any suitable temperature (e.g., a temperature of at least about 400° C.) for any suitable duration (e.g., a duration greater than about 30 minutes). The temperature may be the temperature of the environment within the chamber during the annealing, may be the temperature of a chuck or other structure within the chamber that holds the assembly 10, and / or may be the temperature of the pillars 20 of the semiconductor oxide 22. Annealing may enable the chemical components within the semiconductor oxide 22 to be redistributed so that the composition of the semiconductor oxide 22 becomes more uniform than before the annealing, may enable the grain size to be adjusted within the semiconductor oxide 22, and the like.

[0072] refer to Fig.14 , a conductive contact 37 is formed above the upper surface 63 of the pillar 20 to complete the manufacture of the transistor 14, wherein such a transistor is similar to the above reference Figure 1 Any suitable process may be used to form and pattern the conductive contact 37. In some embodiments, the conductive material 37 is Fig.10 The etched nanorod is deposited over material 22 at a processing stage of and then patterned together with material 22 .

[0073] refer to Fig.15 , Figure 2 The manufacture of the integrated assembly 10a begins by providing the conductive material 19 of the component 16. In some embodiments, the conductive material 19 can have an upper surface that includes, consists essentially of, or consists of one or both of tungsten and ruthenium. The remainder of the conductive material 19 can be the same composition as this upper surface, or can be a different composition relative to this upper surface.

[0074] refer to Fig.16 , the semiconductor oxide 22a is deposited over the conductive material 19; and in the embodiment shown, directly onto the conductive material 19. The semiconductor oxide 22a may be deposited under any suitable conditions using any suitable process; and in some embodiments, the semiconductor oxide may utilize one or more of ALD, CVD, and PVD. In an example embodiment, the deposition of the semiconductor oxide 22a may utilize PVD, and may be performed in a chamber using an environment in the chamber having a temperature in the range of about 20° C. to about 500° C. and a pressure in the range of about 1 mTorr to about 9 mTorr. In some embodiments, the temperature of the environment may be in the range of about 80° C. to about 150° C.

[0075] Fig.16 The semiconductor oxide 22a may include the Figure 2 Any of the compositions described. In some embodiments, the semiconductor oxide may include indium, gallium, and zinc. In such embodiments, physical vapor deposition of the semiconductor oxide may utilize multiple targets to achieve the desired concentrations of indium, gallium, and zinc; or may utilize a single target with the desired concentrations.

[0076] The deposited semiconductor oxide 22a may or may not be crystalline; and in some embodiments may be polycrystalline and / or amorphous. Fig.16 The processing steps show the grain boundaries.

[0077] refer to Fig.17 , the semiconductor oxide 22a is patterned into a vertically extending structure corresponding to the pillar 20a. Such a structure has a Fig.17 The opposite side wall surfaces 23 and 25 of the cross section.

[0078] refer to Fig.18 Insulating material 24 is formed along opposite sidewalls 23 and 25 of pillar 20a and over the pillar. Insulating material 24 includes a first region 26 along sidewall surface 23 and a second region 28 along sidewall surface 25.

[0079] Insulating material 36 is formed over insulating material 24; and gate material 30 is formed over insulating material 36 and pillar 20a. Gate material 30 includes first region 32 along first region 26 of insulating material 24, and includes second region 34 along second region 28 of insulating material 24.

[0080] refer to Fig.19 , materials 24, 36, and 30 are patterned. Patterning may include any suitable combination of masking and etching. Such patterning removes materials 30 and 24 from above upper surface 65 of pillar 20a. Fig.19 The assembly 10a of can be disposed in a chamber and subjected to annealing while the upper surface 65 (i.e., the top portion 65) is exposed to a desired environment. For example, in some embodiments, the upper surface 65 can be exposed to an oxidizing environment (e.g., an environment including one or both of O2 and O3) to replenish oxygen that may have been lost from the semiconductor oxide 22 during the patterning of the materials 24, 30, and 36. In other embodiments, the upper surface 65 can be exposed to a reducing environment (e.g., an environment including a reducing agent; such as an environment including H2). In other embodiments, the environment can be composed of a gas that is inert with respect to reaction with the exposed top portion of the semiconductor oxide 22a (e.g., the environment can be composed of one or both of argon and N2).

[0081] Annealing may be performed at any suitable temperature (e.g., a temperature of at least about 400° C.) for any suitable duration (e.g., a duration greater than about 30 minutes). The temperature may be the temperature of the environment within the chamber during the annealing, may be the temperature of a chuck or other structure within the chamber holding the assembly 10a, and / or may be the temperature of the pillars 20a of the semiconductor oxide 22a. In some embodiments, annealing may be performed while the temperature of the semiconductor oxide is maintained in the range of about 400° C. to about 600° C. for a duration in the range of about 30 minutes to about one day; for example, for a duration of about 30 minutes to about 10 hours.

[0082] Annealing may cause the semiconductor oxide 22a to crystallize and / or recrystallize to form at least one grain boundary 46a (or "seam") extending vertically through the semiconductor oxide 22a, such as Fig. 20 1. In the illustrated embodiment, grain boundary 46a traverses the entire length of vertically extending pillar 20a from top surface 65 to conductive material 19. Grain boundary is offset from first surface 23 and second surface 25 of pillar 20a by intervening regions 50 and 52. In the illustrated embodiment, such intervening regions have approximately the same width as each other along the horizontal direction. In other embodiments, one of the intervening regions may be wider than the other.

[0083] In understanding some embodiments described herein, it may be useful to provide a brief description of possible mechanisms. However, the appended claims are not limited to any particular mechanism unless such mechanisms (if any) are explicitly stated in such claims. It is believed that the vertically extending grain boundaries 46 may be produced by recrystallization of semiconductor oxide 22a, wherein such recrystallization propagates inwardly toward the center of pillar 20a from the surface of adjacent insulating material 24. Grain boundaries 46a are clearly visible in the cross-section of the structure formed according to the processing described herein. Although there may be other smaller grain boundaries, this is far less dominant than grain boundaries 46a. In some embodiments, grain boundaries 46a may be referred to as primary grain boundaries to indicate that in the sense of the presence of other grain boundaries, such grain boundaries are far less dominant than grain boundaries 46a.

[0084] refer to Fig.21 , a conductive contact 37 is formed above the upper surface 65 of the pillar 20a to complete the manufacture of the transistor 14a, wherein such a transistor is similar to the above reference Figure 2 The transistors described are the same.The conductive contacts 37 may be formed and patterned using any suitable process.

[0085] The assemblies and structures discussed above may be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0086] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed using any suitable method now known or to be developed including, for example, ALD, CVD, PVD, etc.

[0087] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used within this disclosure to provide language variation to simplify the premise basis within the appended claims, rather than to indicate any significant chemical or electrical differences.

[0088] The specific orientations of the various embodiments in the figures are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The descriptions and appended claims provided herein relate to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0089] Unless otherwise specified, the cross-sectional views of the accompanying drawings show only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawing.

[0090] When a structure is referred to as being "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure, or there may also be intervening structures. Conversely, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0091] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend substantially orthogonally relative to an upper surface of the base.

[0092] Some embodiments include an integrated assembly having a gate material, an insulating material along the gate material, and a semiconductor oxide along (adjacent to) the insulating material. The semiconductor oxide has a channel region proximate to the gate material and separated from the gate material by at least the insulating material. Carrier flow within the channel region is induced in response to an electric field along the gate material, wherein the carrier flow is along a first direction. The semiconductor oxide is polycrystalline, wherein individual grains of the polycrystalline semiconductor oxide are peripherally bounded by grain boundaries. At least one of the grain boundaries has a portion extending along a second direction, wherein the second direction intersects the first direction of carrier flow.

[0093] Some embodiments include an integrated assembly having a gate material, an insulating material along (adjacent to) the gate material, and a semiconductor oxide along the insulating material. The semiconductor oxide has a channel region proximate to the gate material and separated from the gate material by at least the insulating material. Carrier flow within the channel region is induced in response to an electric field along the gate material, wherein the carrier flow is along a first direction. The semiconductor oxide has at least one grain boundary extending along the first direction and offset from the insulating material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the at least one grain boundary.

[0094] Some embodiments include an integrated assembly having a semiconductor oxide extending between a first conductive contact and a second conductive contact along a vertical direction. The semiconductor oxide has a first sidewall surface and a second sidewall surface opposite each other along a cross section. A first region of insulating material is along the first sidewall surface, and a second region of insulating material is along the second sidewall surface. A first region of gate material is along the first region of insulating material and is separated from the first sidewall surface by at least the first region of insulating material, and a second region of gate material is along the second region of insulating material and is separated from the second sidewall surface by the second region of insulating material. An electric field along the first region and the second region of gate material induces carrier flow within the semiconductor oxide, wherein the carrier flow is along a first direction corresponding to the vertical direction of the semiconductor oxide. The semiconductor oxide is polycrystalline. Individual grains of the polycrystalline semiconductor oxide are peripherally bounded by grain boundaries. At least one of the grain boundaries has a portion extending along a second direction, wherein the second direction intersects the first direction of carrier flow.

[0095] Some embodiments include an integrated assembly having a semiconductor oxide extending between a first conductive contact and a second conductive contact along a vertical direction. The semiconductor oxide has a first sidewall surface and a second sidewall surface opposite along a cross section. A first region of insulating material is along the first sidewall surface, and a second region of insulating material is along the second sidewall surface. A first region of gate material is along the first region of insulating material and is spaced from the first sidewall surface at least by the first region of insulating material, and a second region of gate material is along the second region of insulating material and is spaced from the second sidewall surface by the second region of insulating material. A grain boundary is within the semiconductor oxide and extends along a vertical direction. The grain boundary traverses the entire length of the semiconductor oxide from the first contact to the second contact. The grain boundary is offset from the first region of insulating material by a first intervening portion of the semiconductor oxide, and is offset from the second region of insulating material by a second intervening portion of the semiconductor oxide. Carrier flow within the semiconductor oxide is induced in response to an electric field along the first region and the second region of the gate material, wherein the carrier flow is along a vertical direction of the semiconductor oxide. The carrier flow within the semiconductor oxide is within the intervening region and is substantially parallel to the grain boundary.

[0096] Some embodiments include a method of forming an integrated assembly. A semiconductor oxide is deposited over a conductive material. The semiconductor oxide includes indium, gallium, and zinc. The deposition is physical vapor deposition and is performed in a chamber using an environment in the chamber having a temperature in a range of about 20° C. to about 500° C. and a pressure in a range of about 1 mTorr to about 9 mTorr. The deposited semiconductor oxide is polycrystalline. The deposited semiconductor oxide is patterned into a vertically extending structure. The vertically extending structure has a first sidewall surface and a second sidewall surface opposite to each other along a cross section. An insulating material is formed along the first sidewall surface and the second sidewall surface opposite to each other. A first region of the insulating material is along the first sidewall surface, and a second region of the insulating material is along the second sidewall surface. A gate material is formed along the insulating material. A first region of the gate material is along the first region of the insulating material, and a second region of the gate material is along the second region of the insulating material. The semiconductor oxide, the first and second regions of the insulating material, and the first and second regions of the gate material together form a transistor. The transistor is configured such that an electric field along the first and second regions of the gate material induces carrier flow within the semiconductor oxide, wherein the carrier flow is along a first direction corresponding to a vertical direction of the semiconductor oxide. Individual grains of the polycrystalline semiconductor oxide are peripherally bounded by grain boundaries. At least one of the grain boundaries has a portion extending along a second direction, wherein the second direction intersects the first direction of the carrier flow.

[0097] Some embodiments include a method of forming an integrated assembly. A semiconductor oxide is deposited over a support material. The semiconductor oxide includes indium, gallium, and zinc. The deposited semiconductor oxide is patterned into a vertically extending structure. The vertically extending structure has a first sidewall surface and a second sidewall surface opposite along a cross section. An insulating material is formed along the first sidewall surface and the second sidewall surface opposite. A first region of the insulating material is along the first sidewall surface, and a second region of the insulating material is along the second sidewall surface. A gate material is formed along the insulating material. A first region of the gate material is along the first region of the insulating material, and a second region of the gate material is along the second region of the insulating material. After forming the insulating material, the semiconductor oxide is annealed under conditions where the temperature of the semiconductor oxide is maintained in a range of about 400° C. to about 600° C. for a duration of at least about 30 minutes to less than or equal to about 1 day. After annealing, grain boundaries extend within the semiconductor oxide and along a vertical direction. The grain boundaries traverse the entire length of the semiconductor oxide from the upper surface of the semiconductor oxide to the lower surface of the semiconductor oxide. The grain boundary is offset from the first region of the insulating material by a first intervening portion of the semiconductor oxide, and is offset from the second region of the insulating material by a second intervening portion of the semiconductor oxide. The semiconductor oxide, the first and second regions of the insulating material, and the first and second regions of the gate material together form a transistor. The transistor is configured such that an electric field along the first and second regions of the gate material induces carrier flow within the semiconductor oxide, wherein the carrier flow is along a first direction corresponding to a vertical direction of the semiconductor oxide. The carrier flow within the semiconductor oxide is within the first and second intervening regions and is substantially parallel to the grain boundary.

[0098] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: Gate material; an insulating material adjacent to the gate material; as well as a polycrystalline semiconductor oxide adjacent to the insulating material; The semiconductor oxide has relative sidewall surfaces; the semiconductor oxide is in direct contact with the digital line and has a channel region close to the gate material and separated from the gate material by at least the insulating material; wherein carriers in the channel region flow along a first direction, wherein individual grains of the polycrystalline semiconductor oxide are peripherally delimited by grain boundaries; at least one of the grain boundaries has a portion extending along a second direction, wherein the second direction intersects the first direction of the carrier flow.

2. The integrated assembly of claim 1, wherein the individual grains are dominated by cubic crystallinity.

3. The integrated assembly of claim 1, wherein the semiconductor oxide has primarily cubic crystallinity.

4. The integrated assembly of claim 1, wherein the gate material, insulating material, and semiconductor oxide are supported by a semiconductor substrate having a horizontally extending upper surface, and wherein the carrier flow extends substantially parallel relative to the horizontally extending upper surface.

5. The integrated assembly of claim 1, wherein the gate material, insulating material, and semiconductor oxide are supported by a semiconductor substrate having a horizontally extending upper surface, and wherein the carrier flow extends substantially orthogonally relative to the horizontally extending upper surface.

6. The integrated assembly of claim 1, wherein the semiconductor oxide comprises one or more of indium, zinc, tin, and gallium.

7. The integrated assembly of claim 1 wherein the semiconductor oxide comprises indium, zinc, and gallium.

8. The integrated assembly of claim 7, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 14 to 24; said metal atomic percentage of said gallium is in the range of 37 to 47; and The metal atomic percentage of the zinc is in the range of 35 to 45.

9. The integrated assembly of claim 7, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 16 to 22; said metal atomic percentage of said gallium is in the range of 39 to 45; and The metal atomic percentage of the zinc is in the range of 37 to 43.

10. The integrated assembly of claim 7, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is 19; The metal atomic percentage of the gallium is 42; and The metal atomic percentage of the zinc is 40.

11. The integrated assembly of claim 1, wherein the insulating material is a high-k material.

12. The integrated assembly of claim 1, wherein the insulating material is a metal oxide.

13. The integrated assembly of claim 1, wherein the insulating material comprises one or more of aluminum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

14. An integrated assembly comprising: Gate material; an insulating material adjacent to the gate material; as well as a semiconductor oxide adjacent to the insulating material; The semiconductor oxide has relative sidewall surfaces; the semiconductor oxide is in direct contact with the digital line and has a channel region close to the gate material and separated from the gate material by at least the insulating material; wherein carriers in the channel region flow along a first direction; the semiconductor oxide has at least one grain boundary, the at least one grain boundary extending along the first direction and offset from the insulating material through an intermediate region of the semiconductor oxide; the carriers flow in the intermediate region and substantially parallel to the at least one grain boundary.

15. The integrated assembly of claim 14, wherein individual grains of the semiconductor oxide are dominated by cubic crystallinity.

16. The integrated assembly of claim 14, wherein the semiconductor oxide has primarily cubic crystallinity.

17. The integrated assembly of claim 14, wherein the gate material, insulating material, and semiconductor oxide are supported by a semiconductor substrate having a horizontally extending upper surface, and wherein the carrier flow extends substantially parallel relative to the horizontally extending upper surface.

18. The integrated assembly of claim 14, wherein the gate material, insulating material, and semiconductor oxide are supported by a semiconductor substrate having a horizontally extending upper surface, and wherein the carrier flow extends substantially orthogonally relative to the horizontally extending upper surface.

19. The integrated assembly of claim 14, wherein the semiconductor oxide comprises one or more of indium, zinc, tin, and gallium.

20. The integrated assembly of claim 14, wherein the semiconductor oxide comprises indium, zinc, and gallium.

21. The integrated assembly of claim 20, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 16 to 26; said metal atomic percentage of said gallium is in the range of 45 to 55; and The metal atomic percent of the zinc is in the range of 24 to 34.

22. The integrated assembly of claim 20, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 18 to 24; said metal atomic percentage of said gallium is in the range of 47 to 53; and The metal atomic percent of the zinc is in the range of 26 to 32.

23. The integrated assembly of claim 20, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is 21; The metal atomic percentage of the gallium is 50; and The metal atomic percentage of the zinc was 29.

24. An integrated assembly comprising: a semiconductor oxide extending in a vertical direction between the first conductive contact and the second conductive contact; The semiconductor oxide has first and second sidewall surfaces that are opposite along a cross section; a first region of insulating material adjacent to the first sidewall surface, and a second region of the insulating material adjacent to the second sidewall surface; a first region of gate material adjacent to the first region of insulating material and spaced apart from the first sidewall surface by at least the first region of insulating material, and a second region of gate material along the second region of insulating material and spaced apart from the second sidewall surface by at least the second region of insulating material; and wherein carrier flow within the semiconductor oxide is induced in response to an electric field along the first and second regions of the gate material, wherein the carrier flow is along a first direction corresponding to the vertical direction of the semiconductor oxide; wherein the semiconductor oxide is polycrystalline; wherein individual grains of the polycrystalline semiconductor oxide are peripherally bounded by grain boundaries; and wherein at least one of the grain boundaries has a portion extending along a second direction, wherein the second direction intersects the first direction of the carrier flow.

25. The integrated assembly of claim 24, wherein the individual grains are predominantly cubic in crystallinity.

26. The integrated assembly of claim 24, wherein the semiconductor oxide has primarily cubic crystallinity.

27. The integrated assembly of claim 24, wherein the semiconductor oxide comprises indium, zinc, and gallium.

28. The integrated assembly of claim 27, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 16 to 22; said metal atomic percentage of said gallium is in the range of 39 to 45; and The metal atomic percentage of the zinc is in the range of 37 to 43.

29. The integrated assembly of claim 27, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is 19; The metal atomic percentage of the gallium is 42; and The metal atomic percentage of the zinc is 40.

30. The integrated assembly of claim 24, comprising a digit line coupled to one of the first conductive contact and the second conductive contact, and comprising a charge storage device coupled to the other of the first conductive contact and the second conductive contact.

31. An integrated assembly according to claim 30, wherein: The semiconductor oxide, the first region and the second region of the insulating material; and the first region and the second region of the gate material together form an access device; The access device and the charge storage device together form a memory device; and The memory device is one of many substantially identical memory devices within a memory array.

32. An integrated assembly comprising: a semiconductor oxide extending in a vertical direction between the first conductive contact and the second conductive contact; The semiconductor oxide has first and second sidewall surfaces that are opposite along a cross section; a first region of insulating material adjacent to the first sidewall surface, and a second region of the insulating material adjacent to the second sidewall surface; a first region of gate material adjacent to the first region of insulating material and spaced apart from the first sidewall surface by at least the first region of insulating material, and a second region of gate material adjacent to the second region of insulating material and spaced apart from the second sidewall surface by at least the second region of insulating material; a grain boundary within the semiconductor oxide and extending along the vertical direction; the grain boundary traverses the entire length of the semiconductor oxide from the first conductive contact to the second conductive contact; the grain boundary is offset from the first region of the insulating material through a first intervening region of the semiconductor oxide and is offset from the second region of the insulating material through a second intervening region of the semiconductor oxide; and wherein carrier flow within the semiconductor oxide is induced in response to an electric field along the first region and the second region of the gate material, wherein the carrier flow is along the vertical direction of the semiconductor oxide; and wherein the carrier flow within the semiconductor oxide is within the first intervening region and the second intervening region and is substantially parallel to the grain boundary.

33. The integrated assembly of claim 32, wherein individual grains of the semiconductor oxide are predominantly cubic in crystallinity.

34. The integrated assembly of claim 32, wherein the semiconductor oxide has primarily cubic crystallinity.

35. The integrated assembly of claim 32, comprising a digit line coupled to one of the first conductive contact and the second conductive contact, and comprising a charge storage device coupled to the other of the first conductive contact and the second conductive contact.

36. An integrated assembly according to claim 35, wherein: The semiconductor oxide, the first region and the second region of the insulating material; and the first region and the second region of the gate material together form an access device; The access device and the charge storage device together form a memory device; and The memory device is one of many substantially identical memory devices within a memory array.

37. The integrated assembly of claim 32, wherein the semiconductor oxide comprises indium, zinc, and gallium.

38. The integrated assembly of claim 37, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 18 to 24; said metal atomic percentage of said gallium is in the range of 47 to 53; and The metal atomic percent of the zinc is in the range of 26 to 32.

39. The integrated assembly of claim 37, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is 21; The metal atomic percentage of the gallium is 50; and The metal atomic percentage of the zinc was 29.

40. A method of forming an integrated assembly, comprising: Depositing a semiconductor oxide over a conductive material; the semiconductor oxide comprising indium, gallium and zinc; the deposition being physical vapor deposition and being performed in a chamber using an environment in the chamber having a temperature in a range of 20° C. to 500° C. and a pressure in a range of 1 mTorr to 9 mTorr; the deposited semiconductor oxide being polycrystalline; patterning the deposited semiconductor oxide into a vertically extending structure; the vertically extending structure having opposing first and second sidewall surfaces along a cross section; forming an insulating material along the opposing first and second sidewall surfaces; a first region of the insulating material along the first sidewall surface and a second region of the insulating material along the second sidewall surface; forming a gate material along the insulating material; a first region of the gate material along the first region of the insulating material, and a second region of the gate material along the second region of the insulating material; and wherein the semiconductor oxide, the first and second regions of the insulating material, and the first and second regions of the gate material together form a transistor; wherein the transistor is configured such that an electric field along the first and second regions of the gate material induces a flow of carriers within the semiconductor oxide, wherein the flow of carriers is along a first direction corresponding to the vertical direction of the semiconductor oxide; wherein individual grains of the polycrystalline semiconductor oxide are peripherally delimited by grain boundaries; and wherein at least one of the grain boundaries has a portion extending along a second direction, wherein the second direction intersects the first direction of the flow of carriers.

41. The method of claim 40, wherein the semiconductor oxide is deposited directly onto the conductive material.

42. The method of claim 41, wherein the conductive material comprises one or both of ruthenium and tungsten.

43. The method of claim 40, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 14 to 24; said metal atomic percentage of said gallium is in the range of 37 to 47; and The metal atomic percentage of the zinc is in the range of 35 to 45.

44. The method of claim 40, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 16 to 22; said metal atomic percentage of said gallium is in the range of 39 to 45; and The metal atomic percentage of the zinc is in the range of 37 to 43.

45. The method of claim 40, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is 19; The metal atomic percentage of the gallium is 42; and The metal atomic percentage of the zinc is 40.

46. ​​A method of forming an integrated assembly, comprising: depositing a semiconductor oxide over a support material; The semiconductor oxide includes indium, gallium and zinc; patterning the deposited semiconductor oxide into a vertically extending structure; the vertically extending structure having opposing first and second sidewall surfaces along a cross section; forming an insulating material along the opposing first and second sidewall surfaces; a first region of the insulating material along the first sidewall surface and a second region of the insulating material along the second sidewall surface; forming a gate material along the insulating material; a first region of the gate material along the first region of the insulating material, and a second region of the gate material along the second region of the insulating material; After forming the insulating material, annealing the semiconductor oxide under conditions such that the temperature of the semiconductor oxide is maintained in a range of 400° C. to 600° C. for a duration of at least 30 minutes to less than or equal to 1 day; After the annealing, grain boundaries extend along the vertical direction within the semiconductor oxide; The grain boundary traverses the entire length of the semiconductor oxide from the upper surface of the semiconductor oxide to the lower surface of the semiconductor oxide; the grain boundary is offset from the first region of the insulating material through a first intervening region of the semiconductor oxide and is offset from the second region of the insulating material through a second intervening region of the semiconductor oxide; and wherein the semiconductor oxide, the first and second regions of the insulating material, and the first and second regions of the gate material together form a transistor; wherein the transistor is configured such that an electric field along the first and second regions of the gate material induces a flow of carriers within the semiconductor oxide, wherein the flow of carriers is along a first direction corresponding to the vertical direction of the semiconductor oxide; and the flow of carriers within the semiconductor oxide is within the first and second intermediate regions and substantially parallel to the grain boundaries.

47. The method of claim 46, wherein the depositing comprises one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

48. The method of claim 46, wherein the annealing is performed in the chamber after forming the gate material and when a top portion of the semiconductor oxide is exposed to an environment inside the chamber.

49. The method of claim 48, wherein the environment consists of a gas that is inert with respect to reaction with the exposed top portion of the semiconductor oxide.

50. The method of claim 48, wherein the environment comprises a reducing agent.

51. The method of claim 48, wherein the environment comprises an oxidant.

52. The method of claim 46, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 16 to 26; said metal atomic percentage of said gallium is in the range of 45 to 55; and The metal atomic percent of the zinc is in the range of 24 to 34.

53. The method of claim 46, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is in the range of 18 to 24; said metal atomic percentage of said gallium is in the range of 47 to 53; and The metal atomic percent of the zinc is in the range of 26 to 32.

54. The method of claim 46, wherein the indium, zinc, and gallium are each present in the semiconductor oxide at a certain metal atomic percentage, and wherein: The metal atomic percentage of the indium is 21; The metal atomic percentage of the gallium is 50; and The metal atomic percentage of the zinc was 29.

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