Solution to coherency problem in logical to physical page translation in memory subsystem

Abstract

The present application relates to a solution to a coherency problem in a logical to physical page translation in a memory subsystem. A write request is received to program data to a memory device of the memory subsystem. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request is received to read the data from the memory device, and a seek operation is performed on the data structure to identify the intermediate entry. The pointer is used to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request, and the read request is executed using the read buffer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to solutions to coherency issues in logical to physical page translations in memory subsystems. Background Art

[0002] The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] According to one aspect of the present application, a method is provided. The method includes: receiving, by a processing device, a write request to program data to a memory device of a memory subsystem; generating an intermediate entry of a data structure, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request; receiving a read request to read the data from the memory device; performing a lookup operation on the data structure to identify the intermediate entry; using the pointer to locate the write buffer associated with the intermediate write operation; copying the write buffer to a read buffer associated with the read request; and executing the read request using the read buffer.

[0004] According to another aspect of the present application, a non-transitory computer-readable medium including instructions is provided. The instructions, when executed by a processing device, cause the processing device to perform operations including: receiving a write request from a host system to program data to a memory device of a memory subsystem; generating an intermediate entry of a data structure, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request; receiving a read request from the host system to read the data from the memory device, and using the pointer to locate the write buffer associated with the intermediate write operation.

[0005] According to another aspect of the present application, a system is provided. The system includes: a memory device; and a processing device operatively coupled to the memory device to perform the following operations: receiving a write request to program data to the memory device; generating an intermediate entry of a data structure, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request; receiving a read request to read the data from the memory device; performing a lookup operation on the data structure to identify the intermediate entry; using the pointer to locate the write buffer associated with the intermediate write operation; copying the write buffer to a read buffer associated with the read request; and executing the read request using the read buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem is illustrated in accordance with some embodiments of the present disclosure.

[0008] Figure 2 is a flow chart of an example method of managing a data structure containing entries associated with an intermediate write operation in accordance with some embodiments.

[0009] Figure 3 is a flowchart of an example method of managing a data structure containing entries associated with an intermediate write operation in accordance with some embodiments.

[0010] Figure 4 Illustrated is an example mapping translation component that manages a data structure containing intermediate entries associated with an intermediate write operation in accordance with some embodiments.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure are directed to solutions to coherency issues in logical-to-physical page updates in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (e.g., a memory device that stores data). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] In a memory subsystem, a memory subsystem controller maintains mapping information (also referred to as a "logical to physical (L2P) mapping data structure) between a logical address range corresponding to a logical block of a memory device and a physical address range of a memory cell of the memory device. For some memory subsystems (e.g., a solid-state device (SSD)), a dedicated module (e.g., a flash translation layer (FTL) module) is used to manage logical to physical address translation. In some cases, the translation of the logical address associated with a write operation to write data to a physical address of a target memory device (e.g., a large translation unit (LTU)) occurs during an interval after the L2P table has been updated with the physical address of the target memory device but before the data is completely written to the memory device of the memory subsystem. Therefore, since the physical address of the target memory device has been updated, the L2P table may be updated to the physical address of the target memory device. The L2P table is updated with the physical address of the target memory device, so a subsequent read command to read the data stored at the target memory device causes the controller to read the target memory device before the write operation is completed. Therefore, due to the lack of coherence between the L2P table and the target memory device, the read operation fails. Conventional memory subsystems attempt to solve the coherence problem by implementing a separate module in the memory subsystem to manage a hash table to perform a lookup operation to determine whether the previous write operation is completed. Conventional memory subsystems can also use a coherence checker to search for unresolved write operations to block or prohibit the identification of read operations that end before the write operation. However, the use of additional modules and corresponding coherence-related processing introduces additional cycles and hardware complexity, which adversely affects the performance of the memory subsystem.

[0014] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that implements and manages a data structure containing entries associated with intermediate or in-process write operations to address coherency issues associated with processing subsequent read commands corresponding to intermediate write operations. Specifically, a data structure (also referred to as an "intermediate data structure" or an "intermediate L2P table") may include an entry (also referred to as an "intermediate entry" or an "intermediate L2P entry") that records information identifying a physical address associated with an intermediate (e.g., in-process) write operation and a pointer identifying a write buffer (e.g., stored in a data cache memory) associated with the intermediate write operation (e.g., an incomplete write operation such that data has not yet been written to a target memory device in a physical medium of the memory subsystem). Upon receiving a read command, a controller uses the data structure to perform a lookup operation to identify the corresponding intermediate entry. The controller retrieves the intermediate entry and uses the stored pointer to locate the write buffer (e.g., an address in a cache memory) containing data associated with the intermediate write operation. The controller copies the write buffer to a read buffer and services the received read command. The read command is serviced using the data stored in the updated read buffer.

[0015] Advantages of the present disclosure include, but are not limited to, generating an intermediate entry in a data structure to resolve a coherency issue associated with a read command corresponding to an intermediate write command. The data structure is optimized by storing an intermediate entry containing a pointer to a cache memory address associated with a write buffer corresponding to the intermediate write request. Advantageously, a subsequent read request received from a host system while the write command is in progress (i.e., not yet completed) can be serviced by copying the contents of the write buffer to a read buffer corresponding to the read request. In so doing, read request execution failures associated with the aforementioned coherency issue involving the use of conventional L2P data structures to service read requests corresponding to intermediate write operations are avoided.

[0016] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0017] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, secure digital (SD) cards, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0018] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0019] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, and the like.

[0020] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0021] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting a double data rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., memory device 130). The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0022] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0023] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells.

[0024] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0025] Although non-volatile memory components such as 3D cross-point type and NAND type flash memory are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), "NOR" (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0026] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0027] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0028] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include a read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0029] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0030] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0031] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 may be a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] The memory subsystem 110 includes a mapping translation component 113, which can be used to manage a data structure including mapping information that associates the logical addresses and physical addresses of the memory subsystem. In some embodiments, the memory subsystem controller 115 includes at least a portion of the mapping translation component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 to perform the operations described herein. In some embodiments, the mapping translation component 113 is part of the host system 120, the application program, or the operating system. In the same or alternative embodiments, a portion of the mapping translation component 113 is part of the host system 120, while other portions of the mapping translation component 113 are executed at the memory subsystem controller 115.

[0033] The mapping translation component 113 may be used to manage a data structure (e.g., a table) that includes logical address to physical address mapping information associated with the memory subsystem. In one embodiment, the mapping translation component 113 generates an entry (also referred to as an "intermediate entry") for inclusion in a data structure (also referred to as an "L2P table" or "L2P mapping data structure") that includes additional information (also referred to as "intermediate information") associated with the L2P mapping. In one embodiment, in response to receiving a write request from the host system 120 to write data to a memory device of the memory device 140 of the memory subsystem 110, the mapping translation component 113 generates the intermediate entry and stores the intermediate entry in the L2P table. The intermediate entry includes an identifier (referred to herein as a "pointer") that identifies a write buffer address (e.g., a location in a cache memory) associated with the in-process write request. In one embodiment, the in-process write operation includes a requested write operation while it is pending (i.e., before the media write is completed).

[0034] In response to receiving the subsequent request of the data of write operation in the read process, mapping translation component 113 uses L2P data structure to perform search operation to identify corresponding middle entry.Using the pointer identified in the middle entry, mapping translation component 113 locates the write buffer of the data that stores and write operation is associated with the process.Mapping translation component 113 copies the write buffer to the read buffer associated with the read request, and serves the read request from the read buffer.The use of the middle entry in the L2P data structure solves the coherence problem that produces in the conventional L2P mapping technology.Other details about the operation of mapping translation component 113 are described below.

[0035] Figure 22 is a flow chart of an example method 200 for generating an entry of a data structure for servicing a read request corresponding to an intermediate or in-progress write operation according to some embodiments. The method 200 may be performed by processing logic that may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The mapping translation component 113 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processing program can be modified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated process can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0036] like Figure 2 As shown, at operation 210, processing logic receives a write request to program data to a memory device of a memory subsystem. In one embodiment, the write request is received from a host system and identifies a logical block address associated with a programming operation. Processing logic maintains a data structure (also referred to as an "L2P mapping data structure" or "L2P table") configured to map a logical address range to a corresponding physical address range of the memory subsystem.

[0037] In operation 220, processing logic generates an intermediate entry of a data structure that includes a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. In one embodiment, the intermediate entry is an entry in an L2P mapping data structure. In one embodiment, the intermediate entry identifies the address of a write buffer that stores data associated with an intermediate or in-progress write operation during the pendency of its write operation (e.g., before the write operation has completed and the corresponding data has been written to a target physical location of the memory subsystem. In one embodiment, the intermediate entry includes a pointer (e.g., a tag or other identifier corresponding to the address of the write buffer that stores the data associated with the intermediate write operation). In one embodiment, the pointer may include a system-managed tag (also referred to as a "systag") having one or more additional bits that can be used to store information identifying the intermediate write operation. In one embodiment, the pointer identifies the address of a write buffer in a cache memory that stores data associated with the intermediate write operation.

[0038] In one embodiment, the data structure may include normal or standard entries. Standard entries may be associated with memory locations that are not involved in the write request being processed. Standard entries (also referred to as "standard L2P entries") may include mapping translation information associated with logical addresses to physical addresses, including a logical block address header, a plan number of the logical block address header, a logical unit number (LUN), and physical block address information (e.g., page and block identifiers). In one embodiment, upon receiving a write request, the processing logic may check whether the corresponding entry in the data structure is a standard entry or an intermediate entry (i.e., associated with an intermediate write operation). In one embodiment, the processing logic may identify that the entry corresponding to the write request is a standard entry, generate an intermediate entry, and store the intermediate entry in the data structure. In one embodiment, the processing logic may identify that the entry corresponding to the write request is an intermediate entry (e.g., the entry is associated with another intermediate write operation), and the processing logic may replace the pointer of the current intermediate entry with the updated pointer associated with the write request received in operation 210.

[0039] In operation 230, processing logic receives a read request to read data from a memory device. In one embodiment, the read request is received from a host system and includes a request to read data from a target memory device. In one embodiment, the read request includes information identifying a physical address of a memory subsystem to be read.

[0040] In operation 240, processing logic performs a lookup operation on the data structure to identify the intermediate entry. In one embodiment, processing logic uses physical address information to identify the corresponding intermediate entry.

[0041] In operation 250, processing logic uses the pointer to locate the write buffer associated with the intermediate write operation. As described above, the intermediate entry includes pointer information that can be used to identify the location of the write buffer that includes data associated with the intermediate write operation. In one embodiment, using the pointer, processing logic can determine whether the write buffer is valid. If the write buffer is not valid, then processing logic determines that the transfer from the write buffer to the target memory device is complete (i.e., the write buffer has been released). In this case, processing logic can use the physical address information stored in the data structure and perform a read operation.

[0042] In operation 260, processing logic copies the write buffer to a read buffer associated with the read request. In operation 270, processing logic executes the read request using the read buffer. In one embodiment, the read request is serviced using the read buffer containing the contents copied from the write buffer in operation 260. Advantageously, processing logic can service read requests corresponding to data that is subject to an intermediate write operation.

[0043] Figure 3 is a flow chart of an example method 300 of managing a data structure containing intermediate entries corresponding to intermediate or in-progress write operations according to some embodiments. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The mapping translation component 113 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processing program can be modified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated process can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0044] like Figure 3 As shown, processing logic receives a write request to program data to a memory device of a memory subsystem at operation 310. In one embodiment, the write request includes data to be written to a physical location (eg, one or more memory devices) of the memory subsystem.

[0045] In operation 320, processing logic identifies an entry of a data structure associated with a write request. In one embodiment, processing logic identifies the entry using a logical block address identified from a write request received from a host system. In one embodiment, processing logic may identify the entry as a standard entry (e.g., the entry does not include an intermediate entry with a pointer to an intermediate write operation). In one embodiment, processing logic may determine that a corresponding entry in the data structure is an intermediate entry (e.g., a first intermediate entry), and replace pointer information of the first intermediate entry with an updated pointer associated with a new write request (i.e., generating a second intermediate entry to replace the first intermediate entry).

[0046] In operation 330, processing logic updates the data structure to include an intermediate entry including a pointer identifying a write buffer associated with the intermediate write operation. In one embodiment, in operation 320, processing logic stores the intermediate entry in the data structure in response to identifying the corresponding entry as a standard entry.

[0047] In operation 340, processing logic submits the write request to the memory device (eg, submits the write request to the back end for completion of the programming operation). In an embodiment, submission of the write request to the back end includes transfer of the write buffer to the physical memory device.

[0048] In operation 350 , upon completion of the transfer of the write buffer to the memory device, the processing device releases the write buffer and marks a pointer in the cache memory storing the write buffer as invalid.

[0049] In operation 360, upon completion of the intermediate write operation, the processing device updates the entry with the physical address of the memory device and releases the pointer from the intermediate entry. In one embodiment, when the programming operation is complete, if the pointer stored in the intermediate entry matches, the intermediate entry is updated with the physical address, thereby converting the intermediate entry to a standard entry (e.g., an entry without a pointer to the intermediate write operation). In one embodiment, the processing logic may decrease the valid page count (VPC) of the memory block number stored in the intermediate entry and increase the VPC of the new block (e.g., the block associated with the completed write operation). In one embodiment, if the pointer stored in the intermediate entry does not match, the processing logic may determine that the logical block is overwritten by another operation and determine that the mapping information is invalid. In one embodiment, if the entry is not an intermediate entry, the processing logic may determine that the mapping information is invalid in view of the valid mapping information stored in the standard entry of the data structure.

[0050] Figure 4 The diagram illustrates an example data structure 400 managed by the mapping translation component 113 according to an embodiment. Figure 4 As shown in , the mapping translation component 113 is configured to receive a first write request from the host system 120. The first write request includes an instruction to perform a write operation to program data to a physical page of the memory subsystem. The write request identifies a logical block address associated with one or more logical blocks of the memory subsystem. The mapping translation component 113 uses the data structure 400 to translate the logical block address into a corresponding physical block address. In order to enable the mapping translation component 113 to monitor the intermediate write operation corresponding to the first write request during the pendency of the write operation, the mapping translation component 113 generates an intermediate entry 415 and stores it in the data structure 400. The intermediate entry 415 includes a pointer or other identifier that identifies an address in the cache memory 450 of the write buffer 454 associated with the intermediate write operation. In one embodiment, the pointer is a system management tag (or "systag") number that includes one or more bits to identify the location of the write buffer containing the data associated with the intermediate write operation.

[0051] In one embodiment, upon receiving the second read request from the host system 120, the mapping translation component 113 immediately performs a lookup operation to identify a corresponding entry in the data structure 400. The write request is referred to as "first" because it precedes the "second" read request. In one embodiment, the second read request identifies a logical block address associated with the first write request. In one embodiment, because there is an intermediate write operation associated with the identified logical block address, the mapping translation component 113 identifies a stored pointer associated with the intermediate write operation. In one embodiment, a physical block address entry stored in the data structure 400 may identify that the physical block address is "pending" to signal to the mapping translation component 413 that the data has not yet been written to the physical memory device of the memory subsystem. Figure 4 As shown in , a pointer table 452 (or other data structure) may be stored in cache memory 450 and include pointer information associated with each intermediate write operation.

[0052] In one embodiment, using a pointer, the mapping translation component 113 uses the pointer to identify a write buffer 454 in the cache memory 450. The mapping translation component 113 copies the write buffer 454 to the read buffer 456 corresponding to the second read request. The mapping translation component 113 uses the data stored in the read buffer 464 to service the second read request. In one embodiment, in response to the first write request being transmitted to the physical memory of the memory subsystem, the mapping translation component 113 may release the write buffer 454 and mark, tag, or mark the write buffer 454 as "invalid" in the pointer table 452. In one embodiment, after the write operation is completed, the mapping translation component 113 may determine that the pointer stored in the intermediate entry 415 matches the pointer information stored in the pointer table 452, and update the physical block address entry in the data structure 400 with the physical address corresponding to the programmed data.

[0053] In one embodiment, if upon completion of the write operation, mapping translation component 113 determines that the pointer stored in intermediate entry 415 does not match the pointer information stored in pointer table 452, then mapping translation component 113 determines that the logical block has been overwritten by another operation and therefore the mapping information is invalid.

[0054] Figure 5 An example machine of a computer system 500 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1host system 120), or can be used to perform operations of the controller (for example, execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0055] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, a digital or non-digital circuit system, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0056] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0057] Processing device 502 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 to communicate over a network 520.

[0058] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, in whole or in part, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0059] In one embodiment, instructions 526 include implementing a corresponding mapping translation component (e.g., Figure 1 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for machine execution and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include but not limited to solid-state memory, optical media, and magnetic media.

[0060] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical control of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0061] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0062] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure described herein may be implemented using various programming languages.

[0064] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0065] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method for managing a data structure, comprising: receiving, by a processing device, a write request to program data into a memory device of a memory subsystem; generating an intermediate entry of the data structure, the intermediate entry comprising a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request, wherein the data structure includes a logical to physical L2P address mapping corresponding to the write request; receiving a read request to read the data from the memory device; performing a lookup operation on the data structure to identify the intermediate entry; using the pointer to locate the write buffer associated with the intermediate write operation; copying the write buffer to a read buffer associated with the read request; as well as The read request is performed using the read buffer. 2 . The method of claim 1 , wherein the read request is received prior to completion of the intermediate write operation.

3. The method of claim 1, further comprising storing the write buffer in a cache memory of the memory subsystem. 4 . The method of claim 1 , further comprising communicating the write request to the memory device to complete the intermediate write operation.

5. The method of claim 1, further comprising storing an additional data structure comprising the pointer identifying the write buffer associated with the intermediate write operation.

6. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a write request from a host system to program data into a memory device of the memory subsystem; generating an intermediate entry of a data structure, the intermediate entry comprising a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request, wherein the data structure includes a logical to physical L2P address mapping corresponding to the write request; receiving a read request from the host system to read the data from the memory device, and The pointer is used to locate the write buffer associated with the intermediate write operation.

7. The non-transitory computer-readable medium of claim 6, the operations further comprising copying data from the write buffer to a read buffer associated with the read request. 8 . The non-transitory computer-readable medium of claim 7 , the operations further comprising performing a read operation corresponding to the read request using data from the read buffer.

9. The non-transitory computer readable medium of claim 8, the operations further comprising: An entry of the data structure containing a physical address associated with the write request is identified using the logical address identified by the write request.

10. The non-transitory computer-readable medium of claim 9, the operations further comprising updating the entry to include the intermediate entry.

11. The non-transitory computer readable medium of claim 6, the operations further comprising: transferring the contents of the write buffer to the memory device; releasing the write buffer; as well as The pointer is marked as invalid in a cache memory storing the write buffer.

12. The non-transitory computer readable medium of claim 6, the operations further comprising: completing the intermediate write operation; updating the entry to include a physical address of the memory device; as well as The pointer is released from the intermediate entry.

13. The non-transitory computer readable medium of claim 6, the operations further comprising: performing a lookup operation using the data structure to identify the entry; determining that the entry includes a stored intermediate entry; as well as The stored intermediate entry is replaced with the intermediate entry including the pointer.

14. A memory subsystem comprising: Memory device; as well as A processing device operatively coupled to the memory device to perform the following operations: receiving a write request to program data to the memory device; generating an intermediate entry of a data structure, the intermediate entry comprising a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request, wherein the data structure includes a logical to physical L2P address mapping corresponding to the write request; receiving a read request to read the data from the memory device; performing a lookup operation on the data structure to identify the intermediate entry; using the pointer to locate the write buffer associated with the intermediate write operation; copying the write buffer to a read buffer associated with the read request; as well as The read request is performed using the read buffer.

15. The memory subsystem of claim 14, wherein the read request is received prior to completion of the intermediate write operation.

16. The memory subsystem of claim 14, wherein the processing device further stores the write buffer in a cache memory.

17. The memory subsystem of claim 14, wherein the processing device further transmits the write request to the memory device to complete the intermediate write operation.

18. The memory subsystem of claim 14, wherein the processing device further stores an additional data structure in a cache memory, the additional data structure including the pointer identifying the write buffer associated with the intermediate write operation.

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