Display substrate and manufacturing method thereof, and display device

Abstract

The present invention provides a display substrate and a manufacturing method thereof, and a display device, which relate to the field of display technology, and are intended to solve the problem that when a display product is tested using a test circuit, the uniformity of the test signal received by the display area is poor, resulting in a low test accuracy. The first test signal line in the test circuit in the display substrate extends along the second direction, and the second test signal line includes a first part extending along the first direction and a second part extending along the second direction; the width of the first part of the second test signal line in a direction perpendicular to the first direction is different from the width of the first test signal line in a direction perpendicular to the second direction; the width of the second part of the second test signal line in a direction perpendicular to the second direction is different from the width of the first test signal line in a direction perpendicular to the second direction; the difference between the resistance of the first test signal line and the resistance of the second test signal line is less than a first threshold. The display substrate provided by the present invention is used for display.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) display products are widely used in social life due to their advantages such as self-luminescence, high contrast, and low power consumption. However, compared with liquid crystal display products, AMOLED display products are limited by the complex production process and low product yield, which makes the production cost of AMOLED display products generally higher; therefore, in order to improve the production yield of AMOLED display products, related technologies generally set up test circuits in display products, and use the test circuits to timely test the performance of intermediate products obtained during the production process, which not only helps to solve product defects in a timely manner, but also helps to improve the production yield of products, while also saving production time, reducing production costs, and improving efficiency.

[0003] However, in the related art, when a test circuit is used to test a display product, when the same test signal is provided to the display area of ​​the display product through the test circuit, the uniformity of the test signal received by the display area of ​​the display product is poor, thereby affecting the accuracy of the display product test. Summary of the invention

[0004] The object of the present invention is to provide a display substrate and a manufacturing method thereof, and a display device, which are used to solve the problem in the related art that when a display product is tested using a test circuit, the uniformity of the test signal received by the display area of ​​the display product is poor, resulting in low accuracy in testing the display product.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display substrate, comprising: a display area and a non-display area located around the display area, the display substrate further comprising a test structure located in the non-display area, the test structure comprising a plurality of test circuits arranged along a first direction, each of the test circuits comprising:

[0007] a plurality of test signal lines, the plurality of test signal lines comprising a first test signal line and a second test signal line, the first test signal line extending along a second direction, the second test signal line comprising a first portion extending along the first direction and a second portion extending along the second direction, the second direction intersecting the first direction;

[0008] The width of the first part of the second test signal line in a direction perpendicular to the first direction is different from the width of the first test signal line in the direction perpendicular to the second direction; the width of the second part of the second test signal line in a direction perpendicular to the second direction is different from the width of the first test signal line in the direction perpendicular to the second direction; the difference between the resistance of the first test signal line and the resistance of the second test signal line is less than a first threshold.

[0009] Optionally, the width of the first portion of the second test signal line along a direction perpendicular to the first direction is smaller than the width of the second portion of the second test signal line along the direction perpendicular to the second direction; the width of the first test signal line along the direction perpendicular to the second direction is smaller than the width of the second portion of the second test signal line along the direction perpendicular to the second direction.

[0010] Optionally, each of the test circuits further includes: a first test sub-circuit, wherein the first test sub-circuit includes:

[0011] a first test unit, wherein the orthographic projection of the first test unit on the base of the display substrate is located between the orthographic projection of the first test signal line on the base and the orthographic projection of the second test signal line on the base; an output end of the first test unit is coupled to the first test signal line, and is used to output a first picture test signal and a second picture test signal to the first test signal line in a time-sharing manner;

[0012] A second test unit, wherein the orthographic projection of the second test unit on the substrate is located on a side of the orthographic projection of the second test signal line on the substrate away from the orthographic projection of the first test signal line on the substrate; an output end of the second test unit is coupled to the second test signal line for outputting a third picture test signal to the second test signal line.

[0013] Optionally, the second test signal line includes a first conductive pattern, a second conductive pattern, a third conductive pattern, a fourth conductive pattern, a fifth conductive pattern, a sixth conductive pattern and a seventh conductive pattern coupled in sequence;

[0014] The first part of the second test signal line includes: the second conductive pattern, the fourth conductive pattern and the sixth conductive pattern, and the second part of the second test signal line includes: the first conductive pattern, the third conductive pattern, the fifth conductive pattern and the seventh conductive pattern;

[0015] The second conductive pattern, the third conductive pattern, the fourth conductive pattern, the fifth conductive pattern and the sixth conductive pattern together with the first test signal line define a first accommodation space, and at least a portion of the first test unit is located in the first accommodation space.

[0016] Optionally, each of the test circuits further includes: a second test sub-circuit, wherein the second test sub-circuit includes:

[0017] A third test unit, wherein the orthographic projection of the third test unit on the substrate of the display substrate is located between the orthographic projection of the first test signal line on the substrate and the orthographic projection of the second test signal line on the substrate; the output end of the third test unit is respectively coupled to the first test signal line and the second test signal line, for simultaneously outputting the same functional test signal to the first test signal line and the second test signal line.

[0018] Optionally, the second test signal line includes: an eighth conductive pattern, a ninth conductive pattern, a tenth conductive pattern and an eleventh conductive pattern coupled in sequence;

[0019] The first part of the second test signal line includes: an eighth conductive pattern and a tenth conductive pattern, and the second part of the second test signal line includes: a ninth conductive pattern and an eleventh conductive pattern;

[0020] The eighth conductive pattern, the ninth conductive pattern, the tenth conductive pattern and the first test signal line together define a third accommodation space, and at least a portion of the third test unit is located in the third accommodation space.

[0021] Optionally, the plurality of test signal lines further include a third test signal line and a fourth test signal line, the third test signal line includes a third portion extending along the first direction and a fourth portion extending along the second direction, and the fourth test signal line extends along the second direction;

[0022] The width of the third portion of the third test signal line in a direction perpendicular to the first direction is different from the width of the fourth test signal line in a direction perpendicular to the second direction; the width of the fourth portion of the third test signal line in a direction perpendicular to the second direction is different from the width of the fourth test signal line in a direction perpendicular to the second direction;

[0023] A resistance difference between any two of the first test signal line, the second test signal line, the third test signal line and the fourth test signal line is smaller than a first threshold.

[0024] Optionally, a width of a third portion of the third test signal line in a direction perpendicular to the first direction is smaller than a width of a fourth portion of the third test signal line in a direction perpendicular to the second direction;

[0025] A width of the fourth test signal line along a direction perpendicular to the second direction is smaller than a width of the fourth portion of the third test signal line along a direction perpendicular to the second direction.

[0026] Optionally, the width of the first test signal line along the direction perpendicular to the second direction is equal to the width of the fourth test signal line along the direction perpendicular to the second direction;

[0027] A width of the second portion of the second test signal line along a direction perpendicular to the second direction and a width of the fourth portion of the third test signal line along a direction perpendicular to the second direction are both greater than a width of the first test signal line along a direction perpendicular to the second direction.

[0028] Optionally, each of the test circuits further includes: a first test sub-circuit, wherein the first test sub-circuit includes:

[0029] a fourth test unit, wherein the orthographic projection of the fourth test unit on the substrate is located between the orthographic projection of the second test signal line on the substrate and the orthographic projection of the third test signal line on the substrate; an output end of the fourth test unit is coupled to the third test signal line, and is used to output the first picture test signal and the second picture test signal to the third test signal line in a time-sharing manner;

[0030] a fifth test unit, wherein the orthographic projection of the fifth test unit on the substrate is located between the orthographic projection of the third test signal line on the substrate and the orthographic projection of the fourth test signal line on the substrate; an output end of the fifth test unit is coupled to the fourth test signal line, and is used to output a third picture test signal to the fourth test signal line;

[0031] Each of the test circuits further includes: a second test sub-circuit, wherein the second test sub-circuit includes:

[0032] A sixth test unit, wherein the orthographic projection of the sixth test unit on the substrate is located between the orthographic projection of the third test signal line on the substrate and the orthographic projection of the fourth test signal line on the substrate; the output end of the sixth test unit is respectively coupled to the third test signal line and the fourth test signal line, for simultaneously outputting the same functional test signal to the third test signal line and the fourth test signal line.

[0033] Optionally, the third test signal line includes a twelfth conductive pattern, a thirteenth conductive pattern, a fourteenth conductive pattern, a fifteenth conductive pattern, a sixteenth conductive pattern, a seventeenth conductive pattern, an eighteenth conductive pattern, a nineteenth conductive pattern and a twentieth conductive pattern coupled in sequence;

[0034] The third portion of the third test signal line includes a thirteenth conductive pattern, a fifteenth conductive pattern, a seventeenth conductive pattern and the nineteenth conductive pattern, and the fourth portion of the third test signal line includes a twelfth conductive pattern, a fourteenth conductive pattern, a sixteenth conductive pattern, an eighteenth conductive pattern and a twentieth conductive pattern;

[0035] The fifteenth conductive pattern, the sixteenth conductive pattern, the seventeenth conductive pattern and the second test signal line together define a second accommodation space, and at least a portion of the second test unit is located in the second accommodation space;

[0036] The thirteenth conductive pattern, the fourteenth conductive pattern, the fifteenth conductive pattern and the fourth test signal line together define a fifth accommodation space, and at least part of the fifth test unit is located in the fifth accommodation space;

[0037] The nineteenth conductive pattern, the twentieth conductive pattern and the fourth test signal line jointly define a sixth accommodation space, and at least a portion of the sixth test unit is located in the sixth accommodation space.

[0038] Optionally, the first test sub-circuit and the second test sub-circuit are arranged along the second direction, the first test sub-circuit is located between the display area and the second test sub-circuit, or the second test sub-circuit is located between the display area and the first test sub-circuit.

[0039] Optionally, the test structure further includes: a first control signal line, a second control signal line, a third control signal line, a fourth control signal line, a fifth control signal line, a sixth control signal line and a seventh control signal line, all extending along the first direction; and a first test data line, a second test data line, a third test data line, a fourth test data line, a fifth test data line, a sixth test data line, a seventh test data line and an eighth test data line, all extending along the first direction;

[0040] The plurality of test signal lines further include a third test signal line and a fourth test signal line;

[0041] Each of the test circuits includes a first test subcircuit and a second test subcircuit; the first test subcircuit includes a first test unit, a second test unit, a third test unit and a fourth test unit; the second test subcircuit includes a fifth test unit and a sixth test unit;

[0042] The first test unit includes a first transistor and a second transistor, the gate of the first transistor is coupled to the second control signal line, the first electrode of the first transistor is coupled to the third test data line, and the second electrode of the first transistor is coupled to the first test signal line;

[0043] The gate of the second transistor is coupled to the third control signal line, the first electrode of the second transistor is coupled to the fourth test data line, and the second electrode of the second transistor is coupled to the first test signal line;

[0044] The second test unit comprises a third transistor, a gate of the third transistor is coupled to the fifth control signal line, a first electrode of the third transistor is coupled to the sixth test data line, and a second electrode of the third transistor is coupled to the second test signal line;

[0045] The fourth test unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is coupled to the first control signal line, the first electrode of the fourth transistor is coupled to the first test data line, and the second electrode of the fourth transistor is coupled to the third test signal line;

[0046] A gate of the fifth transistor is coupled to the second control signal line, a first electrode of the fifth transistor is coupled to the second test data line, and a second electrode of the fifth transistor is coupled to the third test signal line;

[0047] The fifth test unit includes a sixth transistor, a gate of the sixth transistor is coupled to the fourth control signal line, a first electrode of the sixth transistor is coupled to the fifth test data line, and a second electrode of the sixth transistor is coupled to the fourth test signal line;

[0048] The third test unit includes a seventh transistor and an eighth transistor, a gate of the seventh transistor and a gate of the eighth transistor are both coupled to the sixth control signal line, a first electrode of the seventh transistor and a first electrode of the eighth transistor are both coupled to the seventh test data line, a second electrode of the seventh transistor is coupled to the first test signal line, and a second electrode of the eighth transistor is coupled to the second test signal line;

[0049] The sixth test unit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor and the gate of the tenth transistor are both coupled to the seventh control signal line, the first electrode of the ninth transistor and the first electrode of the tenth transistor are both coupled to the eighth test data line, the second electrode of the ninth transistor is coupled to the third test signal line, and the second electrode of the tenth transistor is coupled to the fourth test signal line.

[0050] Optionally, the display substrate further includes:

[0051] A plurality of data signal lines located in the display area, the data signal lines corresponding to the test signal lines one by one;

[0052] A plurality of first fan-out lines located in the non-display area, the first fan-out lines corresponding to the data signal lines one by one, the data signal lines being coupled to the corresponding test signal lines through the corresponding first fan-out lines; the plurality of first fan-out lines forming a plurality of sub-fan-out areas arranged along the first direction, each sub-fan-out area including a plurality of the first fan-out lines;

[0053] A plurality of power signal line patterns, each of which has an orthographic projection on the substrate located between the orthographic projections of two adjacent sub-fan-out areas on the substrate, a plurality of the first fan-out lines located on the same side of the central axis of the display substrate, have resistance values ​​gradually increasing in a direction approaching the central axis, a difference in resistance values ​​between any two adjacent first fan-out lines is less than a second threshold, and the central axis extends in a direction parallel to the second direction.

[0054] Optionally, each of the first fan-out lines includes: a first fan-out pattern and a second fan-out pattern coupled to each other, the first fan-out pattern is located between the display area and the second fan-out pattern, the first fan-out pattern extends along the second direction, the second fan-out pattern extends along a third direction, and the third direction intersects with the second direction;

[0055] On the same side of the central axis, along the direction close to the central axis of the display substrate, the widths of the first fan-out patterns included in the plurality of first fan-out lines located in the same sub-fan-out area gradually increase, and the widths of the second fan-out patterns included in the plurality of first fan-out lines located in the same sub-fan-out area are the same;

[0056] On the same side of the central axis, in two adjacent sub-fan-out areas, the width of the first fan-out pattern farthest from the central axis in the sub-fan-out area close to the central axis is greater than the width of the first fan-out pattern closest to the central axis in the sub-fan-out area away from the central axis; the difference between the width of the first fan-out pattern farthest from the central axis in the sub-fan-out area close to the central axis and the width of the first fan-out pattern closest to the central axis in the sub-fan-out area away from the central axis is greater than a third threshold;

[0057] The width of the first fan-out pattern is the width of the first fan-out pattern in a direction perpendicular to the second direction; the width of the second fan-out pattern is the width of the second fan-out pattern in a direction perpendicular to the third direction.

[0058] Based on the technical solution of the above substrate, a second aspect of the present invention provides a display device, comprising the above display substrate.

[0059] Based on the technical solution of the above substrate, a third aspect of the present invention provides a method for manufacturing a display substrate, which is used to manufacture the above display substrate. The manufacturing method includes:

[0060] A test structure is fabricated in a non-display area of ​​the display substrate, the test structure comprising a plurality of test circuits arranged along a first direction, each of the test circuits comprising: a plurality of test signal lines, the plurality of test signal lines comprising a first test signal line and a second test signal line, the first test signal line extending along a second direction, the second test signal line comprising a first portion extending along the first direction and a second portion extending along the second direction, the second direction intersecting the first direction; a width of the first portion of the second test signal line in a direction perpendicular to the first direction is different from a width of the first test signal line in a direction perpendicular to the second direction; a width of the second portion of the second test signal line in a direction perpendicular to the second direction is different from a width of the first test signal line in a direction perpendicular to the second direction; and a difference between a resistance of the first test signal line and a resistance of the second test signal line is less than a first threshold value.

[0061] In the technical solution provided by the present invention, by setting the width of the first part of the second test signal line in a direction perpendicular to the first direction to be different from the width of the first test signal line in the direction perpendicular to the second direction; and the width of the second part of the second test signal line in a direction perpendicular to the second direction to be different from the width of the first test signal line in the direction perpendicular to the second direction, the difference between the resistance of the first test signal line and the resistance of the second test signal line is made smaller than a first threshold value, so that the voltage drop difference of each test signal line is smaller, and when the same test signal is provided to the display area of ​​the display product through the test circuit, the test signal received by the display area of ​​the display product has higher uniformity, which effectively improves the accuracy of testing the display product. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0063] Figure 1 A schematic diagram of the structure of a test circuit provided by an embodiment of the present invention;

[0064] Figure 2 A schematic diagram of the layout of a test circuit provided by an embodiment of the present invention;

[0065] Figure 3a A schematic diagram of a second test signal line provided by an embodiment of the present invention;

[0066] Figure 3b A schematic diagram of a third test signal line provided by an embodiment of the present invention;

[0067] Figure 4 A schematic diagram of the resistance variation trend of the four test signal lines in the test circuit before compensation;

[0068] Figure 5 A schematic diagram of the resistance variation trend of the four test signal lines in the test circuit after compensation;

[0069] Figure 6 A schematic diagram of the layout of a non-display area provided in an embodiment of the present invention;

[0070] Figure 7 for Figure 6 An enlarged schematic diagram of the X portion;

[0071] Figure 8 A schematic diagram of the resistance change of the first fan-out line to compensate for the front D area, E area and F area;

[0072] Fig. 9 Schematic diagram of the resistance change of the first fan-out line in the D area, the E area and the F area after compensation. DETAILED DESCRIPTION

[0073] In order to further illustrate the display substrate and the manufacturing method thereof, and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0074] Based on the problems existing in the background technology, the inventors of the present invention have discovered through research that the reason for the poor uniformity of the test signal received by the display area of ​​the display product is that the resistance values ​​of the test signal lines included in the test circuit differ greatly, resulting in a large difference in the voltage drop of the test signal lines. As a result, when the same test signal is provided to the display area of ​​the display product through the test circuit, the uniformity of the test signal received by the display area of ​​the display product is poor, affecting the accuracy of the test of the display product.

[0075] See also Figure 1 , Figure 2 and Figure 6 As shown, an embodiment of the present invention provides a display substrate, comprising: a display area AA and a non-display area located around the display area AA, the display substrate further comprising a test structure CT located in the non-display area, the test structure CT comprising a plurality of test circuits arranged along a first direction, each of the test circuits comprising:

[0076] a plurality of test signal lines, the plurality of test signal lines comprising a first test signal line 1 and a second test signal line 2, the first test signal line 1 extending along a second direction, the second test signal line 2 comprising a first portion extending along the first direction and a second portion extending along the second direction, the second direction intersecting the first direction;

[0077] The width of the first part of the second test signal line 2 along a direction perpendicular to the first direction is different from the width of the first test signal line 1 along the second direction perpendicular to the second direction; the width of the second part of the second test signal line 2 along a direction perpendicular to the second direction is different from the width of the first test signal line 1 along the second direction perpendicular to the second direction; the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is less than a first threshold.

[0078] Specifically, the display substrate includes a display area AA and a non-display area surrounding the display area AA. Exemplarily, the non-display area includes a first fan-out area N, a test structure CT setting area, a second fan-out area M and a chip binding area (not shown in the figure) arranged in sequence along a direction away from the display area AA. The non-display area also includes a bending area G, which overlaps with the first fan-out area N and is located inside the first fan-out area N.

[0079] Each of the test circuits may include a plurality of test signal lines. For example, the plurality of test signal lines may include a first test signal line 1 and a second test signal line 2 of different shapes, wherein the first test signal line 1 extends along a second direction, and the second direction may be the same as the extension direction of the data line in the display substrate, but is not limited thereto; the second test signal line 2 may include a first portion extending along the first direction and a second portion extending along the second direction, and the first direction may include a plurality of directions intersecting with the second direction, such as: the first direction is perpendicular to the second direction; or the angle between the first direction and the second direction is less than 90 degrees. In addition, the first direction may be set as the X direction, and the second direction may be set as the Y direction.

[0080] By adjusting the width of the first test signal line 1 in a direction perpendicular to the second direction, the width of the first part of the second test signal line 2 in a direction perpendicular to the first direction, and the width of the second part of the second test signal line 2 in a direction perpendicular to the second direction, the resistance of the first test signal line 1 and the resistance of the second test signal line 2 are adjusted, so that the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is less than a first threshold.

[0081] It should be noted that the first threshold value can be set according to actual needs, and illustratively, the first threshold value is 1Ω. In addition, the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is less than the first threshold value, that is, the resistance of the first test signal line 1 and the resistance of the second test signal line 2 are essentially equal.

[0082] It is also worth noting that the width of the first part of the second test signal line 2 along a direction perpendicular to the first direction, the width of the first test signal line 1 along a direction perpendicular to the second direction, the width of the second part of the second test signal line 2 along a direction perpendicular to the second direction, and the width of the first test signal line 1 along the second direction; as well as the "width" mentioned in other parts of the present application document may refer to the maximum width, but is not limited to this.

[0083] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present invention, by setting the width of the first part of the second test signal line 2 in a direction perpendicular to the first direction to be different from the width of the first test signal line 1 in a direction perpendicular to the second direction; and the width of the second part of the second test signal line 2 in a direction perpendicular to the second direction to be different from the width of the first test signal line 1 in a direction perpendicular to the second direction, the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is smaller than the first threshold value, so that the voltage drop difference of each test signal line is smaller, and when the same test signal is provided to the display area of ​​the display product through the test circuit, the test signal received by the display area of ​​the display product has high uniformity, which effectively improves the accuracy of the display product testing.

[0084] like Figure 2 and Figure 3a As shown, in some embodiments, the width h5 of the first portion of the second test signal line 2 along a direction perpendicular to the first direction is smaller than the width h2 of the second portion of the second test signal line 2 along the direction perpendicular to the second direction; the width h1 of the first test signal line 1 along the direction perpendicular to the second direction is smaller than the width h2 of the second portion of the second test signal line 2 along the direction perpendicular to the second direction.

[0085] Specifically, the total lengths of the first test signal line 1 and the second test signal line 2 in the second direction can be set to be the same. Since the first test signal line 1 extends along the second direction, that is, it only includes a portion extending along the second direction, and the second test signal line 2 includes a first portion extending along the first direction and a second portion extending along the second direction, the routing stroke of the second test signal line 2 is greater than the routing stroke of the first test signal line 1. In this way, when setting the line widths of the first test signal line 1 and the second test signal line 2, the width of the first portion of the second test signal line 2 in a direction perpendicular to the first direction can be set to be smaller than the width of the second portion of the second test signal line 2 in a direction perpendicular to the second direction; the width of the first test signal line 1 in a direction perpendicular to the second direction is smaller than the width of the second portion of the second test signal line 2 in a direction perpendicular to the second direction, thereby achieving that the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is smaller than the first threshold, so that the voltage drop difference of each test signal line is small, and when the same test signal is provided to the display area of ​​the display product through the test circuit, the uniformity of the test signal received by the display area of ​​the display product is high, which effectively improves the accuracy of the display product test.

[0086] like Figure 1 and Figure 2 As shown, in some embodiments, each of the test circuits further includes: a first test sub-circuit CT1, wherein the first test sub-circuit CT1 includes:

[0087] A first test unit, wherein the orthographic projection of the first test unit on the substrate of the display substrate is located between the orthographic projection of the first test signal line 1 on the substrate and the orthographic projection of the second test signal line 2 on the substrate; an output end of the first test unit is coupled to the first test signal line 1, and is used to output a first picture test signal and a second picture test signal to the first test signal line 1 in a time-sharing manner;

[0088] A second test unit, the orthographic projection of the second test unit on the substrate is located on a side of the orthographic projection of the second test signal line 2 on the substrate away from the orthographic projection of the first test signal line 1 on the substrate; the output end of the second test unit is coupled to the second test signal line 2, for outputting a third picture test signal to the second test signal line 2.

[0089] Specifically, the working process of the first test sub-circuit CT1 of the above structure is as follows:

[0090] In a first test period, the first test unit writes a first picture test signal to the first test signal line 1 , and the second test unit writes a third picture test signal to the second test signal line 2 , so as to implement a first picture test on the display substrate.

[0091] In the second test period, the first test unit writes a second picture test signal to the first test signal line 1 , and the second test unit writes a third picture test signal to the second test signal line 2 , so as to implement a second picture test on the display substrate.

[0092] Exemplarily, the first picture test signal includes a blue pixel test signal, the second picture test signal includes a red pixel test signal, and the third picture test signal includes a green pixel test signal. During the first test period, a green-blue (GB) picture test is performed on the display substrate, and during the second test period, a green-red (GR) picture test is performed on the display substrate.

[0093] The first test unit and the second test unit of the above structure can perform display screen tests of different screens on the display substrate in a time-sharing manner, thereby achieving more accurate detection of the display performance of the display substrate.

[0094] like Figure 2 and Figure 3a As shown, the specific layout positions of the first test unit and the second test unit are various. In some embodiments, the test signal line includes a first conductive pattern 21, a second conductive pattern 22, a third conductive pattern 23, a fourth conductive pattern 24, a fifth conductive pattern 25, a sixth conductive pattern 26 and a seventh conductive pattern 27 coupled in sequence;

[0095] The first part of the second test signal line 2 includes: the second conductive pattern 22, the fourth conductive pattern 24 and the sixth conductive pattern 26, and the second part of the second test signal line 2 includes: the first conductive pattern 21, the third conductive pattern 23, the fifth conductive pattern 25 and the seventh conductive pattern 27;

[0096] The second conductive pattern 22 , the third conductive pattern 23 , the fourth conductive pattern 24 , the fifth conductive pattern 25 and the sixth conductive pattern 26 together with the first test signal line 1 define a first accommodation space 81 , and at least a portion of the first test unit is located in the first accommodation space 81 .

[0097] Specifically, since the second conductive pattern 22, the fourth conductive pattern 24 and the sixth conductive pattern 26 extend along the first direction, the third conductive pattern 23 and the fifth conductive pattern 25 extend along the second direction, and the second conductive pattern 22, the third conductive pattern 23, the fourth conductive pattern 24, the fifth conductive pattern 25 and the sixth conductive pattern 26 are coupled in sequence, the second conductive pattern 22, the third conductive pattern 23, the fourth conductive pattern 24, the fifth conductive pattern 25 and the sixth conductive pattern 26 can be formed into a first groove structure, and the opening of the first groove structure is directed toward the first test signal line 1. The first groove structure can form the first accommodating space 81 between the first test signal line 1. When laying out the first test unit, the first test unit can be laid out in the first accommodating space 81 to reduce the layout space occupied by the entire test circuit.

[0098] like Figure 1 and Figure 2 As shown, in some embodiments, each of the test circuits further includes: a second test sub-circuit CT2, wherein the second test sub-circuit CT2 includes:

[0099] A third test unit, wherein the orthographic projection of the third test unit on the substrate of the display substrate is located between the orthographic projection of the first test signal line 1 on the substrate and the orthographic projection of the second test signal line 2 on the substrate; the output end of the third test unit is respectively coupled to the first test signal line 1 and the second test signal line 2, for simultaneously outputting the same functional test signal to the first test signal line 1 and the second test signal line 2.

[0100] Specifically, the working process of the third test unit of the above structure is as follows:

[0101] In the same test period, the third test unit writes the same functional test signal to the first test signal line 1 and the second test signal line 2 respectively. Taking the high level of the functional test signal as an example, when the functional test signal is written into the display area of ​​the display substrate, the display area normally displays a black screen. If there is an abnormality in the display area (such as a signal line disconnection), a low level appears at the abnormal position, causing the pixel corresponding to the abnormal position to light up, and an abnormal bright spot appears in the display area. According to the position of the abnormal bright spot, the abnormal position of the display substrate can be determined.

[0102] The third test unit can detect whether there are abnormal conditions such as broken wires or poor contact in the display substrate.

[0103] like Figure 2 and Figure 3aAs shown, in some embodiments, the second test signal line 2 includes: an eighth conductive pattern 28, a ninth conductive pattern 29, a tenth conductive pattern 30 and an eleventh conductive pattern 31 coupled in sequence;

[0104] The first part of the second test signal line 2 includes: an eighth conductive pattern 28 and a tenth conductive pattern 30, and the second part of the second test signal line 2 includes: a ninth conductive pattern 29 and an eleventh conductive pattern 31;

[0105] The eighth conductive pattern 28 , the ninth conductive pattern 29 , the tenth conductive pattern 30 and the first test signal line 1 together define a third accommodation space, and at least a portion of the third test unit is located in the third accommodation space.

[0106] Specifically, since the eighth conductive pattern 28 and the tenth conductive pattern 30 extend along the first direction, the ninth conductive pattern 29 extends along the second direction, and the eighth conductive pattern 28, the ninth conductive pattern 29 and the tenth conductive pattern 30 are coupled in sequence, the eighth conductive pattern 28, the ninth conductive pattern 29 and the tenth conductive pattern 30 can be formed into a third groove structure, and the opening of the third groove structure is directed toward the first test signal line 1. The third groove structure can form the third accommodating space 83 between the first test signal line 1. When laying out the third test unit, the third test unit can be laid out in the third accommodating space 83 to reduce the layout space occupied by the entire test circuit.

[0107] like Figure 1 and Figure 2 As shown, in some embodiments, the plurality of test signal lines further include a third test signal line 3 and a fourth test signal line 4, the third test signal line 3 includes a third portion extending along the first direction and a fourth portion extending along the second direction, and the fourth test signal line 4 extends along the second direction;

[0108] The width of the third portion of the third test signal line 3 along the direction perpendicular to the first direction is different from the width of the fourth test signal line 4 along the direction perpendicular to the second direction; the width of the fourth portion of the third test signal line 3 along the direction perpendicular to the second direction is different from the width of the fourth test signal line 4 along the direction perpendicular to the second direction;

[0109] The resistance difference between any two of the first test signal line 1 , the second test signal line 2 , the third test signal line 3 and the fourth test signal line 4 is smaller than the first threshold.

[0110] Specifically, the multiple test signal lines in each of the test circuits may also include a third test signal line 3 and a fourth test signal line 4 of different shapes, wherein the fourth test signal line 4 extends along a second direction, and the second direction may be the same as the extension direction of the data line in the display substrate, but is not limited to this; the third test signal line 3 may include a third part extending along the first direction and a fourth part extending along the second direction, and the first direction may include multiple directions intersecting with the second direction, such as: the first direction is perpendicular to the second direction; or the angle between the first direction and the second direction is less than 90 degrees.

[0111] By adjusting the width of the fourth test signal line 4 in a direction perpendicular to the second direction, the width of the third portion of the third test signal line 3 in a direction perpendicular to the first direction, and the width of the fourth portion of the third test signal line 3 in a direction perpendicular to the second direction, the resistance of the fourth test signal line 4 and the resistance of the third test signal line 3 are adjusted, so that the difference between the resistance of the third test signal line 3 and the resistance of the fourth test signal line 4 is less than a first threshold value. Exemplarily, the first threshold value is 1Ω.

[0112] It should be noted that the resistance difference between any two test signal lines among the first test signal line 1, the second test signal line 2, the third test signal line 3 and the fourth test signal line 4 is less than the first threshold, that is, the resistance of the first test signal line 1, the resistance of the second test signal line 2, the resistance of the third test signal line 3 and the resistance of the fourth test signal line 4 are essentially equal.

[0113] In the display substrate provided by the above embodiment, by setting the width of the first part of the second test signal line 2 in a direction perpendicular to the first direction to be different from the width of the first test signal line 1 in a direction perpendicular to the second direction; the width of the second part of the second test signal line 2 in a direction perpendicular to the second direction is different from the width of the first test signal line 1 in a direction perpendicular to the second direction; and the width of the third part of the third test signal line 3 in a direction perpendicular to the first direction is different from the width of the fourth test signal line 4 in a direction perpendicular to the second direction; the width of the fourth part of the third test signal line 3 in a direction perpendicular to the second direction is different from the width of the fourth test signal line 4 in a direction perpendicular to the second direction; so that the resistance difference between any two test signal lines among the first test signal line 1, the second test signal line 2, the third test signal line 3 and the fourth test signal line 4 is less than the first threshold value, so that the voltage drop difference of each test signal line in the test circuit is small, when the same test signal is provided to the display area of ​​the display product through the test circuit, the test signal received by the display area of ​​the display product has high uniformity, which effectively improves the accuracy of the display product test.

[0114] like Figure 2 and Figure 3b As shown, in some embodiments, the width h6 of the third portion of the third test signal line 3 along the direction perpendicular to the first direction can be set to be smaller than the width h3 of the fourth portion of the third test signal line 3 along the direction perpendicular to the second direction; the width h4 of the fourth test signal line 4 along the direction perpendicular to the second direction can be set to be smaller than the width h3 of the fourth portion of the third test signal line 3 along the direction perpendicular to the second direction.

[0115] Specifically, the total lengths of the third test signal line 3 and the fourth test signal line 4 in the second direction may be set to be the same. Since the fourth test signal line 4 extends along the second direction, that is, it only includes a portion extending along the second direction, and the third test signal line 3 includes a third portion extending along the first direction and a fourth portion extending along the second direction, the routing stroke of the third test signal line 3 is greater than the routing stroke of the fourth test signal line 4. In this way, when setting the line widths of the third test signal line 3 and the fourth test signal line 4, the third portion of the third test signal line 3 may be set to extend in a direction perpendicular to the first direction. The width of the fourth test signal line 4 along the direction perpendicular to the second direction is smaller than the width of the fourth part of the third test signal line 3 along the direction perpendicular to the second direction, so that the difference between the resistance of the third test signal line 3 and the resistance of the fourth test signal line 4 is smaller than the first threshold value, so that the voltage drop difference of each test signal line is smaller, and when the same test signal is provided to the display area of ​​the display product through the test circuit, the test signal received by the display area of ​​the display product has higher uniformity, which effectively improves the accuracy of the display product test.

[0116] like Figure 2 As shown, in some embodiments, the width h1 of the first test signal line 1 along the direction perpendicular to the second direction can be set to be equal to the width h4 of the fourth test signal line 4 along the direction perpendicular to the second direction; the width h2 of the second part of the second test signal line 2 along the direction perpendicular to the second direction, and the width h3 of the fourth part of the third test signal line 3 along the direction perpendicular to the second direction are both greater than the width h1 of the first test signal line 1 along the direction perpendicular to the second direction.

[0117] Specifically, the above-mentioned setting method makes the resistance value of the first test signal line 1 and the resistance value of the fourth test signal line 4 basically consistent, and because the routing distance of the second test signal line 2 and the third test signal line 3 is greater than the routing distance of the first test signal line 1 and the fourth test signal line 4, by setting the width of the second part of the second test signal line 2 along the second direction perpendicular to the second direction, and the width of the fourth part of the third test signal line 3 along the second direction perpendicular to the second direction, both are greater than the width of the first test signal line 1 along the second direction perpendicular to the second direction, the resistance value of the second test signal line 2 and the third test signal line 3 is closer to the resistance value of the first test signal line 1, which is more conducive to achieving the uniformity of the resistance value of each test signal line in the test circuit.

[0118] It can be seen that when setting the line widths of the first test signal line 1, the second test signal line 2, the third test signal line 3 and the fourth test signal line in the above manner, it is only necessary to consider the routing distance of the third test signal line 3, the fourth test signal line 4, and the routing distance of one of the first test signal line 1 and the fourth test signal line 4, which is more conducive to achieving a resistance difference between each test signal line that is less than the first threshold.

[0119] like Figure 1 As shown, in some embodiments, each of the test circuits further includes: a first test sub-circuit CT1, wherein the first test sub-circuit CT1 includes:

[0120] a fourth test unit, wherein the orthographic projection of the fourth test unit on the substrate is located between the orthographic projection of the second test signal line 2 on the substrate and the orthographic projection of the third test signal line 3 on the substrate; an output end of the fourth test unit is coupled to the third test signal line 3, and is used to output the first picture test signal and the second picture test signal to the third test signal line 3 in a time-sharing manner;

[0121] A fifth test unit, the orthographic projection of the fifth test unit on the substrate is located between the orthographic projection of the third test signal line 3 on the substrate and the orthographic projection of the fourth test signal line 4 on the substrate; the output end of the fifth test unit is coupled to the fourth test signal line 4, for outputting a third picture test signal to the fourth test signal line 4.

[0122] Each of the test circuits further comprises: a second test sub-circuit CT2, wherein the second test sub-circuit CT2 comprises:

[0123] A sixth test unit, the orthographic projection of the sixth test unit on the substrate is located between the orthographic projection of the third test signal line 3 on the substrate and the orthographic projection of the fourth test signal line 4 on the substrate; the output end of the sixth test unit is respectively coupled to the third test signal line 3 and the fourth test signal line 4, for simultaneously outputting the same functional test signal to the third test signal line 3 and the fourth test signal line 4.

[0124] Specifically, the working process of the first test sub-circuit CT1 of the above structure is as follows:

[0125] In the first test period, the fourth test unit writes a first picture test signal to the third test signal line 3, and the fifth test unit writes a third picture test signal to the fourth test signal line 4, so as to implement a first picture test on the display substrate.

[0126] In the second test period, the fourth test unit writes a second picture test signal to the third test signal line 3, and the fifth test unit writes a third picture test signal to the fourth test signal line 4, so as to implement a second picture test on the display substrate.

[0127] Exemplarily, the first picture test signal includes a blue pixel test signal, the second picture test signal includes a red pixel test signal, and the third picture test signal includes a green pixel test signal. During the first test period, a GB picture test is performed on the display substrate, and during the second test period, a GR picture test is performed on the display substrate.

[0128] The fourth test unit and the fifth test unit of the above structure can perform display screen tests of different screens on the display substrate in a time-sharing manner, thereby achieving more accurate detection of the display performance of the display substrate.

[0129] The working process of the sixth test unit of the above structure is as follows:

[0130] In the same test period, the sixth test unit writes the same functional test signal to the third test signal line 3 and the fourth test signal line 4 respectively. Taking the high level of the functional test signal as an example, when the functional test signal is written into the display area of ​​the display substrate, the display area normally displays a black screen. If there is an abnormality in the display area (such as a signal line disconnection), a low level appears at the abnormal position, causing the pixel corresponding to the abnormal position to light up, and an abnormal bright spot appears in the display area. According to the position of the abnormal bright spot, the abnormal position of the display substrate can be determined.

[0131] The sixth test unit can detect whether there are abnormal conditions such as broken wires or poor contact in the display substrate.

[0132] like Figure 2 and Figure 3b As shown, in some embodiments, the third test signal line 3 includes a twelfth conductive pattern 32, a thirteenth conductive pattern 33, a fourteenth conductive pattern 34, a fifteenth conductive pattern 35, a sixteenth conductive pattern 36 and a seventeenth conductive pattern 37 coupled in sequence;

[0133] The third portion of the third test signal line 3 includes a thirteenth conductive pattern 33, a fifteenth conductive pattern 35 and a seventeenth conductive pattern 37, and the fourth portion of the third test signal line 3 includes a twelfth conductive pattern 32, a fourteenth conductive pattern 34 and a sixteenth conductive pattern 36;

[0134] The fifteenth conductive pattern 35 , the sixteenth conductive pattern 36 , and the seventeenth conductive pattern 37 together with the second test signal line 2 define a second accommodation space 82 , and at least a portion of the second test unit is located in the second accommodation space 82 .

[0135] Specifically, since the fifteenth conductive pattern 35 and the seventeenth conductive pattern 37 extend along the first direction, the sixteenth conductive pattern 36 extends along the second direction, and the fifteenth conductive pattern 35, the sixteenth conductive pattern 36 and the seventeenth conductive pattern 37 are coupled in sequence, the fifteenth conductive pattern 35, the sixteenth conductive pattern 36 and the seventeenth conductive pattern 37 can be formed into a second groove structure, and the opening of the second groove structure is directed toward the second test signal line 2. The second groove structure can form the second accommodating space 82 between the second test signal line 2. When laying out the second test unit, the second test unit can be laid out in the second accommodating space 82 to reduce the layout space occupied by the entire test circuit.

[0136] like Figure 2 and Figure 3b As shown, in some embodiments, the thirteenth conductive pattern 33, the fourteenth conductive pattern 34, the fifteenth conductive pattern 35 and the fourth test signal line 4 jointly define a fifth accommodation space 85, and at least part of the fifth test unit is located in the fifth accommodation space 85;

[0137] Along the second direction, the fifth accommodating space 85 is located between the first accommodating space 81 and the second accommodating space 82 , and the fourth testing unit is located on a side of the first accommodating space 81 away from the fifth accommodating space 85 .

[0138] Specifically, since the thirteenth conductive pattern 33 and the fifteenth conductive pattern 35 extend along the first direction, the fourteenth conductive pattern 34 extends along the second direction, and the thirteenth conductive pattern 33, the fourteenth conductive pattern 34 and the fifteenth conductive pattern 35 are coupled in sequence, the thirteenth conductive pattern 33, the fourteenth conductive pattern 34 and the fifteenth conductive pattern 35 can be formed into a fifth groove structure, and the opening of the fifth groove structure is directed toward the fourth test signal line 4. The fifth groove structure can form the fifth accommodating space 85 between the fourth test signal line 4. When laying out the fifth test unit, the fifth test unit can be laid out in the fifth accommodating space 85 to reduce the layout space occupied by the entire test circuit.

[0139] In addition, the above-mentioned setting is along the second direction, the fifth accommodating space 85 is located between the first accommodating space 81 and the second accommodating space 82, and the fourth test unit is located on the side of the first accommodating space 81 away from the fifth accommodating space 85, so that along the second direction, the fourth test unit, the first test unit, the fifth test unit and the second test unit are arranged in sequence, thereby minimizing the layout space of the first test sub-circuit CT1 along the first direction.

[0140] like Figure 2 and Figure 3b As shown, in some embodiments, the third test signal line 3 includes an eighteenth conductive pattern 38, a nineteenth conductive pattern 39, and a twentieth conductive pattern 40 coupled in sequence;

[0141] The third portion of the third test signal line 3 includes the nineteenth conductive pattern 39, and the fourth portion of the third test signal line 3 includes the eighteenth conductive pattern 38 and the twentieth conductive pattern 40;

[0142] The nineteenth conductive pattern 39 , the twentieth conductive pattern 40 and the fourth test signal line 4 jointly define a sixth accommodation space 86 , and at least a portion of the sixth test unit is located in the sixth accommodation space 86 .

[0143] Specifically, since the nineteenth conductive pattern 39 extends along the first direction, the twentieth conductive pattern 40 extends along the second direction, and the nineteenth conductive pattern 39 and the twentieth conductive pattern 40 are coupled sequentially, the sixth accommodating space 86 can be formed between the nineteenth conductive pattern 39, the twentieth conductive pattern 40 and the fourth test signal line 4. When laying out the sixth test unit, the sixth test unit can be laid out in the sixth accommodating space 86 to reduce the layout space occupied by the entire test circuit.

[0144] In the display substrate provided in the above embodiment, the test circuit is formed as a double-row structure, which includes a row formed by the first test signal line 1, the second test signal line 2, the first test unit, the second test unit and the third test unit, and another row formed by the third test signal line 3, the fourth test signal line 4, the fourth test unit, the fifth test unit and the sixth test unit. The test circuit with this double-row structure can be further away from the bending area of ​​the display substrate during layout, so that when bending occurs in the bending area, the influence of the bending on the functional graphics in the test circuit can be reduced, thereby effectively improving the yield of the test circuit.

[0145] In order to more clearly illustrate the specific structure and width setting method of each test signal line included in the test circuit in the display substrate provided by the above embodiment, a specific embodiment is given below.

[0146] like Figure 2 As shown, in the display substrate provided by the above embodiment, the test circuit includes the first test signal line 1, the second test signal line 2, the third test signal line 3 and the fourth test signal line 4 which are arranged in sequence along the first direction; the test circuit includes a first corner area A, a second corner area B and a third corner area C, and the second test signal line 2 in the test circuit includes the first part and the second part in the first corner area A, the second corner area B and the third corner area C; the third test signal line 3 in the test circuit includes the third part and the fourth part in the second corner area B and the third corner area C.

[0147] When laying out the test signal lines in the test circuit, the first test signal line 1 and the third test signal line 3 may be laid out using the first gate metal layer, and the second test signal and the fourth test signal line 4 may be laid out using the second gate metal layer, which is more conducive to reducing the possibility of short circuits between adjacent test signal lines.

[0148] When performing uniform resistance compensation on each test signal line, width compensation can be performed on the first part of the second test signal line 2 located in the first corner area A, the second corner area B and the third corner area C, and width compensation can be performed on the second part of the third test signal line 3 in the second corner area B and the third corner area C.

[0149] In more detail, the width of the first test signal line 1 in the direction perpendicular to the second direction can be set between 2.5μm and 3.5μm; the width of the fourth test signal line 4 in the direction perpendicular to the second direction can be set between 2.5μm and 3.5μm; the width of the second part of the second test signal line 2 in the direction perpendicular to the second direction can be set between 3μm and 4μm, and the width of the first part of the second test signal line 2 in the direction perpendicular to the first direction is smaller than the width of the second part of the second test signal line 2 in the direction perpendicular to the second direction; the width of the fourth part of the third test signal line 3 in the direction perpendicular to the second direction can be set between 3.5μm and 4.5μm, and the width of the third part of the third test signal line 3 in the direction perpendicular to the first direction is smaller than the width of the fourth part of the third test signal line 3 in the direction perpendicular to the second direction.

[0150] Exemplarily, the width of the first test signal line 1 in the direction perpendicular to the second direction can be set to 3μm, the width of the fourth test signal line 4 in the direction perpendicular to the second direction can be set to 3μm, the width of the second part of the second test signal line 2 in the direction perpendicular to the second direction can be set to 3.5μm, and the width of the fourth part of the third test signal line 3 in the direction perpendicular to the second direction can be set to 4μm.

[0151] By compensating the line width of each test signal line, the resistance uniformity compensation of each test signal line is achieved. When each test signal line is set to adopt the above line width, the beneficial effects are as follows:

[0152] like Figure 4 and Figure 5 , as shown in Table 1 below, through resistance simulation calculation, before resistance uniformization compensation, the resistance of the first test signal line 1 is 176.78, the resistance of the second test signal line 2 is 188.75, the resistance of the third test signal line 3 is 190.36, and the resistance of the fourth test signal line 4 is 176.36. Among these four test signal lines, the difference between the maximum resistance and the minimum resistance is 14Ω; after resistance uniformization compensation, the resistance of the first test signal line 1 is 176.78, the resistance of the second test signal line 2 is 176.09, the resistance of the third test signal line 3 is 176.68, and the resistance of the fourth test signal line 4 is 176.36. Among these four test signal lines, the difference between the maximum resistance and the minimum resistance is 0.69Ω.

[0153] Gate line 1 2 3 4 Δ(Max-Min) Before compensation(Ω) 176.78 188.75 190.36 176.36 14 After compensation(Ω) 176.78 176.09 176.68 176.36 0.69

[0154] Table 1

[0155] It can be seen from the obvious effect of the resistance change of the four test signal lines before and after compensation that there is a sudden change in the resistance between the four test signal lines before compensation, and the resistance change range is approximately between 170Ω and 190Ω, and the maximum resistance difference is approximately 14Ω. After compensation, the resistance relationship curve between the four signal lines is relatively smooth and the resistance fluctuation range is small, basically maintained at around 176Ω (176Ω is the core resistance of the test signal line, and each test signal line should be close to 176Ω). It should be noted that the Gate line in Table 1 represents the test signal line.

[0156] like Figure 1As shown, the layout of the first test sub-circuit CT1 and the second test sub-circuit CT2 are various. In some embodiments, the first test sub-circuit CT1 and the second test sub-circuit CT2 are arranged along the second direction, and the first test sub-circuit CT1 is located between the display area and the second test sub-circuit CT2, or the second test sub-circuit CT2 is located between the display area and the first test sub-circuit CT1.

[0157] Specifically, since the second test sub-circuit CT2 is generally connected to the multiplexer (MUX) in the display substrate, when the first test sub-circuit CT1 is set between the display area and the second test sub-circuit CT2, it is not only more convenient to couple the second test sub-circuit CT2 with the MUX, but also, when the display substrate is used to form a display module, the distance between the MUX and the antenna in the display module can be made farther, thereby effectively reducing the interference caused by the antenna to the MUX, making it easier to attach the absorbing material in the module process section, and also effectively reducing the signal interference caused by the antenna to the test circuit, thereby better improving the test efficiency and test accuracy of the test circuit to the display substrate.

[0158] like Figure 1 and Figure 2 As shown, in some embodiments, the test structure CT further includes: a first control signal line SW1, a second control signal line SW2, a third control signal line SW3, a fourth control signal line SW4, a fifth control signal line SW5, a sixth control signal line SW6 and a seventh control signal line SW7, all extending along the first direction; and a first test data line D1, a second test data line D2, a third test data line D3, a fourth test data line D4, a fifth test data line D5, a sixth test data line D6, a seventh test data line D7 and an eighth test data line D8, all extending along the first direction;

[0159] The plurality of test signal lines further include a third test signal line 3 and a fourth test signal line 4;

[0160] Each of the test circuits includes a first test subcircuit CT1 and a second test subcircuit CT2; the first test subcircuit CT1 includes a first test unit, a second test unit, a third test unit and a fourth test unit; the second test subcircuit CT2 includes a fifth test unit and a sixth test unit;

[0161] The first test unit includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 is coupled to the second control signal line SW2, the first electrode of the first transistor T1 is coupled to the third test data line D3, and the second electrode of the first transistor T1 is coupled to the first test signal line 1;

[0162] The gate of the second transistor T2 is coupled to the third control signal line SW3, the first electrode of the second transistor T2 is coupled to the fourth test data line D4, and the second electrode of the second transistor T2 is coupled to the first test signal line 1;

[0163] The second test unit includes a third transistor T3, a gate of the third transistor T3 is coupled to the fifth control signal line SW5, a first electrode of the third transistor T3 is coupled to the sixth test data line D6, and a second electrode of the third transistor T3 is coupled to the second test signal line 2;

[0164] The fourth test unit includes a fourth transistor T4 and a fifth transistor T5, the gate of the fourth transistor T4 is coupled to the first control signal line SW1, the first electrode of the fourth transistor T4 is coupled to the first test data line D1, and the second electrode of the fourth transistor T4 is coupled to the third test signal line 3;

[0165] The gate of the fifth transistor T5 is coupled to the second control signal line SW2, the first electrode of the fifth transistor T5 is coupled to the second test data line D2, and the second electrode of the fifth transistor T5 is coupled to the third test signal line 3;

[0166] The fifth test unit includes a sixth transistor T6, a gate of the sixth transistor T6 is coupled to the fourth control signal line SW4, a first electrode of the sixth transistor T6 is coupled to the fifth test data line D5, and a second electrode of the sixth transistor T6 is coupled to the fourth test signal line 4;

[0167] The third test unit includes a seventh transistor T7 and an eighth transistor T8, the gate of the seventh transistor T7 and the gate of the eighth transistor T8 are both coupled to the sixth control signal line SW6, the first electrode of the seventh transistor T7 and the first electrode of the eighth transistor T8 are both coupled to the seventh test data line D7, the second electrode of the seventh transistor T7 is coupled to the first test signal line 1, and the second electrode of the eighth transistor T8 is coupled to the second test signal line 2;

[0168] The sixth test unit includes a ninth transistor T9 and a tenth transistor T10, the gate of the ninth transistor T9 and the gate of the tenth transistor T10 are both coupled to the seventh control signal line SW7, the first electrode of the ninth transistor T9 and the first electrode of the tenth transistor T10 are both coupled to the eighth test data line D8, the second electrode of the ninth transistor T9 is coupled to the third test signal line 3, and the second electrode of the tenth transistor T10 is coupled to the fourth test signal line 4.

[0169] Specifically, the first test data line D1 and the third test data line D3 are both used to transmit the first picture test signal; the second test data line D2 and the fourth test data line D4 are both used to transmit the second picture test signal; the fifth test data line D5 and the sixth test data line D6 are both used for the third picture test signal; the seventh test data line D7 and the eighth test data line D8 are both used to transmit the functional test signal.

[0170] The test circuit of the above structure includes the following working process when working:

[0171] In the first test period, under the control of the second control signal transmitted by the second control signal line SW2, the first transistor T1 is turned on, and the first picture test signal transmitted by the third test data line D3 is written into the first test signal line 1; under the control of the first control signal transmitted by the first control signal line SW1, the fourth transistor T4 is turned on, and the first picture test signal transmitted by the first test data line D1 is written into the third test signal line 3; under the control of the fifth control signal transmitted by the fifth control signal line SW5, the third transistor T3 is turned on, and the third picture test signal transmitted by the sixth test data line D6 is written into the second test signal line 2.

[0172] In the second test period, under the control of the third control signal transmitted by the third control signal line SW3, the second transistor T2 is turned on, and the second picture test signal transmitted by the fourth test data line D4 is written into the first test signal line 1; under the control of the second control signal transmitted by the second control signal line SW2, the fifth transistor T5 is turned on, and the second picture test signal transmitted by the second test data line D2 is written into the third test signal line 3; under the control of the fourth control signal transmitted by the fourth control signal line SW4, the sixth transistor T6 is turned on, and the third picture test signal transmitted by the fifth test data line D5 is written into the fourth test signal line 4.

[0173] In the third test period, under the control of the sixth control signal transmitted by the sixth control signal line SW6, the seventh transistor T7 and the eighth transistor T8 are both turned on, and the functional test signal transmitted by the seventh test data line D7 is written into the first test signal line 1 and the second test signal line 2; under the control of the seventh control signal transmitted by the seventh control signal line SW7, the ninth transistor T9 and the tenth transistor T10 are both turned on, and the functional test signal transmitted by the eighth test data line D8 is written into the third test signal line 3 and the fourth test signal line 4.

[0174] It should be noted that the sequence of the first test period, the second test period and the third test period can be set according to actual needs.

[0175] It is worth noting that Figure 2 As shown, when the test circuit adopts the above structure, the test circuit can be laid out using the following four film layers: an active layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer are stacked in sequence in the direction away from the base of the display substrate; wherein the active layer is used to form the active layer of each of the transistors, the first gate metal layer is used to form the second test signal line 2, the fourth test signal line 4, the gate of each of the transistors and the first and second electrodes of some transistors; the second gate metal layer is used to form the first test signal line 1, the third test signal line 3 and the first and second electrodes of some transistors; the source-drain metal layer is used to form the first and second electrodes of some transistors, each of the control signal lines and each of the control signal lines.

[0176] like Figure 6 and Figure 7 As shown, in some embodiments, the display substrate further includes:

[0177] A plurality of data signal lines located in the display area, the data signal lines corresponding to the test signal lines one by one;

[0178] a plurality of first fan-out lines 7 located in the non-display area, wherein the first fan-out lines 7 correspond to the data signal lines one by one, and the data signal lines are coupled to the corresponding test signal lines through the corresponding first fan-out lines 7; the plurality of first fan-out lines 7 form a plurality of sub-fan-out areas arranged along the first direction, and each sub-fan-out area includes a plurality of the first fan-out lines 7;

[0179] A plurality of power signal line patterns, each of which has an orthographic projection on the substrate located between the orthographic projections of two adjacent sub-fan-out areas on the substrate, a plurality of first fan-out lines 7 located on the same side of the central axis 6 of the display substrate, have resistance values ​​gradually increasing in a direction approaching the central axis 6, a difference in resistance values ​​between any two adjacent first fan-out lines is less than a second threshold, and the central axis 6 extends in a direction parallel to the second direction.

[0180] Specifically, the display substrate further includes a plurality of data signal lines located in the display area. Exemplarily, the plurality of data signal lines all extend along the second direction, and the data signal lines correspond to the test signal lines one by one.

[0181] The display substrate further includes a plurality of first fan-out lines 7 located in the non-display area, the orthographic projections of the plurality of first fan-out lines 7 on the substrate are located between the orthographic projections of the display area on the substrate and the orthographic projections of the test circuit on the substrate, the first fan-out lines 7 correspond one-to-one with the data signal lines, one end of the first fan-out line 7 close to the display area is coupled to the corresponding data line, and one end of the first fan-out line 7 close to the test circuit is coupled to the corresponding test signal line. The first fan-out line 7 is used to transmit the test signal provided by the corresponding test signal line to the corresponding data line.

[0182] The plurality of first fan-out lines 7 may be divided into a plurality of sub-fan-out areas arranged along the first direction, and each of the sub-fan-out areas includes a plurality of first fan-out lines 7 .

[0183] The display substrate also includes a plurality of power signal line graphics 51, and the orthographic projection of each of the power signal line graphics 51 on the substrate is located between the orthographic projections of two adjacent sub-fan-out areas on the substrate, separating the two adjacent sub-fan-out areas (such as area D and area E); since the first fan-out line 7 cannot be arranged at the power signal line graphics 51, the plurality of first fan-out lines 7 cannot be evenly arranged at equal intervals, resulting in a problem of large resistance jumps of the first fan-out lines 7 on both sides of the power signal line graphics 51.

[0184] In the display substrate provided in the above embodiment, by setting a plurality of first fan-out lines 7 located on the same side of the central axis 6 of the display substrate, the resistance gradually increases in the direction close to the central axis 6, and the difference in resistance between any two adjacent first fan-out lines is less than the second threshold value, so that the resistance of the plurality of first fan-out lines 7 changes uniformly, avoiding the problem of large resistance jumps of the first fan-out lines 7 on both sides of the power signal line graph. It should be noted that the second threshold value can be set according to actual needs. For example, the second threshold value is between 0.5Ω and 10Ω, and may include an endpoint value.

[0185] It should be noted that the difference in resistance between any two adjacent first fan-out lines is less than the second threshold, that is, the resistances of any two adjacent first fan-out lines are essentially equal.

[0186] like Figure 6 and Figure 7 As shown, in some embodiments, each of the first fan-out lines 7 includes: a first fan-out pattern 71 and a second fan-out pattern 72 coupled to each other, the first fan-out pattern 71 is located between the display area and the second fan-out pattern 72, the first fan-out pattern 71 extends along the second direction, the second fan-out pattern 72 extends along a third direction, and the third direction intersects with the second direction;

[0187] On the same side of the central axis 6, along the direction close to the central axis 6 of the display substrate, the width of the first fan-out pattern 71 included in the plurality of first fan-out lines 7 located in the same sub-fan-out area gradually increases, and the width of the second fan-out pattern 72 included in the plurality of first fan-out lines 7 located in the same sub-fan-out area is the same;

[0188] On the same side of the central axis 6, in two adjacent sub-fan-out areas, the width of the first fan-out pattern 71 farthest from the central axis 6 in the sub-fan-out area E close to the central axis 6 is greater than the width of the first fan-out pattern 71 closest to the central axis 6 in the sub-fan-out area D far from the central axis 6; the difference between the width of the first fan-out pattern 71 farthest from the central axis 6 in the sub-fan-out area E close to the central axis 6 and the width of the first fan-out pattern 71 closest to the central axis 6 in the sub-fan-out area D far from the central axis 6 is greater than a third threshold;

[0189] The width of the first fan-out pattern 71 is the width of the first fan-out pattern 71 perpendicular to the second direction; the width of the second fan-out pattern 72 is the width of the second fan-out pattern 72 perpendicular to the third direction.

[0190] Specifically, each of the first fan-out lines 7 includes: a third fan-out pattern 73, a first fan-out pattern 71 and a second fan-out pattern 72 coupled in sequence, the third fan-out pattern 73 and the first fan-out pattern 71 are made of the same layer and the same material, specifically, they can be made of the first gate metal layer and / or the second gate metal layer, the second fan-out pattern 72 and the power signal line pattern 51 are made of the same layer of source and drain metal layer; at the same time, the first fan-out pattern 71 can be set between the display area and the second fan-out pattern 72, the first fan-out pattern 71 extends along the second direction, the second fan-out pattern 72 extends along the third direction, the third direction intersects with the second direction, and exemplarily, the angle between the third direction and the second direction is less than 90 degrees.

[0191] Furthermore, the extension direction of the power signal line pattern can be set to be the same as the extension direction of the second fan-out pattern 72, and the orthographic projections of the power signal line pattern on the substrate are located in two adjacent sub-fan-out areas, and the second fan-out pattern 72 is between the orthographic projections on the substrate.

[0192] Since the second fan-out pattern 72 and the power signal line pattern 51 are both made of the same source and drain metal layer, the power signal line pattern 51 will block the adjacent sub-fan-out areas, making it impossible for the first fan-out lines 7 to be evenly arranged at equal intervals, and the routing distance of the first fan-out lines 7 cannot be evenly increased, resulting in a large jump in the resistance value of the first fan-out lines 7 located on the left and right sides of the power signal line pattern 51.

[0193] The above-mentioned arrangement is performed on the same side of the central axis 6, along the direction close to the central axis 6 of the display substrate, the width of the first fan-out pattern 71 included in the plurality of first fan-out lines 7 located in the same sub-fan-out area gradually increases, and the width of the second fan-out pattern 72 included in the plurality of first fan-out lines 7 located in the same sub-fan-out area is the same; on the same side of the central axis 6, in two adjacent sub-fan-out areas, the width of the first fan-out pattern 71 farthest from the central axis 6 in the sub-fan-out area E close to the central axis 6 is greater than the width of the first fan-out pattern 71 in the sub-fan-out area D far from the central axis 6, which is closest to the central axis 6. The width of a fan-out pattern 71; the difference between the width of the first fan-out pattern 71 farthest from the central axis 6 in the sub-fan-out area E close to the central axis 6 and the width of the first fan-out pattern 71 closest to the central axis 6 in the sub-fan-out area D far from the central axis 6 is greater than a third threshold; it is possible to achieve that on the same side of the central axis 6, along the direction close to the central axis 6 of the display substrate, the resistance of all the first fan-out lines 7 included in the display substrate gradually increases, so that the resistance of the multiple first fan-out lines 7 changes evenly, avoiding the problem of large resistance jumps in the first fan-out lines 7 on both sides of the power signal line pattern.

[0194] Therefore, in the display substrate provided in the above embodiment, the resistance value of the first fan-out line 7 is compensated by adjusting the width of the second fan-out pattern 72, so that the test signal line in the test circuit and the first fan-out line 7 connected between the data line and the test signal line have good resistance uniformity, thereby greatly improving the accuracy of the test circuit's test of the display substrate and better ensuring the production yield of the display substrate.

[0195] It should be noted that the value range of the third threshold can satisfy the requirement that the difference in resistance between any two adjacent first fan-out lines is less than the second threshold.

[0196] In more detail, Figure 8 and Fig. 9As shown in Table 2 below, before compensation, due to the obstruction of the power signal line pattern, the average resistance value of the first fan-out line 7 in the D area to the average resistance value of the first fan-out line 7 in the E area has a large jump, such as: the average resistance value of the D area is 3502Ω, the average resistance value of the E area is 3549Ω, and the average resistance value jump from the D area to the first fan-out line 7 in the E area is close to 50Ω, and the resistance change is 1.34%;

[0197] Through calculation simulation, after using width uniformization compensation, there is a small jump from the average resistance value of the first fan-out line 7 in area D to the average resistance value of the first fan-out line 7 in area E, such as: the average resistance value in area D is 3340Ω, and the average resistance value in area E is 3348Ω; the change between resistance traces after uniformization compensation is relatively smooth, and the change is about 0.24% (the core point of the change).

[0198] D E Δ Δ / D Before compensation(Ω) 3502 3549 47 1.34％ After compensation(Ω) 3340 3348 8 0.24％

[0199] Table 2

[0200] It should be noted that the display substrate may further include an intermediate power signal line pattern 52 located at the central axis 6. Since the first fan-out lines 7 are symmetrically distributed on both sides of the central axis 6, the routing distance of the first fan-out lines 7 in the fan-out sub-areas (i.e., F areas) adjacent to the left and right sides of the intermediate power signal line pattern 52 and the width of the second fan-out pattern 72 included therein are the same, so that the average resistance values ​​of the first fan-out lines 7 in the fan-out sub-areas adjacent to the left and right sides of the intermediate power signal line pattern 52 are basically the same, and no large jumps occur.

[0201] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0202] Due to the display substrate provided by the above embodiment, by setting the width of the first part of the second test signal line 2 in a direction perpendicular to the first direction to be different from the width of the first test signal line 1 in a direction perpendicular to the second direction; and the width of the second part of the second test signal line 2 in a direction perpendicular to the second direction to be different from the width of the first test signal line 1 in a direction perpendicular to the second direction, the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is smaller than the first threshold value, so that the voltage drop difference of each test signal line is smaller, when the same test signal is provided to the display area of ​​the display product through the test circuit, the test signal received by the display area of ​​the display product has higher uniformity, which effectively improves the accuracy of the display product testing.

[0203] Therefore, when the display device provided by the embodiment of the present invention includes the display substrate provided by the above embodiment, it also has the above beneficial effects, which will not be described in detail here.

[0204] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0205] An embodiment of the present invention further provides a method for manufacturing a display substrate, which is used to manufacture the display substrate provided in the above embodiment. The manufacturing method includes:

[0206] A test structure CT is fabricated in a non-display area of ​​the display substrate, the test structure CT comprising a plurality of test circuits arranged along a first direction, each of the test circuits comprising: a plurality of test signal lines, the plurality of test signal lines comprising a first test signal line 1 and a second test signal line 2, the first test signal line 1 extending along a second direction, the second test signal line 2 comprising a first portion extending along the first direction and a second portion extending along the second direction, the second direction intersecting the first direction; a width of the first portion of the second test signal line 2 in a direction perpendicular to the first direction is different from a width of the first test signal line 1 in a direction perpendicular to the second direction; a width of the second portion of the second test signal line 2 in a direction perpendicular to the second direction is different from a width of the first test signal line 1 in a direction perpendicular to the second direction; a difference between a resistance of the first test signal line 1 and a resistance of the second test signal line 2 is less than a first threshold value.

[0207] Specifically, the display substrate includes a display area AA and a non-display area surrounding the display area AA. Exemplarily, the non-display area includes a first fan-out area N, a test structure CT setting area, a second fan-out area M and a chip binding area (not shown in the figure) arranged in sequence along a direction away from the display area AA. The non-display area also includes a bending area G, which overlaps with the first fan-out area N and is located inside the first fan-out area N.

[0208] Each of the test circuits may include a plurality of test signal lines. For example, the plurality of test signal lines may include a first test signal line 1 and a second test signal line 2 of different shapes, wherein the first test signal line 1 extends along a second direction, and the second direction may be the same as the extension direction of the data line in the display substrate, but is not limited thereto; the second test signal line 2 may include a first portion extending along the first direction and a second portion extending along the second direction, and the first direction may include a plurality of directions intersecting with the second direction, such as: the first direction is perpendicular to the second direction; or the angle between the first direction and the second direction is less than 90 degrees. In addition, the first direction may be set as the X direction, and the second direction may be set as the Y direction.

[0209] By adjusting the width of the first test signal line 1 in a direction perpendicular to the second direction, the width of the first part of the second test signal line 2 in a direction perpendicular to the first direction, and the width of the second part of the second test signal line 2 in a direction perpendicular to the second direction, the resistance of the first test signal line 1 and the resistance of the second test signal line 2 are adjusted, so that the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is less than a first threshold.

[0210] It should be noted that the first threshold value can be set according to actual needs, and illustratively, the first threshold value is 1Ω. In addition, the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is less than the first threshold value, that is, the resistance of the first test signal line 1 and the resistance of the second test signal line 2 are essentially equal.

[0211] In the display substrate manufactured by the manufacturing method provided by the embodiment of the present invention, by setting the width of the first part of the second test signal line 2 in a direction perpendicular to the first direction to be different from the width of the first test signal line 1 in the direction perpendicular to the second direction; and the width of the second part of the second test signal line 2 in a direction perpendicular to the second direction to be different from the width of the first test signal line 1 in the direction perpendicular to the second direction, the difference between the resistance of the first test signal line 1 and the resistance of the second test signal line 2 is smaller than the first threshold value, so that the voltage drop difference of each test signal line is smaller, and when the same test signal is provided to the display area of ​​the display product through the test circuit, the test signal received by the display area of ​​the display product has high uniformity, which effectively improves the accuracy of testing the display product.

[0212] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0213] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0214] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0215] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0216] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: The display substrate further comprises a display area and a non-display area located around the display area, wherein the display substrate further comprises a test structure located in the non-display area, wherein the test structure comprises a plurality of test circuits arranged along a first direction, and each of the test circuits comprises: a plurality of test signal lines, the plurality of test signal lines comprising a first test signal line and a second test signal line, the first test signal line extending along a second direction, the second test signal line comprising a first portion extending along the first direction and a second portion extending along the second direction, the second direction intersecting the first direction; The width of the first part of the second test signal line in a direction perpendicular to the first direction is different from the width of the first test signal line in the direction perpendicular to the second direction; the width of the second part of the second test signal line in a direction perpendicular to the second direction is different from the width of the first test signal line in the direction perpendicular to the second direction; the difference between the resistance of the first test signal line and the resistance of the second test signal line is less than a first threshold.

2. The display substrate according to claim 1, characterized in that: The width of the first portion of the second test signal line along a direction perpendicular to the first direction is smaller than the width of the second portion of the second test signal line along the direction perpendicular to the second direction; the width of the first test signal line along the direction perpendicular to the second direction is smaller than the width of the second portion of the second test signal line along the direction perpendicular to the second direction.

3. The display substrate according to claim 1, characterized in that: Each of the test circuits further comprises: a first test sub-circuit, wherein the first test sub-circuit comprises: a first test unit, wherein the orthographic projection of the first test unit on the base of the display substrate is located between the orthographic projection of the first test signal line on the base and the orthographic projection of the second test signal line on the base; an output end of the first test unit is coupled to the first test signal line, and is used to output a first picture test signal and a second picture test signal to the first test signal line in a time-sharing manner; A second test unit, wherein the orthographic projection of the second test unit on the substrate is located on a side of the orthographic projection of the second test signal line on the substrate away from the orthographic projection of the first test signal line on the substrate; an output end of the second test unit is coupled to the second test signal line for outputting a third picture test signal to the second test signal line.

4. The display substrate according to claim 3, characterized in that: The second test signal line includes a first conductive pattern, a second conductive pattern, a third conductive pattern, a fourth conductive pattern, a fifth conductive pattern, a sixth conductive pattern and a seventh conductive pattern coupled in sequence; The first part of the second test signal line includes: the second conductive pattern, the fourth conductive pattern and the sixth conductive pattern, and the second part of the second test signal line includes: the first conductive pattern, the third conductive pattern, the fifth conductive pattern and the seventh conductive pattern; The second conductive pattern, the third conductive pattern, the fourth conductive pattern, the fifth conductive pattern and the sixth conductive pattern together with the first test signal line define a first accommodation space, and at least a portion of the first test unit is located in the first accommodation space.

5. The display substrate according to claim 1, characterized in that: Each of the test circuits further includes: a second test sub-circuit, wherein the second test sub-circuit includes: A third test unit, wherein the orthographic projection of the third test unit on the substrate of the display substrate is located between the orthographic projection of the first test signal line on the substrate and the orthographic projection of the second test signal line on the substrate; the output end of the third test unit is respectively coupled to the first test signal line and the second test signal line, for simultaneously outputting the same functional test signal to the first test signal line and the second test signal line.

6. The display substrate according to claim 5, characterized in that: The second test signal line includes: an eighth conductive pattern, a ninth conductive pattern, a tenth conductive pattern and an eleventh conductive pattern coupled in sequence; The first part of the second test signal line includes: an eighth conductive pattern and a tenth conductive pattern, and the second part of the second test signal line includes: a ninth conductive pattern and an eleventh conductive pattern; The eighth conductive pattern, the ninth conductive pattern, the tenth conductive pattern and the first test signal line together define a third accommodation space, and at least a portion of the third test unit is located in the third accommodation space.

7. The display substrate according to claim 1, characterized in that: The plurality of test signal lines further include a third test signal line and a fourth test signal line, the third test signal line includes a third portion extending along the first direction and a fourth portion extending along the second direction, and the fourth test signal line extends along the second direction; The width of the third portion of the third test signal line in a direction perpendicular to the first direction is different from the width of the fourth test signal line in a direction perpendicular to the second direction; the width of the fourth portion of the third test signal line in a direction perpendicular to the second direction is different from the width of the fourth test signal line in a direction perpendicular to the second direction; A resistance difference between any two of the first test signal line, the second test signal line, the third test signal line and the fourth test signal line is smaller than a first threshold.

8. The display substrate according to claim 7, characterized in that: A width of a third portion of the third test signal line in a direction perpendicular to the first direction is smaller than a width of a fourth portion of the third test signal line in a direction perpendicular to the second direction; A width of the fourth test signal line along a direction perpendicular to the second direction is smaller than a width of the fourth portion of the third test signal line along a direction perpendicular to the second direction.

9. The display substrate according to claim 7, characterized in that: The width of the first test signal line along the direction perpendicular to the second direction is equal to the width of the fourth test signal line along the direction perpendicular to the second direction; A width of the second portion of the second test signal line along a direction perpendicular to the second direction and a width of the fourth portion of the third test signal line along a direction perpendicular to the second direction are both greater than a width of the first test signal line along a direction perpendicular to the second direction.

10. The display substrate according to claim 7, characterized in that: Each of the test circuits further comprises: a first test sub-circuit, wherein the first test sub-circuit comprises: a fourth test unit, wherein the orthographic projection of the fourth test unit on the base of the display substrate is located between the orthographic projection of the second test signal line on the base and the orthographic projection of the third test signal line on the base; an output end of the fourth test unit is coupled to the third test signal line, and is used to output the first picture test signal and the second picture test signal to the third test signal line in a time-sharing manner; a fifth test unit, wherein the orthographic projection of the fifth test unit on the substrate is located between the orthographic projection of the third test signal line on the substrate and the orthographic projection of the fourth test signal line on the substrate; an output end of the fifth test unit is coupled to the fourth test signal line, and is used to output a third picture test signal to the fourth test signal line; Each of the test circuits further includes: a second test sub-circuit, wherein the second test sub-circuit includes: A sixth test unit, wherein the orthographic projection of the sixth test unit on the substrate is located between the orthographic projection of the third test signal line on the substrate and the orthographic projection of the fourth test signal line on the substrate; the output end of the sixth test unit is respectively coupled to the third test signal line and the fourth test signal line, for simultaneously outputting the same functional test signal to the third test signal line and the fourth test signal line.

11. The display substrate according to claim 10, characterized in that: The third test signal line includes a twelfth conductive pattern, a thirteenth conductive pattern, a fourteenth conductive pattern, a fifteenth conductive pattern, a sixteenth conductive pattern, a seventeenth conductive pattern, an eighteenth conductive pattern, a nineteenth conductive pattern and a twentieth conductive pattern coupled in sequence; The third portion of the third test signal line includes a thirteenth conductive pattern, a fifteenth conductive pattern, a seventeenth conductive pattern and the nineteenth conductive pattern, and the fourth portion of the third test signal line includes a twelfth conductive pattern, a fourteenth conductive pattern, a sixteenth conductive pattern, an eighteenth conductive pattern and a twentieth conductive pattern; The fifteenth conductive pattern, the sixteenth conductive pattern, the seventeenth conductive pattern and the second test signal line together define a second accommodation space, and at least a portion of the second test unit is located in the second accommodation space; The thirteenth conductive pattern, the fourteenth conductive pattern, the fifteenth conductive pattern and the fourth test signal line together define a fifth accommodation space, and at least part of the fifth test unit is located in the fifth accommodation space; The nineteenth conductive pattern, the twentieth conductive pattern and the fourth test signal line jointly define a sixth accommodation space, and at least a portion of the sixth test unit is located in the sixth accommodation space.

12. The display substrate according to claim 5, characterized in that: The first test subcircuit and the second test subcircuit are arranged along the second direction, the first test subcircuit is located between the display area and the second test subcircuit, or the second test subcircuit is located between the display area and the first test subcircuit.

13. The display substrate according to claim 1, characterized in that: The test structure further includes: a first control signal line, a second control signal line, a third control signal line, a fourth control signal line, a fifth control signal line, a sixth control signal line and a seventh control signal line, all extending along the first direction; and a first test data line, a second test data line, a third test data line, a fourth test data line, a fifth test data line, a sixth test data line, a seventh test data line and an eighth test data line, all extending along the first direction; The plurality of test signal lines further include a third test signal line and a fourth test signal line; Each of the test circuits includes a first test subcircuit and a second test subcircuit; the first test subcircuit includes a first test unit, a second test unit, a third test unit and a fourth test unit; the second test subcircuit includes a fifth test unit and a sixth test unit; The first test unit includes a first transistor and a second transistor, the gate of the first transistor is coupled to the second control signal line, the first electrode of the first transistor is coupled to the third test data line, and the second electrode of the first transistor is coupled to the first test signal line; The gate of the second transistor is coupled to the third control signal line, the first electrode of the second transistor is coupled to the fourth test data line, and the second electrode of the second transistor is coupled to the first test signal line; The second test unit comprises a third transistor, a gate of the third transistor is coupled to the fifth control signal line, a first electrode of the third transistor is coupled to the sixth test data line, and a second electrode of the third transistor is coupled to the second test signal line; The fourth test unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is coupled to the first control signal line, the first electrode of the fourth transistor is coupled to the first test data line, and the second electrode of the fourth transistor is coupled to the third test signal line; A gate of the fifth transistor is coupled to the second control signal line, a first electrode of the fifth transistor is coupled to the second test data line, and a second electrode of the fifth transistor is coupled to the third test signal line; The fifth test unit includes a sixth transistor, a gate of the sixth transistor is coupled to the fourth control signal line, a first electrode of the sixth transistor is coupled to the fifth test data line, and a second electrode of the sixth transistor is coupled to the fourth test signal line; The third test unit includes a seventh transistor and an eighth transistor, a gate of the seventh transistor and a gate of the eighth transistor are both coupled to the sixth control signal line, a first electrode of the seventh transistor and a first electrode of the eighth transistor are both coupled to the seventh test data line, a second electrode of the seventh transistor is coupled to the first test signal line, and a second electrode of the eighth transistor is coupled to the second test signal line; The sixth test unit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor and the gate of the tenth transistor are both coupled to the seventh control signal line, the first electrode of the ninth transistor and the first electrode of the tenth transistor are both coupled to the eighth test data line, the second electrode of the ninth transistor is coupled to the third test signal line, and the second electrode of the tenth transistor is coupled to the fourth test signal line.

14. The display substrate according to claim 1, characterized in that: The display substrate further comprises: A plurality of data signal lines located in the display area, the data signal lines corresponding to the test signal lines one by one; A plurality of first fan-out lines located in the non-display area, the first fan-out lines corresponding to the data signal lines one by one, the data signal lines being coupled to the corresponding test signal lines through the corresponding first fan-out lines; the plurality of first fan-out lines forming a plurality of sub-fan-out areas arranged along the first direction, each sub-fan-out area including a plurality of the first fan-out lines; A plurality of power signal line patterns, each of which has an orthographic projection on the substrate of the display substrate located between the orthographic projections of two adjacent sub-fan-out areas on the substrate, a plurality of the first fan-out lines located on the same side of the central axis of the display substrate, have resistance values ​​gradually increasing along a direction approaching the central axis, a difference in resistance values ​​between any two adjacent first fan-out lines is less than a second threshold, and the central axis extends in a direction parallel to the second direction.

15. The display substrate according to claim 14, characterized in that: Each of the first fan-out lines includes: a first fan-out pattern and a second fan-out pattern coupled to each other, the first fan-out pattern being located between the display area and the second fan-out pattern, the first fan-out pattern extending along the second direction, the second fan-out pattern extending along a third direction, and the third direction intersecting the second direction; On the same side of the central axis, along the direction close to the central axis of the display substrate, the widths of the first fan-out patterns included in the plurality of first fan-out lines located in the same sub-fan-out area gradually increase, and the widths of the second fan-out patterns included in the plurality of first fan-out lines located in the same sub-fan-out area are the same; On the same side of the central axis, in two adjacent sub-fan-out areas, the width of the first fan-out pattern farthest from the central axis in the sub-fan-out area close to the central axis is greater than the width of the first fan-out pattern closest to the central axis in the sub-fan-out area away from the central axis; the difference between the width of the first fan-out pattern farthest from the central axis in the sub-fan-out area close to the central axis and the width of the first fan-out pattern closest to the central axis in the sub-fan-out area away from the central axis is greater than a third threshold; The width of the first fan-out pattern is the width of the first fan-out pattern in a direction perpendicular to the second direction; the width of the second fan-out pattern is the width of the second fan-out pattern in a direction perpendicular to the third direction.

16. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 15.

17. A method for manufacturing a display substrate, characterized in that: Used to manufacture a display substrate according to any one of claims 1 to 15, the manufacturing method comprising: A test structure is fabricated in a non-display area of ​​the display substrate, the test structure comprising a plurality of test circuits arranged along a first direction, each of the test circuits comprising: a plurality of test signal lines, the plurality of test signal lines comprising a first test signal line and a second test signal line, the first test signal line extending along a second direction, the second test signal line comprising a first portion extending along the first direction and a second portion extending along the second direction, the second direction intersecting the first direction; a width of the first portion of the second test signal line in a direction perpendicular to the first direction is different from a width of the first test signal line in a direction perpendicular to the second direction; a width of the second portion of the second test signal line in a direction perpendicular to the second direction is different from a width of the first test signal line in a direction perpendicular to the second direction; and a difference between a resistance of the first test signal line and a resistance of the second test signal line is less than a first threshold value.

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