Method for multiplexing between power supply signals of voltage limited circuits

Abstract

The present disclosure provides a method for multiplexing between power supply signals of voltage-constrained circuits. In one embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit can generate a shared power signal coupled to each of the functional circuits and generate a plurality of adjustable power signals. One adjustable power signal can be coupled to a particular functional circuit of the functional circuits. The power management circuit can issue a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit can couple respective power nodes of sub-circuits of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit can also be configured to maintain an operating voltage level on the power nodes.

Description

[0001] Divisional Declaration

[0002] The present disclosure is a divisional application of the Chinese Invention Patent Application No. 201880051093.7, with the title of "Method for multiplexing between power supply signals of voltage limited circuits", filed on August 4, 2018. TECHNICAL FIELD

[0003] Embodiments described herein relate to the field of integrated circuits, and more specifically to power management of integrated circuits.

[0004] Related Art

[0005] Some integrated circuits (ICs), including some system on chips (SoCs), can include various functional circuits having different power supply voltage levels. A power rail can be utilized to provide power having a particular voltage level to a functional circuit that uses that particular voltage level. Some functional circuits can receive power from multiple power rails because different portions of a given functional circuit can use different voltage levels. For example, to conserve power, a first portion of a circuit can utilize a low voltage level when operating in a low power mode, and a higher voltage level when fully operational. A second portion of the circuit can utilize a third voltage level that is higher than the low voltage level of the first portion of the circuit in the low power mode, and a higher voltage level when fully operational.

[0006] In some cases, the first portion of the circuit can be coupled to a first power supply signal that is adjustable between the low voltage level and the higher voltage level, while the second portion of the circuit is coupled to a second power supply signal that is adjustable between the third voltage level and the higher voltage level. In the low power mode, the first power supply signal and the second power supply signal can be set to the low voltage level and the third voltage level, respectively. When the circuit is to be fully operational, the first power supply signal and the second power supply signal can both be set to the higher voltage level. If the SoC includes several circuits that utilize multiple power signals, a power supply for the SoC can generate many different power supply signals to allow each circuit to utilize the appropriate voltage level. SUMMARY

[0007] Various embodiments of a processor are disclosed. Broadly speaking, the present disclosure contemplates a system, an apparatus, and a method, where the system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit can be configured to generate a shared power signal coupled to a respective first sub-circuit included in each of the plurality of functional circuits, and generate a plurality of adjustable power signals, where one adjustable power signal of the plurality of adjustable power signals is coupled to a particular functional circuit of the plurality of functional circuits. The power management circuit can be configured to send a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage level to a second voltage level. The particular functional circuit can be configured to selectively couple a respective power node of a second sub-circuit included in the particular functional circuit to either the shared power signal or the one particular adjustable power signal based on a control signal. The particular functional circuit can also be configured to maintain an operating voltage level on the power node when selectively coupling the power node to either the shared power signal or the one particular adjustable power signal.

[0008] In another embodiment, the power management circuit can be further configured to assert the control signal in response to determining that the first voltage level is less than a voltage level of the shared power signal and the second voltage level is greater than the voltage level of the shared power signal. In another embodiment, to change the voltage level of the one particular adjustable power signal from the first voltage level to the second voltage level, the power supply circuit can be further configured to change the voltage level of the one particular adjustable power signal to an intermediate voltage level in response to the request from the power management circuit. The power management circuit can be further configured to assert the control signal to cause the particular functional circuit to selectively couple the respective power node of the second sub-circuit to the one particular adjustable power signal based on the control signal.

[0009] In one embodiment, the power supply circuit can be further configured to change the voltage level of the one particular adjustable power signal to the second voltage level in response to assertion of an acknowledgement signal. The first functional circuit can be further configured to assert the acknowledgement signal in response to determining that the second power node is coupled to the one particular adjustable power signal. In one embodiment, the intermediate voltage level can be greater than both the first voltage level and the second voltage level.

[0010] In another embodiment, another functional circuit of the plurality of functional circuits can be configured to selectively couple a respective power node of a respective second sub-circuit to either the shared power signal or another adjustable power signal based on another control signal. In another embodiment, the power management circuit is further configured to assert the other control signal in response to determining that the particular functional circuit is not transitioning between the shared power signal and the other adjustable power signal. BRIEF DESCRIPTION OF DRAWINGS

[0011] The following detailed description makes reference to the accompanying drawings, which are now briefly described.

[0012] Figure 1 A block diagram illustrating an embodiment of a SoC having multiple power rails is shown.

[0013] Figure 2 A block diagram illustrating an embodiment of a power multiplexing circuit is shown.

[0014] Figure 3 A chart illustrating an embodiment of a timing diagram showing voltage levels of various power signals associated with a SoC is shown.

[0015] Figure 4 A flowchart illustrating an embodiment of a method for multiplexing power signals in a SoC is shown.

[0016] Figure 5 A chart illustrating another embodiment of a timing diagram showing voltage levels of various power signals associated with a SoC is shown.

[0017] Figure 6 A flowchart illustrating an embodiment of a method for multiplexing power rails in a SoC using an intermediate voltage level is shown.

[0018] While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the disclosure to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include," "including," and "includes" mean including, but not limited to.

[0019] Various units, circuits, or other components can be described as being "configured to" perform a task or tasks. In such contexts, "configured to" is often used interchangeably with "having circuitry configured to." Similarly, various units, circuits, or other components can be described as "configured by" one or more components to perform a task or tasks. In such contexts, "configured by" can be used interchangeably with "having...circuitry configured by." Depiction of various components in the figures can therefore vary depending on the particular context of discussion, but such depiction does not generally dictate a particular configuration for a component. For example, an application specific integrated circuit can be configured as a processor system or other component at one time and then as another component at another time. DETAILED DESCRIPTION

[0020] A SoC can include multiple circuits, where each of the multiple circuits utilizes more than one power signal. For example, a given SoC can include three functional circuits that include digital logic circuits in conjunction with respective static random access memory (SRAM) arrays. The digital logic of each of these functional circuits can operate at a lower power voltage level than the SRAM, and thus can be coupled to a different power rail than the SRAM. Additionally, the voltage level of the power rail of each of the functional circuits can be increased and decreased to match a current performance level of each of the functional circuits. In some cases, the voltage level can change from a level lower than the level of the SRAM power rail to a level higher than the level of the SRAM power rail. In some embodiments, when the voltage level of the digital logic is higher than the voltage level of the SRAM, the voltage level of the SRAM power rail can be increased to match the level of the digital logic power rail. To accomplish this, in some embodiments, the SoC can include a power rail for each power signal utilized by each of the three functional circuits, such that in addition to any other power signals for other components of the SoC, this power generates six different power signals for the three functional circuits.

[0021] A need exists for a system to reduce the number of power signals generated by the power of functional circuits in a SoC. The disclosed embodiments can demonstrate methods and systems for transitioning a circuit from a first power rail to a second power rail without interrupting the operation of the circuit.

[0022] Many of the terms used in this disclosure are commonly used in SoC design. For clarity, the intended definition of some of these terms is as follows, unless otherwise indicated.

[0023] Metal oxide semiconductor field effect transistors (MOSFETs) describe a type of conductive device that can be used in modern digital logic designs. MOSFETs are designed in one of two basic types: n-channel and p-channel. Both n-channel and p-channel MOSFETs open a conductive path between the source and drain when a positive voltage greater than the threshold voltage of the device is applied between the gate and source.

[0024] Complementary MOSFETs (CMOS) describe a circuit designed with a mix of n-channel and p-channel MOSFETs. In a CMOS design, n-channel and p-channel MOSFETs can be arranged so that a high on the gate of a MOSFET turns on the n-channel device, i.e., opens a conductive path, and turns off the p-channel MOSFET, i.e., closes a conductive path. Conversely, a low on the gate of a MOSFET turns on the p-channel and turns off the n-channel. Also, the term "conducting" is used in components of the present disclosure. While CMOS logic is used in examples, it is noted that any suitable digital logic process can be used in the circuits described in the present disclosure.

[0025] It is noted that "high," "high level," and "high logic level" refer to a voltage large enough to turn on an n-channel MOSFET and turn off a p-channel MOSFET, while "low," "low level," and "low logic level" refer to a voltage small enough to achieve the opposite. As used herein, a "logic signal" refers to a signal that transitions between a high logic level and a low logic level. In various other embodiments, different techniques can result in different voltage levels for "low" and "high."

[0026] Embodiments shown and described herein can employ CMOS circuits. However, in various other embodiments, other suitable techniques can be employed.

[0027] Figure 1 A block diagram of an embodiment of a SoC with multiple power rails is shown. In the illustrated embodiment, SoC 101 includes power management circuit 105 and functional circuits 107 and 108. SoC 101 also includes shared power rail 121 and adjustable power rails 122 and 123. Functional circuits 107 and 108 each include respective circuit blocks 111a-b and 112a-b, and respective power switches 113 and 114. Power management circuit 105 is coupled to power supply circuit 103, which in turn provides power signals to shared power rail 121 and adjustable power rails 122 and 123. In various embodiments, SoC 101 and power supply circuit 103 can be configured for use in a computing application, such as a desktop computer, a laptop computer, a tablet computer, a smartphone, or a wearable device.

[0028] SoC 101 includes functional circuits 107 and 108. In various embodiments, functional circuits 107 and 108 can perform any of a wide variety of functions within SoC 101. For example, either of functional circuits 107 and 108 can correspond to any of a processor core, a graphics processor, an audio processor, a security processor, a network interface, a camera interface, etc. Circuit blocks 111a and 112a of functional circuits 107 and 108, respectively, are each coupled to adjustable power rails 122 and 123. Circuit blocks 111a and 112a can correspond to digital logic or other types of circuitry capable of operating over a wide range of power supply voltage levels, depending on the desired level of performance. In contrast, circuit blocks 111b and 112b can not be capable of operating at as low a supply voltage as circuit blocks 111a and 112a, respectively. Each of circuit blocks 111b and 112b is coupled to power switches 113 and 114, respectively. Note that circuit blocks 111b are shown as a collection of three blocks. In some embodiments, circuit blocks 111b can include any suitable number of circuits, each coupled to a respective output of power switch 113.

[0029] Circuit block 112b is coupled to power switch 114, and circuit blocks 111b are coupled to power switch 113. In some embodiments, power switch 113 can include a respective power switch for each of the circuit blocks included in circuit blocks 111b. Power switch 113 is coupled to shared power rail 121 and adjustable power rail 122, while power switch 114 is coupled to shared power rail 121 and adjustable power rail 123. As used herein, a “power rail” refers to a circuit node or wire that conducts a power signal to various circuits coupled to the power rail. In the illustrated embodiment, shared power rail 121 is coupled to functional circuit 107 and functional circuit 108, and can also be coupled to additional functional circuits not shown in SoC that are not shown. In operating SoC 101, the voltage level of shared power rail 121 can be held at a suitably constant voltage level. Note, however, that the constant voltage level can include some variation due to various external or internal conditions, such as switching noise from various other circuits or noise from voltage regulation circuitry used for the supply voltage signal.

[0030] Adjustable power rail 122 is coupled to functional circuit 107, and adjustable power rail 123 is coupled to functional circuit 108. In various embodiments, either or both of the adjustable power rails can be coupled to other functional circuits. SoC 101 can include additional adjustable power rails for other functional circuits. The voltage levels of adjustable power rails 122 and 123 can be varied to appropriate levels to match the current power usage of functional circuits 107 and 108, respectively. For example, when functional circuit 107 is idle or has fewer tasks to perform, the frequency of the clock signal provided to functional circuit 107 can be reduced to conserve power. In conjunction with the reduced clock frequency, the voltage level of adjustable power rail 122 can be reduced to further reduce power consumption. In contrast, when functional circuit 107 is in an active state or has many tasks to perform, the frequency of the received clock signal can be increased to increase processing performance. Prior to increasing the frequency of the received clock signal, the voltage level of adjustable power rail 122 can be increased in order to provide sufficient power for the higher operating frequency.

[0031] In the illustrated embodiment, power switches 113 and 114 each output a local power signal based on either the voltage level of shared power rail 121 or the voltage level of a respective one of adjustable power rails 122 and 123. The values of control signals 124 and 125 determine the voltage levels output by power switches 113 and 114, respectively. Power management circuit 105 generates control signals 124 and 125 based on the operating state of functional circuits 107 and 108. In various embodiments, the operating state can correspond to an idle state, an active state, a low-power state, a high-performance state, etc. The operating state can determine the particular voltage level of the local power signal in each of functional circuits 107 and 108. To set the voltage level of the respective local power signal, power management circuit 105 sends a request to power supply circuit 103 to set the voltage level of the power signal distributed via adjustable power rails 122 and 123 to correspond to the operating state of functional circuits 107 and 108. Power supply circuit 103 generates a voltage level on shared power rail 121 that is at least high enough to power any circuits coupled to shared power rail 121. In various embodiments, power management circuit 105 can request a particular voltage level for shared power rail 121, or power supply circuit 103 can be designed to output a particular voltage level for shared power rail 121.

[0032] In the illustrated embodiment, when the functional circuit 107 is in the low power state, the power management circuit 105 requests a low voltage level for the adjustable power rail 122 and asserts a value on the control signal 124 to cause the power switch 113 to output a local power signal having a voltage level based on the voltage level of the shared power rail 121. The power switch 113 can assert an acknowledgement (ack) signal 126 to indicate that the circuit block 111b has been switched to the shared power rail 121. In this low power state, the circuit block 111a operates based on the voltage level of the adjustable power rail 122, while the circuit block 111b operates based on the voltage level of the shared power rail 121, which is higher than the voltage level of the adjustable power rail 122.

[0033] At some point in time, the functional circuit 107 can be placed in a full operational state. The power management circuit 105 then sends a request to the power supply circuit 103 to increase the voltage level of the adjustable power rail 122 to provide sufficient power to the circuit block 111a. This increased voltage level can be greater than the voltage level of the shared power rail 121, and thus the power management circuit 105 can assert a value on the control signal 124 to cause the power switch 113 to output the voltage level based on the adjustable power rail 122 instead of the shared power rail 121. Since the shared power rail 121 can be coupled to circuits other than the circuit block 111b, the voltage level of the shared power rail 121 is maintained at a suitably low voltage level that provides sufficient power to any circuits that can be coupled to the shared power rail. The power switch 113 can not switch from the shared power rail 121 to the adjustable power rail 122 until the voltage level of the adjustable power rail 122 reaches or exceeds the voltage level of the shared power rail 121. When the power switch 113 switches from the shared power rail 121 to the adjustable power rail 122, each output of the power switch 113 that is coupled to a respective one of the circuit blocks 111b can be switched in a particular sequence, such as one after another, allowing the first circuit of the circuit block 111b to reach the new voltage level before the next circuit is switched. In various embodiments, the power switch 113 can assert a single acknowledgement signal 126 to indicate that all of the circuit blocks 111b have been switched to the adjustable power rail 122, or can assert a respective acknowledgement signal 126 (not shown) as each of the circuit blocks 111b is switched to the adjustable power rail 122.

[0034] In the illustrated embodiment, a similar process occurs when the functional circuit 107 returns from the fully operational state to the low power state. The power management circuit 105 requests a voltage level of the adjustable power rail 122 that is sufficient for the low power state. The power management circuit 105 asserts a value on the control signal 124, causing the power switch 113 to again output voltage levels based on the shared power rail 121. The power switch 113 can follow the same sequence to switch each output to the shared power rail 121, or in other embodiments, the power switch can follow an opposite or otherwise different sequence to switch each output of each of the circuit blocks 111b. Thus, the power switch 113 asserts an acknowledgement signal when the circuit blocks 111b are switched to the shared power rail 121. The functional circuit 108 follows a similar process as the power switch 114 to power the circuit blocks 112b.

[0035] In some embodiments, multiple switches in the power switch 113 can be configured to switch between the adjustable power rail 122 and the shared power rail 121 one at a time. By switching between power rails one at a time, voltage level spikes and / or voltage level drops can be avoided or reduced by staggering the switching between power rails rather than having all of the circuit blocks 111b switched between power rails in unison. For example, in the illustrated embodiment, a first switch in the power switch 113 receives a value on the control signal 124 that indicates to switch from the shared power rail 121 to the adjustable power rail 122. The first switch performs the switch on a first circuit of the circuit blocks 111b, and once complete, asserts a first acknowledgement signal. This first acknowledgement signal is received as a control signal by a second switch in the power switch 113, which indicates to switch from the shared power rail 121 to the adjustable power rail 122. In some embodiments, the first acknowledgement signal can be a delayed version of the control signal 124. The second switch performs the switch on a second circuit block, and once complete, asserts a second acknowledgement signal, which can correspond to a further delayed version of the control signal 124. A third switch in the power switch 113 receives this second acknowledgement signal, which indicates to switch from the shared power rail 121 to the adjustable power rail 122, and thus performs the switch on a third circuit block of the circuit blocks 111b. After the switch is complete, a third acknowledgement signal corresponding to the acknowledgement signal 126 is asserted. While three pairs of circuit blocks 111b and power switches 113 are shown in FIG. 1, any suitable number of circuit blocks can be included, and can be coupled in series as just described. Figure 1 While three pairs of circuit blocks 111b and power switches 113 are shown in FIG. 1, any suitable number of circuit blocks can be included, and can be coupled in series as just described.

[0036] It is noted that, Figure 1The illustrated block diagram is merely one example. In other embodiments, different circuit blocks and different configurations of circuit blocks can be possible depending on the particular application intended for the corresponding circuit. In other embodiments, the SoC can include any suitable number of functional circuits, any portion of which can receive power from more than one power rail. Accordingly, a corresponding number of adjustable power rails can be included in such embodiments.

[0037] Turning to Figure 2 , a block diagram of an embodiment of a power-multiplexing circuit is shown. In some embodiments, the power switch 213 can correspond to the power switch 113 or 114 in Figure 1 . The power switch 213 includes the voltage selector 201, the level shifters 202 and 203, the logic gates NAND 204 and NAND 205, the inverter circuit INV 206, and the transistors Q 208 and Q 209. The power switch 213 is coupled to the circuit block 211 via the local power signal 227, which in some embodiments can correspond to the circuit in the circuit block 111b or Figure 1 the circuit block 112b in . The power switch 213 is also coupled to the shared power rail 221 and the adjustable power rail 222, each of which can correspond to the similarly named and numbered items in Figure 1 . The power switch 213 receives the control signal 224 and the enable signal 225.

[0038] In the illustrated embodiment, the power switch 213 is used to generate the local power signal 227 based on either of the voltage levels of the shared power rail 221 or the adjustable power rail 222. The value of the control signal 224 is used to select between the two power rails. Another value on the enable signal 225 is used to enable or disable the local power signal 227. When the enable signal 225 is a logic low value, if the control signal 224 has a logic high value, then at least one input of each of the NAND 204 and 205 is low, causing the output of both NAND 204 and 205 to be logic high. The high value causes both Q 208 and Q 209 to limit current to the local power signal 227. The circuit block 211b can thus be powered down.

[0039] While Q 208 and Q 209 are in Figure 2Q 208 and Q 209 are shown as MOSFETs, but any suitable type of conductive device can be utilized in other implementations. In some implementations, each of Q 208 and Q 209 can be implemented using more than one device. In the illustrated implementation, Q 208 and Q 209 are shown as having three terminals. In other implementations, Q 208 and Q 209 can include a fourth node coupled to a body connection. In such implementations, the body connection of Q 208 and Q 209 can be coupled to shared power rail 221 and adjustable power rail 222, respectively, or to any other suitable signal.

[0040] When enable signal 225 is a logic high value, the output values of NAND 204 and 205 are determined by the value of control signal 224. A high value on control signal 224 results in a low value from NAND 204 and a high value from NAND 205, turning Q 208 on and Q 209 off. Local power signal 227 is then generated from shared power rail 221. Likewise, a low value on control signal 224 results in a high value from NAND 204 and a low value from NAND 205. Q 208 is turned off and Q 209 is turned on, resulting in local power signal 227 being generated from adjustable power rail 222. The outputs of NAND 204 and NAND 205 can be designed to transition from a high value to a low value faster than from a low value to a high value. This can create a brief period of time in which both Q 208 and Q 209 are on, creating a make-before-break connection. As used herein, a make-before-break connection refers to a switch that temporarily couples two or more signals together before one of the signals is broken. If both Q 208 and Q 209 were to turn off simultaneously during a switch between power rails, the use of a make-before-break connection can avoid a temporary loss of local power signal 227.

[0041] State circuit 210 receives the outputs from NAND gates 204 and 205 and generates confirmation signal 226. In some implementations, state circuit 210 can assert confirmation signal 226 to reflect the current state of control signal 224. For example, when control signal 224 is high, selecting shared power rail 221, confirmation signal 226 can also be asserted high based on the low output from NAND 204 and the high value from NAND 205, and vice versa when control signal 224 is low. In other implementations, state circuit 210 can assert a pulse on confirmation signal 226 in response to a change in the output of either NAND 204 or NAND 205. Confirmation signal 226 can be sent to a power management unit, such as power management circuit 105 in Figure 1

[0042] ​To turn off Q 208 and Q 209, the voltage levels of the outputs of NAND 204 and 205 can need to be close to the voltage levels of shared power rail 221 and adjustable power rail 222, respectively. In the illustrated embodiment, to help NAND 204 and 205 produce sufficiently high voltage levels when producing high output values, voltage selector 201 is used to select the higher voltage level between the levels on shared power rail 221 and adjustable power rail 222 as the output. The output of voltage selector 201 is used to power NAND 204, NAND 205, INV 206, and the output portions of level shifters 202 and 203. When the level of adjustable power rail 222 is greater than the level of shared power rail 221, level shifters 202 and 203 can be used to modify the logic high voltage levels of control signal 224 and enable signal 225 from the voltage level of shared power rail 221 to the level of adjustable power rail 222.

[0043] Note that, for purposes of clarity and to help demonstrate the disclosed concepts, Figure 2 The illustrated block diagrams have been simplified. In other embodiments, different and / or additional circuitry and different configurations of these circuits are possible and contemplated.

[0044] Turning to Figure 3 which shows a graph of an embodiment of a timing diagram showing voltage levels of various power signals associated with a SoC. In the illustrated embodiment, graph 300 corresponds to signals associated with power management in SoC 101 in Figure 1 . Graph 300 includes three signals, which correspond to similarly named and numbered power rails in SoC 101: shared power 321, adjustable power 322, and adjustable power 323 voltage levels over time.

[0045] Graph 300 shows how the voltage levels on adjustable power rails 122 and 123 of SoC 101 can vary relative to shared power rail 121 over time. At time to, the voltage level of shared power 321 is greater than the voltage level of adjustable power 322, which in turn is greater than adjustable power 323. In the illustrated embodiment, adjustable power 322 represents the voltage level of adjustable power rail 122, which provides power to functional circuit 107. Likewise, adjustable power 323 represents the voltage level of adjustable power rail 123, which provides power to functional circuit 108. At time to, both functional circuits 107 and 108 can be in respective low power modes, and thus, both circuit blocks 111b and 112b can be coupled to shared power 321.

[0046] At time ti, functional circuit 107 can begin to transition from the low power mode to the active mode. As part of the transition to the active mode, the voltage level of adjustable power 322 can be raised from Vi to V4. Accordingly, power management circuit 105 also sends a request to power supply circuit 103 to increase the level of adjustable power 322 from Vi to V4. In some embodiments, once the level of adjustable power 322 reaches V2, which is the same as shared power 321, power management circuit 105 can assert a value on control signal 124 to cause power switch 113 to begin switching the circuits in circuit block 11 lb from shared power 321 to adjustable power 322. In other embodiments, power management circuit 105 can wait to assert the value on control signal 124 until adjustable power 322 reaches V4 at time t2. In response to the asserted value on control signal 124, power switch 113 will begin switching the circuits in circuit block 11 lb from shared power 321 to adjustable power 322.

[0047] In the illustrated embodiment, functional circuit 108 can begin to transition from the low power mode to the active mode when adjustable power 322 transitions from Vi to V4 and power switch 113 transitions from shared power 321 to adjustable power 322. As part of this transition, functional circuit 108 can send a request to power management circuit 105 to transition adjustable power 323 from Vo to V3. However, power management circuit 105 can delay forwarding this request to power supply circuit 103 until the transition of adjustable power 322 and power switch 113 has completed. At time t3, power switch 113 completes the transition from shared power 321 to adjustable power 322. The last switch assertion of power switch 113 acknowledges signal 126, and in response, power management circuit 105 can now send a request to power supply circuit 103 to increase the level of adjustable power 323 from Vo to V3. As with adjustable power 322, in some embodiments, once the level of adjustable power 323 reaches V2, power switch 114 can begin switching circuit block 112b from shared power 321 to adjustable power 323. In other embodiments, power switch 114 can wait until adjustable power 323 reaches V3 at time t4 before beginning to switch circuit block 112b from shared power 321 to adjustable power 323.

[0048] At time t5, functional circuit 108 can indicate to power management circuit 105 that the level of adjustable power 323 is to be increased from V3 to V5. Since both V3 and V5 are higher than the level of shared power 321 (V3), power switch 114 can leave circuit block 112b coupled to adjustable power 323 when the level is raised to V5.

[0049] The functional circuit 107 begins the process of re-entering the low power state at time t6. The functional circuit 107 indicates to the power management circuit 105 that the level of the adjustable power 322 is to be decreased to Vi. Since the current level of the adjustable power 322 (V4) is greater than the level of the shared power 321 (V2), and the new level (Vi) is less than V2, the power switch 113 will transition the circuit block 111b to the shared power 321 before the level of the adjustable power 322 falls below V2. In some embodiments, the power switch 113 can switch from the adjustable power 322 before the power management circuit 105 issues a request to the power supply circuit 103 to change the level of the adjustable power 322. For example, the last switch of the power switch 113 can assert an indication signal via, for example, the control signal 124 in response to completing the transition of the circuit block 111b to the shared power 321. Upon detecting the assertion of the control signal 124, the power management circuit 105 can issue a request to the power supply circuit 103 to decrease the level of the adjustable power 322. In other embodiments, the time for the level of the adjustable power 322 to decrease from V4 to V2 can be sufficient for the power switch 113 to transition the circuit block 111b to the shared power 321, and the power management circuit 105 can therefore issue the request to the power supply circuit 103 without waiting for the indication.

[0050] In some embodiments, the current voltage level of the adjustable power 322 and the new voltage level of the adjustable power 322 can be compared to a threshold voltage level, rather than comparing the current voltage level of the adjustable power 322 and the new voltage level of the adjustable power 322 to the voltage level of the shared power 321. The threshold voltage level can differ from the voltage level of the shared power 321 by an offset value. For example, if the current voltage level of the adjustable power 322 is greater than both the voltage level of the shared power 321 and the threshold voltage, and the new voltage level of the adjustable power 322 is less than the voltage level of the shared power 321 but greater than the threshold voltage, the power management circuit 105 can refrain from asserting the control signal 124, instead leaving the circuit block 111b coupled to the adjustable power 322. In such embodiments, the offset value can be programmed, for example, by the power management circuit 105 or a processor included in the SoC 100. Such programmable offset values can be set to a positive voltage level, a negative voltage level, or a zero voltage level. A zero voltage level offset value can cause the power management circuit 105 to assert the control signal 124 at any time the voltage level of the adjustable power 322 or 323 exceeds the level of the shared power 321, as described above.

[0051] Note that, Figure 3 The illustrated graph 300 is merely one example. The signals shown in the graph 300 are simplified for clarity. In other embodiments, the voltage level waveforms can differ due to, for example, loading from other circuits coupled to each respective power rail.

[0052] Turning now toFigure 4 which shows a flow diagram of an embodiment of a method for multiplexing power signals in a SoC. The method 400 can be applied to a SoC, such as the SoC 101 in Figure 1 which includes power switches, such as the power switches 213 in Figure 2 With reference to the methods of Figure 1 and Figure 4 collectively, the method 400 begins at block 401.

[0053] The power supply unit generates a shared power signal (block 402). In the illustrated embodiment, the power supply unit, such as the power circuit 103, generates a power signal that is coupled to the shared power rail 121 in the SoC 101. The voltage level of the shared power rail 121 can be set by the power management circuit 105, or in other embodiments, the voltage level can be a default voltage level or a predetermined voltage level that is determined by the power circuit 103. The voltage level can be selected to meet the minimum power level of any circuit block that is coupled to the shared power rail 121. For example, one embodiment of the SoC 101 can include various SRAM arrays that have a minimum operating voltage level of 875 millivolts (mV), and one or more analog circuits that have a minimum operating voltage level of 925 mV. If only the SRAM arrays are to be coupled to the shared power rail 121, then the voltage level can be set to 875 mV. Otherwise, if at least one analog circuit is coupled to the shared power rail 121, then the voltage level can be set to 925 mV.

[0054] The power supply unit generates a plurality of adjustable power signals (block 404). The power circuit 103 generates respective adjustable power signals for the adjustable power rails 122 and 123. In some embodiments, the power circuit 103 can generate additional power signals for additional power rails that are not shown in Figure 1 The initial voltage levels of the adjustable power rails 122 and 123 can be set by the power management circuit 105, or can be set to default voltage levels until new levels are received from the power management circuit 105.

[0055] A new voltage level for one of the adjustable power signals is requested (block 406). In some embodiments, the power management circuit 105 prepares a functional circuit, such as the functional circuit 108, for a change from a low power state to an active state. In other embodiments, the functional circuit 108 can send a request to the power management circuit 105 to change from a low power state to an active state. As part of the transition process, the power management circuit 105 sends a request to the power circuit 103 to increase the voltage level of the adjustable power rail 123. The power management circuit 105 also asserts a first value on the control signal 125 in response to determining that the increased voltage level of the adjustable power rail 123 will exceed the voltage level of the shared power rail 121.

[0056] Further operations of the method can depend on the state of the control signal (block 408). The power switch 114 receives the control signal 125. The power management circuit 105 determines whether the circuit block 112b is powered by the shared power rail 121 or the adjustable power rail 123 and asserts or de-asserts the control signal 125 accordingly. The power management circuit 105 can determine whether the power supply circuit 103 has completed the request to increase the voltage level of the adjustable power rail 123 before asserting the control signal 125 to switch the circuit block 112b to the adjustable power rail 123. In other embodiments, the power management circuit 105 can wait a predetermined amount of time to avoid requesting a voltage level increase before asserting the control signal 125. If the control signal 125 is asserted, the method proceeds to block 410 to couple the circuit block 112b to the adjustable power rail 123. Otherwise, the method 400 proceeds to block 412 to couple the circuit block 112b to the shared power rail 121.

[0057] If the control signal 125 is asserted, the power node of the circuit block 112b is coupled to the adjustable power rail 123 (block 410). When the control signal 125 is asserted, the power switch 114 couples the adjustable power rail 123 to the power node of the circuit block 112b. The power switch 114 can use a transistor or other type of conductive device to disable the shared power rail 121 from the power node and instead couple the node to the adjustable power rail 123.

[0058] If the control signal 125 is de-asserted in block 408, the power node of the circuit block 112b is coupled to the shared power rail 121 (block 412). When the control signal 125 is de-asserted, the power switch 114 couples the shared power rail 121 to the power node of the circuit block 112b and decouples the adjustable power rail 123 from the power node.

[0059] During the switching between power rails, power is maintained at the operating level (block 414). If switching to the adjustable power rail 123, the power switch 114 can couple the adjustable power rail 123 to the power node before decoupling the shared power rail 121, where both power rails are simply coupled to the power node in order to maintain at least one power rail coupled to the power node to avoid a power disruption in the circuit block 112b. If switching to the shared power rail 121, a similar process is used. The shared power rail 121 is coupled to the power node before decoupling the adjustable power rail 123. Once the switching is complete, the power switch 114 can assert the confirmation signal 127. In some embodiments, the power switch 114 can assert a value on the confirmation signal 127 that corresponds to the value of the control signal 125. In other embodiments, the power switch 114 can assert a pulse on the confirmation signal 127 to indicate that the power rail switching is complete. The method ends at block 416.

[0060] Note that, Figure 4 The illustrated method is merely one example for purposes of illustration. Additional operations can be included in some embodiments. Additionally, operations can be performed in different orders in various embodiments.

[0061] Turning now to Figure 5 which shows a graph of another embodiment of a timing diagram showing voltage levels of various power signals associated with a SoC. In the illustrated embodiment, graph 500 corresponds to signals associated with power management in SoC 101 in Figure 1 . Graph 500 includes two signals: shared power 521, which shows the voltage level of shared power rail 121, and adjustable power 522, which shows the voltage level of adjustable power rail 122. In other embodiments, adjustable power 522 can correspond to adjustable power rail 123. Additionally, four particular voltage levels are indicated by dashed lines: voltage level 525, intermediate voltage level 526, voltage level 527, and voltage level 528.

[0062] Similar to graph 300 in Figure 3 , graph 500 shows how the voltage level on adjustable power rail 122 of SoC 101 can vary over time relative to shared power rail 121. Graph 500 shows the use of an intermediate voltage level 526 for a transition circuit, such as circuit block 111b, from shared power rail 121 to adjustable power rail 122. In the illustrated embodiment, at time to, the voltage level of adjustable power 522 is voltage level 525, which is less than the voltage level of shared power 521. Circuit block 111a is powered by adjustable power 522, and circuit block 111b is powered by shared power 521. At time to, functional circuit 107 can be in a low power mode.

[0063] At time ti, the functional circuit 107 can begin to transition from the low power mode to the active mode. As part of the transition to the active mode, the functional circuit 107 requests that the power management circuit 105 increase the voltage level of the adjustable power 522 to a voltage level 525 that is greater than the voltage level of the shared power 521. The power management circuit 105 determines that the voltage level on the adjustable power 522 is to cross change from being less than the level of the shared power 521 to being greater than the level. In response to the determination, the power management circuit 105 sends a request to the power supply circuit 103 to increase the level of the adjustable power 522 to an intermediate voltage level 526. Once the level of the adjustable power 522 has stabilized appropriately at the intermediate voltage level 526, the power management circuit 105 asserts the control signal 124 to cause the power switch 113 to power the circuit block 111b from the adjustable power 522 instead of the shared power 521. In various embodiments, the circuit block 111b can be switched all at once, one at a time, or in any suitable combination.

[0064] At time t2, the power switch 113 completes the transition of the circuit block 111b to the adjustable power 522. The power switch 113 asserts the confirmation signal 126 to indicate that the transition is complete. In response, the power management circuit 105 sends a request to the power supply circuit 103 to change the level of the adjustable power 522 to a voltage level 527, completing the transition to the voltage level 527. Note that although the voltage level 527 is less than the intermediate voltage level 526, the transition to the voltage level 527 includes setting the adjustable power 522 to the intermediate voltage level 526.

[0065] At time t3, the functional circuit 107 sends a request to the power management circuit 105 to increase the level of the adjustable power 522 to a voltage level 528. For example, the functional circuit 107 can need a higher voltage level to complete a current task or to prepare for a new task. Since the change from the voltage level 527 to the voltage level 528 does not exceed the level of the shared power 521, the power management circuit 105 sends the request to the power supply circuit 103 and the voltage level of the adjustable power 522 is increased. The circuit block 111b is already powered by the adjustable power 522, so the power switch 113 can not need an additional transition.

[0066] At time t4, the functional circuit 107 can have completed its task and be ready to return to the low power mode. To prepare for the transition to the low power mode, the functional circuit 107 sends a request to the power management circuit 105 to reduce the level of the adjustable power 522 to the voltage level 525. The power management circuit 105 determines that the change in level exceeds the level of the shared power 521, and therefore, the circuit block 111b will need to switch to the shared power 521 before the level of the adjustable power 522 changes to the voltage level 525. The power management circuit 105 sends a request to the power supply circuit 103 to change the level of the adjustable power 522 to the intermediate voltage level 526. Once the level of the adjustable power 522 is suitably stabilized at the intermediate voltage level 526, the power management circuit 105 de-asserts the control signal 124, causing the power switch 113 to transition the circuit block 111b from the adjustable power 522 to the shared power 521. Again, the transition of the circuit block 111b can be performed in any suitable order.

[0067] Upon completion of the transition of the circuit block 111b to the shared power 521, the power switch 113 asserts the confirmation signal 126 to indicate completion of the transition at time t5. The power management circuit 105 sends a request to the power supply circuit 103 to change the level of the adjustable power 522 to the voltage level 525. In various embodiments, the functional circuit 107 can enter the low power mode in response to the assertion of the confirmation signal 126, or can wait until the level of the adjustable power 522 has suitably stabilized at the voltage level 525.

[0068] Upon completion of the transition of the circuit block 111b to the shared power 521, the power switch 113 asserts the confirmation signal 126 to indicate completion of the transition at time t5. The power management circuit 105 sends a request to the power supply circuit 103 to change the level of the adjustable power 522 to the voltage level 525. In various embodiments, the functional circuit 107 can enter the low power mode in response to the assertion of the confirmation signal 126, or can wait until the level of the adjustable power 522 has suitably stabilized at the voltage level 525. Figure 5In embodiments of the method 500, if changing the current voltage level of the adjustable power 522 to the target voltage level causes the level of the adjustable power 522 to exceed the voltage level of the shared power 521, the level of the adjustable power 522 is set to an intermediate voltage level 526 before being set to the target voltage level. When the target voltage level is higher than the level of the shared power 521, the circuit block 111b is switched to be powered by the adjustable power 522 after the adjustable power 522 is suitably stabilized at the intermediate voltage level 526. When the target voltage level is lower than the level of the shared power 521, the circuit block 111b is switched to be powered by the shared power 521 after the adjustable power 522 is suitably stabilized at the intermediate voltage level 526. When the adjustable power rail is at the intermediate voltage level, the switching circuit can allow the circuit to switch between the adjustable power rail and the shared power rail when the voltage level difference between the two power rails is a known amount of change. In various embodiments, this amount of change can be selected to accommodate changes to and from the power rails while mitigating the risk of falling below or exceeding safe operating levels due to changes in the load powered by each rail. This amount of change can also be programmed by, for example, the power management circuit 105 or a processor in the SoC 100. Although the intermediate voltage level is shown as being greater than the voltage level of the shared power 521, in other embodiments, this amount of change can be programmed to be less than the voltage level of the shared power 521. In some embodiments, using an intermediate voltage level for level changes that exceed the level of the shared power rail can simplify the circuitry in the power management circuit.

[0069] Note that, Figure 5 The chart 500 is just one example. The illustrated waveforms have been simplified for clarity. In other embodiments, the waveforms can differ due to system noise and / or defects in IC manufacturing. Although the chart 500 is described with respect to the functional circuit 107, the chart 500 can be applied to any functional circuit in the SoC 101 that utilizes a shared power rail and an adjustable power rail. Figure 5 Embodiments of the method 500 can be applied to any functional circuit in a SoC 101 that utilizes a shared power rail and an adjustable power rail.

[0070] Turning to Figure 6 FIG. 6 shows a flowchart of embodiments of a method for multiplexing power rails in a SoC using an intermediate voltage level. The method 600 can be applied to a SoC, such as the SoC 101 in Figure 1 FIG. 1. Referring collectively to Figure 1 and Figure 6 The method 600 begins at block 601.

[0071] The power management circuitry sends a request to the power supply unit to change the voltage level of the power rail (block 602). For example, the power management circuitry, such as the power management circuitry 105, sends a request to the power supply circuitry, such as the power supply circuitry 103, to change the voltage level of the adjustable power rail, such as the adjustable power rail 123, from the current voltage level to a new voltage level. In the illustrated embodiment, the functional circuitry 108 initially sends the request to change the voltage level to the power management circuitry 105, but in other embodiments, the power management circuitry 105 can initiate the request.

[0072] Further operations of the method 600 can depend on the new voltage level (block 604). In the illustrated embodiment, the power management circuitry 105 determines whether the level of the adjustable power rail 123 will exceed the level of the shared power rail 121 when changing from the current voltage level to the new voltage level. In some embodiments, it is further determined whether the current voltage level and the new voltage level of the adjustable power rail 123 differ from the voltage level of the shared power rail 121 by more than an offset value. If the level of the adjustable power rail 123 will exceed, the power supply of the circuit block 112b can be switched. If the level of the adjustable power rail 123 is increasing, the power supply of the circuit block 112b can be switched from the shared power rail 121 to the adjustable power rail 123, and vice versa if the level of the adjustable power rail 123 is decreasing. If the level of the adjustable power rail 123 will exceed the level of the shared power rail 121, the method 600 proceeds to block 606 to change the level of the adjustable power rail 123 to an intermediate voltage level. Otherwise, the method proceeds to block 612 to change the level of the adjustable power rail 123 to the new voltage level.

[0073] If the level of the adjustable power rail 123 will exceed the level of the shared power rail 121, the level of the adjustable power rail 123 will be changed to an intermediate voltage level (block 606). The power management circuitry 105 sends a request to the power supply circuitry 103 to change the voltage level of the adjustable power rail 123 to the intermediate voltage level. The change to the intermediate voltage level can occur regardless of the new voltage level. For example, see Figure 5to the voltage level 527, the level of the adjustable power rail 123 will be set to the intermediate voltage level 526 before being set to the voltage level 527. One reason for first switching to the intermediate voltage level can be to have a consistent voltage level difference or amount of change between the levels of the shared power rail 121 and the adjustable power rail 123 while switching the power supply of the circuit block 112b from one power rail to another. Using a consistent voltage level change amount can tend to reduce or avoid damage to the circuit block 112b and the power switch 114 during the transition between power rails. The intermediate voltage level can be selected such that the current flowing from the power rail with the higher voltage level to the rail with the lower voltage level is an acceptable amount in a first-then-last switch (e.g., both power rails are coupled to the circuit block 112b before being decoupled).

[0074] The power supply of the circuit block 112b is switched (block 608). In some embodiments, the power supply circuit 103 can indicate to the power management circuit 105 the new voltage level of the adjustable power rail 123. The power management circuit 105 can assert (or in other embodiments de-assert) the control signal 125, causing the power switch 114 to transition the power supply of the circuit block 112b. If the new voltage level will be higher than the level of the shared power rail 121, the power supply of the circuit block 112b can be switched from the shared power rail 121 to the adjustable power rail 123, and vice versa if the new voltage level is lower than the level of the shared power rail 121. If more than one circuit block is being transitioned, the power switch 114 can transition each circuit block one at a time, in groups, or all at once.

[0075] Continued operation of the method 600 can depend on the acknowledgement signal (block 610). Once the power switch 114 has completed the transition of the power supply of the circuit block 112b, the power switch 114 asserts the acknowledgement signal 127 in the illustrated embodiment. The method 600 is held at block 610 until the power switch 114 asserts the acknowledgement signal 127. After the acknowledgement signal 127 is asserted, the method proceeds to block 612 to change the level of the adjustable power rail 123.

[0076] After the circuit block 112b has been coupled to the appropriate power rail, the level of the adjustable power rail 123 will be changed to the new voltage level (block 612). The power management circuit 105 receives the asserted acknowledgement signal from the power switch 114, and in response, sends a request to the power supply circuit 103 to change the voltage level of the adjustable power rail 123 to the new level. The method ends at block 614.

[0077] It is noted that, Figure 6The method 600 of FIG. 6 is just one example. In some embodiments, the operations can be performed in a different order. Additionally, in various embodiments, additional operations can be included.

[0078] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even if only a single embodiment is described with respect to a particular feature. The examples of features provided in the present disclosure are intended to be illustrative and not restrictive, unless expressly stated otherwise. The above description intends to encompass such alternatives, modifications and equivalents as would be apparent to a person skilled in the art upon reading the above description. The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly) that would be apparent to a person skilled in the art from the descriptions herein insofar as it does not negate any or all of the problems addressed herein.

[0079] The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly) or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Thus, new claims can be made during the pendency of this patent application (or patent applications claiming priority from it) for any such combination of features. In particular, with reference to the appended claims, features from dependent claims can be combined with features from the independent claims and features from a particular independent claim can be combined with features from any of the other independent claims rather than only with the specific combination of features listed in the respective claim.

Claims

1. A system for power management, comprising: Power supply circuit, the power supply circuit being configured as follows: Generate a specific voltage level on the shared power rail; as well as Generate one voltage level from a series of voltage levels on the adjustable power rail; A power switch configured to couple the power nodes of a circuit block to either the shared power rail or the adjustable power rail; as well as Power management circuit, the power management circuit being configured to: Maintain state information associated with the circuit block, the state information indicating that the power node is coupled to the shared power rail and that the adjustable power rail is at a first voltage level less than the specific voltage level; In response to an indication of a state change in the circuit block, wherein the state change includes a request to increase the voltage level of the adjustable power rail to a second voltage level that crosses the specific voltage level, the power supply circuit increases the voltage level of the adjustable power rail to an intermediate voltage level that is greater than the specific voltage level. as well as In response to the voltage level of the adjustable power rail stabilizing at the intermediate voltage level, an assertion control signal is made to cause the power switch to decouple the power node from the shared power rail after coupling the power node to the adjustable power rail; and The power supply circuit is further configured to change the voltage level of the adjustable power rail to the second voltage level after the power switch has coupled the power node to the adjustable power rail.

2. The system of claim 1, wherein the power switch is configured to assert an acknowledgment signal in response to determining that the power node is coupled to the adjustable power rail.

3. The system of claim 2, wherein the power management circuit is further configured to, in response to the assertion of the acknowledgment signal, cause the power supply circuit to change the voltage level of the adjustable power rail from the intermediate voltage level to the second voltage level.

4. The system of claim 1, wherein the power management circuit is further configured to, in response to determining that the second voltage level is greater than the specific voltage level, cause the power supply circuit to increase the voltage level of the adjustable power rail from the first voltage level to the intermediate voltage level.

5. A method for power management, comprising: The power management circuit receives a request to increase the voltage level of the adjustable power rail from a first voltage level to a second voltage level. In response to the increase across a specific voltage level that determines the voltage level of the adjustable power rail, the power management circuitry couples the power nodes of the circuit block to a shared power rail having the specific voltage level. The power management circuit changes the voltage level of the adjustable power rail from the first voltage level to an intermediate voltage level. as well as In response to determining that the voltage level of the adjustable power rail has stabilized at the intermediate voltage level, the power management circuit causes the power switch to couple the power node to the adjustable power rail and then decouples the power node from the shared power rail. as well as After switching the power node to the adjustable power rail, the voltage level of the adjustable power rail is changed to the second voltage level.

6. The method of claim 5, wherein the intermediate voltage level is greater than both the first voltage level and the second voltage level.

7. A system for power management, comprising: Power supply circuit, the power supply circuit being configured as follows: Generate a specific voltage level on the shared power rail; as well as Generate one voltage level from a series of voltage levels on the adjustable power rail; A power switch configured to couple the power node of the circuit block to either the shared power rail or the adjustable power rail; as well as Power management circuit, the power management circuit being configured to: Maintain state information associated with the circuit block, the state information indicating that the power node is coupled to the adjustable power rail and that the adjustable power rail is at a first voltage level greater than the specific voltage level; as well as In response to an indication of a state change in the circuit block, wherein the state change includes a request to reduce the voltage level of the adjustable power rail to a second voltage level that crosses the specific voltage level: The power supply circuit changes the voltage level of the adjustable power rail from the first voltage level to an intermediate voltage level. After the voltage level of the adjustable power rail has stabilized at the intermediate voltage level, the assertion control signal is canceled so that the power switch decouples the power node from the adjustable power rail after coupling the power node to the shared power rail. as well as The power supply circuit reduces the voltage level of the adjustable power rail to a second voltage level that is lower than the specific voltage level.

8. The system of claim 7, wherein the intermediate voltage level is greater than the second voltage level and less than the first voltage level.

9. The system of claim 7, wherein the power switch is configured to assert an acknowledgment signal in response to determining that the power node is coupled to the shared power rail.

10. The system of claim 9, wherein the power management circuitry is further configured to reduce the voltage level of the adjustable power rail in response to determining that the acknowledgment signal has been asserted.

Images