Substrate processing method and substrate processing system

Abstract

The present invention provides a substrate processing method and a substrate processing system. The substrate processing method of the present invention includes: a step of generating a captured image of a processed substrate associated with each layer of a layered film formed on a substrate; and a step of acquiring information indicating a feature quantity calculated based on the captured image for each of a plurality of layers including a top layer of the layered film formed on the substrate. The present invention can appropriately set a processing condition for a substrate having a layered film.

Description

Technical Field

[0001] The present invention relates to a substrate processing method and a substrate processing system. Background Art

[0002] Patent document 1 discloses a processing system having a decompression processing device, a structure discrimination device and a system control device. The decompression processing device uses a resist pattern as a mask to perform an etching process on a wafer. The structure discrimination device uses scatterometry to measure the size of the pattern structure on the wafer surface before the etching process. The system control device stores correlation data between the processing conditions during the etching process and the amount of pattern structure removed from the wafer surface due to the etching process. Moreover, the system control device sets the processing conditions during the etching process based on the measurement results of the size of the pattern structure on the wafer surface and the above-mentioned correlation data, so that the pattern structure on the wafer surface after the etching process becomes the desired size.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-86965 Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] The technology of the present invention can appropriately set processing conditions and the like for a substrate having a laminated film.

[0008] Technical solutions to technical problems

[0009] One embodiment of the present invention is a substrate processing method, which includes: a step of generating a captured image of the processed substrate related to each layer constituting a laminated film on a substrate; and a step of obtaining information representing a feature value inferred based on the above-mentioned captured image for each of a plurality of layers including the outermost layer of the laminated film on the substrate.

[0010] Effects of the Invention

[0011] According to the present invention, processing conditions and the like for a substrate having a laminated film can be appropriately set. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram schematically showing the general configuration of the substrate processing system according to the first embodiment.

[0013] Figure 2 FIG. 1 is a diagram schematically showing a wafer to be processed.

[0014] Figure 3is a view schematically showing a film formed on a wafer as a processing target by a coating and developing device.

[0015] Figure 4 is a view schematically showing a resist pattern formed on a wafer as a processing target by a coating and developing device.

[0016] Figure 5 is a longitudinal sectional view schematically showing a general structure of a photographing unit possessed by a coating and developing device.

[0017] Figure 6 is a transverse sectional view schematically showing a general structure of a photographing unit possessed by a coating and developing device.

[0018] Figure 7 is a view schematically showing a state of a wafer after various etchings performed by an etching device possessed by a substrate processing system.

[0019] Figure 8 is a view for explaining a photographed image of a wafer.

[0020] Figure 9 is a flowchart explaining one example of processing at the time of mass production in a substrate processing system of Figure 1

[0021] Figure 10 is a view schematically showing a general structure of a substrate processing system of the second embodiment.

[0022] Figure 11 is a view schematically showing a general structure of a substrate processing system of the third embodiment.

[0023] BRIEF DESCRIPTION OF DRAWINGS

[0024] 1, 1a, 1b, 1c processing system

[0025] 2, 2a coating and developing device

[0026] 3 etching device

[0027] 5 coating device

[0028] 6a, 6b film forming device

[0029] 8 polishing device

[0030] 31, 71, 91a, 91b, 91c, 9d photographing unit

[0031] 41b, 101b, 102b, 103b image generating section

[0032] W wafer DETAILED DESCRIPTION ​

[0033] In a manufacturing process of a semiconductor device or the like, predetermined processes are performed in order to form a resist pattern on a semiconductor wafer (hereinafter, sometimes referred to as "wafer"). The above-mentioned predetermined processes are, for example, a resist coating process of supplying a resist liquid on the wafer to form a resist film, an exposure process of exposing the resist film to light to form a predetermined pattern, a PEB process of promoting a chemical reaction in the resist film after the exposure, a development process of developing the resist film after the exposure, and the like. Further, after the resist pattern is formed, etching is performed using the resist pattern as a mask. In addition, when the resist pattern is formed, a film other than the resist film such as a base film is formed on the wafer to form a stacked film.

[0034] However, in the etching using the resist pattern as a mask, the shape of the resist pattern has an influence, and therefore, conventionally, the size of the pattern structure on the wafer surface is evaluated before the etching process, and the processing conditions of the etching process are set based on the evaluation result.

[0035] For example, in the processing system disclosed in Patent Literature 1, the size of the pattern structure on the wafer surface before the etching process is measured using a scatterometry method. In addition, in the above-mentioned processing system, correlation data between the processing conditions at the time of the etching process and the amount of removal of the pattern structure on the wafer surface caused by the etching process is obtained in advance. Then, based on the measurement result of the size of the pattern structure on the wafer surface and the above-mentioned correlation data, the processing conditions at the time of the etching process are set so that the pattern structure on the wafer surface after the etching process becomes a desired size.

[0036] However, in the case where the stacked film including the resist film is formed on the etching target film of the wafer, in the etching process using the resist pattern as a mask, the thickness or the like of the film other than the resist film has an influence. Specifically, for example, in the case where the base film is formed in addition to the resist film, the thickness of the base film has an influence on the processing result of the etching using the resist pattern as a mask.

[0037] Therefore, the technology of the present application can appropriately set the processing conditions and the like for the substrate having the stacked film.

[0038] Hereinafter, with reference to the drawings, a substrate processing method and a substrate processing system according to the present embodiment will be described. In addition, in the present specification and the drawings, elements having substantially the same functional structure are denoted by the same reference numerals, and thus, repetitive description will be omitted.

[0039] (First Embodiment)

[0040] Figure 1 Fig. 1 is a diagram schematically showing the outline structure of a substrate processing system according to the first embodiment. Figure 2 Fig. 2 is a diagram schematically showing a wafer as a processing target. Figure 3is a view schematically showing a film formed on a wafer as a processing target by a coating and developing device. Figure 4 is a view schematically showing a resist pattern formed on a wafer as a processing target by a coating and developing device. Figure 5 and Figure 6 are a longitudinal sectional view and a lateral sectional view, respectively, schematically showing a schematic structure of a photographing unit possessed by a coating and developing device. Figure 7 is a view schematically showing a state of a wafer after various etchings by an etching device possessed by a substrate processing system. Figure 8 is a view for explaining a photographing image described later.

[0041] As shown in Figure 1 , a processing system 1 as a substrate processing system includes a coating and developing device 2 as a semiconductor manufacturing device and an etching device 3. Further, although not shown, a wafer cassette station for feeding in and out a wafer cassette in which a plurality of wafers are housed, and a wafer conveying mechanism are provided in the coating and developing device 2 and the etching device 3. The wafer conveying mechanism is used for wafer conveyance between the wafer cassette station and various modules, wafer conveyance between the various modules, and the like.

[0042] The coating and developing device 2 forms a laminated film including a resist film on a wafer, or develops an exposed resist film. Further, in the following description, a wafer W as a processing target fed into the coating and developing device 2 has, as shown in Figure 2 , an oxide film Fl, a TiN film F2, and a low temperature oxide (LTO) film F3 laminated in this order from below on a base wafer Wl, the LTO film F3 is patterned, and an LTO pattern is formed.

[0043] The coating and developing device 2 has a lower film forming unit 11, an intermediate film forming unit 12, a resist film forming unit 13, and a developing unit 14 to laminate a film on a wafer W (specifically, for example, on the LTO film F3), or to process a formed laminated film. Further, the above units 11 to 14 are spin coating units that coat a processing liquid on the wafer W by a spin coating method. In the spin coating method, the processing liquid is discharged onto the wafer W from, for example, a coating nozzle (not shown), and the wafer W is rotated to diffuse the processing liquid on the surface of the wafer W. The lower film forming unit 11, the intermediate film forming unit 12, the resist film forming unit 13, and the developing unit 14 can use a known structure.

[0044] The lower film forming unit 11 coats a lower film material as a processing liquid on the wafer W to form a lower film as a base film of a resist film. Specifically, the lower film forming unit 11 forms, for example, as shown in Figure 3 , an SOC (spin on carbon) film F4 as a lower film on the LTO film F3 (LTO pattern) of the wafer W.

[0045] The intermediate film forming unit 12 applies an intermediate film forming material as a processing liquid on the wafer W to form an intermediate film as a base film of the resist film. Figure 3 As shown, an SOG (spin-on-glass) film F5 is formed on the SOC film F4 of the wafer W as an intermediate layer film.

[0046] The resist film forming unit 13 applies a resist liquid as a processing liquid on the wafer W to form a resist film. Specifically, the resist film forming unit 13 is as follows. Figure 3 As shown, a resist film F6 is formed on the SOG film F5 of the wafer W.

[0047] The developing unit 14 applies a developer as a processing liquid to the wafer W to develop the wafer W. Specifically, the developing unit 14 develops the resist film F6 exposed by the exposure device (not shown) integrally connected to the coating and developing device 2, for example. Figure 4 As shown, a resist pattern P1 is formed on a wafer W.

[0048] In addition, the coating and developing device 2 is as follows Figure 1 The apparatus 2 is shown as having a heat treatment unit 21. This heat treatment unit 21 uses a hot plate capable of mounting the wafer W to perform a heat treatment on the wafer W. The heat treatment unit 21 is used, for example, after the formation of the SOC film F4, after the formation of the SOG film F5, and after the formation of the resist film F6, and before exposure, after exposure, and before development, and after development. While the figure shows only one heat treatment unit 21, the coating and developing apparatus 2 is provided with a plurality of heat treatment units 21, and different heat treatment units 21 are used depending on the application. The heat treatment unit 21 can have a known structure.

[0049] Furthermore, the coating and developing apparatus 2 is provided with first to fifth imaging units 311 to 315 (hereinafter collectively referred to as "imaging units 31"). The imaging units 31 can use their imaging results for wafer inspection. However, as described later, in this embodiment, these imaging results are used to estimate characteristic quantities of each layer (film) of the laminated film on the wafer W.

[0050] The first imaging unit 311 is used to image the wafer W before the lower layer film forming process by the lower layer film forming unit 11 .

[0051] The second imaging unit 312 is used to image the wafer W after the above-mentioned lower layer film forming process and before the intermediate layer film forming process performed by the intermediate layer film forming unit 12 .

[0052] The third imaging unit 313 is used to image the wafer W before the resist film forming process performed by the resist film forming unit 13 after the intermediate layer film forming process.

[0053] The fourth imaging unit 314 is used to image the wafer W after the resist film forming process and before the exposure process.

[0054] The fifth photographing unit 315 is used to photograph the wafer W after the development process.

[0055] like Figure 5 and Figure 6 As shown, the first imaging unit 311 has a housing 200. A mounting table 201 capable of mounting a wafer W is provided in the housing 200. The mounting table 201 can be rotated and stopped by a rotation drive unit 202 such as a motor. A mounting table 201 is provided on the bottom surface of the housing 200 from one end side ( Figure 6 The negative side of the X direction in the middle) extends to the other end side ( Figure 6 The mounting table 201 and the rotation drive unit 202 are provided on the guide rail 203 and can be moved along the guide rail 203 by the drive device 204.

[0056] On the other end side in the housing 200 ( Figure 6 An imaging mechanism 210 is provided on the side surface (positive direction side of the X direction) of the image sensor. As a camera of the imaging mechanism 210, for example, a line sensor camera is used.

[0057] A half-mirror 211 is provided near the center of the upper portion of the housing 200. The half-mirror 211 is provided at a position opposite to the photographing mechanism 210, with the mirror surface facing vertically downwards being tilted 45 degrees upwards toward the photographing mechanism 210. An illumination mechanism 212 serving as a light source is provided above the half-mirror 211. The half-mirror 211 and the illumination mechanism 212 are fixed to the upper surface inside the housing 100. The illumination light from the illumination mechanism 212 is irradiated downwards through the half-mirror 211. Therefore, the light reflected by an object below the illumination mechanism 212 is further reflected by the half-mirror 211 and enters the photographing mechanism 210. That is, the photographing mechanism 210 can photograph objects in the irradiation area of ​​the illumination mechanism 212.

[0058] The first photographing unit 311 allows the wafer W to move along the guide rail in one direction ( Figure 6 The surface of the wafer W is scanned by a line sensor camera of an imaging mechanism 210 having a long imaging field of view in a direction substantially perpendicular to the above-mentioned one direction.

[0059] Furthermore, the structures of the second to fifth imaging units 312 to 315 are substantially the same as the structure of the first imaging unit 311 described above.

[0060] In addition, if Figure 1As shown, the coating and developing device 2 is provided with a control unit 41 .

[0061] The control unit 41 is, for example, a computer having a CPU, memory, and the like, and includes a program storage unit (not shown). This program storage unit stores programs for controlling the operation of the various units and drive systems such as the transport device (not shown) described above to perform various processes on the wafer W. Alternatively, the programs may be recorded on a computer-readable storage medium and installed from the storage medium into the control unit 41. Part or all of the programs may be implemented by dedicated hardware (circuit board).

[0062] The control unit 41 includes a storage unit 41a, an image generating unit 41b, and an estimating unit 41c, which will be described later.

[0063] The etching device 3 includes an LTO film etching unit 51, a TiN film etching unit 52, and an oxide film etching unit 53. The units 51 to 53 are, for example, plasma-based dry etching units.

[0064] The LTO film etching unit 51 etches the LTO film F3 using the laminated film on the wafer W formed by the coating and developing device 2 as a mask. Figure 4 and Figure 7 As shown in FIG. 1 (A), the resist pattern P1 is transferred to the LTO film F3 to form a pattern P2 of the LTO film.

[0065] The TiN film etching unit 52 uses the LTO film pattern P2 formed by the LTO film etching unit 51 as a mask to etch the TiN film F2. Figure 7 (A) and Figure 7 As shown in (B), the LTO film pattern P2 is transferred to the TiN film F2 to form a TiN film pattern P3.

[0066] The oxide film etching unit 53 uses the pattern P3 of the TiN film formed by the TiN film etching unit 52 as a mask to etch the oxide film F1. Figure 7 (B) and Figure 7 As shown in (C), the pattern P3 of the TiN film is transferred to the oxide film F1.

[0067] like Figure 1 As shown, the processing system 1 also has an overall control device 4 .

[0068] The overall control device 4 is, for example, a computer having a CPU, a memory, and the like, and has a program storage portion (not shown). In the program storage portion, a program and the like for generating a correlation model to be described later are stored. Further, the above program can be recorded in a non-transitory storage medium that is readable by a computer, and the storage medium can be installed in the overall control device 4. Part or all of the program can be implemented by a dedicated hardware (circuit board).

[0069] The overall control device 4 includes a storage portion 61, a model generation portion 62, an acquisition portion 63, a processing condition decision portion 64, and a processing condition correction portion 65.

[0070] Here, the storage portion 41a, the image generation portion 41b, and the estimation portion 41c of the control portion 41, and the storage portion 61, the model generation portion 62, the acquisition portion 63, the processing condition decision portion 64, and the processing condition correction portion 65 of the overall control device 4 will be described.

[0071] The storage portion 41a of the control portion 41 stores various information. In the storage portion 41a, for example, the estimation model to be described later generated by the model generation portion 62 of the overall control device 4 and the like are stored.

[0072] The image generation portion 41b generates a captured image of the wafer W based on the capturing result of the wafer W by the capturing mechanism 210 of the capturing unit 31. For example, the image generation portion 41b divides the wafer W in the capturing result of the capturing mechanism 210 into 437 regions, and calculates the average value of the pixel value of each of R (red), G (green), and B (blue) in each region. Then, the image generation portion 41b generates a table in which the coordinates of each region are associated with the average value of the above pixel value, that is, the average value of RGB data. Then, the image generation portion 41b corrects the table in correspondence with the optical system and the like in the capturing unit 31. According to the corrected table, the image Im shown in FIG. 1 can be generated. Figure 8 Hereinafter, the above table acquired from the capturing result of the capturing mechanism 210 as described above will be referred to as a "captured image".

[0073] The image generation portion 41b generates a captured image of the processed wafer in association with each layer of the laminated film on the wafer W. The processing in association with the layer is, for example, the formation processing of the layer (the formation processing of the intermediate layer film and the like), the development processing of the layer (the development processing of the resist film and the like).

[0074] The captured image generated by the image generation portion 41b is basically stored in the storage portion 41a for each wafer W.

[0075] The estimation unit 41c estimates a characteristic quantity of the mth (m is an integer of 1 or more) layer formed on the wafer W in the processing system 1, based on a pixel value or the like in the captured image of the processed wafer W related to the mth layer. The estimation is performed in each region constituting the captured image of the wafer W. For example, in the case where the wafer W is divided into 437 regions as described above, the characteristic quantity of the mth layer is estimated based on a pixel value or the like of each of the 437 regions in the captured image of the processed wafer W related to the mth layer. The characteristic quantity of the mth layer is, for example, a characteristic related to the shape of the mth layer, and specifically, a dimension such as the thickness of the mth layer, the line width of the mth layer, or the like. When the estimation results of the characteristic quantity of each of the above regions are acquired in association with the positional information of the regions, the estimation unit 41c specifically estimates an in-plane distribution of the film thickness of the mth layer (distribution of thick and thin portions), an in-plane distribution of the line width of the mth layer (distribution of thick and thin portions).

[0076] The estimation unit 41c estimates the characteristic quantity for all the layers constituting the laminated film on the wafer W, for example.

[0077] Further, in the case where the characteristic quantity of the outermost layer (i.e., the nth layer) of the laminated film composed of n (n is an integer of 2 or more) layers is estimated, the estimation unit 41c acquires the estimated characteristic quantity for each of the layers up to the (n-1)th layer on a region-by-region basis. Then, the estimation unit 41c estimates the characteristic quantity of the nth layer of the processed wafer based on the above-mentioned acquired results of the estimated characteristic quantity, a pixel value in the captured image of the processed wafer W related to the nth layer, a later-described estimation model generated in advance, and the like on a region-by-region basis. The above-mentioned estimation model is generated in advance using a wafer W for model generation (hereinafter, a preparation wafer W). The above-mentioned estimation model is, for example, a model representing the correlation of (X) and (Y), in which (X) is the characteristic quantity of each of the layers up to the (n-1)th layer formed on the wafer W and a pixel value in the captured image of the processed wafer W related to the nth layer, and (Y) is the characteristic quantity of the nth layer of the processed wafer W.

[0078] The characteristic quantity estimated by the estimation unit 41c (hereinafter, sometimes referred to as an "estimated characteristic quantity") is stored in the storage unit 41a on a wafer-by-wafer basis.

[0079] The storage unit 61 of the overall control device 4 stores various kinds of information. The storage unit 61 stores, for example, information used when the above-mentioned estimation model is generated by the model generation unit 62 or the like.

[0080] The model generation unit 62 generates the above-described estimation model in advance for each kind of characteristic quantity of the film (layer). For example, the model generation unit 62 specifically generates an estimation model in advance for each of the thickness of the underlayer film, the thickness of the intermediate layer film, the thickness of the resist film, and the line width of the resist pattern. Details of the generation method are described later.

[0081] The estimation model generated by the model generation unit 62 is stored in the storage unit 61 and is transmitted to the coating and developing apparatus 2 to be stored in the storage unit 41a.

[0082] The acquisition unit 63 acquires information used for the decision of the processing condition in the processing condition decision unit 64 and the correction of the processing condition in the processing condition correction unit 65. Specifically, the acquisition unit 63 acquires, from the coating and developing apparatus 2, the characteristic quantity (of the in-plane distribution) of each of a plurality of layers including the topmost layer of the layered film on the wafer W, which is estimated by the estimation unit 41c of the coating and developing apparatus 2 based on the captured image. For example, the acquisition unit 63 acquires the in-plane distribution of the estimated characteristic quantity from the coating and developing apparatus 2 for each of all the layers of the layered film on the wafer W.

[0083] The processing condition decision unit 64 decides the processing condition in the downstream process based on the acquisition result of the acquisition unit 63, that is, based on the estimated characteristic quantity of each layer of the layered film formed on the above-described wafer W. Specifically, the processing condition decision unit 64 decides the etching processing condition for the wafer W on which the layered film is formed in the etching apparatus 3 based on the estimated characteristic quantity of each layer of the layered film formed on the wafer W.

[0084] The processing condition correction unit 65 corrects the processing condition of the film formation processing and the developing processing related to the layer constituting the layered film on the wafer W based on the acquisition result of the acquisition unit 63, that is, based on the estimated characteristic quantity of each layer of the layered film formed on the above-described wafer W.

[0085] Next, one example of the generation method of the estimation model will be described.

[0086] (1. Initial state capturing process)

[0087] When the estimation model is generated, first, in the coating and developing apparatus 2, the capturing of the preparation wafer W in the initial state before the formation of various films such as the underlayer film is performed, and a captured image thereof is generated.

[0088] Specifically, for example, the surface of the preparation wafer W in the initial state is captured by the capturing mechanism 210 of the first capturing unit 311. Then, based on the capturing result of the capturing mechanism 210, the captured image of the preparation wafer W in the initial state is generated by the image generation unit 41b (hereinafter, sometimes referred to as "initial state captured image"). The generated captured image is transmitted to the overall control apparatus 4 and is stored in the storage unit 61 for each wafer W.

[0089] Further, the prepared wafer W is, for example, a production wafer used at the time of forming a resist pattern at the time of mass production of semiconductor devices, and the surface of the wafer is Figure 2 The pattern is formed similarly.

[0090] (2. Lower layer film forming step)

[0091] After the initial state imaging step, a lower layer film is formed on the prepared wafer W. Specifically, the SOC film is formed on the prepared wafer W by the lower layer film forming unit 11 under predetermined processing conditions, and thereafter, the prepared wafer W is subjected to heat treatment under predetermined processing conditions by the heat treatment unit 21 for the SOC film.

[0092] (3. Post-lower layer film forming imaging step)

[0093] Next, imaging of the prepared wafer W on which the lower layer film is formed is performed, and an imaged image of the prepared wafer W is generated.

[0094] Specifically, for example, the surface of the prepared wafer W on which the SOC film is formed after the lower layer film is imaged by the imaging mechanism 210 of the second imaging unit 312. Then, based on the imaging result of the imaging mechanism 210, the imaged image of the prepared wafer W after the lower layer film is generated by the image generation section 41b (hereinafter, sometimes referred to as "post-lower layer film imaging image"). The generated imaged image is transmitted to the overall control device 4 and stored in the storage section 61 for each wafer W.

[0095] (4. Lower layer film thickness actual measurement step)

[0096] Next, the thickness of the lower layer film formed on the prepared wafer W is measured by a film thickness measurer (not shown) provided outside the processing system 1.

[0097] At this time, for example, the prepared wafer W is divided into 437 regions which are the same number of division regions as the imaged image, and in each region, the film thickness of the lower layer film on the region is measured.

[0098] The measurement result is input to the overall control device 4 and stored in the storage section 61 for each wafer W. Further, as the film thickness measurer, for example, a film thickness gauge using a reflection spectrum method or the like can be used.

[0099] (5. Middle layer film forming step)

[0100] Then, after the film thickness actual measurement process of the intermediate layer film, the preparation wafer W is sent back to the processing system 1, and a resist film is formed on the intermediate layer film of the preparation wafer W. Specifically, the resist film formation unit 13 forms a resist film on the intermediate layer film of the preparation wafer W under predetermined processing conditions, and then the heat treatment unit 21 for PAB processing performs PAB processing on the preparation wafer W under predetermined processing conditions.

[0101] (6. Post-intermediate layer film formation imaging process)

[0102] Next, imaging of the preparation wafer W on which the intermediate layer film is formed is performed, and an imaged image of the preparation wafer W is generated.

[0103] Specifically, for example, the surface of the preparation wafer W on which the SOG film as the intermediate layer film is formed is imaged by the imaging mechanism 210 of the third imaging unit 313. Then, based on the imaging result of the imaging mechanism 210, an imaged image of the preparation wafer W on which the intermediate layer film is formed (hereinafter, sometimes referred to as "post-intermediate layer film formation imaged image") is generated by the image generation section 41b. The generated imaged image is sent to the overall control device 4 and stored in the storage section 61 for each wafer W.

[0104] (7. Film thickness actual measurement process of intermediate layer film)

[0105] Next, similarly to the film thickness actual measurement process of the lower layer film, the thickness of the intermediate layer film formed on the preparation wafer W is measured by a film thickness measurer (not shown) provided outside the processing system 1.

[0106] The measurement result of the thickness of the intermediate layer film is input to the overall control device 4 and stored in the storage section 61 for each wafer W.

[0107] (8. Resist film formation process)

[0108] Then, after the film thickness actual measurement process of the intermediate layer film, the preparation wafer W is sent back to the processing system 1, and a resist film is formed on the intermediate layer film of the preparation wafer W. Specifically, the resist film formation unit 13 forms a resist film on the intermediate layer film of the preparation wafer W under predetermined processing conditions, and then the heat treatment unit 21 for PAB processing performs PAB processing on the preparation wafer W under predetermined processing conditions.

[0109] (9. Post-resist film formation imaging process)

[0110] Next, imaging of the preparation wafer W on which the resist film is formed is performed, and an imaged image of the preparation wafer W is generated.

[0111] Specifically, the surface of the prepared wafer W after the resist film formation is imaged, for example, by the imaging mechanism 210 of the fourth imaging unit 314. Then, by the image generation section 41b, a captured image of the prepared wafer W after the resist film formation (hereinafter, sometimes referred to as "resist film formation after captured image") is generated based on the imaging result of the imaging mechanism 210. The generated captured image is sent to the overall control device 4 and stored in the storage section 61 for each wafer W.

[0112] (10. Resist film thickness actual measurement step)

[0113] Next, the thickness of the resist film formed on the prepared wafer W is measured by a film thickness measurer (not shown) provided outside the processing system 1, as in the film thickness actual measurement step of the underlayer film.

[0114] The measurement result of the thickness of the resist film is input to the overall control device 4 and stored in the storage section 61 for each wafer W.

[0115] (11. Exposure step)

[0116] In addition, after the resist film thickness actual measurement step, the exposure processing of the prepared wafer W is performed in an exposure device connected integrally with the coating and developing device 2. Thus, the resist film on the prepared wafer W is exposed to a predetermined pattern.

[0117] (12. PEB step)

[0118] After that, the prepared wafer W is subjected to the PEB processing by the heat treatment unit 21 for the PEB processing under predetermined processing conditions.

[0119] (13. Developing step)

[0120] Next, the prepared wafer W is subjected to the developing processing. Specifically, the developing processing is performed under predetermined processing conditions by the developing unit 14, and the resist pattern is formed on the wafer W.

[0121] (14. Pattern formation after imaging step)

[0122] Next, the imaging of the prepared wafer W on which the resist pattern is formed is performed, and a captured image of the prepared wafer W is generated.

[0123] Specifically, the surface of the prepared wafer W after the resist pattern formation is imaged, for example, by the imaging mechanism 210 of the fifth imaging unit 315. Then, by the image generation section 41b, a captured image of the prepared wafer W after the resist pattern formation (hereinafter, sometimes referred to as "pattern formation after captured image") is generated based on the imaging result of the imaging mechanism 210. The generated captured image is sent to the overall control device 4 and stored in the storage section 61 for each wafer W.

[0124] (15. Line width actual measurement process of resist pattern)

[0125] Next, the line width of the resist pattern formed on the preparation wafer W is measured with a line width measurer (not shown) provided outside the processing system 1.

[0126] At this time, for example, the preparation wafer W is divided into 437 regions same as the number of divided regions of the captured image, and in each region, the line width of the resist pattern on the region is measured.

[0127] The measurement result is input to the overall control device 4 and stored in the storage section 61 for each wafer W. Further, as the line width measurer, for example, a SEM (SEM: Scanning Electron Microscope) can be used.

[0128] The processes from the above 1. initial state capturing process to the 15. line width actual measurement process of resist pattern are performed on a plurality of preparation wafers W, respectively. It is also possible to intentionally make the processing conditions different between the preparation wafers W so that the thickness of each film on the preparation wafer W, the line width of the resist pattern are different between the preparation wafers W. That is, it is also possible to process the preparation wafers W under a plurality of processing conditions different from each other to generate the estimation model.

[0129] (16. Estimation model generation process of thickness of lower layer film)

[0130] After that, based on the initial state captured image, the measurement result of the thickness of the lower layer film formed on the preparation wafer W measured by the film thickness measurer, and the lower layer film formed after captured image, the estimation model of the thickness of the lower layer film is generated.

[0131] Specifically, for example, by the model generation section 62 of the overall control device 4, from the information of (al) to (a3) below, the estimation model of the film thickness of the lower layer film indicating the correlation between (Al) to (A3) below is generated.

[0132] (al) pixel value in the initial state captured image of each of the above 437 regions of the preparation wafer W

[0133] (a2) pixel value in the lower layer film formed after captured image of each of the above 437 regions of the preparation wafer W

[0134] (a3) measurement result of the thickness of the lower layer film measured by the film thickness measurer of each of the above 437 regions of the preparation wafer W

[0135] (A1) pixel value in the captured image of the wafer W in the initial state

[0136] (A2) Pixel value in a captured image of the wafer W after the lower layer film is formed

[0137] (A3) Thickness of the lower layer film on the wafer W

[0138] Further, in a case where the production wafer is a bare wafer, or the like, a calculation model of the film thickness of the lower layer film indicating the correlation between the above (A2) and (A3) can also be generated from the information of the above (a2) to (a3). In this case, the initial state captured image is not required when the calculation model is generated.

[0139] (Calculation model generation process of thickness of the intermediate layer film)

[0140] Further, a calculation model of the thickness of the intermediate layer film is generated based on the measurement results of the thickness of the intermediate layer film and the thickness of the lower layer film formed on the preparation wafer W measured by the film thickness measurer and the captured image after the intermediate layer film is formed.

[0141] Specifically, for example, the model generation section 62 of the overall control device 4 generates a calculation model of the film thickness of the intermediate layer film indicating the correlation between the following (B1) to (B3) from the information of the following (b1) to (b3) for each of the above 437 regions of the preparation wafer W.

[0142] (b1) Measurement result of the thickness of the lower layer film measured by the film thickness measurer

[0143] (b2) Pixel value in a captured image of the wafer W after the intermediate layer film is formed

[0144] (b3) Measurement result of the thickness of the intermediate layer film measured by the film thickness measurer

[0145] (B1) Thickness of the lower layer film

[0146] (B2) Pixel value in a captured image of the wafer W after the intermediate layer film is formed

[0147] (B3) Thickness of the intermediate layer film

[0148] (Calculation model generation process of thickness of the resist film)

[0149] Further, a calculation model of the thickness of the resist film is generated based on the measurement results of the thickness of the resist film, the thickness of the intermediate layer film, and the thickness of the lower layer film formed on the preparation wafer W measured by the film thickness measurer and the captured image after the resist film is formed.

[0150] Specifically, for example, the model generation section 62 of the overall control device 4 generates a calculation model of the film thickness of the lower layer film indicating the correlation between the following (C1) to (C4) from the information of the following (c1) to (c4) for each of the above 437 regions of the preparation wafer W.

[0151] (c1) Measurement result of thickness of lower layer film measured by film thickness measurer

[0152] (c2) Measurement result of thickness of intermediate layer film measured by film thickness measurer

[0153] (c3) Pixel value in photographed image after resist film formation

[0154] (c4) Measurement result of thickness of resist film measured by film thickness measurer

[0155] (C1) Thickness of lower layer film

[0156] (C2) Thickness of intermediate layer film

[0157] (C3) Pixel value in photographed image of wafer W after resist layer film formation

[0158] (C4) Thickness of resist film

[0159] (Resist pattern line width estimation model generation step)

[0160] In addition, based on the measurement result of line width of the resist pattern formed on the preparation wafer W measured by the line width measurer, the measurement result of thickness of the resist film formed on the preparation wafer W, the thickness of the intermediate layer film, and the thickness of the lower layer film measured by the film thickness measurer, and the photographed image after the pattern formation, the estimation model of the line width of the resist pattern is generated.

[0161] Specifically, for example, the model generation section 62 of the overall control device 4 generates the estimation model of the line width of the resist pattern indicating the correlation between the following (D1) to (D5) from the following (d1) to (d5) of each of the above 437 regions of the preparation wafer W.

[0162] (d1) Measurement result of thickness of lower layer film measured by film thickness measurer

[0163] (d2) Measurement result of thickness of intermediate layer film measured by film thickness measurer

[0164] (d3) Measurement result of thickness of resist film measured by film thickness measurer

[0165] (d4) Pixel value in photographed image after pattern formation

[0166] (d5) Measurement result of line width of resist pattern measured by line width measurer

[0167] (D1) Thickness of lower layer film

[0168] (D2) Thickness of intermediate layer film

[0169] (D3) Thickness of resist film

[0170] (D4) Pixel value in captured image of wafer W after resist pattern formation

[0171] (D5) Line width of resist pattern

[0172] As described above, each estimation model is generated in advance before processing in the production in the processing system 1. The each estimation model generated in advance is transmitted to the coating and developing apparatus 2 and stored in the storage section 41a.

[0173] Next, the processing in the production in the processing system 1 will be described. Figure 9 is a flowchart illustrating one example of the processing in the production in the processing system 1.

[0174] In the production in the processing system 1, for example, as shown in Figure 9 , the process of laminating films on the wafer W and forming a resist pattern (step S1) and the process of generating a captured image of the wafer W (step S2) are performed in parallel.

[0175] Specifically, the wafer W is subjected to the same processing as the above 1. initial state capturing process, 2. lower layer film formation process, 3. lower layer film formation after capturing process, 5. intermediate layer film formation process, 6. intermediate layer film formation after capturing process, 8. resist film formation process, 9. resist film formation after capturing process, 11. exposure process, 12. PE process, 13. developing process, 14. pattern formation after capturing process. Thereby, after the lower layer film, the intermediate layer film, and the resist film are laminated on the wafer W, the resist film is developed to form a resist pattern. Also, the captured image of the wafer W in the initial state, the captured image of the wafer W after the lower layer film formation, the captured image of the wafer W after the intermediate layer film formation, the captured image of the wafer W after the resist film formation, and the captured image of the wafer W after the resist pattern formation are generated by the image generation section 41b. The generated captured images are stored in the storage section 41a for each wafer W.

[0176] In addition, in the production, for example, the process of estimating the thickness of the lower layer film (step S3), the process of estimating the thickness of the layers after the second layer (the intermediate layer and the resist film) (step S4), and the process of estimating the line width of the resist pattern (step S5) are performed. Each estimation result is stored in the storage section 41a for each wafer W.

[0177] In the process of calculating the thickness of the underlayer film as step S3, the thickness of the underlayer film is calculated, for example, by the calculation section 41c, based on the captured image of the wafer W in the initial state, the captured image of the wafer W after the underlayer film is formed, and the calculation model of the thickness of the underlayer film stored in the storage section 41a. Specifically, for each of the above-mentioned 437 regions of the wafer W, the thickness of the underlayer film is calculated based on the pixel value in the captured image of the wafer W in the initial state, the pixel value in the captured image of the wafer W after the underlayer film is formed, and the calculation model of the thickness of the underlayer film. That is, the in-plane distribution of the thickness of the underlayer film is estimated. Further, in generating the calculation model of the thickness of the underlayer film, the pixel value of the captured image of the wafer W in the initial state is not used for the calculation of the thickness of the underlayer film in the case where the captured image in the initial state is not used.

[0178] In the process of calculating the thickness of the second layer and subsequent layers (the intermediate layer and the resist film) as step S4, first, for example, the in-plane distribution of the calculated thickness is acquired from the storage section 41a by the calculation section 41c for the layer located below the topmost layer of the layered film that is the object of the calculation of the film thickness. In the case where the thickness of the intermediate layer film is calculated, the in-plane distribution of the calculated thickness of the underlayer film is acquired from the storage section 41a, and in the case where the thickness of the resist film is calculated, the in-plane distribution of the calculated thickness of the underlayer film and the intermediate layer film is acquired from the storage section 41a.

[0179] Then, the thickness of the topmost layer of the layered film that is the object of the calculation is calculated by the calculation section 41c based on the acquired result of the calculated thickness, the captured image of the wafer W in which the topmost layer of the layered film is formed, and the calculation model corresponding to the topmost layer.

[0180] For example, the thickness of the intermediate layer film is calculated based on the in-plane distribution of the calculated thickness of the underlayer film, the captured image of the wafer W after the intermediate layer film is formed, and the calculation model of the thickness of the intermediate layer film. Specifically, for each of the above-mentioned 437 regions of the wafer W, the thickness of the intermediate layer film is calculated based on the calculated thickness of the underlayer film, the pixel value in the captured image of the wafer W after the intermediate layer film is formed, and the calculation model of the thickness of the intermediate layer film. That is, the in-plane distribution of the thickness of the intermediate layer film is calculated. Further, the thickness of the resist film is calculated based on the in-plane distribution of the calculated thickness of the underlayer film and the intermediate layer film, the captured image of the wafer W after the resist film is formed, and the calculation model of the thickness of the resist film. Specifically, for each of the above-mentioned 437 regions of the wafer W, the thickness of the resist film is calculated based on the calculated thickness of the underlayer film and the intermediate layer film, the pixel value in the captured image of the wafer W after the resist layer film is formed, and the calculation model of the thickness of the resist film. That is, the in-plane distribution of the thickness of the resist film is calculated.

[0181] In the process of estimating the line width of the resist pattern as step S5, for example, first, the in-plane distribution of the estimated thickness is acquired from the storage section 41a by the estimation section 41c for each layer including the topmost layer of the laminated film on the wafer W before development. Specifically, the estimated thicknesses of the underlayer film, the intermediate layer film, and the resist film (before development) are acquired from the storage section 41a.

[0182] Then, the line width of the resist pattern is estimated by the estimation section 41c based on the acquired in-plane distributions of the estimated thicknesses of the underlayer film, the intermediate layer film, and the resist film, the captured image of the wafer W after the resist pattern is formed, and the estimation model of the line width of the resist pattern. Specifically, the line width of the resist pattern can be estimated for each of the above-mentioned 437 regions of the wafer W by estimating the estimated thicknesses of the underlayer film, the intermediate layer film, and the resist film, the pixel values in the captured image of the wafer W after the resist pattern is formed, and the estimation model of the line width of the resist pattern. That is, the in-plane distribution of the line width of the resist pattern is estimated.

[0183] When the estimation of each characteristic quantity is completed, a process of deciding the etching treatment condition is performed (step S6).

[0184] In this process, for example, first, the acquisition section 63 acquires the in-plane distribution of the estimated line width of the resist pattern formed on the wafer W by the coating and developing device 2 and the in-plane distribution of the estimated thickness of the intermediate layer film from the coating and developing device 2.

[0185] Then, the processing condition decision section 64 decides the etching treatment condition of the etching device 3 based on the information acquired by the acquisition section 63. For example, in a case where the estimated line width of the resist pattern acquired by the acquisition section 63 falls within the desired range in all regions in the plane of the wafer W and the estimated thickness of the intermediate layer film acquired by the acquisition section 63 is thinner than the desired thickness only at the outer periphery of the wafer, the processing condition decision section 64 decides the etching treatment condition as follows. That is, in this case, the processing condition decision section 64 decides (that is, adjusts) the etching treatment condition of the LTO film etching unit 51 so that the etching amount per unit time in the LTO film etching unit 51 is smaller only at the outer periphery of the wafer. The etching treatment condition to be adjusted is the flow rate of the processing gas for etching, the temperature of the wafer, and the like. The adjusted etching treatment condition is transmitted to the control section (not shown) of the etching device 3.

[0186] Next, a process of etching by the etching device 3 is performed (step S7).

[0187] In this process, etching by the LTO film etching unit 51, etching by the TiN film etching unit 52, and etching by the oxide film etching unit 53 are sequentially performed under the control of the control section (not shown) of the etching device 3. In a case where the adjustment of the etching treatment condition is performed in step S6, the etching in the etching device 3 is performed under the adjusted etching treatment condition.

[0188] In addition, a process of correcting the processing conditions in the coating and developing apparatus 2 is performed (step S8).

[0189] In this process, for example, first, the acquisition unit 63 acquires the in-plane distribution of the estimated thickness of the resist film formed on the wafer W by the coating and developing apparatus 2, the in-plane distribution of the estimated thickness of the intermediate layer film, and the in-plane distribution of the estimated thickness of the lower layer film.

[0190] Then, the processing condition correction unit 65 corrects the processing conditions in the coating and developing apparatus 2 based on the results acquired by the acquisition unit 63. For example, in the case where the entire laminated film composed of the lower layer film, the intermediate layer film, and the resist film has a characteristic film thickness distribution (for example, a distribution in which the film thickness becomes thick as it goes toward the center of the substrate or a distribution in which the film thickness becomes thick as it goes toward the outer periphery of the substrate), the processing condition correction unit 65 corrects it as follows. That is, in this case, the processing condition correction unit 65 determines the film among the lower layer film, the intermediate layer film, and the resist film that has the same film thickness distribution as the above characteristic film thickness distribution based on the results acquired by the acquisition unit 63. The processing condition correction unit 65 corrects the processing condition related to the determined film, for example, the heat treatment condition in the heat treatment unit 21 for the film.

[0191] The above processes are performed for each wafer W.

[0192] Further, in the above, the information acquired by the acquisition unit 63 from the coating and developing apparatus 2 used in the determination by the processing condition determination unit 64 and the correction by the processing condition correction unit 65 is information of the characteristic amount itself of each layer (specifically, the in-plane distribution thereof). The information acquired by the acquisition unit 63 is information indicating the characteristic amount of each layer, and for example, information of the pixel value in the captured image of the wafer W related to the characteristic amount (specifically, the in-plane distribution thereof) can be used instead of or in addition to the information of the characteristic amount itself (specifically, the in-plane distribution thereof).

[0193] As described above, the processing system 1 of the present embodiment has the coating and developing apparatus 2 and the like as a semiconductor manufacturing device and the imaging units 31. Further, the processing system 1 has the image generation section 41b that generates an imaging image of each layer constituting the stacked film on the wafer W based on the imaging result of the processed wafer W based on the imaging by the imaging units 31 with respect to the layer. Further, the processing system 1 has the acquisition section 63 that acquires information indicating a characteristic amount calculated based on the imaging image with respect to each of a plurality of layers including the topmost layer of the stacked film on the wafer W. That is, in the present embodiment, the acquisition section 63 also acquires the processing result applied to the wafer W with respect to the layers other than the topmost layer. Therefore, based on the acquisition result of the acquisition section 63, it is possible to more appropriately set the processing condition of the wafer W having the stacked film, such as the etching processing condition, or more appropriately correct the processing condition in the coating and developing apparatus 2.

[0194] Further, in the present embodiment, the imaging image of the wafer W is used for the calculation of the characteristic amount, and therefore, compared with the case where the characteristic amount is actually measured using a film thickness meter, a line width meter, or the like, it is possible to acquire the processing result applied to the wafer W with respect to the layers other than the topmost layer without loss of throughput.

[0195] Further, in the present embodiment, the acquisition section 63 acquires information indicating a characteristic amount calculated based on the imaging image with respect to each of a plurality of layers including the topmost layer of the stacked film on the wafer W, and the processing condition correction section 65 corrects the processing condition in the coating and developing apparatus 2 based on the acquisition result. Therefore, in the processing condition correction section 65, the characteristic amount is grasped with respect to not only the topmost layer but also the lower layers in the stacked layer, and the state of each layer is compared with each other and comprehensively studied, and it is possible to appropriately select the process of the correction of the processing condition and determine the correction amount thereof.

[0196] Further, in the present embodiment, the structures of the imaging units 31 used for acquiring each imaging image are substantially the same as each other. Therefore, even if the correction is not performed with respect to each imaging unit 31, it is possible to acquire the same imaging image from the same imaging object, and therefore, it is possible to easily perform the calculation of the characteristic amount based on the imaging image and the like.

[0197] Further, in the present embodiment, the imaging units 31 are individually provided for each layer constituting the stacked film formed on the wafer W, and specifically, for each processing with respect to the layer. Further, the imaging units 31 each have the same kind of light source and camera, that is, the same kind of imaging optical system. By performing the imaging of the surface of each layer with the same kind of imaging optical system, it is possible to reduce the machine difference in performance (for example, precision, reproducibility) of the imaging result at each time point and make it uniform, and it is possible to ensure the reliability when the same model, that is, the related information is used.

[0198] In this embodiment, imaging unit 31 captures a single layer of the laminated film on wafer W within a time period that does not exceed the time required for the exposure process. Specifically, imaging is performed within a time period that does not exceed the time from the moment wafer W is loaded into an exposure device (not shown) to the moment wafer W is removed from the exposure device after the exposure process is complete. This prevents the time between one exposure process and the next from being increased due to imaging, thereby preventing a decrease in production throughput caused by imaging.

[0199] Furthermore, in this embodiment, the model generation unit 62 is provided in the same control device as the acquisition unit 63 and the processing condition determination unit 64. Alternatively, the model generation unit 62, the acquisition unit 63, and the processing condition determination unit 64 may be provided in separate control devices. In this case, when the information acquired by the acquisition unit 63 from the coating and developing device 2 is information on pixel values ​​in a captured image of the wafer W related to characteristic quantities of each layer (specifically, its in-plane distribution), the acquisition unit 63 also acquires related information indicating the correlation between the characteristic quantities and the pixel values, namely, the estimation model. Thus, for example, if the information acquired by the acquisition unit 63 from the coating and developing device 2 is the in-plane distribution of the pixel values, and the pixel values ​​indicate abnormal values, it is possible to determine whether the cause is a malfunction of the imaging unit 31 or an inaccuracy in the estimation model.

[0200] (Second embodiment)

[0201] Figure 10 It is a diagram schematically showing the general configuration of a substrate processing system according to the second embodiment.

[0202] As shown in the figure, the processing system 1 a as the substrate processing system of this embodiment includes a coating device 5 in addition to the coating and developing device 2 a , the etching device 3 , and the overall control device 4 .

[0203] The coating and developing device 2a omits the lower film forming unit 11 of the coating and developing device 2 in the first embodiment. Furthermore, the omitted lower film forming unit 11 is provided in the coating device 5. Therefore, the processing system 1a includes: the coating and developing device 2a as semiconductor manufacturing equipment, which includes an intermediate film forming unit 12 as a spin coating unit, a resist film forming unit 13, and a developing unit 14; and the coating device 5 including the lower film forming unit 11 as a spin coating unit. In other words, the processing system 1a includes a plurality of semiconductor manufacturing equipment equipped with spin coating units.

[0204] In addition, in the coating and developing device 2 a , the second imaging unit 312 of the coating and developing device 2 in the first embodiment is omitted.

[0205] On the other hand, the coating device 5 is provided with a first imaging unit 711 and a second imaging unit 712 (hereinafter collectively referred to as the imaging unit 71). The structure of the imaging unit 71 is substantially the same as that of the imaging unit 31 of the coating and developing device 2a. The substantially identical structure of the imaging units means that the same imaging results can be obtained when imaging the same object.

[0206] The first imaging unit 711 is used to image the wafer W before the lower layer film forming process by the lower layer film forming unit 11 in the coating apparatus 5 .

[0207] The second photographing unit 712 is used to photograph the wafer W after the lower layer film forming process.

[0208] Furthermore, the coating device 5 includes a heat treatment unit 21 for heat treatment after the SOC film F4 as the lower layer film is formed.

[0209] Furthermore, the coating device 5 is provided with a control unit 81 .

[0210] The control unit 81 is, for example, a computer having a CPU, memory, and the like, and includes a program storage unit (not shown). This program storage unit stores programs for controlling the operation of various units and a drive system such as a conveyor device (not shown) to perform various processes on the wafer W. Alternatively, the programs may be stored on a computer-readable storage medium and installed from the storage medium into the control unit 81. Part or all of the programs may be implemented by dedicated hardware (circuit board).

[0211] The control unit 81 includes a storage unit 81 a , an image generating unit 81 b , and an estimating unit 81 c .

[0212] The storage unit 81 a stores various information, such as an estimation model for the thickness of the lower layer film generated in advance by the model generation unit 62 of the overall control device 4 .

[0213] The image generating unit 81b generates a captured image of the wafer W based on the image capturing result of the wafer W by the image capturing mechanism 210 of the image capturing unit 71. Specifically, the image generating unit 81b generates a captured image of the wafer W in its initial state and a captured image of the wafer W after the lower layer film is formed.

[0214] Basically, the captured image generated by the image generating unit 81 b is stored in the storage unit 81 a for each wafer W.

[0215] The estimation unit 81c estimates the thickness of the underlayer film formed by the coating device 5 for each of the above-mentioned 437 regions of the wafer W, based on the pixel value in the captured image of the wafer W in the initial state, the pixel value in the captured image of the wafer W after the underlayer film is formed, and the estimation model of the thickness of the underlayer film generated in advance. That is, the estimation unit 81c estimates the in-plane distribution of the thickness of the underlayer film formed by the coating device 5. The generation method of the above-mentioned estimation model is the same as that of the first embodiment.

[0216] The characteristic quantity estimated by the estimation unit 81c is stored in the storage unit 81a for each wafer W.

[0217] In addition, in the present embodiment, when the estimation of the in-plane distribution of the thickness of the intermediate layer by the estimation unit 41c of the coating and developing device 2a is performed, the in-plane distribution of the estimated thickness of the underlayer film used for the estimation is acquired from, for example, the coating device 5. Also when the estimation of the thickness of the resist film, the resist pattern by the estimation unit 41c of the coating and developing device 2a is performed, the in-plane distribution of the estimated thickness of the underlayer film used for the estimation is acquired from, for example, the coating device 5.

[0218] In addition, in the present embodiment, when the etching treatment condition is decided, in the case where the in-plane distribution of the estimated thickness of the underlayer film is required, the information of the in-plane distribution of the estimated thickness is acquired from, for example, the coating device 5 by the acquisition unit 63.

[0219] In the present embodiment, when the modification of the treatment condition in the coating and developing device 2a, the coating device 5 by the treatment condition modification unit 65 is performed, in the case where the in-plane distribution of the estimated thickness of the underlayer film is required, the information of the in-plane distribution of the estimated thickness is also acquired from, for example, the coating device 5 by the acquisition unit 63.

[0220] (Third Embodiment)

[0221] Figure 11 is a diagram schematically showing the outline structure of the substrate processing system of the third embodiment.

[0222] As the processing system 1b of the present embodiment, as shown in the figure, in addition to the coating and developing device 2, the etching device 3, and the overall control device 4, there are the film forming devices 6a, 6b, 6c, the photographing devices 7a, 7b, 7c, 7d, and the polishing device 8.

[0223] The film forming devices 6a, 6b, 6c form a single layer constituting the laminated film by an evaporation method such as a CVD method, an ALD method, or the like. The film forming device 6a forms, for example, a TiN film F2 on the wafer W. Figure 2 The film forming device 6b forms, for example, an LTO film F3 on the wafer W. Figure 2 In addition, the film forming device 6c forms, for example, a TiN film F2 on the wafer W after the etching by the etching device 3. Figure 7In the wafer W in the state shown in (C), a Cu film is formed as a metal wiring layer.

[0224] The imaging devices 7a, 7b, 7c, and 7d respectively include imaging units 91a, 91b, 91c, and 91 having substantially the same structure as the imaging unit 31. Semiconductor manufacturing equipment such as the film forming devices 6a, 6b, and 6c and the coating and developing device 2 are separately provided.

[0225] The imaging unit 91a is used to image the wafer W before being carried into the film forming apparatus 6a, that is, before the TiN film is formed.

[0226] The imaging unit 91 b is used to image the wafer W after the TiN film forming process by the film forming apparatus 6 a and before being carried into the film forming apparatus 6 b .

[0227] The imaging unit 91 c is used to image the wafer W after the LTO film formation process performed by the film forming apparatus 6 b .

[0228] The imaging unit 91d is used to image the wafer W after the Cu film forming process performed by the film forming apparatus 6c.

[0229] Furthermore, the imaging devices 7b to 7d are provided with control units 101 to 103, respectively.

[0230] The control units 101, 102, and 103 have storage units 101a, 102a, and 103a that are the same as the storage units 41a and 81a of the control units 41 and 81, image generation units 101b, 102b, and 103b that are the same as the image generation units 41b and 81b, and calculation units 101c, 102c, and 103c that are the same as the calculation units 41c and 81c.

[0231] Similar to the estimation units 41 c and 81 c of the first and second embodiments, the estimation unit 101 c estimates the thickness of the TiN film formed by the film forming apparatus 6 a, for example, for each of the 437 regions of the wafer W, based on the pixel values ​​in the image captured of the wafer W before the TiN film formation process, the pixel values ​​in the image captured of the wafer W after the TiN film formation process, and a pre-generated estimation model for the thickness of the TiN film. Specifically, the estimation unit 101 c estimates the in-plane distribution of the thickness of the TiN film formed by the film forming apparatus 6 a.

[0232] Similarly, the estimation unit 102c estimates the thickness of the LTO film formed by the film forming device 6b, for example, for each of the above-mentioned 437 areas of the chip W based on the estimated thickness of the TiN film, the pixel value in the captured image of the chip W after the LTO film is formed, and the pre-generated estimation model of the thickness of the LTO film.

[0233] Similarly, the estimation section 103c estimates the thickness of the Cu film formed by the film formation device 6c, for example, for each of the above-mentioned 437 regions of the wafer W, from the pixel values in the captured image of the wafer W before the Cu film formation processing and the pixel values in the captured image of the wafer W after the Cu film formation, and the like.

[0234] The method of generating the estimation model used in the estimation sections 101c, 102c, 103c is the same as the estimation model of the thickness of the underlayer film and the estimation model of the thickness of the intermediate layer film in the first embodiment.

[0235] The polishing device 8 is a device that removes an unnecessary film by polishing the wafer W. For example, the polishing device 8 removes an unnecessary portion of the Cu layer formed by the film formation device 6c.

[0236] In the present embodiment, the acquisition section 63 of the overall control device 4 also acquires information indicating the estimated thickness of the TiN film of the wafer W that is a processing target and information indicating the estimated thickness of the Cu film from the capturing device 7b and the capturing device 7c.

[0237] Then, the processing condition decision section 64 decides the polishing processing condition in the polishing device 8 based on the information indicating the estimated thickness of the TiN film of the wafer W that is a processing target and the information indicating the estimated thickness of the Cu film acquired by the acquisition section 63. The polishing processing condition is, for example, a polishing pressure, a polishing track of a polishing pad, and the like.

[0238] For example, in a case where the estimated thickness of the Cu film is the same in the wafer surface and the estimated thickness of the TiN film is only greater than a desired thickness at the wafer periphery, the Cu layer at the wafer periphery is easily shaved off, and thus, when the polishing pressure and the polishing time are made the same in the wafer surface, the thickness of the Cu layer after polishing becomes different in the wafer surface. Therefore, in the above case, the processing condition decision section 64 sets a larger polishing pressure for the wafer center, for example, or adjusts the above-mentioned polishing track so that the polishing time at the wafer center becomes longer.

[0239] In the present embodiment, the polishing processing can be appropriately performed.

[0240] In addition, it is also possible that, in the processing system lb, a device that estimates a characteristic quantity of the wafer W after processing transmits the following information (A), (B) to a device that estimates the same as the processing performed downstream of the estimation object of the device (for example, the capturing device 7b transmits to the capturing device 7c, or the capturing device 7c transmits to the coating and developing device 2).

[0241] (A) correlation information indicating the in-plane distribution of the pixel values in the captured image of the wafer W used in the device and the correlation between the pixel values and the above-mentioned characteristic quantity, that is, an estimation model

[0242] (B) the in-plane distribution of the pixel values used by the device that performs the same estimation as the device that estimates the process of the film on the wafer on the upstream side of the estimation target, and the estimation model

[0243] Then, the in-plane distribution of the pixel values in the captured image of the wafer W and the estimation model are stored in association with the corresponding layer.

[0244] In the present embodiment, the wafer W is captured by the capturing device 7b to 7d after the process by the film forming device 6a to 6c, and the captured image based on the captured result is used to estimate the process result of the film forming device 6a to 6c. Similarly, the wafer W is captured by the capturing device after the process by the etching device 3 and the polishing device 8, and the captured image based on the captured result is used to estimate the process result of the etching device 3 and the process result of the polishing device 8. The process result of the etching device 3 is, for example, the dimension of the line width and the like of the pattern after etching, and the process result of the polishing device 8 is, for example, the polishing amount of the Cu layer.

[0245] Further, in the above example, when the characteristic quantity is estimated for each region for the film on the wafer W after the second layer, the film thickness in each region of each layer is used as the characteristic quantity of each layer on the wafer W before the process related to the film of the estimation target. However, the characteristic quantity of each layer is not limited to this, and can be, for example, the in-plane average of the thickness of the layer.

[0246] Further, in the above example, when the characteristic quantity is estimated for each region for the film on the wafer W after the second layer, the film thickness in each region of each layer is used as the characteristic quantity of each layer on the wafer W before the process related to the film of the estimation target. However, the characteristic quantity of each layer is not limited to this, and can be, for example, the in-plane average of the thickness of the layer.

[0247] Further, in the above example, the processing condition decision section 64 adjusts the processing condition in the in-plane direction of the wafer W. However, in the case where the estimation result of the characteristic quantity differs between wafers and between lots, the processing condition decision section 64 can also adjust the processing condition for each wafer W or for each lot.

[0248] Similarly, in the case where the estimation result of the characteristic quantity differs between wafers W or between lots, the processing condition correction section 65 can also correct the processing condition for each wafer W or for each lot.

[0249] In the above example, in calculating the feature quantity of the film on the second layer on the wafer W, the captured image of the wafer W before the film is not used. However, the captured image of the wafer W before the film can be used. For example, in calculating the thickness of the resist film, the captured image of the wafer W after the resist film is formed, the captured image of the wafer W after the intermediate layer film is formed, the captured image of the wafer W after the lower layer film is formed, and the captured image of the wafer W in the initial state can be used. Further, for example, in calculating the line width of the resist pattern, the captured image of the wafer W after the resist pattern is formed, the captured image of the wafer W after the resist film is formed, the captured image of the wafer W after the intermediate layer film is formed, the captured image of the wafer W after the lower layer film is formed, and the captured image of the wafer W in the initial state can be used. In addition, in calculating the thickness of the resist film and the line width of the resist pattern in the third embodiment, the captured image of the wafer W after the LTO film is formed, and the captured image of the wafer W after the TiN film is formed can be used.

[0250] Thus, the calculation of the feature quantity that more accurately reflects the past processing state can be performed.

[0251] In the drawings, the entire control device 4 is provided separately from the semiconductor manufacturing device such as the coating and developing device 2, and the capturing devices 7a to 7d. However, part or all of the functions of the entire control device 4 can be incorporated in the semiconductor manufacturing device such as the coating and developing device 2, and the capturing devices 7a to 7d.

[0252] In addition, the functions of the image generation section and the calculation section provided in the coating and developing device 2, the capturing devices 7b to 7d, and the like can be incorporated in the entire control device 4 and the like.

[0253] The embodiments disclosed herein are illustrative in all aspects and should not be considered limiting. The above-described embodiments can be omitted, replaced, changed in various ways without departing from the scope of the appended claims and the spirit thereof.

[0254] Further, the following configurations also belong to the technical scope of the present application.

[0255] (1) A substrate processing method, comprising:

[0256] generating a captured image of a processed substrate related to each layer constituting a laminated film on the substrate; and

[0257] acquiring information indicating a feature quantity calculated based on the captured image for each of a plurality of layers including the top layer of the laminated film on the substrate.

[0258] According to the above (1), the processing conditions and the like for the substrate having the layered film can be appropriately set.

[0259] (2) In the substrate processing method described in the above (1), the information indicating the characteristic quantity is at least either of information of the characteristic quantity itself and information of a pixel value in the captured image related to the characteristic quantity.

[0260] (3) In the substrate processing method described in the above (2),

[0261] the information indicating the characteristic quantity includes information of a pixel value in the captured image related to the characteristic quantity,

[0262] the substrate processing method further includes a step of acquiring correlation information indicating a correlation between the characteristic quantity and the pixel value.

[0263] (4) In the substrate processing method described in any one of the above (1) to (3),

[0264] including a step of deciding a condition of processing of the substrate on which the layered film is formed, based on an acquisition result in the step of acquiring the information indicating the characteristic quantity.

[0265] (5) In the substrate processing method described in the above (4),

[0266] the processing of the substrate on which the layered film is formed is etching processing.

[0267] (6) In the substrate processing method described in the above (4) or (5),

[0268] the processing of the substrate on which the layered film is formed is polishing processing.

[0269] (7) In the substrate processing method described in any one of the above (1) to (6),

[0270] including a step of correcting a condition of processing related to a layer constituting the layered film on the substrate, based on an acquisition result in the step of acquiring the information indicating the characteristic quantity.

[0271] (8) In the substrate processing method described in any one of the above (1) to (7),

[0272] the layered film is formed using a plurality of semiconductor manufacturing apparatuses.

[0273] (9) In the substrate processing method described in the above (8),

[0274] the plurality of semiconductor manufacturing apparatuses include a plurality of semiconductor manufacturing apparatuses each having a spin coating unit that applies a processing liquid to a substrate by a spin coating method.

[0275] (10) The substrate processing method according to any one of (8) or (9) above,

[0276] The plurality of semiconductor manufacturing apparatuses include:

[0277] A semiconductor manufacturing apparatus having a spin coating unit that forms a single layer constituting the layered film by a spin coating method; and

[0278] A film forming apparatus that forms a single layer constituting the layered film by an evaporation method.

[0279] (11) The substrate processing method according to any one of (1) to (10) above,

[0280] further comprising a step of photographing, by a photographing unit, a surface of the substrate in a state where no other layer is formed on a layer after processing related to the layer, for each layer constituting the layered film on the substrate,

[0281] The photographing units have substantially the same structure.

[0282] (12) The substrate processing method according to (11) above,

[0283] The photographing units are provided individually for each layer of the layered film,

[0284] The photographing units each use the same kind of light source and camera for photographing.

[0285] (13) The substrate processing method according to any one of (1) to (10) above, further comprising:

[0286] a step of photographing, by a photographing unit, a surface of the substrate in a state where no other layer is formed on a layer after processing related to the layer, for each layer constituting the layered film on the substrate; and

[0287] a step of exposing processing, by an exposure device, any one layer constituting the layered film on the substrate,

[0288] the photographing of the one layer constituting the layered film on the substrate is performed within a time not exceeding a time from when the substrate is fed into the exposure device to when the substrate is discharged from the exposure device after the exposure processing is completed.

[0289] (14) A substrate processing system comprising:

[0290] a semiconductor manufacturing apparatus;

[0291] a photographing unit;

[0292] an image generation section that acquires a photographed image based on a result of photographing, by the photographing unit, the substrate after processing related to each layer constituting the layered film on the substrate, for each layer constituting the layered film on the substrate, and

[0293] An acquisition unit acquires information indicating a feature quantity calculated based on the captured image, for each of a plurality of layers including the outermost layer of the layered film on the substrate.

[0294] (15) In the substrate processing system described in the above (14),

[0295] The above-described capturing unit is provided for each process related to a layer constituting the layered film on the substrate.

[0296] (16) In the substrate processing system described in the above (14) or (15),

[0297] At least a part of the above-described capturing unit is provided in a device separate from the semiconductor manufacturing device.

Claims

1. A method of processing a substrate, characterized by, comprises: a step of generating a captured image of the processed substrate associated with each layer of the layered film formed on the substrate from the captured image; a step of acquiring information indicating a feature quantity calculated based on the captured image for each of a plurality of layers including the topmost layer of the layered film formed on the substrate, the feature quantity being related to a feature associated with the shape of the layer; and a step of comparing the state of each of the plurality of layers with each other based on the information indicating the feature quantity of each of the plurality of layers in the step of acquiring information indicating the feature quantity, and determining a condition for processing of the substrate on which the layered film is formed, or correcting a condition for processing associated with each layer of the layered film formed on the substrate.

2. The substrate processing method according to claim 1, wherein: the information indicating the feature quantity is at least either information of the feature quantity itself or information of a pixel value in the captured image associated with the feature quantity.

3. The substrate processing method according to claim 2, wherein: the information indicating the feature quantity includes information of a pixel value in the captured image associated with the feature quantity, the substrate processing method further comprises a step of acquiring correlation information indicating a correlation between the feature quantity and the pixel value.

4. The substrate processing method according to claim 1, wherein: the processing of the substrate on which the layered film is formed is etching processing.

5. The substrate processing method according to claim 1 or 4, wherein: the processing of the substrate on which the layered film is formed is polishing processing.

6. The substrate processing method according to any one of claims 1 to 4, wherein: the layered film is formed using a plurality of semiconductor manufacturing apparatuses.

7. The substrate processing method according to claim 6, wherein: the plurality of semiconductor manufacturing apparatuses include a plurality of semiconductor manufacturing apparatuses each having a spin coater unit that applies a processing liquid to a substrate by a spin coating method.

8. The substrate processing method according to claim 6, wherein: the plurality of semiconductor manufacturing apparatuses include: a semiconductor manufacturing apparatus having a spin coater unit that forms a single layer constituting the layered film by a spin coating method; and a film forming apparatus that forms a single layer constituting the layered film by an evaporation method.

9. The substrate processing method according to any one of claims 1 to 4, further comprising: a step of capturing, by a capturing unit, a surface of a substrate in a state where no other layer is formed on a layer associated with the layer after processing of the layer, for each layer constituting a layered film formed on the substrate; the capturing units all have substantially the same structure.

10. The method for processing a substrate as set forth in claim 9, wherein further comprising: the capturing unit is provided separately for each layer of the layered film, the capturing units respectively use the same kind of light source and camera to capture.

11. The substrate processing method according to any one of claims 1 to 4, wherein: further comprising: a step of capturing, by a capturing unit, a surface of a substrate in a state where no other layer is formed on a layer associated with the layer after processing of the layer, for each layer constituting a layered film formed on the substrate; and a step of exposing any layer constituting the layered film formed on the substrate by an exposure apparatus, The imaging of one layer constituting the laminated film on the substrate is performed within a time period not exceeding the time from when the substrate is fed into the exposure device to when the substrate is fed out of the exposure device after the exposure process is completed.

12. A substrate processing system, comprising: include: semiconductor manufacturing equipment; Filming unit; an image generating section for acquiring an image of each layer constituting the laminated film on the substrate based on an image pickup result of the substrate after the processing related to the layer being picked up by the imaging unit; an acquisition unit that acquires information indicating a feature value estimated based on the captured image for each of a plurality of layers including an outermost layer of a laminated film on a substrate, wherein the feature value relates to a feature related to a shape of the layer; and A processing condition determination unit that compares the states of each of the multiple layers with each other based on the information representing the characteristic amount of each of the multiple layers acquired by the acquisition unit and determines the processing conditions for the substrate on which the stacked film is formed, or a processing condition correction unit that compares the states of each of the multiple layers with each other based on the information representing the characteristic amount of each of the multiple layers acquired by the acquisition unit and corrects the processing conditions related to the layers constituting the stacked film on the substrate.

13. The substrate processing system according to claim 12, wherein: The imaging unit is provided for each process associated with a layer constituting the laminated film on the substrate.

14. The substrate processing system according to claim 12 or 13, wherein: At least a portion of the imaging unit is provided in a device separate from the semiconductor manufacturing device.

Images