Semiconductor device

Abstract

A semiconductor device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least: one or more semiconductor channels; a dielectric; a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or more semiconductor channels via the dielectric; a planarization layer; a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via a via in at least the planarization layer, and wherein a semiconductor channel region is at least partially located outside a via region.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with stable performance and a method for manufacturing the same. Background Technology

[0002] A semiconductor device may include a stack of layers that defines at least two conductor patterns on two of its layers; and one or more semiconductor channels that are electrically connected in series between portions of one conductor pattern and that are capacitively coupled to a conductor of the other conductor pattern.

[0003] Conventionally, insulating layers or stacks of insulating layers both provide a coupling dielectric and protect the lower conductor pattern during the formation of the upper conductor pattern.

[0004] The inventors of this application have invented techniques aimed at improving the performance and / or stability of such semiconductor devices. Summary of the Invention

[0005] The present invention provides an apparatus comprising a stack of layers defining one or more electronic components, wherein the stack comprises at least:

[0006] One or more semiconductor channels;

[0007] Dielectric;

[0008] A first conductor pattern defines one or more coupling conductors, wherein the one or more coupling conductors are coupled to the one or more semiconductor channels via the dielectric capacitance;

[0009] Planarization layer;

[0010] A second conductor pattern defines one or more wiring conductors, wherein the second conductor pattern contacts the first conductor pattern via a via in at least the planarization layer, and wherein a semiconductor channel region is at least partially located outside the via region.

[0011] According to one embodiment, the via is located entirely outside the semiconductor channel region.

[0012] According to one embodiment, the stack includes a third conductor pattern comprising conductor elements electrically connected in series via the semiconductor channel; and wherein the vias are located in one or more regions not occupied by any conductor elements of the third conductor pattern.

[0013] According to one embodiment, the second conductor pattern includes a metal pattern, and the first conductor pattern includes a conductive metal oxide pattern.

[0014] According to one embodiment, the stack includes a third conductor pattern located beneath the dielectric and a patterned semiconductor layer defining the one or more semiconductor channels; wherein the patterned semiconductor layer and the dielectric partially overlap with the third semiconductor pattern; and wherein the first conductor pattern and the third conductor pattern are configured such that the first conductor pattern and the third conductor pattern do not overlap.

[0015] According to one embodiment, the third conductor pattern is formed on a portion of the fourth conductor pattern, wherein the portion of the fourth conductor pattern not covered by the third conductor pattern defines an electrode connected through the one or more semiconductor channels.

[0016] The present invention also provides a method comprising:

[0017] At least a semiconductor, a dielectric, and a first conductor pattern are formed on a support substrate, wherein the semiconductor defines one or more semiconductor channels, and the one or more semiconductor channels are capacitively coupled to one or more coupling conductors of the first conductor pattern via the dielectric.

[0018] A planarization layer is formed on the supporting substrate;

[0019] A via is formed on at least the planarization layer, wherein the semiconductor channel is at least partially located in a region outside the via region; and

[0020] A wiring conductor layer is formed on the support substrate, and the wiring conductor layer is etched to define a second wiring conductor pattern, the second wiring conductor pattern being in contact with the first conductor pattern via the one or more vias.

[0021] According to one embodiment, the method further includes: forming a third conductor pattern at least before forming the dielectric, wherein the third conductor pattern includes conductor elements electrically connected in series via the semiconductor channel; and wherein the etching includes removing portions of the wiring conductor layer occupied by one or more regions of the third conductor pattern.

[0022] According to one embodiment, the via region is located entirely outside the semiconductor channel region.

[0023] According to one embodiment, the semiconductor and the dielectric include semiconductor and dielectric patterns that substantially match and overlap with the second conductor pattern, and the one or more vias are located in one or more regions not occupied by any conductor element of the third conductor pattern.

[0024] According to one embodiment, forming the semiconductor, the dielectric, and the first conductor pattern includes forming a semiconductor layer, a dielectric layer, and a coupling conductor layer on the support substrate; patterning the coupling conductor layer to form a coupling conductor pattern; and patterning the semiconductor layer and the dielectric layer using the coupling conductor pattern and / or a mask used to form the first coupling conductor pattern.

[0025] According to one embodiment, the second wiring conductor pattern includes a metal pattern, and the first coupling conductor pattern includes a conductive metal oxide pattern.

[0026] According to one embodiment, the method further includes: forming a third conductor pattern prior to forming the semiconductor; wherein the semiconductor and the dielectric partially overlap with the third conductor pattern; and wherein the first conductor pattern and the third conductor pattern are configured such that the first conductor pattern does not overlap with the third conductor pattern.

[0027] According to one embodiment, the third conductor pattern is formed on at least some regions of the fourth conductor pattern, wherein portions of the fourth conductor pattern not covered by the third conductor pattern define electrodes connected via one or more semiconductor channels.

[0028] The present invention also provides an apparatus comprising a stack of layers defining one or more electronic components, wherein the stack comprises at least:

[0029] A patterned semiconductor layer that defines one or more semiconductor channels;

[0030] Patterned dielectrics;

[0031] A first conductor pattern defines one or more coupled conductors, wherein the one or more coupled conductors are coupled to the one or more semiconductor channels via the patterned dielectric capacitance;

[0032] Planarization layer;

[0033] A second conductor pattern, the second conductor pattern defining one or more wiring conductors, wherein the second conductor pattern contacts the first conductor pattern via a via in at least the planarization layer; and

[0034] The first conductor pattern is configured not to overlap with a third conductor pattern beneath a patterned semiconductor layer in the stack, wherein the patterned semiconductor layer and the patterned dielectric partially overlap with the third conductor pattern.

[0035] According to one embodiment, the third conductor pattern is formed over a portion of the fourth conductor pattern, wherein the portion of the fourth conductor pattern not covered by the third conductor pattern defines an electrode connected via one or more semiconductor channels.

[0036] The present invention also provides a method comprising:

[0037] At least a semiconductor pattern, a dielectric pattern, and a first conductor pattern are formed on a support substrate, wherein the semiconductor pattern defines one or more semiconductor channels of one or more coupled conductors coupled to the first conductor pattern via a dielectric capacitance.

[0038] A planarization layer is formed on the supporting substrate;

[0039] Forming vias in at least the planarization layer; and

[0040] A wiring conductor layer is formed on the support substrate, and the wiring conductor layer is patterned to define a second wiring conductor pattern that contacts the first conductor pattern via one or more of the vias;

[0041] The first conductor pattern is configured not to overlap with a third conductor pattern formed prior to the semiconductor pattern; wherein the semiconductor pattern and the dielectric pattern overlap with the third conductor pattern.

[0042] According to one embodiment, the third conductor pattern is formed on a portion of the fourth conductor pattern, wherein the portion of the fourth conductor pattern not covered by the third conductor pattern defines an electrode connected via one or more semiconductor channels. Attached Figure Description

[0043] The embodiments of the present invention will be described in detail below by way of example and with reference to the accompanying drawings, wherein:

[0044] Figures 1 to 6 This is a schematic screenshot illustrating an example of a technique according to an embodiment of the present invention;

[0045] Figures 7 to 10 This is a schematic cross-sectional view of another example of the technology according to another embodiment of the present invention;

[0046] Figure 11 It is shown Figures 1 to 6 and Figures 7 to 10 A schematic plan view showing the positional relationships between the components; and

[0047] Figures 12 to 14 Show Figures 1 to 6 and Figures 7 to 10 Example variations of the technology. Detailed Implementation

[0048] In one example embodiment, the technology is used in the production of an organic liquid crystal display (OLCD) device, which includes organic transistor devices (e.g., organic thin-film transistor (OTFT) devices) for control components. The OTFT includes organic semiconductors (such as, for example, organic polymers or small-molecule semiconductors) for semiconductor channels.

[0049] The terms “row” and “column” used below are used to indicate a pair of substantially orthogonal directions, not any absolute directions.

[0050] Taking a thin-film transistor (TFT) array as an example of a control component for an edge field switching (FFS) liquid crystal device, embodiments of the technology according to embodiments of the present invention are described in detail below. However, the technology is also applicable to TFT arrays of any kind of semiconductor device, including, for example: control components of other types of liquid crystal display devices (LCDs); control components of other types of display devices (such as electrophoretic display devices (EPDs) and organic light-emitting diode (OLED) display devices); circuitry for sensor devices; and circuitry for logic devices.

[0051] To simplify the explanation, Figures 1 to 10 Only two semiconductor channels are shown. Figure 11 Only four semiconductor channels are shown, but semiconductor devices can include a great many semiconductor channels.

[0052] refer to Figure 1 The description of the technology according to a first exemplary embodiment of the present invention begins at the workpiece stage, the workpiece comprising a planarized plastic film assembly 2 supporting: lower metal patterns 4a, 4b, 4c; a transparent conductor pattern 6; a continuous semiconductor layer 8; a continuous first gate dielectric layer 10 interfacing with the semiconductor layer 8; a continuous second gate dielectric layer 12; and a continuous conductive metal oxide layer 50.

[0053] In this example, the plastic film assembly 2 includes an ultrathin plastic support film (such as a 40-micron or 60-micron thick cellulose triacetate (TAC) film) and may also support one or more functional elements, such as a patterned metal layer configured to shield semiconductor channels to block light incident on the rear surface of the plastic film assembly 2.

[0054] In this example, the lower metal pattern defines at least (i) an array of source conductors, each providing a source 4a for a corresponding column of TFTs, and each source conductor including a conductor line 4c extending outside the array of TFTs; and (ii) an array of drain conductors 4b, each drain conductor associated with a corresponding pixel electrode (discussed below). Here, the term "source conductor" refers to a conductor electrically connected in series between a semiconductor channel and a driver chip / circuit (not shown), and the term "drain conductor" refers to a conductor electrically connected in series with the driver chip / circuit via a semiconductor channel. The lower metal pattern may also define gate terminals and wiring conductors through which higher-level gate lines are connected to the gate terminals.

[0055] In this example, the lower metal patterns 4a, 4b, and 4c include silver (Ag). The lower metal patterns may include, for example, non-precious metals that are even less resistant to oxidation and corrosion than silver, or precious metals that are more resistant to oxidation and corrosion than silver.

[0056] The transparent conductor pattern 6 is more transparent than the lower metal patterns 4a, 4b, and 4c, at least in the visible light portion of the electromagnetic spectrum. In this example, the transparent conductor pattern 6 comprises conductive indium tin oxide (ITO). The ITO pattern 6 defines pixel electrodes, each of which contacts a corresponding drain conductor 4b. The ITO pattern 6 also includes ITO over at least the entire area of ​​the conductor line 4c defined by the lower metal pattern (but not over the portion where the source and drain conductors are closest to each other). In this example, ITO will be retained on the silver conductor line 4c to protect the silver conductor line 4c in subsequent processing steps (e.g., during dry etching of the organic layer in the region above the conductor line 4c described below, where ITO acts as a good etch stop layer). For other examples of devices (such as, for example, EPDs, OLED displays, sensors and logic devices, and certain other types of LCD devices), where high-transmittance (highly transparent) pixel electrodes with the same level as the source and drain conductors are not required: then (a) the ITO pattern 6 may be confined to areas where subsequent patterning steps may require or desire ITO as a good etch stop, or (b) if the lower metal patterns 4a, 4b, 4c themselves have the required etch stop layer function, the ITO pattern can be omitted entirely. Gold (Au) metal patterns are an example of lower metal patterns resistant to dry etching processes, which can be used to pattern overlying organic layers.

[0057] In this example, semiconductor layer 8 comprises an organic conjugated polymer semiconductor, and semiconductor layer 8 is formed, for example, by spin-coating a solution of semiconductor polymer material. Semiconductor layer 8 defines an electrically connected semiconductor channel between each drain conductor 4b and the portion of the source conductor 4a closest to that drain conductor 4b. Hereinafter, the region in semiconductor layer 8 where the source and drain conductors are closest is referred to as channel region 9. One or more layers (e.g., self-assembled monolayers of organic materials) may be selectively formed on the exposed surfaces of the lower metal patterns 4a, 4b to facilitate charge carrier transfer between the source-drain conductors 4a, 4b and semiconductor layer 8.

[0058] In this example, the gate dielectric comprises a stack of two dielectric layers 10, 12, but the gate dielectric may alternatively comprise only one dielectric layer, or a stack of two or more dielectric layers.

[0059] In this example, the interface gate dielectric layer 10 and the uppermost gate dielectric layer 12 also comprise corresponding polymers and are formed, for example, by spin-coating solutions of the respective dielectric polymers. The uppermost gate dielectric polymer 12 has a higher dielectric constant than the interface gate dielectric polymer 10, but the interface gate dielectric polymer 10 is more suitable for forming a good interface with the semiconductor layer 8. In this example, the uppermost gate dielectric polymer 12 is a product purchased from the Merck group under the trade name... AP048 is formed of a crosslinkable dielectric polymer, but the topmost gate dielectric polymer 12 can also be formed of a non-crosslinkable polymer.

[0060] In this example, the continuous conductive metal oxide layer 50 above the uppermost gate dielectric layer 12 comprises indium tin oxide (ITO). Other examples of conductive metal oxides, such as TiOx, can also be used. The conductive metal oxide layer is preferably less than about 10. 4The resistivity is measured in ohms per square. In this example, ITO and other conductive metal oxides can provide good etch-stop functionality in the dry etch patterning process (discussed below) to create vias in the overlying organic layer. ITO is a conductive material with high white light transmittance, but conductive materials with lower transmittance (more opaque) can also be used. Gold (Au) is another example of a conductive material that has good conductivity and provides good etch-stop functionality in the dry etch patterning process used to pattern the organic layer. If the conductive layer 50 does not need to provide good etch-stop functionality in the patterning process (discussed below) for forming vias in the overlying layer, another example option is to use an organic material with the necessary conductivity level that will not negatively affect the semiconductor channel.

[0061] The stack of layers 8, 10, 12, and 50 may include additional layers, such as a light-absorbing material (e.g., carbon black particles dispersed in an insulating organic polymer) between the upper gate dielectric layer 12 and the ITO layer 50, to better protect the semiconductor channel in the finished device from damage by white light.

[0062] refer to Figure 2 The workpiece is further processed to achieve patterning of a sub-stack comprising semiconductor layer 8, gate dielectric layers 10, 12, and metal oxide layer 50. This patterning defines islands 100, each associated with a corresponding TFT. In this example, the patterning is performed by photolithography, including: forming a photoresist layer on the metal oxide layer 50; projecting an image of the desired pattern for the sub-stack (positive or negative depending on the type of photoresist used) using radiation that causes a change in the solubility of the photoresist, thereby generating a potential solubility pattern in the photoresist layer; developing the potential solubility pattern; using the resulting physical photoresist pattern as an etching mask, wet etching the ITO layer 50 (using an etchant (e.g., an etchant containing oxalic acid), wherein at least the uppermost gate dielectric layer 12 is substantially resistant to the etchant and impermeable); and dry etching the semiconductor layer 8 and gate dielectric layers 10, 12 using at least the ITO pattern as an etching mask. Dry etching is compatible with the selection of metals used for the lower metal patterns 4a, 4b, and 4c. Plasma generated from a gas mixture excluding chemically reactive gases such as oxygen is compatible with a wide range of metals used for the lower metal patterns 4a, 4b, and 4c. More chemically reactive plasmas may only be compatible with the use of precious metals (such as gold or platinum) used for the lower metal patterns 4a, 4b, and 4c.

[0063] exist Figures 1 to 6In the example shown, no photoresist mask remains in the product device. In an example variant, the photoresist etched mask includes material that performs the function in the product device and is retained. For example, the photoresist mask may include a mixture of photoresist material and light-absorbing material such as carbon black particles; and the photoresist mask remains in the product device to provide additional white light shielding for the semiconductor channel. To maintain a sufficient thickness of photoresist mask in the product device, the initial thickness of the photoresist mask is calculated to account for the amount of thickness reduction caused by the dry etching process.

[0064] refer to Figure 3 The workpiece is further processed by forming a continuous planarization layer 14 of electrically insulating material in situ on the upper surface of the workpiece, over at least the entire area of ​​the TFT array (including the entire area of ​​the aforementioned island 100 and the entire area between islands 100). In this example, the planarization layer 14 is formed by a solution processing technique such as spin coating.

[0065] refer to Figure 4 The workpiece is further processed by patterning the planarization layer 14 to define vias 54 (interconnect vias, ICVs), each via 54 exposing the ITO layer (of the corresponding island 100). In this example, each via 54 is formed in a region completely outside the corresponding channel region 9 to optimally protect the semiconductor 8a in the channel region 9 from the process of forming the via 54. However, in an example variant (particularly suitable for high-resolution display devices), the region where the via 54 is formed may occupy a portion of the semiconductor channel region. In both cases, for each island 100, there is at least a portion of the semiconductor channel region occupied by the patterned ITO layer 50a rather than the via 54; and good operation of the TFT over the entire channel region therefore depends on the ITO layer 50a.

[0066] The area forming the through-hole 54 also exists in areas where the lower metal pattern does not define any conductor element. This feature ( Figure 7 (As shown) minimizes the risk of a short circuit between the gate metal pattern (described below) and the lower metal pattern. In this example, the planarization layer 14 comprises a crosslinkable polymer (e.g., an epoxy-based crosslinkable polymer, such as SU-8 negative photoresist from MicroChem); and the patterning comprises: projecting a negative image of the desired via pattern (i.e., a positive image of the desired pattern of the planarization layer 14) onto the crosslinkable planarization layer 14 using radiation that causes crosslinking and thereby reduces the solubility of the insulating material of the planarization layer 14, to generate a potential solubility image in the planarization layer 14; and developing the potential solubility image.

[0067] The patterning of the planarization layer 14 may also include forming other vias (not shown), such as vias for the gate conductor 56a (mentioned below) in the region outside the TFT array (active region) to contact the wiring conductors defined by the lower metal pattern.

[0068] In addition to serving as a gate electrode, the ITO layer 50a on top of each island 100 can be used as a dry etching stop layer, which facilitates its alternative use as an alternative to dry etching to create vias 54 in the planarization layer 14. As an alternative example of using dry etching to form vias 54, a photoresist and etch mask are formed on the planarization layer 14 and removed after being used to pattern the planarization layer 14. More specifically, the ITO on top of each island 100 facilitates dry etching of the entire thickness of the planarization layer 14 without exposing the uppermost gate dielectric layer 12 to dry etching conditions. Creating vias 54 in the planarization layer 14 using dry etching technology can provide an upper workpiece surface with a smoother gradient in the boundary region between the inside and outside of the via 54 region, thereby better facilitating the formation of gate conductor lines 56a (discussed below) that extend without breaking on the upper surface of the workpiece.

[0069] For an alternative example using dry etching, the planarization layer 14 comprises the same negative photoresist material (e.g., SU-8) as in the wet etching example, and the photoresist layer used to pattern the planarization layer 14 comprises a positive photoresist material.

[0070] refer to Figure 5 The workpiece is further processed by forming at least one continuous metal layer 56 in situ on the upper surface of the workpiece, which is defined by the uppermost gate dielectric layer 12 and the patterned ITO layer 50a (in the region of the via 54). The at least one metal layer 56 is continuously formed over and beyond the entire region of the TFT array. In this example, a sub-stack of metal layers is used, including an aluminum (Al) layer sandwiched between two molybdenum (Mo) layers. In this example, each metal layer of the sub-stack is formed in situ on the workpiece using a vapor deposition technique such as sputtering.

[0071] refer to Figure 6The workpiece is further processed by patterning the metal sub-stacking 56 to define gate conductors 56a, each gate conductor providing a gate electrode for a corresponding row of transistors, and each gate conductor extending beyond the edge of the TFT array. In this example, the patterning is performed by photolithography, which includes: forming a photoresist layer on the metal sub-stacking 56; projecting an image of the desired pattern of the gate conductors 56a (positive or negative depending on the type of photoresist used) onto the photoresist using radiation that causes a change in the solubility of the photoresist to produce a potential solubility image; developing the potential solubility image; and using the resulting physical pattern in the photoresist as an etching mask to pattern the metal sub-stacking 56 using one or more patterning agents. In this example, the patterning agent is a wet metal etchant whose main component is phosphoric acid (H3PO4). In this example, the planarization layer 14 comprises a material that is less susceptible (compared to the uppermost gate dielectric material 12) to damage (surface roughening) by the wet metal etchant and / or less susceptible (compared to the second gate dielectric material 12) to penetration by the wet metal etchant. The area where the metal sub-stacking 56 is removed includes the area of ​​the overlying conductor element defined by the lower metal pattern (e.g., source conductor line 4c), and this relatively high resistance to wet metal etchant and impermeability better protects the underlying lower metal pattern from being etched by the wet metal etchant.

[0072] The upper surface of the planarization layer 14 is higher than the upper surface of the topmost gate dielectric layer 12. This relatively large thickness of the planarization layer 14 can help improve the breakdown characteristics of the dielectric; and the relatively small thickness of the gate dielectric layer 12 can be advantageous for improving the capacitance between the ITO gate electrode 50a and the semiconductor 8a in the channel region 9.

[0073] The planarization layer 14 and the topmost gate dielectric layer 12 may have different physical and / or chemical properties. For example, the two layers may differ in one or more of the following characteristics: dielectric constant; layer thickness; etch resistance; adhesion to the interface layer; density; dielectric breakdown strength; and purity.

[0074] In the above example, the planarization layer 14 and the uppermost gate dielectric layer 12a are both crosslinking layers in the final device; and the method of crosslinking in the planarization layer 14 may be different from or the same as the method of crosslinking in the uppermost gate dielectric layer 12a.

[0075] Furthermore, the planarization layer 14 includes a material selected to have good (compared to the uppermost gate dielectric layer 12a) adhesion to at least one or more (preferably all) of the gate metal pattern 56a, the lower metal patterns 4a, 4b, 4c, and the upper surface of the plastic film assembly 2 (e.g., an organic polymer planarization layer at the upper surface of the plastic film assembly 2). For example, good adhesion to the gate metal pattern 56a better prevents the gate conductor line 56a from detaching from the underlying insulator surface.

[0076] Each pixel electrode is associated with a unique combination of source and gate conductors, thereby allowing each pixel electrode to be addressed independently via portions of the gate and source conductors outside the TFT array.

[0077] Further processing (not shown in the figures) includes forming a continuous layer of transparent conductor material (e.g., ITO) in situ on the upper surface of the workpiece (defined by gate conductor 56a and planarization layer 14), and then patterning the continuous layer to define patterned common electrodes for the FFS liquid crystal device.

[0078] A second example technique according to another embodiment of the present invention is in Figures 7 to 10 As shown in the figure. Except for forming an inorganic insulating passivation layer 60 (with high white light transmittance) on the upper surface of the workpiece (at least over the entire active region) before forming the organic planarization layer 14, the second example differs from the first example ( Figures 1 to 6 The inorganic insulating layer 60 may, for example, comprise an inorganic nitride layer, such as an aluminum nitride (AlNx) layer, an aluminum oxide (AlOx) layer, or a silicon nitride (SiNx) layer. The thickness of the inorganic insulating layer may, for example, be between about 40 nm and 100 nm. The inorganic insulating layer 60 may be formed, for example, by a vapor deposition technique, such as sputtering, plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). The inorganic insulating layer 60 is patterned using the same photoresist etch mask as the planarization layer. Figure 10 This allows via 54 to extend down into the ITO layer 50a. The inorganic insulating layer 60 can be patterned using either dry or wet etching (using an etchant compatible with the retention of the underlying ITO layer 50a). The inorganic insulating layer 60 serves as an additional gate dielectric layer and can improve yield and reduce the risk of dielectric breakdown. The inorganic insulating layer 60 also provides further protection for the underlying metal pattern from the etchant used to pattern the upper metal sub-stack 56.

[0079] The variations, additions, and processing details mentioned in the first example also apply to this second example. In particular, the gate dielectric may comprise a single dielectric layer or a stack of dielectric layers.

[0080] The above-described technology reduces the requirements for the topmost gate dielectric layer 12 to achieve good resistance to erosion and impermeability to gate metal etchants and good adhesion to the bonding layer, thereby facilitating the selection of gate dielectrics with dielectric materials optimized for good capacitance and TFT stability (e.g., the topmost gate dielectric layer in an example using a stack of gate dielectric layers).

[0081] Based on the above content and Figures 1 to 10 In one example variation of the technology shown, the ITO layer 50 is patterned onto the underlying semiconductor layer 8 and dielectric layers 10, 12, respectively. Masks with different configurations are used for patterning the ITO layer 50, as well as the underlying semiconductor layer 8 and dielectric layers 10, 12. Figure 12 schematic cross-section and Figure 13 As shown in the schematic plan view: the lower ITO pattern 6 and the upper ITO pattern 150a are configured such that there is no overlap between the lower ITO pattern 6 and the upper ITO pattern 150a; and the islands 100 of the semiconductor layer 8 and the dielectric layers 10, 12 are configured such that the islands 100 overlap with the lower ITO pattern 6. As shown in the schematic cross-section Figure 14 As shown, this example variant includes forming an additional photoresist mask 80 after patterning the ITO layer 50 for patterning the semiconductor layer 8 and dielectric layers 10, 12. This example variant can further improve yield by reducing the risk of short circuits between the upper ITO pattern 150a and the lower ITO pattern 6.

[0082] Based on the above content and Figures 1 to 14 Exemplary variations of all the methods shown involve replacing the upper conductor patterns 50a, 150a with a conductive material having lower white light transmittance, such as a metal or metal alloy layer, such as, for example, an alloy containing tantalum and molybdenum (MoTa alloy). MoTa alloy is also an example of a material resistant to dry etching used to pattern the underlying semiconductor 8 layer and dielectric layers 10, 12 into islands 100 and / or the upper planarization layer 14 to create vias 54 down to the conductor patterns 50a, 150a. Depending on the technique used to pattern the upper planarization layer 14, in Figures 12 to 14 In the example variant shown above, resistance to dry etching may be less important, wherein the conductive capping layer 150a has a pattern different from the pattern of the underlying semiconductor layer 8 and dielectric layers 10, 12, and is not used as a mask for patterning the underlying semiconductor layer 8 and dielectric layers 10, 12.

[0083] As described above, examples of the technology according to the present invention have been described in detail with reference to specific processing details; however, the technology is applicable more broadly within the general teachings of this application. Furthermore, according to the general teachings of the present invention, the technology according to the present invention may include additional processing steps not described above, and / or omit some of the processing steps described above.

[0084] Apart from any modifications explicitly mentioned above, it will be apparent to those skilled in the art that various other modifications can be made to the described examples within the scope of this invention.

[0085] The applicant thereby independently discloses each individual feature described herein, as well as any combination of two or more such features, to the extent that such features or combinations can be performed on the basis of this description in their entirety, to the extent that such features or combinations of features can be performed based on this description, regardless of whether such features or combinations of features solve any of the problems disclosed herein, and without limiting the scope of the claims. The applicant notes that aspects of the invention can be comprised of any such individual features or combinations of features.

Claims

1. An apparatus comprising a stack of layers defining one or more electronic components, characterized in that, The stacking includes at least: One or more semiconductor channels in one or more semiconductor channel regions; Dielectric; A first conductor pattern, which defines one or more coupled conductors in the one or more semiconductor channel regions, wherein the one or more coupled conductors are capacitively coupled to the one or more semiconductor channels via the dielectric; Planarization layer; A second conductor pattern defines one or more wiring conductors, wherein the second conductor pattern contacts the first conductor pattern via one or more vias in one or more via regions in at least the planarization layer, and wherein the one or more vias are located entirely outside the one or more semiconductor channel regions, wherein the wiring conductors extend through the one or more semiconductor channel regions.

2. The apparatus according to claim 1, characterized in that, The stack includes a third conductor pattern comprising conductor elements electrically connected in series via the one or more semiconductor channels; and wherein the one or more vias are located in one or more regions not occupied by any conductor element of the third conductor pattern.

3. The apparatus according to claim 1, characterized in that, The second conductor pattern includes a metal pattern, and the first conductor pattern includes a conductive metal oxide pattern.

4. The apparatus according to claim 1, characterized in that, The stack includes a third conductor pattern beneath the dielectric and a patterned semiconductor layer defining the one or more semiconductor channels; wherein the patterned semiconductor layer and the dielectric partially overlap with the third conductor pattern. And wherein the first conductor pattern and the third conductor pattern are configured such that the first conductor pattern and the third conductor pattern do not overlap.

5. The apparatus according to claim 4, characterized in that, The third conductor pattern is formed on a portion of the fourth conductor pattern, wherein the portion of the fourth conductor pattern not covered by the third conductor pattern defines the electrodes connected through the one or more semiconductor channels.

6. The apparatus according to claim 1, characterized in that, The planarization layer does not include any other vias in the semiconductor channel region.

7. The apparatus according to claim 1, characterized in that, The wiring conductor extends through the semiconductor channel region.

8. The apparatus according to claim 1, characterized in that, The planarization layer does not include vias in the semiconductor channel region.

9. The apparatus according to claim 1, characterized in that, It also includes a light-absorbing layer located between the dielectric and the first conductor pattern.

10. The apparatus according to claim 9, characterized in that, The light-absorbing layer comprises carbon black particles dispersed in an insulating organic polymer.

11. The apparatus according to claim 1, characterized in that, It also includes a retained photoresist mask used to at least form the pattern of the first conductor.

12. The apparatus according to claim 11, characterized in that, The photoresist mask with retained photoresist provides white light shielding for the semiconductor channel.

13. The apparatus according to claim 11, characterized in that, The photoresist mask with retained photoresist comprises photoresist material and carbon black particles.

14. The apparatus according to claim 1, characterized in that, The planarization layer includes a gentle stepped surface located in the boundary region between the inside and outside of the via region.

15. A method, characterized in that, The method includes: A semiconductor, a dielectric, and a first conductor pattern are formed on a support substrate, wherein the semiconductor defines one or more semiconductor channels in one or more semiconductor channel regions, wherein the one or more semiconductor channels in the one or more semiconductor channel regions are capacitively coupled to one or more coupling conductors of the first conductor pattern via the dielectric. A planarization layer is formed on the supporting substrate; One or more vias are formed in one or more via regions on at least the planarization layer, wherein the one or more via regions are entirely located outside the one or more semiconductor channel regions; and A wiring conductor layer is formed on the support substrate, and the wiring conductor layer is etched to define a second wiring conductor pattern, the second wiring conductor pattern contacting the first conductor pattern via the one or more vias, wherein the second wiring conductor pattern defines one or more wiring conductors extending through the one or more semiconductor channel regions.

16. The method according to claim 15, characterized in that, The method further includes: forming a third conductor pattern at least before forming the dielectric, wherein the third conductor pattern includes conductor elements electrically connected in series via the one or more semiconductor channels; and wherein the etching includes: removing portions of the wiring conductor layer in one or more regions occupied by the third conductor pattern.

17. The method according to claim 16, characterized in that, The semiconductor and the dielectric include semiconductor and dielectric patterns that substantially match and overlap with the second wiring conductor pattern, and the one or more vias are located in one or more regions not occupied by any conductor element of the third conductor pattern.

18. The method according to claim 15, characterized in that, Forming the semiconductor, the dielectric, and the first conductor pattern includes: forming a semiconductor layer, a dielectric layer, and a coupling conductor layer on the support substrate; patterning the coupling conductor layer to form a coupling conductor pattern; and patterning the semiconductor layer and the dielectric layer using the coupling conductor pattern and / or a mask used to form the first conductor pattern.

19. The method according to claim 15, characterized in that, The second wiring conductor pattern includes a metal pattern, and the first conductor pattern includes a conductive metal oxide pattern.

20. The method according to claim 15, characterized in that, The method further includes: forming a third conductor pattern prior to forming the semiconductor; wherein the semiconductor and the dielectric partially overlap with the third conductor pattern; and wherein the first conductor pattern and the third conductor pattern are configured such that the first conductor pattern does not overlap with the third conductor pattern.

21. The method according to claim 20, characterized in that, The third conductor pattern is formed on at least some areas of the fourth conductor pattern, wherein portions of the fourth conductor pattern not covered by the third conductor pattern define electrodes connected through the one or more semiconductor channels.

22. The method according to claim 15, characterized in that, The method further includes forming a light-absorbing layer between the dielectric and the first conductor pattern.

23. The method according to claim 22, characterized in that, The light-absorbing layer comprises carbon black particles dispersed in an insulating organic polymer.

24. The method according to claim 15, characterized in that, The method further includes: using a photoresist mask to form at least the first conductor pattern, and forming the planarization layer without removing the photoresist mask.

25. The method according to claim 24, characterized in that, The photoresist mask provides white light shielding for the semiconductor channel.

26. The method according to claim 25, characterized in that, The photoresist mask comprises a photoresist material and carbon black particles.

27. An apparatus, characterized in that, The device includes a stack of layers defining one or more electronic components, wherein the stack includes at least: The first conductor pattern defines one or more conductor lines; A conductive oxide pattern that protects the conductor lines; A patterned semiconductor layer that defines one or more semiconductor channels; Patterned dielectrics; A second conductor pattern defines one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or more semiconductor channels via the patterned dielectric; Planarization layer; A third conductor pattern defining one or more wiring conductors, wherein the third conductor pattern contacts the second conductor pattern via a via in at least the via region of the planarization layer; and The second conductor pattern and the conductive oxide pattern are configured such that the second conductor pattern and the conductive oxide pattern do not overlap. The patterned semiconductor layer and the patterned dielectric partially overlap with the conductive oxide pattern.

28. The apparatus according to claim 27, characterized in that, The third conductor pattern is formed above a portion of the fourth conductor pattern, wherein a portion of the fourth conductor pattern not covered by the third conductor pattern defines an electrode connected through the one or more semiconductor channels; and the first conductor pattern overlaps with the electrode.

29. The apparatus according to claim 27 or 28, characterized in that, The first conductor pattern occupies the area not occupied by the patterned dielectric.

30. The apparatus according to claim 27 or 28, characterized in that, It also includes a light-absorbing layer located between the dielectric and the first conductor pattern.

31. The apparatus according to claim 27 or 28, characterized in that, It also includes a retained photoresist mask used to at least form the pattern of the first conductor.

32. A method, characterized in that, The method includes: A first conductor pattern is formed, the first conductor pattern defining the conductor line; A conductive oxide pattern is formed, which protects the conductor wire; At least a semiconductor pattern, a dielectric pattern, and a second conductor pattern are formed on a support substrate, wherein the semiconductor pattern defines one or more semiconductor channels in a semiconductor channel region, and the one or more semiconductor channels are capacitively coupled to one or more coupling conductors of the second conductor pattern via a dielectric. Forming a planarized layer; At least a through-hole is formed in the planarization layer; and A wiring conductor layer is formed and the wiring conductor layer is patterned to define a third conductor pattern that contacts the second conductor pattern via one or more of the vias; The semiconductor pattern and the dielectric pattern partially overlap with the conductive oxide pattern; and The second conductor pattern and the conductive oxide pattern are configured such that the second conductor pattern and the conductive oxide pattern do not overlap.

33. The method according to claim 32, characterized in that, The third conductor pattern is formed on a portion of the fourth conductor pattern, wherein the portion of the fourth conductor pattern not covered by the third conductor pattern defines an electrode connected through the one or more semiconductor channels; and the first conductor pattern overlaps with the electrode.

34. The method according to claim 32 or 33, characterized in that, The first conductor pattern occupies the area occupied by the unpatterned dielectric.

35. The method according to claim 32 or 33, characterized in that, The method further includes forming a light-absorbing layer between the dielectric and the first conductor pattern.

36. The method according to claim 32 or 33, characterized in that, The method further includes: using a photoresist mask to form at least the first conductor pattern, and forming the planarization layer without removing the photoresist mask.

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