Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and a method for operating the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array, an error correction circuit, and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder, which is used to perform ECC decoding on a codeword including main data and parity data read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on commands and addresses from an external memory controller. The ECC decoder has a t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during t-2 cycles to generate an error locating polynomial based on the syndrome, searches for an error position in the codeword based on the error locating polynomial, and corrects the error in the codeword based on the searched error position.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0173099 filed on December 23, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to memories, and more particularly, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Art

[0003] Semiconductor memory devices can be classified into non-volatile memory devices such as flash memory devices and volatile memory devices such as DRAM. The high-speed operation and cost efficiency of DRAM make it possible to use DRAM for system memory. Due to the continuous reduction of the manufacturing design specifications of DRAM, the bit errors of memory cells in DRAM may increase rapidly, and the yield of DRAM may decrease. Therefore, it is necessary to improve the reliability of semiconductor memory devices by reducing the bit errors of memory cells in DRAM. Summary of the invention

[0004] Example embodiments may provide a semiconductor memory device having enhanced performance.

[0005] Example embodiments may provide a method of operating a semiconductor memory device having enhanced performance.

[0006] According to an example embodiment, a semiconductor memory device includes a memory cell array, an error correction circuit, and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, and also includes a plurality of sense amplifiers for sensing data stored in the plurality of memory cells. The error correction circuit includes an error correction code (ECC) decoder for performing ECC decoding on a codeword read from a target page of the memory cell array to correct an error in the read codeword. The codeword includes main data and parity data. The control logic circuit controls the error correction circuit based on a command and an address from an external memory controller. The ECC decoder is configured to: perform t-bit error correction (t is an even integer greater than three), generate a syndrome based on the codeword using a parity check matrix, perform t iterations during t-2 cycles to generate an error locator polynomial based on the syndrome, search for an error position in the codeword based on the error locator polynomial, and correct the error in the codeword based on the searched error position.

[0007] According to an example embodiment, a method for operating a semiconductor memory device is provided, the semiconductor memory device including a memory cell array and an error correction circuit, the memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines. According to the method, a codeword including main data and parity data is read from a target page of the memory cell array; and an error correction code (ECC) decoder of the error correction circuit corrects an error in the codeword by performing ECC decoding on the codeword. The ECC decoder is configured to: perform t-bit error correction (t is an even integer greater than three), generate a syndrome based on the codeword using a parity check matrix, perform t iterations during t-2 cycles to generate an error locator polynomial based on the syndrome, search for an error position in the codeword based on the error locator polynomial, and correct the error in the codeword based on the searched error position.

[0008] According to an example embodiment, a semiconductor memory device includes a memory cell array, an error correction circuit, and a control logic circuit. The memory cell array includes a plurality of memory cells and a plurality of sense amplifiers, the plurality of memory cells being coupled to a plurality of word lines and a plurality of bit lines, the plurality of sense amplifiers being used to sense data stored in the plurality of memory cells. The error correction circuit includes an error correction code (ECC) decoder, the error correction code decoder being used to perform ECC decoding on a codeword read from a target page of the memory cell array to correct an error in the read codeword. The codeword includes main data and parity check data. The control logic circuit controls the error correction circuit based on a command and an address from an external memory controller. The ECC decoder is configured to: perform t-bit error correction (t is an even integer greater than three), generate a syndrome based on the codeword using a parity check matrix, perform t iterations during t-2 cycles to generate an error locator polynomial based on the syndrome, search for an error position in the codeword based on the error locator polynomial, and correct the error in the codeword based on the searched error position. The ECC decoder includes a Bérégain-Marseille generator for generating coefficients of an error locator polynomial based on the syndrome during t-2 cycles.

[0009] Therefore, the ECC decoder can perform t iterations during t-2 cycles to generate an error locating polynomial based on the syndrome, can search for an error position in the codeword based on the error locating polynomial, and can correct the error based on the searched error position when performing ECC decoding. Therefore, the ECC decoder can reduce latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0012] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a semiconductor memory device in FIG.

[0013] Figure 3 Shows Figure 2 A memory cell and a sense amplifier in a semiconductor memory device.

[0014] Figure 4 Shown by Figure 3 The sense amplifier in the memory cell senses the multi-bit data.

[0015] Figure 5 is a diagram showing a method according to an example embodiment Figure 3 A circuit diagram of an example of a sense amplifier in FIG.

[0016] Figure 6 According to an example embodiment, Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0017] Figure 7 According to an example embodiment, Figure 6 A portion of a first memory bank array.

[0018] Figure 8 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of an error correction circuit in a semiconductor memory device.

[0019] Fig. 9 is a diagram showing a method according to an example embodiment Figure 8 Block diagram of the ECC decoder in the error correction circuit.

[0020] Fig.10 is a diagram showing a method according to an example embodiment Fig. 9 Block diagram of a BM calculator or generator in an ECC decoder.

[0021] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 A block diagram of one of the processing elements within a BM calculator or generator.

[0022] Fig.12 is a diagram showing a method according to an example embodiment Fig.10 Block diagram of the shared processing elements in a BM calculator or generator.

[0023] Fig.13 Shows Fig.10 The BM calculator implements the simplified inverse-free BM (SiBM) algorithm.

[0024] Fig.14 is a diagram showing a method according to an example embodiment Fig.12 Block diagram of a first intermediate coefficient calculator or generator in.

[0025] Fig.15A and Fig. 15B is a diagram showing a method according to an example embodiment Fig.12 Block diagram of a second intermediate coefficient calculator or generator in.

[0026] Fig.16 is a diagram showing a method according to an example embodiment Fig.12 A block diagram of an example of a control signal generator in FIG.

[0027] Fig.17 According to an example embodiment, Fig.10 Operation of the BM calculator or generator.

[0028] Fig.18 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0029] Fig.19 is a flowchart illustrating a method of ECC decoding in a semiconductor memory device according to example embodiments.

[0030] Fig. 20 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0031] Fig.21 According to the exemplary embodiment, Fig. 20 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0032] Fig. 22 is a diagram illustrating a semiconductor package including a stacked memory device according to example embodiments. DETAILED DESCRIPTION

[0033] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

[0034] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0035] Reference Figure 1 , the memory system 20 may include a memory controller 100 and a semiconductor memory device 200 .

[0036] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the external host and the semiconductor memory device 200.

[0037] For example, the memory controller 100 may write data into the semiconductor memory device 200 or read data from the semiconductor memory device 200 in response to a request from the host. In addition, the memory controller 100 may issue an operation command to the semiconductor memory device 200 to control the semiconductor memory device 200. The memory controller 100 transmits a clock signal CLK, a command CMD (signal), and an address (signal) ADDR to the semiconductor memory device 200, and exchanges main data MD with the semiconductor memory device 200.

[0038] In some embodiments, the semiconductor memory device 200 is a memory device including a dynamic memory cell, such as a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a DDR5 SDRAM low power DDR4 (LPDDR4) SDRAM, or a LPDDR5 SDRAM.

[0039] The semiconductor memory device 200 includes a memory cell array 300 storing main data MD and parity data, an error correction circuit 400, and a control logic circuit 210. The parity data may be transmitted from the memory controller 100 together with the main data MD.

[0040] The memory cell array 300 may include a plurality of memory cells MC coupled to each word line WL and each bit line BTL, and a sense amplifier BLSA 280 coupled to the bit line BTL and a complementary bit line BTLB.

[0041] The control logic circuit 210 controls the error correction circuit 400 so that the error correction circuit 400 can perform ECC encoding on the data to be stored in the target page of the memory cell array 300, and can perform ECC decoding on the data read from the target page. The error correction circuit 400 can have a t-bit error correction capability (t is an even integer greater than three), can perform t iterations during t-2 cycles and generate coefficients of an error locator polynomial.

[0042] The control logic circuit 210 may control access to the memory cell array 300 , and may control the error correction circuit 400 based on a command CMD and an address ADDR from the memory controller 100 .

[0043] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a semiconductor memory device in FIG.

[0044] Reference Figure 2, the semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a memory body control logic 230, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, a data input / output (I / O) buffer 295, a refresh counter 245, an error correction circuit 400 and a voltage generator 600.

[0045] The memory cell array 300 includes first to eighth bank arrays 310 to 380. The row decoder 260 includes first to eighth bank row decoders 260a to 260h coupled to the first to eighth bank arrays 310 to 380, respectively. The column decoder 270 includes first to eighth bank column decoders 270a to 270h coupled to the first to eighth bank arrays 310 to 380, respectively. The sense amplifier unit 285 includes first to eighth bank sense amplifiers 285a to 285h coupled to the first to eighth bank arrays 310 to 380, respectively.

[0046] The first memory bank array 310 to the eighth memory bank array 380, the first memory bank row decoder 260a to the eighth memory bank row decoder 260h, the first memory bank column decoder 270a to the eighth memory bank column decoder 270h, and the first memory bank sense amplifier 285a to the eighth memory bank sense amplifier 285h may form the first memory bank to the eighth memory bank. Each of the first memory bank array 310 to the eighth memory bank array 380 includes a plurality of memory cells MC coupled to the word line WL and the bit line BTL. The plurality of memory cells MC may correspond to volatile memory cells having a DRAM cell structure.

[0047] Each of the first memory array 310 to the eighth memory array 380 may include a plurality of memory cells MC coupled to each word line WL and each bit line BTL and a bit line sense amplifier BLSA 280 coupled to a bit line BL and a complementary bit line BTLB. Each of the memory cells MC includes a cell transistor CT and a cell capacitor CC. The gate of the cell transistor CT is connected to one of the word lines WL arranged along the row direction of the memory cell array 300. One end of the cell transistor CT is connected to one of the bit lines BL arranged along the column direction of the memory cell array 300. The other end of the cell transistor CT is connected to the cell capacitor CC. The cell capacitor CC may store various capacities of charge corresponding to multi-bit data (e.g., 2-bit data), or may store single-bit data. The cell capacitor CC may be restored with an amount of charge corresponding to the capacity of each multi-bit data item, that is, the cell capacitor CC may be restored to the cell voltage Vcell.

[0048] Although the semiconductor memory device 200 is Figure 2 2 is shown as including eight memory banks, but example embodiments of the present disclosure are not limited thereto, and the semiconductor memory device 200 may include any number of memory banks.

[0049] The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and / or a column address COL_ADDR, and a command CMD from the memory controller 100 .

[0050] The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 , provide the received row address ROW_ADDR to the row address multiplexer 240 , and provide the received column address COL_ADDR to the column address latch 250 .

[0051] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. One of the first bank row decoders 260a to the eighth bank row decoders 260h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal, and one of the first bank column decoders 270a to the eighth bank column decoders 270h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0052] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220, and may receive a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output one of the row address ROW_ADDR and the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h.

[0053] The activated one of the first to eighth bank row decoders 260a to 260h may decode the row address RA output from the row address multiplexer 240 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0054] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In an example embodiment, in a burst mode, the column address latch 250 may generate a column address incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 270a to 270h.

[0055] An activated one of the first to eighth bank column decoders 270 a to 270 h may decode the column address COL_ADDR output from the column address latch 250 and may control the input / output gating circuit 290 to output data corresponding to the bank address BANK_ADDR and the column address COL_ADDR.

[0056] The I / O gating circuit 290 includes a circuit for gating input / output data. The I / O gating circuit 290 also includes a read data latch for storing data output from the first memory bank array 310 to the eighth memory bank array 380, and a write driver for writing data to the first memory bank array 310 to the eighth memory bank array 380.

[0057] The codeword CW read from one of the first to eighth memory bank arrays 310 to 380 may be sensed by a sense amplifier coupled to the one memory bank array from which the codeword is to be read, and may be stored in the read data latch. The codeword CW stored in the read data latch is decoded by the error correction circuit 400ECC and may be provided to the memory controller 100 via the data I / O buffer 295.

[0058] Data (or main data) MD to be written in one of the first to eighth bank arrays 310 to 380 may be provided from the memory controller 100 to the data I / O buffer 295 . The main data MD is provided to the error correction circuit 400 .

[0059] The error correction circuit 400 performs ECC encoding on the main data MD to generate parity data, and provides the codeword CW including the main data MD and the parity data to the I / O gating circuit 290. The I / O gating circuit 290 can store the main data MD and the parity data in the target page of the memory cell array 300 after the ECC encoding has been performed based on the second control signal CTL2. In addition, the error correction circuit 400 can correct t-bit errors in the read data by performing ECC decoding on the codeword CW read from the memory cell array 300 based on the parity data.

[0060] The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100, and a mode register 212 that sets an operation mode of the semiconductor memory device 200.

[0061] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 may generate a first control signal CTL1 to control the I / O gating circuit 290, and generate a second control signal CTL2 to control the error correction circuit 400. In addition, the control logic circuit 210 may control the voltage generator 600 to adjust the driving voltage VDR applied to the bit line sense amplifier 280 through a third control signal CTL3.

[0062] The data I / O buffer 295 may receive the clock signal CLK and main data MD from the memory controller 100 , and may provide the main data MD to the error correction circuit 400 .

[0063] Figure 3 Shows Figure 2 A memory cell and a sense amplifier in a semiconductor memory device.

[0064] Reference Figure 3, the sense amplifier 280 may be connected to the memory cell MC and the equalization circuit 160 through the bit line pair BTL and BTLB (as a complementary bit line of the bit line BTL). The equalization circuit 160 includes a first transistor 161, a second transistor 162, and a third transistor 163. The first transistor 161, the second transistor 162, and the third transistor 163 equalize the bit line pair BTL and BTLB with the precharge voltage VBL in response to the equalization signal PEQ. The equalization signal PEQ may be provided by the control logic circuit 210 according to the precharge command. The precharge voltage VBL may be set to have a level corresponding to half the level of the power supply voltage driving the sense amplifier 280.

[0065] The sense amplifier 280 may be configured in an open bit line structure and connected to the memory cell MC. In the open bit line structure, the bit line pair BTL and BTLB are separately located in different adjacent main cell blocks 205 and 207. In the open bit line structure, when the word line WL of the selected memory cell MC is enabled, the data of the memory cell MC may be read or written through the selected bit line BTL. At this time, while accessing the data of the memory cell MC via the selected bit line BTL, since the selected memory cell is not on the complementary bit line BTLB, the level of the precharge voltage VBL is maintained as a reference voltage level. Therefore, the sense amplifier 280 can sense the cell voltage Vcell of the memory cell MC by using the charge shared through the bit line BTL.

[0066] The sense amplifier 280 may be configured to sense the cell voltage Vcell stored in the memory cell MC as a first bit corresponding to the most significant bit (MSB) and a second bit corresponding to the least significant bit (LSB) of the 2-bit data, and after the sensing, the sense amplifier 280 may be configured to restore the cell voltage Vcell corresponding to the sensed MSB and LSB in the memory cell MC. For example, the sense amplifier 280 may sense the cell voltage Vcell stored in the memory cell MC as a first bit corresponding to the most significant bit (MSB) and a second bit corresponding to the least significant bit (LSB) of the 2-bit data. After the sensing, the sense amplifier 280 may be configured to restore the cell voltage Vcell corresponding to the sensed MSB and LSB in the memory cell MC. For example, the sense amplifier 280 may sense the cell voltage Vcell by using the cell capacitance of the memory cell MC, the bit line capacitance of each of the bit line pairs BTL and BTLB, and the holding bit line pairs HBL and HBLB ( Figure 5 ), the first sensing bit line pair SBL1 and SBLB1 ( Figure 5 ) of each of the bit line capacitances of the second sensing bit line pair SBL2 and SBLB2 ( Figure 5 ) and the change in the bit line capacitance of each of the bit line capacitors ) to perform the first to third charge sharing operations. The sense amplifier 280 senses the MSB and LSB of the 2-bit data by performing the first to third charge sharing operations, and can restore the cell voltage Vcell corresponding to the sensed MSB and LSB in the memory cell MC.

[0067] The sense amplifier 280 may combine the sensed MSB and LSB by performing the third charge sharing operation. The sense amplifier 280 may restore the cell voltage Vcell generated according to the combination of the sensed MSB and LSB in the memory cell MC.

[0068] Figure 4 Shown by Figure 3 The sense amplifier in the memory cell senses the multi-bit data.

[0069] Reference Figure 4 , the cell voltage Vcell of the memory cell MC represents the MSB and LSB of the 2-bit data. The different cell voltages Vcell stored in the memory cell MC can represent different combinations of the bit combinations "00", "01", "10" and "11". For example, when the power supply voltage VINTA is 1.0V, it can be set to provide a voltage difference of about 330mV to 340mV between multiple bit combinations. That is, a cell voltage Vcell of 0V can represent the bit combination "00", a cell voltage Vcell of 0.33V can represent the bit combination "01", a cell voltage Vcell of 0.67V can represent the bit combination "10", and a cell voltage Vcell of 1.0V can represent the bit combination "11".

[0070] In example embodiments, the level of the cell voltage Vcell representing each of the bit combinations of '00', '01', '10', or '11' may be changed.

[0071] In the sense amplifier 280 for sensing the MSB of the memory cell MC, when a first charge sharing operation including charge sharing between the charge stored in the cell capacitor CC and the charge stored in the bit line BTL and the holding bit line HBL is performed, the bit line BTL and the holding bit line HBL are captured to have a prescribed MSB voltage V MSB The bit line BTL can be changed from the precharge voltage VBL level (ie, 0.5V) to the MSB voltage V MSB At this time, the complementary bit line BTLB may maintain the level of the precharge voltage VBL.

[0072] For example, for a cell voltage Vcell of 0V for the bit combination “00”, the voltage level of the bit line BTL can be captured as an MSB voltage Vcell of about 0.35V through the first charge sharing operation. MSB For the cell voltage Vcell of 0.33V of the bit combination “01”, the voltage level of the bit line BTL can be captured as the MSB voltage Vcell of about 0.45V through the first charge sharing operation. MSBFor the cell voltage Vcell of 0.67V of the bit combination “10”, the voltage level of the bit line BTL can be captured as the MSB voltage Vcell of about 0.55V through the first charge sharing operation. MSB For the cell voltage Vcell of 1.0V of the bit combination “11”, the voltage level of the bit line BTL can be captured as the MSB voltage Vcell of about 0.65V through the first charge sharing operation. MSB .

[0073] Therefore, the voltage level of the bit line BTL of each of the bit combinations “00”, “01”, “10”, and “11” according to the first charge sharing operation may be captured as the MSB voltage V of approximately 0.35 V, 0.45 V, 0.55 V, and 0.65 V, respectively. MSB At this time, the complementary bit line BTLB maintains the precharge voltage VBL of 0.5V. A specified voltage difference (ie, -150mV, -50mV, 50mV or 150mV) may exist between the MSB voltage V MSB The complementary bit line voltage V BLB The different specified voltage differences correspond to the bit combinations “00”, “01”, “10” and “11” respectively.

[0074] In the sense amplifier 280 for sensing the LSB of the memory cell MC, when the second charge sharing operation is performed, the bit line BTL is captured as the prescribed LSB voltage V LSB The second charge sharing operation includes charge sharing generated between the charge stored in the bit line BTL and the holding bit line HBL and the charge stored in the first sensing bit line SBL1, and also includes charge sharing generated between the charge stored in the complementary bit line BTLB and the complementary holding bit line HBLB and the charge stored in the first complementary sensing bit line SBLB1. The bit line BTL can be from the MSB voltage V MSB Transition to LSB voltage V LSB .

[0075] For example, for the bit combination “00”, the MSB voltage V is about 0.35V. MSB The voltage level of the bit line BTL can be captured as an LSB voltage V of about 0.45V under the second charge sharing operation. LSB At this time, the voltage level of the complementary bit line BTLB can be captured as a complementary bit line voltage V of about 0.5V. BLB For the bit combination "01", the MSB voltage V is about 0.45V. MSB The voltage level of the bit line BTL can be captured as an LSB voltage V of about 0.45V under the second charge sharing operation. LSB , and the complementary bit line voltage V BTLBcan be captured as 0.5V. For the bit combination "10", the MSB voltage V is 0.55V MSB The voltage level of the bit line BTL can be captured as an LSB voltage V of about 0.55V under the second charge sharing operation. LSB , and the complementary bit line voltage V BTLB can be captured as 0.5V. For the bit combination "11", the MSB voltage V is 0.65V MSB The voltage level of the bit line BTL can be captured as an LSB voltage V of about 0.55V under the second charge sharing operation. LSB , and the complementary bit line voltage V BTLB can be captured as 0.5V.

[0076] The voltage level of the bit line BTL according to the second charge sharing operation for each of the bit combinations “00” and “01” is captured as LSB voltages V of approximately 0.45 V and 0.45 V, respectively. LSB , and the complementary bit line voltage V BTLB The level of the bit line BTL is captured as approximately 0.5 V. The voltage level of the bit line BTL of each of the bit combinations "10" and "11" is captured as the LSB voltage V of approximately 0.55 V and 0.55 V, respectively. LSB , and the complementary bit line voltage V BTLB The level of is captured as about 0.5 V. A prescribed voltage difference corresponding to each of the bit combinations "00", "01", "10", and "11" (i.e., -50 mV, -50 mV, 50 mV, and 50 mV) exists at the LSB voltage V of the bit line BTL. LSB Complementary bit line voltage V BTLB This represents the LSB voltage V corresponding to each of the bit combinations "00", "01", "10", and "11". LSB Used as a sensor that does not require a LSB voltage V LSB An additional reference voltage is provided for self-reference.

[0077] Figure 5 is a diagram showing a method according to an example embodiment Figure 3 A circuit diagram of an example of a sense amplifier in FIG.

[0078] Reference Figure 5 The sense amplifier 280 may include a sense amplifier circuit 281 , a latch circuit 283 , and a switch circuit, wherein the switch circuit includes a bit line switch SWa, a complementary bit line switch SWb, a power switch SW10 , and first to sixth switches SW1 to SW6 .

[0079] The sense amplifier circuit 281 is connected to the first sense signal LA1 and the second sense signal LAB1, and includes p-channel metal oxide semiconductor (PMOS) transistors P11 and P12 and n-channel metal oxide semiconductor (NMOS) transistors N11 and N12. According to the control of the control logic circuit 210, the first power supply voltage VINTA1, the ground voltage VSS and the precharge voltage VBL can be applied to each of the first sense signal LA1 and the second sense signal LAB1 to control the operation of the sense amplifier 280. The first power supply voltage VINTA1, the ground voltage VSS and the precharge voltage VBL may be included in the first driving voltage group. The sense amplifier circuit 280 may sequentially read the first bit and the second bit of the multi-bit data stored in the memory cell MC.

[0080] One end of the PMOS transistor P11 is connected to the line of the first sensing signal LA1, the other end of the PMOS transistor P11 is connected to the first sensing bit line SBL1, and the gate of the PMOS transistor P11 is connected to the first complementary sensing bit line SBLB1. One end of the PMOS transistor P12 is connected to the line of the first sensing signal LA1, the other end of the PMOS transistor P12 is connected to the first complementary sensing bit line SBLB1, and the gate of the PMOS transistor P12 is connected to the first sensing bit line SBL1. One end of the NMOS transistor N11 is connected to the power switch SW10, the other end of the NMOS transistor N11 is connected to the first sensing bit line SBL1, and the gate of the NMOS transistor N11 is connected to the holding bit line HBL. One end of the NMOS transistor N12 is connected to the power switch SW10, the other end of the NMOS transistor N12 is connected to the first complementary sensing bit line SBLB1, and the gate of the NMOS transistor N12 is connected to the complementary holding bit line HBLB.

[0081] The bit line switch SWa is connected between the bit line BTL and the holding bit line HBL, and is turned on or off in response to the control of the control logic circuit 210. The complementary bit line switch SWb is connected between the complementary bit line BTLB and the complementary holding bit line HBLB, and is turned on or off in response to the control of the control logic circuit 210. The power switch SW10 is connected between one end of each of the NMOS transistors N11 and N12 and the line of the second sensing signal LAB1, and is turned on or off in response to the control of the control logic circuit 210.

[0082] The first switch SW1 is connected between the holding bit line HBL and the first sensing bit line SBL1, and is turned on or off in response to the control of the control logic circuit 210. The second switch SW2 is connected between the complementary holding bit line HBLB and the first complementary sensing bit line SBLB1, and is turned on or off in response to the control of the control logic circuit 210. The third switch SW3 is connected between the holding bit line HBL and the first complementary sensing bit line SBLB1, and is turned on or off in response to the control of the control logic circuit 210. The fourth switch SW4 is connected between the complementary holding bit line HBLB and the first sensing bit line SBL1, and is turned on or off in response to the control of the control logic circuit 210.

[0083] The latch circuit 283 is connected to the third sensing signal LA2 and the fourth sensing signal LAB2, and includes PMOS transistors P21 and P22 and NMOS transistors N21 and N22. According to the control of the control logic circuit 210, the second power supply voltage VINTA2, the ground voltage VSS, and the negative voltage VBB or the precharge voltage VBL may be applied to each of the third sensing signal LA2 and the fourth sensing signal LAB2 to control the operation of the sense amplifier 280. The second power supply voltage VINTA2, the ground voltage VSS, and the negative voltage VBB or the precharge voltage VBL may be included in the second driving voltage group. The latch circuit 283 may receive the first bit sensed by the sense amplifier circuit 281, and may store the received first bit.

[0084] One end of the PMOS transistor P21 is connected to the line of the third sensing signal LA2, the other end of the PMOS transistor P21 is connected to the second sensing bit line SBL2, and the gate of the PMOS transistor P21 is connected to the second complementary sensing bit line SBLB2. One end of the PMOS transistor P22 is connected to the line of the third sensing signal LA2, the other end of the PMOS transistor P22 is connected to the second complementary sensing bit line SBLB2, and the gate of the PMOS transistor P22 is connected to the second sensing bit line SBL2. One end of the NMOS transistor N21 is connected to the line of the fourth sensing signal LAB2, the other end of the NMOS transistor N21 is connected to the second sensing bit line SBL2, and the gate of the NMOS transistor N21 is connected to the second complementary sensing bit line SBLB2. One end of the NMOS transistor N22 is connected to the line of the fourth sensing signal LAB2, the other end of the NMOS transistor N22 is connected to the second complementary sensing bit line SBLB2, and the gate of the NMOS transistor N22 is connected to the second sensing bit line SBL2.

[0085] The fifth switch SW5 is connected between the first sensing bit line SBL1 of the sense amplifier circuit 281 and the second sensing bit line SBL2 of the latch circuit 283, and is turned on or off in response to the control of the control logic circuit 210. The sixth switch SW6 is connected between the first complementary sensing bit line SBLB1 of the sense amplifier circuit 281 and the second complementary sensing bit line SBLB2 of the latch circuit 283, and is turned on or off in response to the control of the control logic circuit 210.

[0086] Figure 6 According to an example embodiment, Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0087] Reference Figure 6 , in the first memory bank array 310, I sub-array blocks SCB may be arranged along the second direction D2, and J sub-array blocks SCB may be arranged along the first direction D1 substantially perpendicular to the second direction D2. I and J represent the number of sub-array blocks SCB along the second direction and the first direction, respectively, and are natural numbers greater than 2. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the bit lines and the word lines are arranged in each of the sub-array blocks SCB.

[0088] I+1 sub-word line driver regions SWB may be disposed between sub-array blocks SCB along the second direction D2. Sub-word line drivers may be disposed in the sub-word line driver regions SWB. J+1 bit line sense amplifier regions BLSAB may be disposed, for example, between sub-array blocks SCB along the first direction D1. Bit line sense amplifiers for sensing data stored in memory cells may be disposed in the bit line sense amplifier regions BLSAB.

[0089] A plurality of junction regions CONJ may be adjacent to the sub-word line driver region SWB and the bit line sense amplifier region BLSAB. A voltage generator is provided in each junction region CONJ. Figure 7 A portion 390 in the first memory bank array 310 is depicted.

[0090] Figure 7 According to an example embodiment, Figure 6 A portion of a first memory bank array.

[0091] Reference Figure 6 and Figure 7 In the portion 390 of the first memory bank array 310, a sub-array block SCB, a bit line sense amplifier region BLSAB, a sub-word line driver region SWB, and a coupling region CONJ are provided.

[0092] The sub-array block SCB includes a plurality of word lines WL1 to WL4 extending in a row direction (second direction D2) and a plurality of bit line pairs BTL1 to BTL2 and BTLB1 to BTLB2 extending in a column direction (first direction D1). The sub-array block SCB includes a plurality of memory cells MC disposed at intersections between the word lines WL1 to WL4 and the bit line pairs BTL1 to BTL2 and BTLB1 to BTLB2.

[0093] Reference Figure 7 , the sub-word line driver area SWB includes a plurality of sub-word line drivers (SWD) 651, 652, 653, and 654 that drive the word lines WL1 to WL4, respectively. The sub-word line drivers 651 and 652 may be disposed in the sub-word line driver area SWB on the left (in this example) relative to the sub-array block SCB. In addition, the sub-word line drivers 653 and 654 may be disposed in the sub-word line driver area SWB on the right (in this example) relative to the sub-array block SCB.

[0094] The bit line sense amplifier area BLSAB includes bit line sense amplifiers BLSA 660 and 670 coupled to the bit line pairs BTL1 to BTL2 and BTLB1 to BTLB2 and local sense amplifier circuits 680 and 690. The bit line sense amplifier 660 may sense and amplify a voltage difference between the bit line pair BTL and BTLB to provide the amplified voltage difference to the local I / O line pair LIO1 and LIOB1.

[0095] Local sense amplifier circuit 680 controls the connection between local I / O line pair LIO1 and LIOB1 and global I / O line pair GIO1 and GIOB1, and local sense amplifier circuit 690 controls the connection between local I / O line pair LIO2 and LIOB2 and global I / O line pair GIO2 and GIOB2.

[0096] like Figure 7 As shown in FIG. 1 , the bit line sense amplifiers 660 and 670 may be alternately disposed at the upper and lower portions of the sub-array block SCB. The junction region CONJ is disposed adjacent to the bit line sense amplifier region BLSAB, the sub-word line driver region SWB, and the sub-array block SCB. A plurality of voltage generators (VG) 610, 620, 630, and 640 may be disposed in the junction region CONJ.

[0097] Figure 8 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of an error correction circuit in a semiconductor memory device.

[0098] Reference Figure 8 , the error correction circuit 400 includes an ECC memory 410 , an ECC encoder 430 , and an ECC decoder 450 .

[0099] The ECC memory 410 stores the ECC 415. The ECC 415 may be represented by a generator matrix (eg, the data format / structure of the ECC 415 may be the generator matrix), and may include a plurality of column vectors corresponding to data bits in the main data (eg, MD) and the parity data.

[0100] The ECC encoder 430 is connected to the ECC memory 410 and may perform ECC encoding on the main data MD to generate parity data PRT using the ECC 415 stored in the ECC memory 410 in a write operation of the semiconductor memory device 200. The ECC encoder 430 may provide a codeword CW including the main data MD and the parity data PRT to the I / O gating circuit 290.

[0101] The ECC decoder 450 is connected to the ECC memory 410, can receive the codeword CW including the main data MD and the parity data PRT, can perform ECC decoding on the main data MD based on the parity data PRT using the ECC 415 to correct and / or detect an error bit in the main data MD, and can output the corrected main data C_MD. In an example embodiment, the ECC decoder 450 can correct t-bit or more errors in the main data using the ECC 415.

[0102] Although the reference Figure 8 It is described that the ECC memory 410 is coupled to the ECC encoder 430 and the ECC decoder 450 , but in example embodiments, the ECC memory 410 may be implemented using XOR gates within the ECC encoder 430 and the ECC decoder 450 .

[0103] Fig. 9 is a diagram showing a method according to an example embodiment Figure 8 Block diagram of the ECC decoder in the error correction circuit.

[0104] Reference Fig. 9 , the ECC decoder 450 may include a syndrome generator 460, a Berlekamp-Massey (BM) calculator 500 of a BM generator, a chien search block 470, a data corrector 480, a buffer 490, a control circuit 485, and a multiplexer or selection circuit 495.

[0105] The ECC decoder 450 may have a t-bit error correction capability, may generate a syndrome based on the read codeword CW using a parity check matrix, may perform t iterations during t-2 cycles to generate an error locating polynomial ELP based on the syndrome SDR, may search for an error position in the read codeword CW based on the error locating polynomial ELP, and may correct errors in the read codeword CW based on the searched error position.

[0106] The syndrome generator 460 can generate a syndrome SDR by performing a matrix multiplication operation on the read codeword CW and the parity check matrix. The BM calculator or generator 500 can generate coefficients of the error locator polynomial ELP based on the syndrome SDR during t-2 cycles. The money search block 470 can search for error positions based on the coefficients of the error locator polynomial ELP to output an error position signal EPS. The data corrector 480 can receive the read codeword CW and correct errors in the read codeword CW based on the error position signal EPS to output the corrected main data C_MD.

[0107] The buffer 490 may receive the codeword CW, may temporarily store the codeword CW, and may provide the codeword CW to the data corrector 480 and the selection circuit 495 .

[0108] The control circuit 485 can be based on the Fig.10 The BM calculator or generator 500 shown in FIG. 1 generates a selection signal SEL and provides the selection signal SEL to the selection circuit 495. The selection circuit 495 may output one of the output of the data corrector 480 and the output of the buffer 490 as the corrected main data C_MD in response to the selection signal SEL.

[0109] When the vector representation of the codeword CW stored in the target page of the memory cell array 300 corresponds to CV, Equation 1 is derived.

[0110] CV = WDV × G, [Equation 1]

[0111] Among them, WDV is the vector representation of the main data MD, and G is the vector representation of the parity check generator matrix.

[0112] When the vector representation of the codeword CW read from the target page of the memory cell array 300 corresponds to the RV, the RV may include an error, and the RV may be represented by Equation 2.

[0113] RV = WDV × G + E, [Equation 2]

[0114] Here, E corresponds to the vector representation of the error.

[0115] The syndrome generator 460 may perform calculations on the read codeword CW using the parity check matrix. When the vector representation of the parity check matrix corresponds to H, the output of the syndrome generator 460 corresponds to Equation 3.

[0116] RV×H T =WDV×G×H T +E×H T [Equation 3]

[0117] The parity check generation matrix G and the parity check matrix H are set to satisfy Equation 4.

[0118] G×H T =0[Equation 4]

[0119] Therefore, Equation 5 is derived.

[0120] RV×H T =E×H T [Equation 5]

[0121] The result of Equation 5 may correspond to the vector representation S(x) of the syndrome SDR.

[0122] Fig.10 is a diagram showing a method according to an example embodiment Fig. 9 Block diagram of a BM calculator or generator in an ECC decoder.

[0123] Reference Fig.10 , the BM calculator 500 may include a shared processing element (SPE) 510 , 3t / 2+2 processing elements (MPEs) 571 - 0 to 571 -([3t / 2]+1) connected to the shared processing element 510 , and a controller 590 .

[0124] The controller 590 can use the first control signal CL0 and the intermediate coefficient δ 0 The shared processing element 510 and the processing elements 571 - 0 to 571 -([3t / 2]+1) are controlled by using γ(r) and γ(r). The processing element 571 - 0 may also generate a syndrome Si, and Si may be provided to the controller 590.

[0125] The shared processing element 510 may perform the 0th iteration and the first iteration based on the sub-syndrome during the 0th cycle to generate the second iteration intermediate coefficient δ associated with the second iteration i (2) and θ i (2) (refer to Fig.12 ), and the second iteration intermediate coefficient δ i (2) and θ i (2) Supplied to processing elements 571-0 to 571-([3t / 2]+1).

[0126] The processing elements 571-0 to 571-([3t / 2]+1) may be based on the second iteration intermediate coefficient δ i (2) and θ i (2) Execute the second iteration to the t-2th iteration to provide the shared processing element 510 with the t-1th iteration intermediate coefficient δ i (t-1) and θ i (t-1)(Ref. Fig.12 ). The shared processing element 510 may calculate the intermediate coefficient δ based on the t-1th iteration. i (t-1) and θ i (t-1) to perform the t-1th iteration to generate the coefficient λ(t) of the error locator polynomial ELP.

[0127] In an example embodiment, the shared processing element 510 may perform the t-1th iteration by using logic or circuits for generating second iteration intermediate coefficients.

[0128] exist Fig.10 In the figure, each of the processing elements 571-0 to 571-([3t / 2]+1) may include registers rg1 and rg2 for storing initial values, reference numerals 502 and 503 represent signals transmitted from the shared processing element 510 to the processing elements 571-0 to 571-([3t / 2]+1) in the 0th iteration, and reference numeral 505 represents a signal transmitted from the processing elements 571-0 to 571-([3t / 2]+1) to the shared processing element 510 in the t-2th iteration.

[0129] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 A block diagram of one of the processing elements within the BM calculator.

[0130] Reference Fig.11 The processing element MPE may include a plurality of D flip-flops (DFFs) 581 to 584 , first multiplexers 585 a and 585 b , Galois field multipliers 586 and 587 , an XOR gate 588 , and a second multiplexer 589 .

[0131] D flip-flops 581 to 584 can store intermediate coefficients δ i+2 (r+1),δ i+2 (2) θ i (r+1) and θ i (2), the intermediate coefficient δ i+2 (r+1) and δ i+2 (2) is provided to the multiplexer 585a, and the intermediate coefficient θ i (r+1) and θ i (2) is provided to the multiplexer 585b. The multiplexer 585a selects the intermediate coefficient δ in response to the iteration control signal ITRC1 designating the 0th iteration. i+2 (r+1) and δ i+2 (2), the multiplexer 585b selects the intermediate coefficient θ in response to the iteration control signal ITRC1. i (r+1) and θ i (2) One of the following.

[0132] Galois field multiplier 586 performs (Galois field) multiplication on the output of multiplexer 585a and the intermediate coefficient γ(r), and Galois field multiplier 587 performs (Galois field) multiplication on the output of multiplexer 585b and the intermediate coefficient δ 0 (r) Perform (Galois Field) multiplication.

[0133] XOR gate 588 performs an XOR operation on the outputs of Galois field multipliers 586 and 587 to provide an intermediate coefficient δ i (r+1). The multiplexer 589 may select one of the outputs of the multiplexers 585a and 585b and a zero value in response to the first control signal CL0 and the second control signal CL1 to provide an intermediate coefficient θ i (r+1).

[0134] Intermediate coefficient δ i (r) represents the ith difference coefficient of the difference polynomial in the rth iteration, which indicates the difference between the current value and the previous value, and the intermediate coefficient θ i (r) represents the i-th auxiliary coefficient of the auxiliary polynomial in the r-th iteration, and the intermediate coefficient γ(r) represents the auxiliary differential value in the r-th iteration.

[0135] Therefore, processing elements 571-0 to 571-([3t / 2]+1) are sequentially connected to each other, and a second iteration can be performed in a second loop based on the second iteration intermediate coefficients δi(2) and θi(2), and a corresponding iteration can be performed in each of the third loop to the t-2th loop based on the output of the previous processing element.

[0136] Fig.12 is a diagram showing a method according to an example embodiment Fig.10 Block diagram of the shared processing elements in a BM calculator or generator.

[0137] Reference Fig.12 , the shared processing element 510 may include a first intermediate coefficient (IMC) calculator 515 or a first IMC generator, a second intermediate coefficient (IMC) calculator 530 or a second IMC generator, and a control signal generator 565.

[0138] The first intermediate coefficient calculator 515 may be based on the syndrome S i and the first control signal CL0 to generate the auxiliary coefficients θ of the auxiliary polynomial in the second iteration i (2) The second intermediate coefficient calculator 530 may be based on the t-1th iteration coefficient δ i (t-1),θ i (t-1),θ 0(t-1) and γ(t-1), the first control signal CL0 and the second control signal CL1 to generate the differential coefficient δ of the differential polynomial i (2) and the coefficient λ of the error localization polynomial ELP i (t).

[0139] The control signal generator 565 can be based on the syndrome S i The second control signal CL1 is generated and provided to the first intermediate coefficient calculator 515 and the second intermediate coefficient calculator 530 .

[0140] Fig.13 Shows Fig.10 The BM calculator implements the simplified inverse-free BM (SiBM) algorithm.

[0141] Fig.10 The BM calculator 500 executes during the t-2 cycles Fig.13 The SiBM algorithm is used to generate the coefficients λ of the error localization polynomial ELP i (t).

[0142] Fig.14 is a diagram showing a method according to an example embodiment Fig.12 Block diagram of the first intermediate coefficient calculator 515 in FIG.

[0143] Reference Fig.14 , the first intermediate coefficient calculator 515 may include a first sub-calculator (generator) 516 , a second sub-calculator (generator) 520 , and a third sub-calculator (generator) 525 .

[0144] The first sub-calculator 516 operates in the interval (0≤i≤[t / 2]-1), and generates an i-th auxiliary coefficient θ based on the syndrome, the first control signal CL0 and the second control signal CL1. i (2) The first sub-calculator 516 includes a Galois field multiplier 517, an XOR gate 518, and a first multiplexer 519. The Galois field multiplier 517 performs a multiplication of the sub-syndrome S 1 and S 2i+4 To perform Galois field multiplication, an exclusive OR (XOR) gate 518 performs a summation of the output of the Galois field multiplier 517 and the sub-syndrome S 2i+5 To perform an exclusive OR (XOR) operation, the first multiplexer 519 selects the output of the exclusive OR gate 518 and the sub-syndrome S in response to the first control signal CL0 and the second control signal CL1. 2i+3 and S 2i+2 One of the two is used to provide the auxiliary coefficient θ i (2).

[0145] The second sub-calculator 520 includes first registers 521 and 522 and a second multiplexer 523. The registers 521 and 522 store "1" and "0", respectively. The second multiplexer 523 outputs one of "1" and "0" as the auxiliary coefficient θ in response to the first control signal CL0 and the second control signal CL1. t-1 (2), and output the second control signal as the auxiliary coefficient θ t-2 (2).

[0146] The third sub-calculator 525 includes second registers 526 and 527, a third multiplexer 528, and a fourth multiplexer 529. The second registers 526 and 527 store "1" and "0", respectively. The third multiplexer 528 outputs one of "1" and "0" as the auxiliary coefficient θ in response to the first control signal CL0. [3t / 2]+1 (2) The fourth multiplexer 529 outputs the sub-syndrome S in response to the first control signal CL0 and the second control signal CL1. 1 and "0" as the auxiliary coefficient θ [3t / 2] (2).

[0147] Fig.15A and Fig. 15B is a diagram showing a method according to an example embodiment Fig.12 Block diagram of the second intermediate coefficient calculator in .

[0148] Reference Fig.15A and Fig. 15B , Fig.12 The second intermediate coefficient calculator 530 (530a and 530b) includes a first sub-calculator or generator 531a, a second sub-calculator or generator 531b and a third sub-calculator or generator 531c.

[0149] Fig.15A A first sub-calculator 531a is shown, Fig. 15B A second sub-calculator 531b and a third sub-calculator 531c are shown.

[0150] Reference Fig.15A , the first sub-calculator 531a includes multiplexers 532 to 541, multiplexers 542, 543 and 544, an XOR gate 546, Galois field multipliers 547 and 548, an XOR gate 549, a Galois field multiplier 550, Galois field multipliers 551a and 551b, an XOR gate 552, Galois field multipliers 553 and 554 and an XOR gate 555.

[0151] The multiplexers 532 to 541 may select one of the input signals as shown in the figure in response to the iteration control signal ITRC2 designating the t-2th iteration, where S 1 , S 2 , S3 , S 4+2i , S 3+2i , S 2+2i represents the sub-syndrome, γ(t-1), θ 0 (t-1),δ 0 (t-1),δ t+2i-2 (t-1),δ t+2i-3 (t-1),δ t+2i-2 (t-1),δ t+2i-1 (t-1) represents the t-1th iteration coefficient. The multiplexer 542 selects the sub-syndrome S in response to the iteration control signal ITRC2. 5+2i and the difference coefficient δ 0 The multiplexer 543 outputs one of the output of the XOR gate 549 and the output of the multiplexer 542 as the coefficient λ of the error locator polynomial ELP in response to the first control signal CL0 in the interval (0≤i≤[t / 2]). 2i (t).

[0152] XOR gate 546 performs an XOR operation on the outputs of multiplexers 543 and 544 to provide a differential coefficient δ in the interval (0≤i≤[t / 2]) i (2) XOR gate 549 performs an XOR operation on the outputs of Galois field multipliers 547 and 548 .

[0153] Galois field multiplier 550 performs a Galois field multiplication operation on the outputs of multiplexers 532 and 533 to provide the output to multiplexer 538. XOR gate 552 performs an XOR operation on the outputs of Galois field multipliers 551a and 551b to provide coefficients λ of the error locator polynomial ELP in the interval (1≤i≤[t / 2]-1) 4i-3 (t).

[0154] XOR gate 555 performs an XOR operation on the outputs of Galois field multipliers 553 and 554 to provide coefficients λ of the error locator polynomial ELP in the interval (1≤i≤[t / 2]-2) 4i-1 (t).

[0155] exist Fig.15A In the example, Galois field multipliers 547 and 548 and XOR gate 549 may constitute shared logic SLG1, Galois field multipliers 551a and 551b and XOR gate 552 may constitute shared logic SLG2, and Galois field multipliers 553 and 554 and XOR gate 555 may constitute shared logic SLG3. Shared logic or shared circuits SLG1, SLG2 and SLG3 are used together to generate the second iteration intermediate coefficients and perform the t-1th iteration.

[0156] Reference Fig. 15B The second sub-calculator 531 b includes registers 558 and 559 , a Galois field multiplier 556 , an XOR gate 557 , and multiplexers 560 and 561 .

[0157] Registers 558 and 559 store "1" and "0" respectively. Galois field multiplier 556 performs a multiplication of the sub-syndrome S 1 and S 2 The Galois Field multiplication is performed. The multiplexer 560 selects the syndrome S in response to the first control signal CL0. 1 and one of "1" to provide the differential coefficient δ t-2 (2) XOR gate 557 processes the output of Galois field multiplier 556 and the sub-syndrome S 3 To perform an XOR operation, the multiplexer 561 selects "0" and one of the outputs of the XOR gate 557 in response to the first control signal CL0 to provide a differential coefficient δ t-1 (2).

[0158] The third sub-calculator 531c includes a register 562 and a multiplexer 563. The register 562 stores "0", and the multiplexer 563 selects the sub-syndrome S in response to the first control signal CL0. 3 and "0" to provide the differential coefficient δ [3t / 2]+1 (2) In addition, the third sub-calculator 531c provides the sub-syndrome S 2 As the difference coefficient δ [3t / 2] (2).

[0159] Fig.16 is a diagram showing a method according to an example embodiment Fig.12 0066] A block diagram of an example of a control signal generator 565 in FIG.

[0160] Reference Fig.16 , the control signal generator 565 includes a Galois field multiplier 566 , an XOR gate 567 and an OR gate 568 .

[0161] Galois field multiplier 566 pair syndrome S 1 and S 2 Performing Galois field multiplication, XOR gate 567 performs an operation on the output of Galois field multiplier 566 and the sub-syndrome S 3 Performing the XOR operation, the OR gate 568 performs a bitwise OR operation on the output of the XOR gate 567 to provide a second control signal CL1.

[0162] Fig.17 According to an example embodiment, Fig.10 Operation of the BM calculator.

[0163] Reference Fig.10 and Fig.17, the shared processing element 510 performs the 0th iteration 0-th ITR and the first iteration 1st ITR based on the syndrome SDR during the 0th cycle to generate the second iteration intermediate coefficient associated with the second iteration, and provides the second iteration intermediate coefficient to the processing elements 571-0 to 571-([3t / 2]+1). The processing elements 571-0 to 571-([3t / 2]+1) perform the second iteration 2nd ITR to the t-2th iteration (t-2)-th ITR based on the second iteration intermediate coefficient to provide the shared processing element 510 with the t-1th iteration coefficient associated with the t-1th iteration. The shared processing element 510 performs the t-1th iteration (t-1)-th ITR based on the t-1th iteration coefficient to generate the coefficient of the error locator polynomial. Therefore, the ECC decoder 450 with t-bit error correction capability performs t iterations during t-2 cycles to provide the coefficient λ(t) of the error locator polynomial. Therefore, the ECC decoder 450 can reduce the latency of the BM calculator 500.

[0164] Fig.18 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0165] Reference Figures 2 to 18 , a method of operating a semiconductor memory device is provided, the semiconductor memory device including a memory cell array 300 including a plurality of memory cells coupled to word lines and bit lines and an error correction circuit 400.

[0166] In this method, the error correction circuit 400 performs ECC decoding on the data (codeword) read from the target page of the memory cell array 300. The error correction circuit 400 generates parity data PRT by performing ECC encoding on the main data MD, and provides the codeword including the main data MD and the parity data PRT to the I / O gating circuit 290 (operation S110).

[0167] The I / O gating circuit 290 stores the codeword CW in the target page of the memory cell array 300 (operation S120). The I / O gating circuit 290 reads the codeword CW from the target page of the memory cell array 300 and provides the read codeword CW to the error correction circuit 400 (operation S130).

[0168] The ECC decoder 450 in the error correction circuit 400 corrects an error in the read codeword CW based on the parity data PRT (operation S140). The ECC decoder 450 performs t iterations during t-2 cycles to generate an error locator polynomial based on the syndrome SDR, searches for an error position in the read codeword CW based on the error locator polynomial, and corrects the error in the read codeword CW based on the searched error position.

[0169] Fig.19 is a flowchart illustrating a method of ECC decoding in a semiconductor memory device according to example embodiments.

[0170] Reference Figures 2 to 17 as well as Fig.19 , a method of ECC decoding in a semiconductor memory device is provided. According to the method, the ECC decoder 450 in the error correction circuit 400 receives a codeword CW including main data and parity data read from a target page of the memory cell array 300 (operation S310).

[0171] The syndrome generator 460 in the ECC decoder 450 generates a syndrome S(x) based on the codeword CW by using a parity check matrix (operation S320). The BM calculator 500 determines whether the syndrome S(x) has a zero value (operation S330). When the syndrome S(x) has a zero value ("yes" in operation S330), the ECC decoder 450 outputs the main data in the codeword CW.

[0172] When the syndrome S(x) does not have a zero value (No in operation S330), it means that the codeword CW includes an error, and the BM calculator 500 performs t iterations during t-2 cycles to perform the SiBM algorithm to generate an error locator polynomial ELP based on the syndrome S(x) (operation S340).

[0173] The money search block searches for an error position based on the coefficients of the error locator polynomial ELP to output an error position signal EPS to the data corrector (operation S350). The data corrector 480 corrects errors in the codeword CW based on the error position signal EPS to output corrected main data C_MD (operation S360).

[0174] Fig. 20 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0175] Reference Fig. 20 , the semiconductor memory device 700 may include a first group of dies 710 and a second group of dies 720 that provide soft error analysis and correction functions in a stacked chip structure. The second group of dies 720 may be a high bandwidth memory (HBM).

[0176] The first group of dies 710 may include at least one buffer die 711. The second group of dies 720 may include a plurality of memory dies 720-1 to 720-u (u is a natural number greater than two) that are stacked on the memory die 711 and may transmit data to the at least one buffer die 711 through a plurality of through silicon vias (TSVs, also referred to as through silicon vias) lines.

[0177] Each of the memory dies 720-1 to 720-u may include a cell core 722 and an error correction circuit 724. The cell core 722 may include a plurality of memory cells coupled to word lines and bit lines. The error correction circuit 724 may be referred to as an ECC circuit and may be implemented in Figure 8 The error correction circuit 400 of FIG. 400. Therefore, the error correction circuit 724 can perform t iterations during t-2 cycles to generate an error locator polynomial based on the syndrome, can search for an error position in the read codeword based on the error locator polynomial, and can correct the error based on the searched error position when performing ECC decoding. Therefore, the error correction circuit 724 can reduce latency.

[0178] The buffer die 711 may include an error correction circuit 712 that corrects a transmission error using a transmission parity bit and generates error-corrected data when a transmission error is detected from transmission data received through the TSV line. The error correction circuit 712 may be referred to as a via error correction circuit.

[0179] The semiconductor memory device 700 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines. The TSV lines may also be referred to as through electrodes.

[0180] A transmission error occurring at the transmission data may be caused by noise generated at the TSV line. Since data failures caused by noise generated at the TSV line can be distinguished from data failures caused by erroneous operation of the memory die, data failures caused by noise generated at the TSV line can be considered as soft data failures (or soft errors). Soft data failures may be caused by transmission failures on the transmission path and can be detected and remedied by ECC operations.

[0181] The TSV line group 732 formed at one memory die 720 - u may include TSV lines L1 to Lu, and the parity TSV line group 734 may include TSV lines L10 to Lv.

[0182] The TSV lines L1 to Lu of the data TSV line group 732 and the parity TSV lines L10 to Lv of the parity TSV line group 734 may be connected to micro bumps MCB correspondingly formed in the memory dies 720 - 1 to 720 - u.

[0183] Each of the memory dies 720 - 1 to 720 - u may include a DRAM cell, each DRAM cell including at least one access transistor and one storage capacitor.

[0184] The semiconductor memory device 700 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a memory controller through a data bus B10. The buffer die 710 may be connected to the memory controller through the data bus B10.

[0185] The error correction circuit 712 may determine whether a transmission error occurs at transmission data received through the data TSV line group 732 based on the transmission parity bit received through the parity TSV line group 734 .

[0186] When a transmission error is detected, the error correction circuit 712 may correct the transmission error for the transmission data using the transmission parity bit. When the transmission error is uncorrectable, the error correction circuit 712 may output information indicating that an uncorrectable data error has occurred.

[0187] Fig.21 According to the exemplary embodiment, Fig. 20 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0188] Fig.21 A 3D chip structure 800 is shown where the host and HBM are directly connected without an intermediate layer.

[0189] Reference Fig.21 , a host die 810 (such as a system on chip (SOC), a central processing unit (CPU), or a graphics processing unit (GPU)) may be disposed on a printed circuit board (PCB) 820 using flip chip bumps FB. The memory dies D11 to D14 may be stacked on the host die 820 to achieve the following. Fig. 20 HBM structure 720 of the memory die in FIG. Fig.21 In, omitted Fig. 20 However, the buffer die 710 or the logic die may be disposed between the memory die D11 and the host die 820.

[0190] To implement the HBM (720) structure, TSV lines may be formed at the memory dies D11 and D14. The TSV lines may be electrically connected to the microbumps MCB located between the memory dies. In addition, each of the memory dies D11 to D14 may include a Figure 8 The error correction circuit 400 is an error correction circuit.

[0191] Fig. 22 is a diagram illustrating a semiconductor package including a stacked memory device according to example embodiments.

[0192] Reference Fig. 22, the semiconductor package 900 may include one or more stacked memory devices 910 and a graphics processor (GPU) 920 , and the GPU 920 includes a memory controller (CONT) 925 .

[0193] The stacked memory device 910 and the GPU 920 may be mounted on the intermediate layer 930, and the intermediate layer on which the stacked memory device 910 and the GPU 920 are mounted may be mounted on the package substrate 940. The memory controller 925 may be implemented using Figure 1 The memory controller 100 in FIG.

[0194] Each of the stacked memory devices 910 may be implemented in various forms, and may be a memory device in the form of a high bandwidth memory (HBM) in which a plurality of layers are stacked. Therefore, each of the stacked memory devices 910 may include a buffer die and a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array and an error correction circuit.

[0195] A plurality of stacked memory devices 910 may be mounted on the intermediate layer 930, and the GPU 920 may communicate with the plurality of stacked memory devices 910. For example, each of the stacked memory device 910 and the GPU 920 may include a physical area, and communication may be performed between the stacked memory device 910 and the GPU 920 through the physical area.

[0196] According to an example embodiment, the ECC decoder may perform t iterations during t-2 cycles to generate an error locating polynomial based on a syndrome, may search for an error position in a read codeword based on the error locating polynomial, and may correct an error based on the searched error position when performing ECC decoding. Therefore, the error correction circuit may reduce latency.

[0197] Example embodiments of the present disclosure may be applied to a system using a semiconductor memory device employing a DRAM cell and an error correction circuit.

[0198] The foregoing is an illustration of example embodiments and is not to be construed as limiting the example embodiments. Although several example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims.

Claims

1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array further comprising a plurality of sense amplifiers configured to sense data stored in the plurality of memory cells; an error correction circuit including an error correction code decoder configured to perform error correction code decoding on a codeword read from a target page of a memory cell array to correct an error in the read codeword, the codeword including main data and parity data; as well as a control logic circuit configured to control the error correction circuit based on commands and addresses from the memory controller, The error correction code decoder has a t-bit error correction capability, where t is an even number greater than three. The error correction code decoder is configured to perform operations, the operations comprising: generating a syndrome based on the codeword using a parity check matrix; performing t iterations during t-2 cycles to generate an error localization polynomial based on the syndrome; Searching for error locations in the codeword based on an error locator polynomial; and Correct the errors in the codeword based on the searched error positions, wherein the error correction code decoder comprises a Bole-Gant-Massey generator configured to generate coefficients of an error locator polynomial based on the syndrome during t-2 cycles, Among them, the Bollegan-Marseille generator includes: Shared processing elements; 3t / 2+2 processing elements connected to a shared processing element; and a controller configured to control the shared processing element and the 3t / 2+2 processing elements, wherein the shared processing element is configured to: perform the 0th iteration and the first iteration based on the syndrome during the 0th cycle to generate a second iteration intermediate coefficient associated with the second iteration, and is configured to provide the second iteration intermediate coefficient to the 3t / 2+2 processing elements, The 3t / 2+2 processing elements are configured to: perform the second iteration to the t-2th iteration based on the second iteration intermediate coefficient to provide the t-1th iteration coefficient associated with the t-1th iteration to the shared processing element, The shared processing element is configured to: perform the t-1th iteration based on the t-1th iteration intermediate coefficient to generate coefficients of the error locator polynomial, The t-2th iteration and the t-1th iteration are executed during the same cycle.

2. The semiconductor memory device according to claim 1, wherein The error correction code decoder also includes: a syndrome generator configured to generate a syndrome by performing a matrix multiplication operation on the codeword and a parity check matrix; a front search block configured to search for an error location based on coefficients of an error locator polynomial to output an error location signal; and A data corrector is configured to receive the codeword and to correct errors in the codeword based on the error location signal.

3. The semiconductor memory device according to claim 1, wherein: The shared processing element is configured to perform the t-1th iteration by using circuitry configured to generate second iteration intermediate coefficients.

4. The semiconductor memory device according to claim 1, wherein: Shared processing elements include: A first intermediate coefficient generator configured to generate auxiliary coefficients of an auxiliary polynomial among the second iterative intermediate coefficients based on the syndrome and the first control signal; A second intermediate coefficient generator configured to generate differential coefficients of the differential polynomial and coefficients of the error locator polynomial among the second iteration intermediate coefficients based on the t-1th iteration coefficient, the first control signal, and the second control signal; and The control signal generator is configured to generate a second control signal based on the syndrome.

5. The semiconductor memory device according to claim 4, wherein: The first intermediate coefficient generator comprises: A first sub-generator configured to: when i is in the interval 0≤i≤(t / 2)-1, generate an i-th auxiliary coefficient among the auxiliary coefficients based on the syndrome, the first control signal and the second control signal; A second sub-generator configured to: when i=t-1 or i=t-2, generate an i-th auxiliary coefficient based on the first control signal and the second control signal; and The third sub-generator is configured to generate an i-th auxiliary coefficient based on the first sub-syndrome of the syndrome, the first control signal and the second control signal when i=3t / 2 or i=(3t / 2)+1.

6. The semiconductor memory device according to claim 5, in, The first sub-generator includes a Galois field multiplier, an XOR gate, and a first multiplexer; Wherein, the second sub-generator includes a first register and a second multiplexer; The third sub-generator includes a second register, a third multiplexer and a fourth multiplexer.

7. The semiconductor memory device according to claim 4, wherein: The second intermediate coefficient generator comprises: A first sub-generator configured to generate coefficients of an error locator polynomial and differential coefficients in a second iteration based on a syndrome, differential coefficients in a t-1th iteration, an auxiliary differential value in a t-1th iteration, and an iteration control signal designating a t-2th iteration; a second sub-generator configured to generate a t-2 th differential coefficient and a (t-2)+1 th differential coefficient among the differential coefficients based on the syndrome and the first control signal; and The third sub-generator is configured to generate a 3t / 2th differential coefficient and a (3t / 2)+1th differential coefficient among the differential coefficients based on the syndrome and the first control signal.

8. The semiconductor memory device according to claim 7, in, The first sub-generator includes: a plurality of first multiplexers, a plurality of first Galois field multipliers, and a plurality of first XOR gates; Wherein, the second sub-generator comprises: a first register, a second Galois field multiplier, a second XOR gate and a second multiplexer; The third sub-generator includes a second register and a third multiplexer.

9. The semiconductor memory device according to claim 8, wherein: The first sub-generator is configured to generate second iteration intermediate coefficients and perform a t-1th iteration by using one or more of the plurality of first multiplexers, the plurality of first Galois field multipliers, and the plurality of first XOR gates.

10. The semiconductor memory device according to any one of claims 4 to 9, wherein: The control signal generator includes: a Galois field multiplier configured to perform a Galois field multiplication on a first sub-syndrome and a second sub-syndrome of the syndrome; an XOR gate configured to perform an XOR operation on an output of the Galois field multiplier and a third sub-syndrome of the syndrome; and An OR gate is configured to perform an OR operation on the output of the XOR gate to provide a second control signal.

11. The semiconductor memory device according to claim 1, wherein: The 3t / 2+2 processing elements are connected sequentially and are configured to: perform a second iteration in a second loop based on a second iteration intermediate coefficient, and perform a corresponding iteration in each of a third loop to a t-2th loop based on an output of a previous processing element among the 3t / 2+2 processing elements.

12. The semiconductor memory device according to claim 11, in, Each of the 3t / 2+2 processing elements includes: a plurality of D flip-flops, a plurality of first multiplexers, a Galois field multiplier, an XOR gate, and a second multiplexer, wherein the plurality of first multiplexers are configured to select one or more of the outputs of the plurality of D flip-flops in response to an iteration control signal, The iteration control signal is associated with the 0th iteration.

13. The semiconductor memory device according to any one of claims 1 to 9, wherein: The error correction circuit also includes: an error correction code encoder configured to perform error correction code encoding on main data from the memory controller by using a parity generation matrix to generate parity data; and The memory is configured to store a parity check matrix and a parity check generation matrix.

14. The semiconductor memory device according to any one of claims 1 to 9, in, Each of the plurality of memory cells stores a plurality of bits of data, wherein a first sense amplifier of the plurality of sense amplifiers is coupled to a bit line and a complementary bit line of a first memory cell of the plurality of memory cells, Wherein, the first sense amplifier comprises: a sense amplifier circuit configured to sense a first bit and a second bit of multi-bit data stored in the first memory cell, wherein the sense amplifier circuit is configured to receive a first drive voltage group and is configured to operate based on the first drive voltage group; and The latch circuit is configured to store a first bit provided from the sense amplifier circuit, wherein the latch circuit is configured to receive a second driving voltage group and is configured to operate based on the second driving voltage group.

15. The semiconductor memory device according to any one of claims 1 to 9, wherein: Each of the plurality of memory cells is configured to store a single bit of data.

16. The semiconductor memory device according to any one of claims 1 to 9, comprising: at least one buffer die; as well as a plurality of memory dies stacked on the at least one buffer die and transmitting data through a plurality of through silicon via lines, Wherein, at least one of the plurality of memory dies comprises a memory cell array and an error correction circuit.

17. The semiconductor memory device according to claim 16, wherein: The at least one buffer die includes a via error correction circuit configured to correct transmission errors included in data transmitted through the through-silicon via line.

18. A method of operating a semiconductor memory device, wherein: A semiconductor memory device includes a memory cell array and an error correction circuit, the memory cell array including a plurality of memory cells coupled to word lines and bit lines, the method including: reading a codeword including main data and parity data from a target page of a memory cell array; and The error in the codeword is corrected by an error correction code decoder of the error correction circuit by performing error correction code decoding on the codeword, The error correction code decoder has a t-bit error correction capability, where t is an even number greater than three. The error correction code decoder is configured to perform operations, the operations comprising: generating a syndrome based on the codeword using a parity check matrix; performing t iterations during t-2 cycles to generate an error localization polynomial based on the syndrome; Searching for error locations in the codeword based on an error locator polynomial; and Correct the errors in the codeword based on the searched error positions, wherein the error correction code decoder comprises a Bole-Gant-Massey generator configured to generate coefficients of an error locator polynomial based on the syndrome during t-2 cycles, Among them, the Bollegan-Marseille generator includes: Shared processing elements; 3t / 2+2 processing elements connected to a shared processing element; and a controller configured to control the shared processing element and the 3t / 2+2 processing elements, wherein the shared processing element is configured to: perform the 0th iteration and the first iteration based on the syndrome during the 0th cycle to generate a second iteration intermediate coefficient associated with the second iteration, and is configured to provide the second iteration intermediate coefficient to the 3t / 2+2 processing elements, The 3t / 2+2 processing elements are configured to: perform the second iteration to the t-2th iteration based on the second iteration intermediate coefficient to provide the t-1th iteration coefficient associated with the t-1th iteration to the shared processing element, The shared processing element is configured to: perform the t-1th iteration based on the t-1th iteration intermediate coefficient to generate coefficients of the error locator polynomial, The t-2th iteration and the t-1th iteration are executed during the same cycle.

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