Pixel sensing device and panel driving device for sensing characteristics of pixels

Abstract

The present invention provides a pixel sensing device and a panel driving device for sensing characteristics of pixels. The present invention provides a technique in pixel sensing, in which a parasitic impedance formed on a sensing line does not affect an integration circuit by using a current mirror circuit coupled with an operational amplifier.

Description

Technical Field

[0001] The present invention relates to pixel sensing technology, and more particularly, to a technology for improving the performance of a pixel sensing circuit. Background Art

[0002] A display device includes a source driver for driving pixels arranged on a panel.

[0003] The source driver determines data voltages according to image data and supplies these data voltages to the pixels to control the brightness of each pixel.

[0004] Here, even when the same data voltage is supplied, the brightness of each pixel varies according to the characteristics of each pixel. For example, a pixel includes a driving transistor, and when the threshold voltage of the driving transistor changes, even if the same data voltage is supplied to the pixel, the brightness of the pixel changes. If the source driver does not reflect such a characteristic change of the pixel, the pixel will be driven with an undesired brightness, and this may cause deterioration of image quality.

[0005] Specifically, the characteristics of a pixel change according to time or the surrounding environment of the pixel. However, if the source driver supplies data voltages without reflecting such a changing characteristic of the pixel, this may cause deterioration of image quality, such as aging.

[0006] To solve such a problem of image quality deterioration, a display device may include a pixel sensing device for sensing the characteristics of pixels.

[0007] The pixel sensing device may receive sensing signals of pixels through sensing lines respectively connected to the pixels. The pixel sensing device converts the sensing signals into sensing data and transmits the sensing data to a timing controller, and the timing controller identifies the characteristics of each pixel using the sensing data. The timing controller may compensate the image data by reflecting the characteristics of the pixels to reduce deterioration of image quality caused by differences between pixels. The pixel sensing device generally uses an integrated circuit to sense the characteristic current of a pixel. The pixel sensing device uses an analog-to-digital conversion circuit to convert a voltage signal into digital data, and thus, uses an integrated circuit to convert the characteristic current of the pixel into a voltage signal available in the analog-to-digital conversion circuit. The integrated circuit may include an operational amplifier and an integrating capacitor. The characteristic current transmitted from the pixel through the sensing line is accumulated in the integrating capacitor to form a voltage signal.

[0008] However, in such a structure, the parasitic resistance and parasitic capacitance formed in the sensing lines may cause the performance of the integrated circuit to deteriorate. The pixel and the integrated circuit are connected through the sensing lines, and the sensing lines have their own parasitic resistance according to the width and length of the lines, and form parasitic capacitance with the surrounding electrodes. Such parasitic resistance and parasitic capacitance in the sensing lines are perceived by the integrated circuit as a load, and this causes the so-called load effect. The load effect results in a reduction in the accuracy of the integrated circuit. Summary of the Invention

[0009] In this context, one aspect of the present invention is to provide a technique for improving the performance of a pixel sensing device. Another aspect of the present invention is to provide a technique for improving the sensing accuracy of a pixel sensing device. Still another aspect of the present invention is to provide a technique for minimizing the load effect in the sensing lines of a pixel sensing device.

[0010] To this end, in one aspect, the present invention provides a pixel sensing device, comprising: an analog front-end circuit including an amplifier circuit and an integration circuit, the amplifier circuit including an operational amplifier formed with a first input terminal, a second input terminal, and an output terminal, a first transistor connected to the output terminal of the operational amplifier, and a second transistor forming a current mirror circuit with the first transistor, wherein the first input terminal is connected to the pixel and the output terminal, and the integration circuit is configured to integrate the current flowing into the second transistor; an analog-to-digital conversion circuit for generating sensing data corresponding to the voltage output from the integration circuit; and a data transmission circuit for transmitting the sensing data to an external device.

[0011] The current flowing from the first input terminal to the output terminal can flow into the first transistor. The amplifier circuit may further include a third transistor and a fourth transistor, and the current output from the output terminal of the operational amplifier flows through the third transistor, and the fourth transistor forms a current mirror circuit with the third transistor. The integration circuit may integrate the current flowing into the second transistor or the current flowing into the fourth transistor.

[0012] The first transistor may be connected to a low bias voltage on one side and to the output terminal on the other side. The second transistor may be connected to the low bias voltage on one side and to a mirror terminal on the other side. The integration circuit may be connected to the mirror terminal.

[0013] The first transistor and the second transistor may form an N:1 current mirror circuit, and the level of the current flowing into the second transistor may be 1 / N times the level of the current flowing into the first transistor, where N is a positive real number.

[0014] A reference voltage can be connected to the second input terminal, and the reference voltage can be formed in the first input terminal by the operational amplifier.

[0015] The integrating circuit may include another operational amplifier. One input terminal of the operational amplifier may be connected to the second transistor and its other input terminal may be connected to a reference voltage. An integrating capacitor may be arranged between the one input terminal and the other input terminal of the operational amplifier.

[0016] The pixel sensing device may further include: a sample-and-hold circuit for temporarily storing the voltage output from the integrating circuit; and another amplifying circuit for amplifying the signal output from the sample-and-hold circuit and transmitting the amplified signal to the analog-to-digital conversion circuit.

[0017] In another aspect, the present invention provides a panel driving device for driving a panel on which a plurality of pixels are arranged and a plurality of data lines and a plurality of sensing lines are arranged, the plurality of data lines and the plurality of sensing lines being respectively connected to the plurality of pixels, the panel driving device including: a data driving circuit for converting image data into a data voltage and supplying the data voltage through the data lines; a pixel sensing circuit for generating sensing data corresponding to an integrated voltage of a characteristic current transmitted from a pixel; and a data processing circuit for compensating the image data using the sensing data, wherein in the pixel sensing circuit, the characteristic current is input into the operational amplifier through an output terminal of the operational amplifier, and the integrated voltage is formed by integrating the current of a second transistor arranged in the operational amplifier, the second transistor and a first transistor arranged in the operational amplifier form a current mirror circuit, and the characteristic current flows in the first transistor.

[0018] The first transistor and the second transistor may form an N:1 current mirror circuit, and the level of the current flowing into the second transistor may be 1 / N times the level of the current flowing into the first transistor, where N is a positive real number.

[0019] The integrating circuit for integrating the current of the second transistor includes another operational amplifier.

[0020] The pixel sensing circuit may include: a sample-and-hold circuit for temporarily storing the integrated voltage; an amplifying circuit for amplifying the signal output from the sample-and-hold circuit; and an analog-to-digital conversion circuit for converting the signal output from the amplifying circuit into sensing data.

[0021] The pixel may include an organic light emitting diode (OLED).

[0022] The pixel sensing circuit may be connected to a contact node between the organic light emitting diode and a driving transistor for supplying a driving current to the organic light emitting diode, and receive a current flowing into the driving transistor or a current flowing into the organic light emitting diode as a characteristic current.

[0023] The characteristics of the driving transistor may be compensated using image data based on the characteristic current.

[0024] As described above, the present invention can minimize the load effect of the sensing lines of the pixel sensing device, improve the sensing accuracy of the pixel sensing device, and improve the performance of the pixel sensing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a structural diagram of a display device according to an embodiment;

[0026] Figure 2 shows Figure 1 the structure of each pixel of and signals output and / or input to / from the data driving circuit, the pixel, and the sensing circuit;

[0027] Figure 3 is a structural diagram of a sensing circuit according to an embodiment;

[0028] Figure 4 is a structural diagram of an analog front end circuit according to an embodiment;

[0029] Figure 5 is a diagram showing the internal structure of an amplifier circuit; and

[0030] Figure 6 shows Figure 4 the change over time of a delta voltage corresponding to the difference between the sensing voltage and the reference voltage of. DETAILED DESCRIPTION

[0031] Figure 1 is a structural diagram of a display device according to an embodiment.

[0032] Referring Figure 1 , the display device 100 may include a panel 160 and a panel driving device for driving the panel 160. On the panel 160, a plurality of data lines DL, a plurality of gate lines GL, and a plurality of sensing lines SL may be arranged and a plurality of pixels P may be arranged.

[0033] The panel driving device may include a data driving circuit 120, a sensing circuit 130, a gate driving circuit 140, and a data processing circuit 150.

[0034] The gate driving circuit 140 can supply a scanning signal such as a turn-on voltage or a turn-off voltage through the gate line GL. When the scanning signal of the turn-on voltage is supplied to the pixel P, the pixel P is connected to the data line DL, and when the scanning signal of the turn-off voltage is supplied to the pixel, the pixel is disconnected from the data line DL. The data driving circuit 120 supplies a data voltage to the data line DL. The data voltage supplied to the data line DL is transmitted to the pixel P connected to the data line DL according to the scanning signal.

[0035] The sensing circuit 130 receives sensing signals such as voltage or current formed in each pixel P. The sensing circuit 130 can be connected to each pixel P according to the scanning signal or according to the sensing scanning signal. Here, the sensing scanning signal can be generated by the gate driving circuit 140.

[0036] The data processing circuit 150 can supply various control signals to the gate driving circuit 140 and the data driving circuit 120. The data processing circuit 150 can generate a gate control signal GCS to initiate scanning according to the timing executed in each frame, and transmit the gate control signal to the gate driving circuit 140. The data processing circuit 150 can convert the image data input from the outside into image data RGB in a format suitable for use in the data driving circuit 120, and output the converted image data RGB to the data driving circuit 120. In addition, the data processing circuit 150 can transmit a data control signal DCS at an appropriate timing to control the data driving circuit 120 to supply a data voltage to each pixel P.

[0037] The data processing circuit 150 can compensate the image data RGB according to the characteristics of the pixel P and transmit the compensated image data. To this end, the data processing circuit 150 can receive sensing data SDAT from the sensing circuit 130. The sensing data SDAT can include measured values of the characteristics of the pixel P.

[0038] On the other hand, the data driving circuit 120 can be referred to as a source driver, the gate driving circuit 14 can be referred to as a gate driver, and the data processing circuit 150 can be referred to as a timing controller. The data driving circuit 120 and the sensing circuit 130 can be included in the integrated circuit 110 and are referred to as a source driver integrated circuit (IC) or a pixel sensing device. Otherwise, the data driving circuit 120, the sensing circuit 130, and the data processing circuit 150 can be included in the integrated circuit and are referred to as a combined IC. However, the present invention is not limited thereto, and descriptions of some well-known components of the source driver, the gate driver, or the timing controller will be omitted in the following description of the embodiments. Therefore, considering the fact that such some component descriptions are omitted, the description of the embodiments should be understood.

[0039] The panel 160 may be an organic light emitting display panel. In this case, each pixel P disposed on the panel 160 may include an organic light emitting diode (OLED) and at least one transistor. The characteristics of the organic light emitting diode OLED and the at least one transistor included in each pixel P may vary according to time or the surrounding environment of the pixel. The sensing circuit 130 according to an embodiment may sense the characteristics of such elements included in each pixel P and transmit them to the data processing circuit 150.

[0040] Figure 2 is a diagram showing Figure 1 the structure of each pixel and the signals output and / or input to / from the data driving circuit, the pixel, and the sensing circuit.

[0041] Referring to Figure 2 , the pixel P may include a light emitting diode OLED, a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, and a storage capacitor Cstg.

[0042] The organic light emitting diode OLED may include an anode electrode, an organic layer, and a cathode electrode. Under the control of the driving transistor DRT, the anode electrode is connected in the direction of the driving voltage EVDD, and the cathode electrode is connected to the base voltage EVSS, so that the organic light emitting diode emits light.

[0043] The driving transistor DRT may control the brightness of the organic light emitting diode OLED by controlling the driving current supplied to the organic light emitting diode OLED.

[0044] The first node N1 of the driving transistor DRT may be electrically connected to the anode electrode of the light emitting diode OLED and may be a source node or a drain node. The second node N2 of the driving transistor DRT may be electrically connected to the source node or the drain node of the switching transistor SWT and may be a gate node. The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL for supplying the driving voltage EVDD and may be a drain node or a source node.

[0045] The switching transistor SWT may be electrically connected between the data line DL and the second node N2 of the driving transistor DRT and is turned on by providing a scan signal via the first gate line GL1.

[0046] When the switching transistor SWT is turned on, the data voltage Vdata supplied from the data driving circuit 120 through the data line DL is transmitted to the second node N2 of the driving transistor DRT.

[0047] The storage capacitor Cstg may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0048] The storage capacitor Cstg can be a parasitic capacitor existing between the first node N1 and the second node N2 or an external capacitor intentionally arranged outside the driving transistor DRT.

[0049] The sensing transistor SENT can connect the first node N1 of the driving transistor DRT to the sensing line SL, and through the sensing line SL, a reference voltage can be transmitted to the first node N1, and characteristic values such as the voltage or current Is of the first node N1 can be transmitted to the sensing circuit 130.

[0050] The sensing circuit 130 uses the sensing signal Is transmitted through the sensing line SL to measure the characteristics of the pixel P. The sensing signal Is, which is a characteristic current indicating the characteristics of the pixel, can be a current flowing in the driving transistor DRT or in the organic light-emitting diode OLED. The sensing circuit 130 can measure this characteristic current and transmit the measured value to the data processing circuit (see Figure 1 in 150). The data processing circuit (see Figure 1 in 150) can analyze the measured value of the characteristic current to identify the characteristics of each pixel P.

[0051] The characteristics of each pixel P can be the threshold voltage or mobility of the driving transistor DRT.

[0052] Figure 3 is a structural diagram of the sensing circuit according to an embodiment.

[0053] Refer to Figure 3 , the sensing circuit 130 can include an analog front-end circuit (AFE) 310, a sample-and-hold circuit (S / H) 320, an amplifier circuit (AMP) 330, an analog-to-digital conversion circuit (ADC) 350, and a data transmission circuit (TX) 360.

[0054] The analog front-end circuit 310 can sense the pixel P and form a sensing voltage Vi by processing the current Is transmitted from the pixel P. According to an embodiment, the sensing voltage Vi can be the same as the voltage obtained by integrating the current Is transmitted from the pixel P. The analog front-end circuit 310 can transmit the sensing voltage Vi to the amplifier circuit 330, and the amplifier circuit 330 can amplify the sensing voltage Vi or the difference ΔVi between the sensing voltage Vi and the reference voltage, and transmit the amplified sensing voltage Vi or the difference ΔVi to the analog-to-digital conversion circuit 350. Between the analog front-end circuit 310 and the amplifier circuit 330, a sample-and-hold circuit 320 can be arranged. The sample-and-hold circuit 320 can separate the analog front-end circuit 310 from the amplifier circuit 330 in terms of signals, temporarily store the sensing voltage Vi output from the analog front-end circuit 310, and input the sensing voltage Vi or the difference ΔVi between the sensing voltage Vi and the reference voltage to the amplifier circuit 330.

[0055] The amplifier circuit 330 can amplify the sensed voltage Vi or the difference ΔVi between the sensed voltage Vi and the reference voltage transmitted through the input terminal, and then transmit the amplified sensed voltage Vi or difference ΔVi to the analog-to-digital conversion circuit 350. The analog-to-digital conversion circuit 350 can convert the voltage output from the amplifier circuit 330 into a digital signal Ao. The data transmission circuit 360 can generate sensed data SDAT by processing the digital signals Ao collected from multiple channels, and transmit the sensed data SDAT to an external device (e.g., the data processing circuit 150).

[0056] Figure 4 is a structural diagram of an analog front-end circuit according to an embodiment.

[0057] Reference Figure 4 , the analog front-end circuit 310 can include an amplifier circuit 410 and an integration circuit 420.

[0058] The analog front-end circuit 310 can receive the characteristic current Is from the pixel P through the sensing line SL. In the sensing line SL, there can be a parasitic resistance Rp and a parasitic capacitance Cp. The analog front-end circuit 310 can minimize the load effect of the sensing line SL on the integration circuit 420 by separating the integration circuit 420 from the pixel P using the amplifier circuit 410.

[0059] The amplifier circuit 410 can include a first operational amplifier AP1.

[0060] The first operational amplifier AP1 can include a first input terminal, a second input terminal, and an output terminal. The first input terminal can be connected to the first node N1, and the sensing line SL connected to the pixel P can be connected to the first node N1. The second input terminal can be connected to the second node N2, and a first reference voltage Vpre1 can be supplied through the second node N2. The output terminal can be connected to the third node N3, and the first node N1 can be connected to the third node N3. In the feedback structure where the first input terminal and the output terminal are connected, due to the very large amplification gain of the operational amplifier, the voltage of the second input terminal can be substantially the same as the voltage of the first input terminal. Therefore, when the first reference voltage Vpre1 is supplied through the second input terminal, the first reference voltage Vpre1 can be formed at the first input terminal, and the sensing line SL can be initialized or maintained to have the first reference voltage Vpre1.

[0061] The first operational amplifier AP1 can be driven by setting a high bias voltage VDD and a low bias voltage VSS as the bias voltage.

[0062] The two transistors TR1 and TR3 can be internally connected to the output terminal of the first operational amplifier AP1. The amplifier circuit 410 may further include two other transistors TR2 and TR4 that respectively form a current mirror circuit with the two transistors TR1 and TR3.

[0063] Among the two transistors TR1 and TR3 connected to the output terminal of the first operational amplifier AP1, the first transistor TR1 can provide a path through which the current input via the output terminal flows out to the low bias voltage VSS. The third transistor TR3 can provide a path through which the current output via the output terminal flows out from the high bias voltage VDD.

[0064] The second transistor TR2 can form a current mirror circuit with the first transistor TR1. The second transistor TR2 and the first transistor TR1 can respectively have gates connected to each other and both can be N-type transistors connected to the low bias voltage VSS. Due to this structure, a current having a level proportional to or the same as the level of the current flowing into the first transistor TR1 can flow into the second transistor TR2.

[0065] The fourth transistor TR4 can form a current mirror circuit with the third transistor TR3. The fourth transistor TR4 and the third transistor TR3 can respectively have gates connected to each other and both can be P-type transistors connected to the high bias voltage VDD. Due to this structure, a current having a level proportional to or the same as the level of the current flowing into the third transistor TR3 can flow into the fourth transistor TR4.

[0066] The characteristic current Is transmitted from the pixel P can be transmitted to the first node N1 via the sensing line SL. Since the internal impedance of the first operational amplifier AP1 is very high, the current transmitted to the first node N1 can flow to the output terminal of the first operational amplifier without flowing to its first input terminal. When the characteristic current Is has a positive level, the characteristic current Is can flow out from the output terminal to the low bias voltage VSS via the first transistor TR1. When the characteristic current IS has a negative level (for example, when the current flows out towards the pixel P), the characteristic current Is can flow out from the high bias voltage VDD via the third transistor TR3 and out through the output terminal.

[0067] The integrating circuit 420 can integrate the current flowing into the second transistor TR2 or the fourth transistor TR4. The second transistor TR2 can be connected to the low bias voltage VSS on one side and to the fourth node N4 as a mirror terminal on the other side. The fourth transistor TR4 can be connected to the high bias voltage VDD on one side and to the fourth node N4 as a mirror terminal on the other side.

[0068] The integrating circuit 420 can be connected to the mirror terminal (the fourth node N4) of the amplifying circuit 410, rather than its output terminal. The integrating circuit 420 can integrate the current formed in the mirror terminal (the fourth node N4). Since the current formed in the mirror terminal has a level proportional to or the same as the level of the current formed in the output terminal, the integrating circuit 420 can generate an integrated voltage of the characteristic current Is as the sensing voltage Vi. However, since the pixel P is only connected to the output terminal of the first operational amplifier AP1 and is separated from the mirror terminal, the integrating circuit 420 is hardly affected by the sensing line SL.

[0069] The integrating circuit 420 can include a second operational amplifier AP2, and also includes an integrating capacitor Ci disposed between the first input terminal and the output terminal of the second operational amplifier AP2. The first input terminal of the second operational amplifier AP2 can be connected to the fifth node N5, and the fifth node N5 can be connected to the fourth node N4 which is the mirror terminal of the fifth node N5.

[0070] The second reference voltage Vpre2 can be connected to the sixth node N6 which is connected to the second input terminal of the second operational amplifier AP2. Since the second operational amplifier AP2 has a very high amplification gain, the voltages formed in the second input terminal and the first input terminal can be substantially the same, and when the second reference voltage Vpre2 is supplied to the sixth node N6, the fifth node N5 can maintain the second reference voltage Vpre2 as its voltage. Therefore, the voltage formed in the third node N3 and the voltage formed in the fourth node N4 can be the same. Here, the second reference voltage Vpre2 can have the same voltage level as the voltage level of the first reference voltage Vpre1, or they can have different levels.

[0071] The integrating capacitor Ci can be connected to the fifth node N5 on one side and to the seventh node on the other side. The output terminal of the second operational amplifier AP2 can be connected to the seventh node N7.

[0072] The current flowing into the second transistor TR2 or the fourth transistor TR4 can increase the voltage of the integrating capacitor Ci while flowing along the path through the fifth node N5, the integrating capacitor Ci, and the seventh node N7. The voltage formed in the seventh node N7 according to the voltage of the integrating capacitor Ci can be transmitted to the sample-and-hold circuit or the analog-to-digital conversion circuit.

[0073] The first transistor TR1 and the second transistor TR2 can form an N:1 current mirror circuit (N is a positive real number). Therefore, the current flowing into the second transistor TR2 can be 1 / N times the amount of current flowing into the first transistor TR1.

[0074] The third transistor TR3 and the fourth transistor TR4 can form an N:1 current mirror circuit (N is a positive real number). Therefore, the current flowing into the fourth transistor TR4 can be 1 / N times the level of the current flowing into the third transistor TR3.

[0075] When the amount of current flowing into the second transistor TR2 or the fourth transistor TR4 decreases, the amount of current flowing into the integration capacitor Ci can also decrease. Therefore, the capacitance of the integration capacitor Ci can be set small.

[0076] Figure 5 is a diagram showing the internal structure of the amplifier circuit.

[0077] Reference Figure 5 , in the amplifier circuit 410, multiple transistors can be used to form the first operational amplifier AP1. The first transistor TR1 and the third transistor TR3 can be connected to the output terminal of the first operational amplifier AP1 connected to the third node N3. The second transistor TR2 sharing the gate voltage with the first transistor TR1 can be arranged between the fourth node N4 and the low bias voltage VSS, and the fourth transistor TR4 sharing the gate voltage with the third transistor TR3 can be arranged between the fourth node N4 and the high bias voltage VDD. Due to this structure, the amplifier circuit 410 can output a current having a level proportional to or the same as the level of the characteristic current of the pixel input or output through the third node N3 through the fourth node N4 separated from the third node N3.

[0078] Figure 6 is a diagram showing Figure 4 the change over time of the differential voltage corresponding to the difference between the sensed voltage and the reference voltage.

[0079] Reference Figure 4 and Figure 6 , the analog front-end circuit 310 can operate differently in the standby time interval T1 and the integration time interval T2. The analog front-end circuit 310 does not receive the characteristic current Is in the standby time interval T1. Therefore, no current flows in the integration capacitor Ci, and the voltages across both ends of the integration capacitor Ci can be the same. The differential voltage ΔVi corresponding to the difference between the sensed voltage Vi and the second reference voltage Vpre2 can be the same as the voltage across both ends of the integration capacitor Ci. Therefore, the differential voltage ΔVi in the standby time interval T1 can be 0.

[0080] During the integration time interval T2, the analog front-end circuit 310 may receive the characteristic current Is from the pixel P. Here, in the integration capacitor Ci, a current at a level that is 1 / N times the level of the characteristic current Is flows from the seventh node N7 to the fifth node N5, and the voltage across the integration capacitor Ci (i.e., the differential voltage ΔVi) may increase in the positive direction. The differential voltage ΔVi and the characteristic current Is may have the relationship represented by Equation 1.

[0081] [Equation 1]

[0082] ΔVi(t) = (Is / N)·t (where t is time)

[0083] The analog front-end circuit 310 may integrate the integration capacitor Ci with a current at a level that is 1 / N times the level of the characteristic current Is, and output the correlated voltage as the sensed voltage Vi.

[0084] The sample-and-hold circuit, the amplifier circuit, and the analog-to-digital conversion circuit may generate a digital signal corresponding to the sensed voltage Vi, and the data transmission circuit may collect digital signals from each channel, generate sensed data, and transmit the sensed data to the data processing circuit.

[0085] The data processing circuit may use the sensed data to compensate the image data, and transmit the compensated image data to the data driving circuit. The data driving circuit may use the compensated image data to display an image on the panel.

[0086] According to the present invention, the load effect of the sensing line of the pixel sensing device can be minimized, the sensing accuracy of the pixel sensing device can be improved, and the performance of the pixel sensing device can be improved.

[0087] Cross - Reference to Related Applications

[0088] This application claims the priority of Korean Patent Application No. 10-2019-0172592, filed on December 23, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A pixel sensing device, comprising: An analog front-end circuit, which includes an amplification circuit and an integration circuit. The amplification circuit includes an operational amplifier formed with a first input terminal, a second input terminal, and an output terminal, a first transistor connected to the output terminal of the operational amplifier, and a second transistor forming a current mirror circuit with the first transistor. Wherein, a characteristic current is transmitted from a pixel through a sensing line through the first input terminal, the first input terminal is connected to the pixel and the output terminal, and the integration circuit is configured to integrate the current flowing into the second transistor; An analog-to-digital conversion circuit for generating sensing data corresponding to the voltage output from the integration circuit; and A data transmission circuit for transmitting the sensing data to an external device, wherein the amplification circuit is located between the pixel and the integration circuit.

2. The pixel sensing device according to claim 1, wherein, The current flowing from the first input terminal to the output terminal flows into the first transistor.

3. The pixel sensing device according to claim 1, wherein, The amplification circuit further includes a third transistor and a fourth transistor. The current output through the output terminal of the operational amplifier flows through the third transistor, the fourth transistor forms a current mirror circuit with the third transistor, and the integration circuit integrates the current flowing into the second transistor or the current flowing into the fourth transistor.

4. The pixel sensing device according to claim 1, wherein The first transistor is connected to a low bias voltage on one side and to the output terminal on the other side, the second transistor is connected to the low bias voltage on one side and to a mirror terminal on the other side, and the integration circuit is connected to the mirror terminal.

5. The pixel sensing device according to claim 1, wherein, The first transistor and the second transistor form an N:1 current mirror circuit, and the level of the current flowing into the second transistor is 1 / N times the level of the current flowing into the first transistor, where N is a positive real number.

6. The pixel sensing device according to claim 1, wherein A reference voltage is connected to the second input terminal, and the operational amplifier forms the reference voltage at the first input terminal.

7. The pixel sensing device according to claim 1, wherein The integration circuit includes another operational amplifier. Wherein, this operational amplifier is connected to the second transistor at one of its input terminals and to a reference voltage at the other input terminal, and an integration capacitor is arranged between this one input terminal and this other input terminal of this operational amplifier.

8. The pixel sensing device according to claim 1 further comprises: A sample-and-hold circuit for temporarily storing the voltage output from the integration circuit; and another amplification circuit for amplifying the voltage output from the sample-and-hold circuit and transmitting the amplified voltage to the analog-to-digital conversion circuit.

9. A panel driving device for driving a panel on which a plurality of pixels are arranged and a plurality of data lines and a plurality of sensing lines are arranged. The panel driving device includes: A data driving circuit for converting image data into a data voltage and supplying the data voltage through the data lines; A pixel sensing circuit for generating sensing data corresponding to an integrated voltage of a characteristic current transmitted from a pixel; and A data processing circuit for compensating the image data using the sensing data, Among them, in the pixel sensing circuit, the characteristic current is input through the output terminal of the operational amplifier, and the integration voltage is formed by integrating the current of a second transistor arranged in the operational amplifier by an integration circuit. The second transistor is used to form a current mirror circuit with a first transistor in the operational amplifier, and wherein, the operational amplifier is located between the pixel and the integration circuit.

10. The panel driving device according to claim 9, wherein, The first transistor and the second transistor form an N:1 current mirror circuit, and the level of the current flowing into the second transistor is 1 / N times the level of the current flowing into the first transistor, where N is a positive real number.

11. The panel driving device according to claim 9, wherein, The integration circuit for integrating the current of the second transistor includes another operational amplifier.

12. The panel driving device according to claim 9, wherein, The pixel sensing circuit includes: a sample and hold circuit for temporarily storing the integration voltage; an amplification circuit for amplifying the signal output from the sample and hold circuit; and an analog-to-digital conversion circuit for converting the signal output from the amplification circuit into sensing data.

13. The panel driving device according to claim 9, wherein, The pixel includes an organic light emitting diode.

14. The panel driving device according to claim 13, wherein, The pixel sensing circuit is connected to a contact node between the organic light emitting diode and a driving transistor for supplying a driving current to the organic light emitting diode, and receives the current flowing into the driving transistor or the current flowing into the organic light emitting diode as the characteristic current.

15. The panel driving device according to claim 14, wherein, Compensate the characteristics of the driving transistor according to the characteristic current.

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