Semiconductor structure and method for forming the same

Abstract

In one embodiment, a structure includes: a first integrated circuit die including a first die connector; a first dielectric layer located on the first die connector; a first conductive via extending through the first dielectric layer, the first conductive via connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors using a first reflowable connector; a first encapsulant surrounding the second integrated circuit die and the first conductive via, the first encapsulant and the first integrated circuit die being laterally adjacent; a second conductive via adjacent to the first integrated circuit die; a second encapsulant surrounding the second conductive via, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including a first redistribution line, the first redistribution line connected to the first conductive via and the second conductive via. Embodiments of the present application also provide a method of forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application provide a semiconductor structure and a method for forming the same. Background Art

[0002] As semiconductor technology continues to develop, integrated circuit dies are becoming smaller and smaller. In addition, more functions are integrated into the die. As a result, the number of input / output (I / O) pads required for the die has increased, while the area available for the I / O pads has decreased. Over time, the density of I / O pads has increased rapidly, increasing the difficulty of chip packaging. Some applications require greater parallel processing capabilities of integrated circuit dies. Packaging technology can be used to integrate multiple dies, allowing for a greater degree of parallel processing capabilities.

[0003] In some packaging technologies, the integrated circuit die is separated from the wafer before it is packaged. An advantageous feature of this packaging technology is that a fan-out package can be formed, which allows the I / O pads on the die to be redistributed to a larger area. The number of I / O pads on the die surface can thus be increased. Summary of the invention

[0004] In one embodiment, a structure includes: a first integrated circuit die, including a first die connector; a first dielectric layer, located on the first die connector; a first conductive via, extending through the first dielectric layer, the first conductive via connected to a first subset of the first die connectors; a second integrated circuit die, bonded to a second subset of the first die connectors using a first reflowable connector; a first sealant, surrounding the second integrated circuit die and the first conductive via, the first sealant and the first integrated circuit die being laterally adjacent; a second conductive via, adjacent to the first integrated circuit die; a second sealant, surrounding the second conductive via, the first sealant, and the first integrated circuit die; and a first redistribution structure, including a first redistribution line, the first redistribution line being connected to the first conductive via and the second conductive via.

[0005] In one embodiment, a structure includes: a first integrated circuit die, including a post-passivation interconnect (PPI); a dielectric layer, located on the post-passivation interconnect; a first conductive via, extending through the dielectric layer, the first conductive via connected to the post-passivation interconnect; a second integrated circuit die, including a semiconductor substrate and a die connector, the semiconductor substrate being bonded to the dielectric layer using an adhesive; a first encapsulant, surrounding the second integrated circuit die and the first conductive via, the first encapsulant and the first integrated circuit die being laterally adjacent; a second conductive via, adjacent to the first integrated circuit die; a second encapsulant, surrounding the second conductive via, the first encapsulant, and the first integrated circuit die; a first redistribution structure, including a first redistribution line, the first redistribution line being connected to the first conductive via, the die connector, and the second conductive via.

[0006] In one embodiment, a method includes: forming a first conductive via on a first integrated circuit die; bonding a second integrated circuit die to the first integrated circuit die using a first reflowable connector, the second integrated circuit die being adjacent to the first conductive via; sealing the first conductive via and the second integrated circuit die using a first molding compound; singulating the first molding compound and the first integrated circuit die to form a die stack; placing the die stack adjacent to a second conductive via; sealing the second conductive via and the die stack using a second molding compound; and forming a first redistribution structure on the second molding compound and the die stack, the first redistribution structure including a first redistribution line connected to the first conductive via and the second conductive via.

[0007] Embodiments of the present application provide an integrated circuit package and method. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 ,and Figure 8 is a cross-sectional view of an intermediate step during a process for forming a die stack according to some embodiments;

[0010] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 ,and Fig.18A is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package implementing a die stack according to some embodiments;

[0011] Fig.18B is a cross-sectional view of an integrated circuit package implementing a die stack according to some further embodiments;

[0012] Fig.19 , Fig. 20 , Fig.21 ,and Fig. 22is a cross-sectional view of an intermediate step during a process for forming a die stack according to some further embodiments;

[0013] Fig.23A is a cross-sectional view of an integrated circuit package implementing a die stack according to some further embodiments;

[0014] Fig. 23B is a cross-sectional view of an integrated circuit package implementing a die stack according to some further embodiments;

[0015] Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 ,and Fig.29 is a cross-sectional view of an intermediate step during a process for forming a die stack according to some further embodiments;

[0016] Fig.30 is a cross-sectional view of an integrated circuit package implementing a die stack according to some further embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0018] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] According to some embodiments, a die stack including a plurality of integrated circuit dies is formed. The die stack is formed by stacking the dies in a face-to-face or back-to-back manner. The integrated circuit dies of the die stack can be bonded with a reflowable connector or an adhesive. Such bonding techniques may not allow for a die connector pitch as fine as other bonding techniques such as hybrid bonding or the same number of input / output (I / O) connectors, but such bonding techniques allow bonding to be implemented at a lower cost. When the die stack is a low-performance device, it may be particularly desirable to form the die stack at a low cost. The resulting die stack can be, for example, a system on integrated circuit (SoIC) device. Once formed, the SoIC device can be incorporated into an integrated circuit package.

[0020] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 ,and Figure 8 1 is a cross-sectional view of an intermediate step during a process for forming a die stack 100 according to some embodiments. The die stack 100 is formed by stacking integrated circuit dies on a wafer 102. The stacking of integrated circuit dies in one device region 102A of the wafer 102 is shown, but it should be understood that the wafer 102 may have any number of device regions and integrated circuit dies may be stacked to form a die stack in each device region. The integrated circuit dies of the die stack 100 are directly bonded in a face-to-face manner using reflowable connectors.

[0021] exist Figure 1 In the process, a wafer 102 is formed or obtained. The wafer 102 includes a first integrated circuit die 110 in a device area 102A. The first integrated circuit die 110 will be singulated in a subsequent process to be incorporated into the die stack 100. The first integrated circuit die 110 can be any acceptable processor or logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), an arithmetic logic unit (ALU), a system on a chip (SoC), an application processor (AP), an image signal processor (ISP), a digital signal processing (DSP), a field programmable gate array (FPGA), a microcontroller, an artificial intelligence (AI) accelerator, etc.

[0022] The first integrated circuit die 110 is processed according to an applicable manufacturing process to form an integrated circuit. For example, the first integrated circuit die 110 includes a semiconductor substrate 112, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 112 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The semiconductor substrate 112 has an active surface 112A and an inactive surface 112N.

[0023] Devices are formed on the active surface 112A of the semiconductor substrate 112. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The passive surface 112N is located on the back side 110B of the first integrated circuit die 110, and may be free of devices. An interconnect structure is formed on the active surface 112A of the semiconductor substrate 112. The interconnect structure interconnects the devices at the active surface 112A of the semiconductor substrate 112 to form an integrated circuit. The interconnect structure may be formed, for example, by a metallization pattern in a dielectric layer, and may be formed by a damascene process such as a single damascene process, a dual damascene process, etc. The metallization pattern includes metal lines and vias formed in one or more dielectric layers. The metallization pattern of the interconnect structure is electrically connected to the devices at the active surface 112A of the semiconductor substrate 112.

[0024] Contact pads 116 are also formed over active surface 112A of semiconductor substrate 112. Contact pads 116 may be aluminum pads, copper pads, etc., and may be formed, for example, by plating, deposition, etc. A dielectric layer 118 is formed around contact pads 116. Dielectric layer 118 may be: a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymer, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; etc.; or a combination thereof. Dielectric layer 118 may be formed, for example, by spin coating, lamination, deposition, etc. Contact pads 116 and dielectric layer 118 may be part of an interconnect structure, for example, part of the topmost layer of an interconnect structure.

[0025] One or more passivation layers 120 are formed on the contact pads 116 and the semiconductor substrate 112. The passivation layer(s) 120 may be formed of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimide, solder resist, PBO, BCB-based polymers, molding compounds, etc., or combinations thereof. The passivation layer(s) 120 may be formed by spin coating, lamination, deposition, etc., or combinations thereof.

[0026] The die connector 122 is formed on a corresponding one of the contact pads 116 and is exposed on the front side 110F of the first integrated circuit die 110. The die connector 122 may be a conductive column, a bump, a via, etc., and may be formed by a metal such as copper. The die connector 122 is connected (e.g., physically and electrically connected) to a corresponding one of the contact pads 116 and is electrically connected to the corresponding integrated circuit of the first integrated circuit die 110. As an example for forming the die connector 122, an opening is formed in (some) of the passivation layer 120, and a seed layer is formed along (some) of the passivation layer 120 and in the opening through (some) of the passivation layer 120. The opening may be formed by acceptable photolithography and etching techniques. In some embodiments, the seed layer is a metal layer, which may be a single layer, or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a copper layer above a titanium layer and a titanium layer. The seed layer may be formed by deposition such as PVD. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to the tube core connector 122. Patterning forms an opening through the photoresist, thereby exposing the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include a metal, such as copper, nickel, titanium, tungsten, aluminum, etc. In some embodiments, the conductive material can be a composite layer including a plurality of sublayers formed by different materials. For example, the conductive material can include a nickel layer between two copper layers. The photoresist can be removed by an acceptable ashing process or a stripping process such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer can be removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the tube core connector 122.

[0027] Then, a circuit probe (CP) test is performed on the first integrated circuit die 110 to find out whether the first integrated circuit die 110 is a known good die (KGD). The first integrated circuit die 110 is tested by using a probe. The probe is connected to the die connector 122 through, for example, a reflowable connector. Only the integrated circuit dies that are KGDs are subsequently processed and packaged, while the integrated circuit dies that fail the CP test are not packaged. The test may include a test of the functionality of the first integrated circuit die 110, or may include a test of a known open circuit or short circuit that can be expected based on the design of the first integrated circuit die 110. After the test is completed, the probe is removed, and any excess reflowable material on the die connector 122 may be removed by, for example, an etching process, chemical mechanical polishing (CMP), a grinding process, etc.

[0028] exist Figure 2 In the embodiment, dielectric layer 130 is formed on wafer 102, for example, on die connector 122 and passivation layer(s) 120. In some embodiments, dielectric layer 130 is formed of a polymer such as polyimide, PBO, BCB-based polymer, etc. In other embodiments, dielectric layer 130 is formed of an oxide such as silicon oxide, PSG, BSG, BPSG, etc. and a nitride such as silicon nitride, etc. Dielectric layer 130 may be formed by any acceptable deposition process such as spin coating, CVD, lamination, etc., or a combination thereof.

[0029] Then, the dielectric layer 130 is patterned to form an opening 132 that exposes a portion of the die connector 122. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 130 to light when the dielectric layer 130 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 130 is a photosensitive material, the dielectric layer 130 can be developed after exposure.

[0030] A first subset of die connectors 122A is exposed through a subset of openings 132A. Each opening 132A exposes a corresponding die connector 122A. As discussed further below, a conductive via will be formed in each opening 132A and connected to a corresponding die connector 122A. A second subset of die connectors 122B is exposed through openings 132B. Specifically, openings 132B expose a plurality of die connectors 122B. As discussed further below, an integrated circuit die will be placed in openings 132B and connected to die connectors 122B. Openings 132B are wider than each opening 132A. For example, openings 132A may each have a width in the range of about 10 μm to about 15 μm, while openings 132B may have a width in the range of about 3000 μm to about 6000 μm. Wider openings 132B help accommodate integrated circuit dies.

[0031] exist Figure 3 132A, a conductive via 134 is formed in the opening 132A, extending through the dielectric layer 130 and away from the wafer 102. The conductive via 134 is connected to the die connector 122A. As an example for forming the conductive via 134, a seed layer is formed above the dielectric layer 130, and a portion of the die connector 122A is exposed through the opening 132A. In some embodiments, the seed layer is a metal layer, which can be a single layer, or can be a composite layer including multiple sublayers formed by different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to the conductive via. Patterning forms an opening through the photoresist, thereby exposing the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing process or a stripping process such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer may be removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms a conductive via 134. The conductive via 134 may be formed, for example, at a pitch in the range of about 40 μm to about 80 μm.

[0032] exist Figure 4 In some embodiments, the second integrated circuit die 140 is formed or obtained. The second integrated circuit die 140 has several possible functions and has a different function from the first integrated circuit die 110. In some embodiments, the second integrated circuit die 140 is an analog device die, such as a power gating die, a power management integrated circuit (PMIC), etc. In some embodiments, the second integrated circuit die 140 is an input / output (I / O) die, such as an interface die, a through substrate via (TSV) die, etc. In some embodiments, the second integrated circuit die 140 is a memory die, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a resistive random access memory (RRAM) die, a magnetoresistive random access memory (MRAM) chip, a phase change random access memory (PCRAM) die, etc. In some embodiments, the second integrated circuit die 140 is another processor or logic device, such as a GPU, a DSP, etc.

[0033] The second integrated circuit die 140 may be formed in a wafer that may include different device regions that are singulated in a subsequent step to form a plurality of integrated circuit dies. When the second integrated circuit die 140 includes active devices, it may be a larger technology node than the first integrated circuit die 110. The second integrated circuit die 140 is processed according to an applicable manufacturing process to form an integrated circuit. For example, the second integrated circuit die 140 includes a semiconductor substrate 142, a contact pad 146, a dielectric layer 148, one or more passivation layers 150, and a die connector 152, which are similar to the semiconductor substrate 112, contact pad 116, dielectric layer 118, (some) passivation layer 120, and die connector 122 of the first integrated circuit die 110, respectively. The die connector 152 is exposed on the front side 140F of the second integrated circuit die 140. After the second integrated circuit die 140 is singulated, the semiconductor substrate 142, the dielectric layer 148, and (some) passivation layer 150 are laterally adjacent. The second integrated circuit die 140 also includes a conductive via 154 formed to extend into the semiconductor substrate 142. The conductive via 154 is electrically connected to devices of the semiconductor substrate 142, such as through a metallization pattern of an interconnect structure.

[0034] As an example for forming the conductive via 154, a recess may be formed in the semiconductor substrate 142 by, for example, etching, milling, laser technology, a combination thereof, and / or the like. A thin dielectric material may be formed in the recess, for example, by using an oxidation technique. A thin barrier layer may be conformally deposited in the opening, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and / or the like. The barrier layer may be formed by an oxide, nitride, or oxynitride such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, a combination thereof, and / or the like. A conductive material may be deposited over the barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, and / or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like. Excess conductive material and barrier layer are removed from the surface of the semiconductor substrate 142 by, for example, CMP. The remaining portions of the barrier layer and the conductive material form conductive vias 154 .

[0035] According to some embodiments, the conductive via 154 has not yet been exposed at the back side 140B of the second integrated circuit die 140. Instead, the conductive via 154 is buried in the semiconductor substrate 142. As discussed further below, the conductive via 154 will be exposed at the back side 140B of the second integrated circuit die 140 by an exposure process in a subsequent process. After exposure, the conductive via 154 may be referred to as a TSV.

[0036] exist Figure 5In the embodiment of the present invention, the second integrated circuit die 140 is placed in the opening 132B and bonded to the first integrated circuit die 110 (e.g., wafer 102). The first integrated circuit die 110 and the second integrated circuit die 140 can be directly bonded in a face-to-face manner using a reflowable connector 160, so that the front side 110F of the first integrated circuit die 110 is bonded to the front side 140F of the second integrated circuit die 140. The reflowable connector 160 can be a ball grid array (BGA) connector, a solder ball, etc. The reflowable connector 160 can be formed by a metal or metal alloy such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the reflowable connector 160 is formed by first forming a solder layer by methods such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc. The reflowable connector 160 can be first formed on the die connector 122B or on the die connector 152. Once the solder layer is formed, reflow can be implemented to shape the material into the desired bump shape. The first integrated circuit die 110 and the second integrated circuit die 140 are bonded by contacting the reflowable connector 160 to the die connector 122B and the die connector 152, and reflowing the reflowable connector 160. After reflow, the die connector 122B is connected to the die connector 152. Using the reflowable connector 160 to bond the first integrated circuit chip 110 and the second integrated circuit chip 140 may allow bonding to be performed at a lower cost than other bonding techniques such as hybrid bonding.

[0037] Before the reflowable connector 160 is reflowed, the reflowable connector 160 may have a flux (not shown) formed thereon. In some embodiments, after the reflowable connector 160 is reflowed, the flux is removed using a flux cleaning process. An underfill 162 is optionally formed between the first integrated circuit die 110 and the second integrated circuit die 140, surrounding the reflowable connector 160. The underfill 162 may be formed by a capillary flow process after the first integrated circuit die 110 and the second integrated circuit die 140 are joined, or may be formed by a suitable deposition method before the first integrated circuit die 110 and the second integrated circuit die 140 are joined. The underfill 162 fills the opening 132B, may extend along the sidewalls of the second integrated circuit die 140, and may extend along a portion of the top surface of the dielectric layer 130.

[0038] exist Figure 6In the embodiment of the present invention, the sealant 164 is formed on and around the conductive vias 134 and the second integrated circuit die 140. After formation, the sealant 164 seals the conductive vias 134 and the second integrated circuit die 140. The sealant 164 can be a molding compound, an epoxy resin, etc. The sealant 164 can be applied by compression molding, transfer molding, etc., and can be formed above the wafer 102, so as to bury or cover the conductive vias 134 and / or the second integrated circuit die 140. The sealant 164 can be applied in the form of a fluid or a semi-fluid and then cured. As described above, the bottom filler 162 is optional. When the bottom filler 162 is omitted, the sealant 164 can surround and physically contact the sidewalls of each die connector 122B, the die connector 152, and the reflowable connector 160. In addition, when the bottom filler 162 is omitted, the sealant 164 can extend through the dielectric layer 130.

[0039] exist Figure 7 In the embodiment of the present invention, a planarization process is performed on the encapsulant 164 to expose the conductive via 134 and the back side 140B of the second integrated circuit die 140. The planarization process can remove the material of the encapsulant 164, the conductive via 134, and / or the semiconductor substrate 142 until the conductive via 134 and the back side 140B of the second integrated circuit die 140 are exposed. After the planarization process, the top surface of the planarized component is coplanar. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc.

[0040] In some embodiments, the planarization process includes thinning the semiconductor substrate 142, which helps to more easily expose the conductive vias 154 at the back side 140B of the second integrated circuit die 140 in subsequent processing. The thinning process can be, for example, chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc. Even when the semiconductor substrate 142 is thinned in this processing step, the conductive vias 154 are still buried in the semiconductor substrate 142. After the planarization process, the sealant 164 and the dielectric layer 130 can have a combined thickness, for example, in the range of about 30 μm to about 50 μm, for example, about 50 μm.

[0041] Optionally, the semiconductor substrate 112 may be thinned, which helps reduce the overall thickness of the die stack 100. The thinning process may be, for example, chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc., which may be performed on the back side 110B of the first integrated circuit die 110. After the thinning process, the semiconductor substrate 112 may have a thickness, for example, in the range of about 100 μm to about 150 μm, for example, about 130 μm.

[0042] exist Figure 8102A, a singulation process is performed by sawing along the scribe line areas (e.g., the area surrounding the device area 102A). The singulation process includes sawing the wafer 102, the dielectric layer 130, and the encapsulant 164. The singulation process separates the device area 102A (including the first integrated circuit die 110) from the adjacent device area (not shown) of the wafer 102 to form a die stack 100 including the first integrated circuit die 110. After singulation, the semiconductor substrate 112, the dielectric layer 118, (some) passivation layers 120, the dielectric layer 130, and the encapsulant 164 are laterally adjacent.

[0043] The adhesive 168 is formed on the back side 110B of the first integrated circuit die 110. As discussed further below, the adhesive 168 will be used to bond the die stack 100 to another component in a subsequent process. The adhesive 168 can be any suitable adhesive, epoxy, die attach film (DAF), etc. In the illustrated embodiment, the adhesive 168 is applied to the back side 110B of the first integrated circuit die 110 (see FIG. 1 ) prior to singulation to separate the first integrated circuit die 110. Figure 7 ). In another embodiment, adhesive 168 is not applied until a subsequent processing step.

[0044] After singulation, the die stack 100 may be placed, for example, on a tape 166. After applying adhesive 168 to the back side 110B of the first integrated circuit die 110 (see Figure 7 ), adhesive 168 may be used to bond the die stack 100 to the tape 166 .

[0045] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 ,and Fig.18A 2 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package implementing a die stack 100 according to some embodiments. The die stack 100 is packaged in an integrated circuit package 200. The packaging of the device in one packaging area 202A is shown, but it should be understood that any number of packaging areas can be formed simultaneously. The packaging area 202A will be singulated in a subsequent process. The singulated integrated circuit package 200 can be a fan-out package, such as an integrated fan-out (InFO) package. The individual integrated circuit packages 200 are then mounted on a packaging substrate to form a complete system.

[0046] exist Fig. 9In the embodiment, a carrier substrate 202 is provided, and a peeling layer 204 is formed on the carrier substrate 202. The carrier substrate 202 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 202 may be a wafer so that a plurality of packages may be formed on the carrier substrate 202 at the same time. The peeling layer 204 may be formed by a polymer-based material, which may be removed from an overlying structure to be formed in a subsequent step together with the carrier substrate 202. In some embodiments, the peeling layer 204 is an epoxy-based thermal isolation material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) peeling coating. In other embodiments, the peeling layer 204 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The peeling layer 204 may be dispensed in the form of a liquid and cured, may be a laminated film laminated to the carrier substrate 202, or may be the like. The top surface of the peeling layer 204 may be horizontal and may have a high degree of flatness.

[0047] A backside redistribution structure 206 may be optionally formed on the release layer 204. In the embodiment shown, the backside redistribution structure 206 includes a dielectric layer 208, a metallization pattern 210 (sometimes referred to as a redistribution layer or redistribution line), and a dielectric layer 212. The backside redistribution structure 206 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer 204 instead of the backside redistribution structure 206.

[0048] The dielectric layer 208 is formed on the lift-off layer 204. The bottom surface of the dielectric layer 208 may be in contact with the top surface of the lift-off layer 204. In some embodiments, the dielectric layer 208 is formed of a polymer such as PBO, polyimide, a BCB-based polymer, etc. In other embodiments, the dielectric layer 208 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), etc., or the like. The dielectric layer 208 may be formed by any acceptable deposition process such as spin coating, CVD, lamination, etc., or a combination thereof.

[0049] Metallization pattern 210 is formed on dielectric layer 208. As an example for forming metallization pattern 210, seed layer is formed above dielectric layer 208. In some embodiments, seed layer is a metal layer, which can be a single layer, or can be a composite layer including multiple sublayers formed by different materials. In some embodiments, seed layer includes a titanium layer and a copper layer above the titanium layer. Seed layer can be formed using, for example, physical vapor deposition (PVD) and the like. Then, photoresist is formed and patterned on seed layer. Photoresist can be formed by spin coating and the like, and can be exposed for patterning. The pattern of photoresist corresponds to metallization pattern 210. Patterning forms an opening through photoresist, thereby exposing seed layer. Conductive material is formed in the opening of photoresist and on the exposed portion of seed layer. Conductive material can be formed by plating such as electroplating or chemical plating. Conductive material can include metal, such as copper, titanium, tungsten, aluminum, etc. Then, remove the portion where conductive material is not formed on photoresist and seed layer. The photoresist may be removed by an acceptable ashing process or a stripping process such as using an oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer may be removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization pattern 210.

[0050] The dielectric layer 212 is formed on the metallization pattern 210 and the dielectric layer 208. In some embodiments, the dielectric layer 212 is formed by a polymer, which can be a photosensitive material, such as PBO, polyimide, BCB, etc., which can be patterned using a photolithography mask. In other embodiments, the dielectric layer 212 is formed by a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 212 can be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0051] It should be understood that the backside redistribution structure 206 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, the above steps and processes may be repeated. The metallization pattern may include conductive wires and conductive vias. Conductive vias may be formed during the formation of the metallization pattern by forming the conductive material of the seed layer and the metallization pattern in the opening of the underlying dielectric layer. Thus, the conductive vias may interconnect and electrically connect the various conductive wires.

[0052] exist Fig.10In the embodiment of the present invention, a conductive via 220 is formed, which extends through the topmost dielectric layer (e.g., dielectric layer 212) of the back redistribution structure 206 and away from the carrier substrate 202. The conductive via 220 is connected to the topmost metallization pattern (e.g., metallization pattern 210) of the back redistribution structure 206. The conductive via 220 is optional and can be omitted as further discussed below. For example, in an embodiment where the back redistribution structure 206 is omitted, the conductive via 220 may (or may not) be omitted. As an example of forming the conductive via 220, the dielectric layer 212 may be patterned to form an opening that exposes a portion of the metallization pattern 210. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer 212 to light when the dielectric layer 212 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 212 is a photosensitive material, the dielectric layer 212 may be developed after exposure. Then, a seed layer is formed above the dielectric layer 212, and a portion of the metallization pattern 210 is exposed through the opening. In some embodiments, the seed layer is a metal layer, which can be a single layer, or can be a composite layer including multiple sublayers formed by different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to a conductive via. Patterning forms an opening through the photoresist, thereby exposing the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The portion where the conductive material is not formed on the photoresist and the seed layer is removed. The photoresist can be removed by an acceptable ashing process or a stripping process such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer may be removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the conductive via 220.

[0053] The singulated die stack 100 is then placed adjacent to the conductive via 220. The die stack 100 may be placed on the backside redistribution structure 206 (e.g., dielectric layer 212) when the backside redistribution structure 206 is formed, or may be placed on the peeling layer 204 when the backside redistribution structure 206 is omitted. The adhesive 168 is used to bond the singulated die stack 100 to the underlying layer (e.g., dielectric layer 212 or peeling layer 204). In embodiments where the adhesive 168 is not applied to the backside 110B of the first integrated circuit die 110, the adhesive 168 is alternatively applied over a surface of the carrier substrate 202, such as on the dielectric layer 212 or peeling layer 204.

[0054] exist Fig.11 In the embodiment of the present invention, sealant 222 is formed on and around each component. After formation, sealant 222 seals conductive via 220 and die stack 100. Sealant 222 can be a molding compound, epoxy resin, etc. Sealant 222 can be applied by compression molding, transfer molding, etc., and sealant 222 is formed above carrier substrate 202, thereby burying or covering conductive via 220 and / or die stack 100. Sealant 222 can be applied in the form of a fluid or semi-fluid and then cured. In some embodiments, sealants 164 and 222 include different molding materials. For example, sealant 222 can be formed by molding compound, while sealant 164 can be formed by molding bottom filler (e.g., a molding material having a filler of smaller size than the molding material used for sealant 222).

[0055] Fig.12 , Fig.13 ,and Fig.14 It is shown that a planarization process can be performed on the encapsulant 222 and the die stack 100 to expose the conductive vias 134, 154, 220. The planarization process removes material of the semiconductor substrate 142, the vias 134, 154, 220, and / or the encapsulant 164, 222 until the conductive vias 134, 154, 220 are exposed. After the planarization process, the top surfaces of the planarized components are coplanar. After planarization, the conductive via 134 extends through the encapsulant 164 (e.g., the conductive via 134 is a through via), and the conductive via 220 extends through the encapsulant 222 (e.g., the conductive via 220 is a through via). According to some embodiments, the planarization process includes a combination of grinding, etching, and CMP processes. Fig.12 , Fig.13 ,and Fig.14is an example of a planarization process that can be used to expose the conductive vias 134, 154, 220. It should be understood that other planarization processes can also be used. For example, other combinations of grinding, etching, and / or CMP processes can be used to expose the conductive vias 134, 154, 220.

[0056] exist Fig.12 In the process, the encapsulant 222 is ground to expose the die stack 100, such as the semiconductor substrate 142. One or more grinding processes may be performed, which may also (or may not) expose the conductive vias 220. The semiconductor substrate 142 may also be thinned in (some) of the grinding processes. Thinning the semiconductor substrate 142 in this processing step helps reduce the cost of exposing the conductive vias 154 in subsequent processing steps. In some embodiments, a first grinding process is performed to expose the semiconductor substrate 142, and a second grinding process is performed to thin the semiconductor substrate 142, wherein the second grinding process is performed at a removal rate less than the first grinding process. For example, the first grinding process may be performed using a first grinding head having a first surface roughness, and the second grinding process may be performed using a second grinding head having a second surface roughness, wherein the second surface roughness is less than the first surface roughness. Thinning the semiconductor substrate 142 at a slower removal rate helps avoid over-grinding that may damage the conductive vias 154.

[0057] exist Fig.13 In the embodiment, the encapsulant 222 and the semiconductor substrate 142 are ground to expose the conductive via 154. One or more grinding processes may be performed to also expose the conductive via 220 if the conductive via 220 is not already exposed. In some embodiments, a third grinding process is performed to thin the semiconductor substrate 142 and expose the conductive via 154, wherein the third grinding process is performed at a thickness less than about Fig.12 For example, the removal rates of the first and second grinding processes discussed can be used. Fig.12 The third grinding process can be performed using a grinding head having a surface roughness smaller than that of the grinding head used in the first and second grinding processes discussed. Continuing with the previous example, the third grinding process can be performed using a third grinding head having a third surface roughness, wherein the third surface roughness is smaller than that of the first and second grinding processes discussed. Fig.12 The first and second surface roughnesses discussed herein expose the conductive vias 154 at a slower removal rate, helping to avoid over-grinding that could damage the conductive vias 154 .

[0058] exist Fig.14In the embodiment of the present invention, a barrier layer 224 may be optionally formed around the conductive via 154. The barrier layer 224 helps to electrically isolate the conductive vias 154 from each other, thereby avoiding short circuits. As an example of forming the barrier layer 224, the semiconductor substrate 142 may be recessed to expose a sidewall portion of the conductive via 154. The recess may be performed by an etching process such as dry etching. Then a barrier material may be formed in the recess. The barrier material may be a dielectric material such as a low-temperature polyimide material, but any other suitable dielectric may also be utilized, such as PBO, a sealant, a combination thereof, and the like. A planarization process such as CMP, grinding, or etch-back may be implemented to remove excess portions of the barrier material above the semiconductor substrate 142. The remaining portion of the barrier material in the recess forms a barrier layer 224. After the barrier layer 224 is formed, it is laterally surrounded by the sealant 164.

[0059] exist Fig.15 , a front redistribution structure 240 is formed over the encapsulant 222, the conductive vias 220, and the die stack 100. The front redistribution structure 240 includes dielectric layers 242, 246, 250, 254 and metallization patterns 244, 248, 252. The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The front redistribution structure 240 is shown as an example having three layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the front redistribution structure 240. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0060] As an example of forming the front redistribution structure 240, a dielectric layer 242 can be deposited on the encapsulant 222, the conductive vias 220, and the die stack 100. The barrier layer 224 thus contacts the dielectric layer 242. In some embodiments, the dielectric layer 242 is formed by a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. The dielectric layer 242 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. Then, the dielectric layer 242 is patterned. The patterning forms an opening, thereby exposing a portion of the conductive vias 134, 154, 220. The patterning can be formed by an acceptable process, such as by exposing the dielectric layer 242 to light when the dielectric layer 242 is a photosensitive material, or by etching using anisotropic etching, etc. If the dielectric layer 242 is a photosensitive material, the dielectric layer 242 can be developed after exposure.

[0061] Then a metallization pattern 244 is formed. The metallization pattern 244 includes a trace portion (also referred to as a wire) located on the main surface of the dielectric layer 242 and extending along the main surface of the dielectric layer 242. The metallization pattern 244 also includes a via portion (also referred to as a conductive via) extending through the dielectric layer 242 to connect to the conductive vias 134, 154, 220. As an example for forming the metallization pattern 244, a seed layer is formed above the dielectric layer 242 and in an opening extending through the dielectric layer 242. In some embodiments, the seed layer is a metal layer, which can be a single layer, or can be a composite layer including a plurality of sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern 244. Patterning forms an opening through the photoresist, thereby exposing the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the portion below the seed layer forms a metallization pattern 244. The portion of the photoresist and the seed layer where the conductive material is not formed is removed. The photoresist can be removed by an acceptable ashing process or a stripping process such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer can be removed, for example, by using an acceptable etching process, such as by wet etching or dry etching.

[0062] Then, a dielectric layer 246 is deposited on the metallization pattern 244 and the dielectric layer 242. The dielectric layer 246 may be formed in a similar manner and with similar materials as the dielectric layer 242.

[0063] Then, metallization pattern 248 is formed. Metallization pattern 248 includes a trace portion located on and extending along the main surface of dielectric layer 246. Metallization pattern 248 also includes a via portion extending through dielectric layer 246 to connect to metallization pattern 244. Metallization pattern 248 can be formed in a similar manner and with similar materials as metallization pattern 244. In some embodiments, metallization pattern 248 has a different size from metallization pattern 244. For example, the wires and / or vias of metallization pattern 248 can be wider or thicker than the wires and / or vias of metallization pattern 244. In addition, metallization pattern 248 can be formed to have a larger pitch than metallization pattern 244.

[0064] Then, a dielectric layer 250 is deposited on the metallization pattern 248 and the dielectric layer 246. The dielectric layer 250 may be formed in a similar manner as the dielectric layer 242 and with similar materials.

[0065] Then, a metallization pattern 252 is formed. The metallization pattern 252 includes a trace portion located on and extending along the main surface of the dielectric layer 250. The metallization pattern 252 also includes a via portion extending through the dielectric layer 250 to connect to the metallization pattern 248. The metallization pattern 252 can be formed in a similar manner and with similar materials as the metallization pattern 244. The metallization pattern 252 is the topmost metallization pattern of the front redistribution structure 240. In this way, all the intermediate metallization patterns (e.g., metallization patterns 244 and 248) of the front redistribution structure 240 are disposed between the metallization pattern 252 and the die stack 100. In some embodiments, the metallization pattern 252 has a different size from the metallization patterns 244 and 248. For example, the wires and / or vias of the metallization pattern 252 can be wider or thicker than the wires and / or vias of the metallization patterns 244 and 248. In addition, the metallization pattern 252 can be formed to have a larger pitch than the metallization pattern 248.

[0066] Then, a dielectric layer 254 is deposited on the metallization pattern 252 and the dielectric layer 250. The dielectric layer 254 may be formed in a similar manner and with similar materials as the dielectric layer 242.

[0067] exist Fig.16 In the embodiment of the present invention, an under bump metallization layer (UBM) 256 is formed for external connection to the front redistribution structure 240. The UBM 256 has a bump portion located on and extending along the main surface of the dielectric layer 254, and has a via portion extending through the dielectric layer 254 to connect to the metallization pattern 252. As a result, the UBM 256 is electrically connected to the conductive vias 134, 154, 220. The UBM 256 can be formed of a material similar to the metallization pattern 244. In some embodiments, the UBM 256 has a different size than the metallization patterns 244, 248, 252.

[0068] Then, a conductive connector 258 is formed on the UBM 256. The conductive connector 258 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel-chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 258 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 258 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into the desired bump shape. In another embodiment, the conductive connector 258 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0069] One or more integrated passive devices (IPDs) 260 are optionally connected to the UBM 256 using a subset of the conductive connectors 258. The IPD 260 may be a surface mounted device (SMD), a 2-terminal integrated passive device (IPD), a multi-terminal IPD, or other types of passive devices. The IPD 260 may include a main structure and one or more passive devices in the main structure. The main structure may be, for example, a semiconductor substrate, an encapsulant, etc. The passive devices may include capacitors, resistors, inductors, etc., or a combination thereof, which may be formed in and / or on the main structure. The IPD 260 may be connected to the UBM 256 by reflowing the conductive connectors 258. In some embodiments (hereinafter with respect to Figures 19 to 23B Further discussed), the die stack 100 may include passive devices bonded to the die of the die stack 100, and thus the IPD 260 may be omitted. In some embodiments, an underfill (not shown) may be formed between the topmost dielectric layer (e.g., dielectric layer 254) of the front side redistribution structure 240 and each IPD 260.

[0070] exist Fig.17 In the embodiment, carrier substrate peeling is performed to separate (peel off) the carrier substrate 202 from the backside redistribution structure 206 (e.g., the dielectric layer 208). According to some embodiments, peeling includes projecting light such as laser or UV light onto the peeling layer 204 so that the peeling layer 204 decomposes under the heat of the light, thereby removing the carrier substrate 202. The structure can then be turned over and placed on, for example, an adhesive tape.

[0071] Additionally, a conductive connector 262 is formed through the dielectric layer 208 of the backside redistribution structure 206. An opening may be formed through the dielectric layer 208 of the backside redistribution structure 206, exposing a portion of the metallization pattern 210. The opening may be formed, for example, by using laser drilling, etching, etc. The conductive connector 262 is formed in the opening and connected to the exposed portion of the metallization pattern 210. The conductive connector 262 may be formed in a similar manner and with similar materials as the conductive connector 258.

[0072] exist Fig.18A In the embodiment of the present invention, a singulation process is performed by sawing along the scribe line areas (e.g., the area surrounding the packaging area 202A). The singulation process includes sawing the redistribution structures 206, 240 and the encapsulant 222. The singulation process separates the packaging area 202A from the adjacent packaging area (not shown) to form the integrated circuit package 200. After singulation, the redistribution structures 206, 240 and the encapsulant 222 are laterally adjacent.

[0073] Another integrated circuit package 300 may be connected to the integrated circuit package 200 to form a package-on-package structure. The integrated circuit package 300 may be a memory device. The integrated circuit package 300 may be connected to the integrated circuit package 200 before or after the integrated circuit package 200 is singulated.

[0074] The integrated circuit package 300 includes a substrate 302 and one or more dies 304 connected to the substrate 302. In some embodiments, a stack of one or more dies 304 is connected to the substrate 302. The substrate 302 can be made of semiconductor materials such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like can also be used. In addition, the substrate 302 can be a silicon on insulator (SOI) substrate. Typically, the SOI substrate includes a layer of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In another embodiment, the substrate 302 is based on an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Other core materials include bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials or films, etc. A build-up film such as Ajinomoto build-up film (ABF) or other lamination materials may be used for the substrate 302 .

[0075] The substrate 302 may include active and passive devices (not shown). As will be appreciated by those of ordinary skill in the art, a wide variety of devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements for the design of the integrated circuit package 300. Any suitable method may be used to form the device. The substrate 302 may also include a metallization layer (not shown) and through vias. The metallization layer may be formed over the active and passive devices and is designed to connect the various devices to form a functional circuit. The metallization layer may be formed by alternating layers of a dielectric (e.g., a low-k dielectric material) and a conductive material (e.g., copper) having vias interconnecting the conductive material layers, and may be formed by any suitable process (e.g., deposition, inlay, dual inlay, etc.). In some embodiments, the substrate 302 is substantially free of active and passive devices.

[0076] The substrate 302 may have a bonding pad 306 on one side of the substrate 302 to connect to the conductive connector 262. In some embodiments, the bonding pad 306 is formed by forming a recess (not shown) in a dielectric layer (not shown) on one side of the substrate 302. The recess may be formed to allow the bonding pad 306 to be embedded in the dielectric layer. In other embodiments, the recess is omitted because the bonding pad 306 may be formed on the dielectric layer. In some embodiments, the bonding pad 306 includes a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. The conductive material of the bonding pad 306 may be deposited above the thin seed layer. The conductive material may be formed by an electrochemical plating process, a chemical plating process, CVD, ALD, PVD, etc., or a combination thereof. In one embodiment, the conductive material of the bonding pad 306 is copper, tungsten, aluminum, silver, gold, etc., or a combination thereof.

[0077] In one embodiment, the bonding pad 306 is a UBM that includes three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. For example, the bonding pad 306 can be formed of copper, can be formed on a titanium layer (not shown), and has a nickel finish, which can improve the life of the integrated circuit package 300, which is particularly advantageous when the integrated circuit package 300 is a memory device such as a DRAM module. However, one of ordinary skill in the art will recognize that there are many suitable material and layer arrangements, such as a chromium / chrome copper alloy / copper / gold arrangement, a titanium / titanium tungsten / copper arrangement, or a copper / nickel / gold arrangement, which are suitable for forming the bonding pad 306. Any suitable material or material layer that can be used for the bonding pad 306 is fully intended to be included within the scope of the present application.

[0078] In the embodiment shown, die 304 is connected to substrate 302 by wire bonds 308, but other connections, such as conductive bumps, may be used. In one embodiment, die 304 is a stacked memory die. For example, die 304 may be a memory die such as a low power (LP) double data rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc.

[0079] The die 304 and the wire bonds 308 (when present) may be encapsulated by a molding material 310. For example, the molding material 310 may be molded over the die 304 and the wire bonds 308 using compression molding. In some embodiments, the molding material 310 is a molding compound, a polymer, an epoxy, a silicon oxide filler material, or the like, or a combination thereof. A curing process may be performed to cure the molding material 310; the curing process may be a thermal cure, a UV cure, or the like, or a combination thereof. In some embodiments, the die 304 is buried in the molding material 310, and after the molding material 310 is cured, a planarization step such as grinding is performed to remove excess portions of the molding material 310 and provide a substantially planar surface for the integrated circuit package 300.

[0080] After the integrated circuit package 300 is formed, the integrated circuit package 300 is connected to the integrated circuit package 200 through the conductive connector 262. The conductive connector 262 can be connected to the bonding pad 306 by reflowing the conductive connector 262. The die 304 can thus be electrically connected to the die stack 100 through the conductive connector 262, the conductive via 220, and the redistribution structures 206, 240.

[0081] In some embodiments, solder resist (not shown) is formed on a side of substrate 302 opposite die 304. Conductive connectors 262 may be disposed in openings in the solder resist to connect to conductive features (e.g., bonding pads 306) in substrate 302. The solder resist may be used to protect areas of substrate 302 from external damage.

[0082] In some embodiments, the conductive connector 262 has an epoxy flux (not shown) formed thereon before it is reflowed, wherein at least some epoxy portion of the epoxy flux remains after the integrated circuit package 300 is connected to the redistribution structure 206 .

[0083] In some embodiments, an underfill 312 is formed between the redistribution structure 206 and the substrate 302 and around the conductive connector 262. The underfill 312 can reduce stress and protect the joint caused by the reflow of the conductive connector 262. The underfill 312 can be formed by a capillary flow process after the integrated circuit package 300 is connected, or can be formed by a suitable deposition method before the integrated circuit package 300 is connected. In an embodiment in which epoxy flux is formed, it can act as the underfill 312. When the underfill 312 is formed before the integrated circuit package 300 is connected, the underfill 312 and the integrated circuit package 200 can be laterally adjacent.

[0084] Then, the integrated circuit package 200 is connected to the package substrate 400 using the conductive connector 258. The package substrate 400 can be made of semiconductor materials such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like can also be used. In addition, the package substrate 400 can be an SOI substrate. Typically, the SOI substrate includes a layer of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In another embodiment, the package substrate 400 is based on an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternative materials for the core material include bismaleimide triazine (BT) resin, or alternatively include other printed circuit board (PCB) materials or films. A stacking film such as Ajinomoto (Ajinomoto) stacking film (ABF) or other laminated materials can be used for the package substrate 400.

[0085] The package substrate 400 may include active and passive devices (not shown). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate structural and functional requirements for system design. Any suitable method may be used to form the devices.

[0086] The package substrate 400 may also include metallization layers and vias (not shown), and bonding pads 402 located above the metallization layers and vias. The metallization layers may be formed above the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed by alternating layers of dielectrics (e.g., low-k dielectric materials) and conductive materials (e.g., copper) with vias interconnecting the conductive material layers, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the package substrate 400 is substantially free of active and passive devices.

[0087] The conductive connector 258 is reflowed to connect the UBM 256 to the bonding pad 402. The conductive connector 258 connects the package substrate 400 including the metallization layer in the package substrate 400 to the integrated circuit package 200 including the metallization pattern of the redistribution structure 240. In some embodiments, a surface mounted passive device (e.g., SMD, not shown) can be connected to the package substrate 400, for example, to the bonding pad 402.

[0088] The conductive connector 258 may have an epoxy flux (not shown) formed thereon before it is reflowed, wherein at least some epoxy portion of the epoxy flux remains after the integrated circuit package 200 is connected to the package substrate 400. The remaining epoxy portion may be used as an underfill to reduce stress and protect the joint caused by the reflow of the conductive connector 258. In some embodiments, an underfill (not shown) may be formed between the integrated circuit package 200 and the package substrate 400, surrounding the conductive connector 258. The underfill may be formed by a capillary flow process after the integrated circuit package 200 is connected, or may be formed by a suitable deposition method before the integrated circuit package 200 is connected.

[0089] Fig.18B 1 is a cross-sectional view of an integrated circuit package implementing the die stack 100 according to some further embodiments. In this embodiment, the underfill 162 is omitted from the die stack 100 (see FIG. Figure 5 ). As mentioned above Figure 5 and Figure 6 As described above, when underfill 162 is omitted, encapsulant 164 may surround and physically contact the sidewalls of each die connector 122B, die connector 152, and reflowable connector 160. Additionally, when underfill 162 is omitted, encapsulant 164 may extend through dielectric layer 130.

[0090] Fig.19 , Fig. 20 , Fig.21 ,and Fig. 22 5 is a cross-sectional view of an intermediate step during a process for forming a die stack 500 according to some further embodiments. In this embodiment, the integrated circuit dies of the die stack 500 lack TSVs, which allows for the use of a plurality of integrated circuits. Figures 1 to 18BThe embodiments discussed herein have thicker integrated circuit dies. Therefore, other types of thick devices such as IPDs may also be incorporated into the die stack 500. The integrated circuit dies of the die stack 500 are directly joined in a face-to-face manner using reflowable connectors. The integrated circuit dies are shown stacked in one device region 102A of the wafer 102, but it should be understood that the wafer 102 may have any number of device regions, and the integrated circuit dies may be stacked to form a die stack in each device region.

[0091] exist Fig.19 In, form or obtain something similar to Figure 3 The intermediate structure discussed, except that the dielectric layer 130 is also patterned with openings 132C. As discussed further below, passive devices are to be placed in the openings 132C. The openings 132C expose a third subset of the die connectors 122C to which the passive devices are to be bonded.

[0092] Form or obtain something similar to Figure 4 The second integrated circuit die 140 discussed. In this embodiment, the second integrated circuit die 140 lacks the conductive vias 154 (see Figure 4 ). In this way, the second integrated circuit die 140 can be formed with a greater thickness without substantially increasing manufacturing costs. The overall thickness of the die stack 500 can therefore be increased, allowing the die stack 500 to accommodate other types of thick devices, such as passive devices.

[0093] Passive device 170 is formed or obtained. Passive device 170 can be an IPD, such as a 2-terminal integrated passive device (IPD), a multi-terminal IPD, or another type of passive device. Passive device 170 can be formed in a wafer, and the wafer can include different device areas that are singulated in subsequent steps to form multiple integrated circuit dies. Passive device 170 is processed according to applicable manufacturing processes to form a passive electronic component. For example, passive device 170 includes a main structure 172 and one or more passive devices in the main structure 172. Main structure 172 can be, for example, a semiconductor substrate, a sealant, etc. Passive devices can include capacitors, resistors, inductors, etc., or a combination thereof, which can be formed in and / or on the main structure 172. The passive device 170 may also include contact pads 176, dielectric layers 178, one or more passivation layers 180, and die connectors 182, which may be similar to the contact pads 116, dielectric layers 118, passivation layer(s) 120, and die connectors 122, respectively, of the first integrated circuit die 110. The die connectors 182 are exposed at the front side 170F of the passive device 170. After singulation of the passive device 170, the main structure 172, dielectric layers 178, and passivation layer(s) 180 are laterally adjacent.

[0094] exist Fig. 20 In the embodiment, the second integrated circuit die 140 is placed in the opening 132B and bonded to the first integrated circuit die 110 (e.g., wafer 102), and the passive device 170 is placed in the opening 132C and bonded to the first integrated circuit die 110 (e.g., wafer 102). The bonding may be similar to that described with respect to Figure 5 Specifically, the first integrated circuit die 110 and the second integrated circuit die 140 are directly bonded in a face-to-face manner using a first subset of reflowable connectors 160A, so that the front side 110F of the first integrated circuit die 110 is bonded to the front side 140F of the second integrated circuit die 140. The first integrated circuit die 110 and the second integrated circuit die 140 are bonded by contacting the reflowable connectors 160A to the die connectors 122B and the die connectors 152, and reflowing the reflowable connectors 160A. Similarly, the first integrated circuit die 110 and the passive device 170 are also directly bonded in a face-to-face manner using a second subset of the reflowable connectors 160B, so that the front side 110F of the first integrated circuit die 110 is bonded to the front side 170F of the passive device 170. The first integrated circuit die 110 and the passive device 170 are bonded by contacting the reflowable connector 160B to the die connector 122C and the die connector 182 and reflowing the reflowable connector 160B. Using the reflowable connector 160 to bond the first integrated circuit die 110, the second integrated circuit die 140, and the passive device 170 can allow the bonding to be performed at a lower cost than other bonding techniques such as hybrid bonding. In some embodiments, the second integrated circuit die 140 and the passive device 170 are bonded to the first integrated circuit die 110 at the same time, for example, by reflowing the reflowable connectors 160A, 160B using the same reflow process.

[0095] An underfill 162 is optionally formed between the first integrated circuit die 110 and each of the second integrated circuit die 140 and the passive device 170, surrounding the reflowable connectors 160A, 160B. Specifically, a first underfill 162A is formed between the first integrated circuit die 110 and the second integrated circuit die 140, and a second underfill 162B is formed between the first integrated circuit die 110 and the passive device 170. The underfills 162A, 162B may be formed in a manner similar to that described with respect to FIG. Figure 5 Formed in a similar manner as discussed.

[0096] Then, the sealant 164 is formed on and around the conductive via 134, the second integrated circuit die 140, and the passive device 170. The sealant 164 may be formed in a similar manner to the Figure 6 After sealing, the components of the structure are buried or covered.

[0097] exist Fig.21 In the embodiment, a planarization process is performed on the encapsulant 164 to expose the conductive via 134, the back side 140B of the second integrated circuit die 140, and the back side 170B of the passive device 170. The planarization process may be performed on the encapsulant 164 to expose the conductive via 134, the back side 140B of the second integrated circuit die 140, and the back side 170B of Figure 7 Similar to what is discussed.

[0098] In some embodiments, the planarization process includes thinning semiconductor substrate 142 and main structure 172. The thinning process may be, for example, chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc. After the planarization process, encapsulant 164 and dielectric layer 130 may have a combined thickness, for example, in a range of about 70 μm to about 180 μm, for example, about 100 μm.

[0099] Optionally, the semiconductor substrate 112 may be thinned, which helps reduce the overall thickness of the die stack 500. The thinning process may be, for example, chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc., which is performed on the back side 110B of the first integrated circuit die 110. After the thinning process, the semiconductor substrate 112 may have a thickness in the range of, for example, about 100 μm to about 150 μm, for example, about 130 μm.

[0100] exist Fig. 22 In the embodiment of the present invention, the singulation process is performed by sawing along the scribe line area (eg, the area surrounding the device area 102A). The singulation process can be similar to the one described above. Figure 8 The singulation process separates the device region 102A (including the first integrated circuit die 110) from the adjacent device region (not shown) of the wafer 102 to form a die stack 500. The singulated die stack 500 may then be placed on, for example, the tape 166. An adhesive 168 may be optionally formed on the back side 110B of the first integrated circuit die 110. The adhesive 168 may be formed in a manner similar to that described with respect to FIG. Figure 8 Formed in a similar manner as discussed.

[0101] Fig.23A is a cross-sectional view of an integrated circuit package implementing a die stack 500 according to some further embodiments. Figure 9-Figure 17 The process discussed packages the die stack 500 in an integrated circuit package 600. The integrated circuit package 600 may be a fan-out type package, such as an integrated fan-out (InFO) package. Another integrated circuit package 300 may be connected to the integrated circuit package 600 using a conductive connector 262 to form a package-on-package structure. The integrated circuit package 300 may be connected to the integrated circuit package 600 with respect to Fig.18AThe integrated circuit package 600 is then connected to the package substrate 400 using the conductive connector 258 to form a complete system. The package substrate 400 may be connected to the integrated circuit package 600 using the conductive connector 258 to form a complete system. Fig.18A Similar to what is discussed.

[0102] As described above, die stack 500 includes passive components, such as passive component 170 (see FIG. Fig. 22 Thus, in this embodiment, IPD260 can be omitted (see Fig.18A ). Therefore, the integrated circuit package 600 may not have passive devices such as SMDs mounted to the front redistribution structure 240. In another embodiment, the die stack 500 may include passive devices, and the integrated circuit package 600 may also include SMDs.

[0103] Fig. 23B 5 is a cross-sectional view of an integrated circuit package implementing a die stack 500 according to some further embodiments. In this embodiment, the bottom filler 162 is omitted from the die stack 500 (see FIG. Figure 5 ). As mentioned above Figure 5 and Figure 6 As described above, when underfill 162 is omitted, encapsulant 164 may surround and physically contact the sidewalls of each die connector 122B, die connector 122C, die connector 152, die connector 182, and reflowable connector 160. Additionally, when underfill 162 is omitted, encapsulant 164 may extend through dielectric layer 130.

[0104] Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 ,and Fig.29 1 is a cross-sectional view of an intermediate step during a process for forming a die stack 700 according to some further embodiments. In this embodiment, the integrated circuit dies of the die stack 700 are directly bonded in a back-to-face manner without using a reflowable connector. The integrated circuit dies are shown stacked in one device region 102A of the wafer 102, but it should be understood that the wafer 102 can have any number of device regions and the integrated circuit dies can be stacked to form a die stack in each device region.

[0105] exist Fig.24 In the process, a wafer 102 is formed or obtained. The wafer 102 and the Figure 1The die connector 122 is similar to that discussed above, except that the die connector 122 is a post-passivation interconnect (PPI). Thus, the die connector 122 includes a first portion extending through (some) of the passivation layer 120, and also includes a second portion extending along (some) of the passivation layer 120. As discussed further below, using a die connector that is a PPI allows more conductive vias 134 to be formed in the die stack 700.

[0106] exist Fig.25 In the embodiment of the present invention, dielectric layer 130 is formed on wafer 102, for example, on die connector 122 and (some) passivation layer 120. Dielectric layer 130 may be formed in a manner similar to that of Figure 2 Then, a conductive via 134 is formed through the dielectric layer 130 and extends away from the wafer 102. The conductive via 134 may be formed in a manner similar to that discussed above. Figure 3 Since the die connector 122 is a PPI, it helps to redistribute the stress caused by the conductive via 134 over the area of ​​the entire die stack 700. Figure 3 and Fig.19 Compared to the embodiments discussed above, more conductive vias 134 may be formed in the die stack 700. When more conductive vias 134 are formed, they may have a greater Figure 3 and Fig.19 The conductive vias 134 discussed have a finer pitch. For example, the conductive vias 134 may be formed with a pitch in the range of about 40 μm to about 80 μm.

[0107] exist Fig.26 In the process, a second integrated circuit die 140 is formed or obtained. The second integrated circuit die 140 is connected to the Figure 4 Similar to the discussion above, except that the second integrated circuit die 140 lacks the conductive via 154 (see Figure 4 ), and the second integrated circuit die 140 includes another dielectric layer 156 on the front side 140F covering the die connector 152. The back side 140B of the second integrated circuit die 140 is placed on the dielectric layer 130 between the conductive vias 134 and bonded to the dielectric layer 130 using an adhesive 158. The adhesive 158 is formed on the back side 140B of the second integrated circuit die 140. The adhesive 158 can be any suitable adhesive, epoxy, die attach film (DAF), etc. In the illustrated embodiment, the adhesive 158 is applied to the back side 140B of the second integrated circuit die 140 before singulation to separate the second integrated circuit die 140.

[0108] The first integrated circuit die 110 and the second integrated circuit die 140 are directly bonded in a back-to-face manner using adhesive 158. This bonding can be performed at a lower cost than other bonding techniques such as hybrid bonding. Due to the orientation of the dies, conductive vias 134 will be used to electrically connect the first integrated circuit die 110 and the second integrated circuit die 140. The die stack 700 may therefore require more die stacks than the die stack 100 (see FIG. Figure 8 ) or die stack 500 (see Fig. 22 ) More conductive vias 134 are formed to accommodate the I / O connector of the first integrated circuit die 110. As described above, since the die connector 122 is a PPI, more conductive vias 134 can be formed in the die stack 700, and back-to-face bonding can be achieved.

[0109] exist Fig. 27 In the embodiment, the sealant 164 is formed on and around the conductive via 134 and the second integrated circuit die 140. The sealant 164 may be formed in a manner similar to that of Figure 6 are formed in a similar manner as discussed.

[0110] exist Fig.28 In the embodiment, a planarization process is performed on the encapsulant 164 and the dielectric layer 156 to expose the conductive vias 134 and the die connector 152 of the second integrated circuit die 140. The planarization process may be performed on the encapsulant 164 and the dielectric layer 156 to expose the conductive vias 134 and the die connector 152 of the second integrated circuit die 140. Figure 7 After the planarization process, the remaining portion of the dielectric layer 156 surrounds the die connector 152 .

[0111] Optionally, the semiconductor substrate 112 may be thinned, which helps reduce the overall thickness of the die stack 500. The thinning process may be, for example, chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc., which may be performed on the back side 110B of the first integrated circuit die 110. After the thinning process, the semiconductor substrate 112 may have a thickness, for example, in the range of about 50 μm to about 90 μm, for example, about 70 μm.

[0112] exist Fig.29 In the embodiment of the present invention, the singulation process is performed by sawing along the scribe line area (eg, the area surrounding the device area 102A). The singulation process can be similar to the one described above. Figure 8 The singulation process separates the device region 102A (including the first integrated circuit die 110) from the adjacent device region (not shown) of the wafer 102 to form a die stack 700. The singulated die stack 700 can then be placed on, for example, the tape 166. An adhesive 168 is optionally formed on the back side 110B of the first integrated circuit die 110. The adhesive 168 can be formed in a manner similar to that described with respect to FIG. Figure 8 are formed in a similar manner as discussed.

[0113] Fig.30 is a cross-sectional view of an integrated circuit package implementing die stack 700 according to some further embodiments. Figure 9-Figure 17 The process discussed packages the die stack 700 in an integrated circuit package 800. The integrated circuit package 800 may be a fan-out type package, such as an integrated fan-out (InFO) package. The metallization pattern of the front redistribution structure 240 electrically connects the first integrated circuit die 110 and the second integrated circuit die 140. In some embodiments, the die stack 700 lacks passive devices. In such an embodiment, the IPD 260 may be connected to the UBM 256. The IPD 260 may be connected to the UBM 256. Fig.16 Another integrated circuit package 300 may be connected to the integrated circuit package 800 using the conductive connector 262 to form a package-on-package structure. The integrated circuit package 300 may be connected to the integrated circuit package 800 using the conductive connector 262 to form a package-on-package structure. Fig.18A The integrated circuit package 800 is then connected to the package substrate 400 using conductive connectors 258 to form a complete system. The package substrate 400 may be connected to the integrated circuit package 800 using conductive connectors 258 to form a complete system. Fig.18A Similar discussion.

[0114] Embodiments can achieve advantages. Forming die stacks 100, 500, 700 by bonding integrated circuit dies 110, 140 using reflowable connectors or adhesives can allow bonding to be implemented at a cost lower than other bonding techniques such as hybrid bonding. When the die stack is a low-performance device, it may be particularly desirable to form die stacks 100, 500, 700 at a lower cost. In addition, although hybrid bonding can allow die stacks 100, 500, 700 to have finer die connector spacing or a larger number of input / output (I / O) connectors, these features may be unnecessary when the die stack is a low-performance device. Some embodiments may also allow passive components to be incorporated into integrated circuit packages in a low-cost manner.

[0115] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of known good dies to increase yield and reduce costs.

[0116] In one embodiment, a structure includes: a first integrated circuit die, including a first die connector; a first dielectric layer, located on the first die connector; a first conductive via, extending through the first dielectric layer, the first conductive via connected to a first subset of the first die connectors; a second integrated circuit die, bonded to a second subset of the first die connectors using a first reflowable connector; a first sealant, surrounding the second integrated circuit die and the first conductive via, the first sealant and the first integrated circuit die being laterally adjacent; a second conductive via, adjacent to the first integrated circuit die; a second sealant, surrounding the second conductive via, the first sealant, and the first integrated circuit die; and a first redistribution structure, including a first redistribution line, the first redistribution line being connected to the first conductive via and the second conductive via.

[0117] In some embodiments, the structure further comprises: an underfill surrounding each first reflowable connector and the second subset of the first die connectors, the underfill extending through the first dielectric layer. In some embodiments of the structure, the first encapsulant has a first portion surrounding each first reflowable connector and the second subset of the first die connectors, the first portion of the first encapsulant extending through the first dielectric layer. In some embodiments of the structure, the second integrated circuit die comprises: a through substrate via (TSV), the first redistribution line of the first redistribution structure connected to the through substrate via; and a barrier layer surrounding the through substrate via, the barrier layer contacting the second dielectric layer of the first redistribution structure. In some embodiments of the structure, the second integrated circuit die lacks a through substrate via, and the structure further comprises: a passive device bonded to the third subset of the first die connectors using the second reflowable connector, the first encapsulant surrounding the passive device. In some embodiments of the structure, the first encapsulant comprises a first molding material, the second encapsulant comprises a second molding material, and the first molding material is different from the second molding material. In some embodiments of the structure, the first molding material comprises a filler having a size smaller than the second molding material. In some embodiments, the structure further comprises: a second redistribution structure comprising a second redistribution line, the second redistribution line connected to the second conductive via; a memory device connected to the second redistribution line of the second redistribution structure; and a package substrate connected to the first redistribution line of the first redistribution structure. In some embodiments, the structure further comprises: a surface mounted passive device connected to the first redistribution line of the first redistribution structure.

[0118] In one embodiment, a structure includes: a first integrated circuit die, including a post-passivation interconnect (PPI); a dielectric layer, located on the post-passivation interconnect; a first conductive via, extending through the dielectric layer, the first conductive via connected to the post-passivation interconnect; a second integrated circuit die, including a semiconductor substrate and a die connector, the semiconductor substrate being bonded to the dielectric layer using an adhesive; a first encapsulant, surrounding the second integrated circuit die and the first conductive via, the first encapsulant and the first integrated circuit die being laterally adjacent; a second conductive via, adjacent to the first integrated circuit die; a second encapsulant, surrounding the second conductive via, the first encapsulant, and the first integrated circuit die; a first redistribution structure, including a first redistribution line, the first redistribution line being connected to the first conductive via, the die connector, and the second conductive via.

[0119] In some embodiments of the structure, the first encapsulant includes a first molding material, the second encapsulant includes a second molding material, and the first molding material is different from the second molding material. In some embodiments of the structure, the first molding material includes a filler having a size smaller than the second molding material. In some embodiments, the structure further includes: a second redistribution structure including a second redistribution line connected to the second conductive via; and a memory device connected to the second redistribution line of the second redistribution structure; and a packaging substrate connected to the first redistribution line of the first redistribution structure. In some embodiments, the structure further includes: a surface mounted passive device connected to the first redistribution line of the first redistribution structure.

[0120] In one embodiment, a method includes: forming a first conductive via on a first integrated circuit die; bonding a second integrated circuit die to the first integrated circuit die using a first reflowable connector, the second integrated circuit die being adjacent to the first conductive via; sealing the first conductive via and the second integrated circuit die using a first molding compound; singulating the first molding compound and the first integrated circuit die to form a die stack; placing the die stack adjacent to a second conductive via; sealing the second conductive via and the die stack using a second molding compound; and forming a first redistribution structure on the second molding compound and the die stack, the first redistribution structure including a first redistribution line connected to the first conductive via and the second conductive via.

[0121] In some embodiments of the method, the first integrated circuit die includes a first die connector, the second integrated circuit die includes a second die connector, and bonding the second integrated circuit die to the first integrated circuit die includes: depositing a dielectric layer on the first integrated circuit die; patterning the dielectric layer with a first opening, the first opening exposing a first subset of the first die connectors; placing the second integrated circuit die in the first opening; and connecting the second die connector to the first subset of the first die connectors with a first reflowable connector. In some embodiments, the method further includes: patterning the dielectric layer with a second opening, the second opening exposing a second subset of the first die connectors; placing a passive device in the second opening, the passive device including a third die connector; connecting the third die connector to the second subset of the first die connectors with a second reflowable connector. In some embodiments of the method, the second integrated circuit die includes a semiconductor substrate and a through substrate via (TSV) extending through the semiconductor substrate, and further includes: after sealing the second conductive via and the die stack with a second molding compound, planarizing the second molding compound, wherein after planarization, the first conductive via, the second conductive via, and the through substrate via are exposed. In some embodiments of the method, planarizing includes: thinning the second molding compound using a first grinding process to expose the semiconductor substrate; thinning the semiconductor substrate using a second grinding process, the second grinding process having a smaller removal rate than the first grinding process; and thinning the semiconductor substrate using a third grinding process to expose the through-substrate via, the third grinding process having a smaller removal rate than the second grinding process. In some embodiments, the method further includes: after the third grinding process, recessing the semiconductor substrate to expose a sidewall portion of the through-substrate via; and depositing a barrier layer around the sidewall portion of the through-substrate via.

[0122] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a first integrated circuit die including a first die connector; a first dielectric layer disposed on the first die connector; a first conductive via extending through the first dielectric layer, the first conductive via being connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors using a first reflowable connector; a first encapsulant surrounding the second integrated circuit die and the first conductive via, the first encapsulant comprising a first molding material, the first molding material extending continuously between the second integrated circuit die and the first conductive via, the first encapsulant and the first integrated circuit die being laterally adjacent; a second conductive via adjacent to the first integrated circuit die; a second encapsulant surrounding the second conductive via, the first encapsulant, and the first integrated circuit die; as well as The first redistribution structure includes a first redistribution line connected to the first conductive via and the second conductive via.

2. The semiconductor structure according to claim 1, further comprising: An underfill surrounds each of the first reflowable connectors and the second subset of the first die connectors, the underfill extending through the first dielectric layer.

3. The semiconductor structure according to claim 1, wherein: The first encapsulant has a first portion surrounding each of the first reflowable connectors and the second subset of the first die connectors, the first portion of the first encapsulant extending through the first dielectric layer.

4. The semiconductor structure according to claim 1, wherein: The second integrated circuit die comprises: a through substrate via (TSV) to which the first redistribution line of the first redistribution structure is connected; and A barrier layer surrounds the through substrate via, the barrier layer contacting the second dielectric layer of the first redistribution structure.

5. The semiconductor structure according to claim 1, wherein: The second integrated circuit die lacks a through-substrate via, and the structure further comprises: A passive component is bonded to the third subset of the first die connectors using a second reflowable connector, and the first encapsulant surrounds the passive component.

6. The semiconductor structure according to claim 1, wherein: The second encapsulant includes a second molding material, and the first molding material is different from the second molding material.

7. The semiconductor structure according to claim 6, wherein: The first molding material includes a filler having a smaller size than the second molding material.

8. The semiconductor structure according to claim 1, further comprising: a second redistribution structure comprising a second redistribution line connected to the second conductive via; a memory device connected to the second redistribution line of the second redistribution structure; as well as A package substrate is connected to the first redistribution line of the first redistribution structure.

9. The semiconductor structure according to claim 8, further comprising: A surface mounted passive device is connected to the first redistribution line of the first redistribution structure.

10. A semiconductor structure comprising: a first integrated circuit die including a post-passivation interconnect (PPI); a dielectric layer disposed on the post-passivation interconnect; a first conductive via extending through the dielectric layer, the first conductive via being connected to the post-passivation interconnect; a second integrated circuit die comprising a semiconductor substrate and a die connector, the semiconductor substrate being bonded to the dielectric layer with an adhesive; a first encapsulant surrounding the second integrated circuit die and the first conductive via, the first encapsulant and the first integrated circuit die being laterally adjacent; a second conductive via adjacent to the first integrated circuit die; a second encapsulant surrounding the second conductive via, the first encapsulant, and the first integrated circuit die; as well as A first redistribution structure includes a first redistribution line connected to the first conductive via, the die connector, and the second conductive via.

11. The semiconductor structure according to claim 10, wherein: The first encapsulant includes a first molding material, the second encapsulant includes a second molding material, and the first molding material is different from the second molding material.

12. The semiconductor structure according to claim 11, wherein: The first molding material includes a filler having a smaller size than the second molding material.

13. The semiconductor structure of claim 10, further comprising: a second redistribution structure comprising a second redistribution line connected to the second conductive via; a memory device connected to the second redistribution line of the second redistribution structure; as well as A package substrate is connected to the first redistribution line of the first redistribution structure.

14. The semiconductor structure of claim 13, further comprising: A surface mounted passive device is connected to the first redistribution line of the first redistribution structure.

15. A method of forming a semiconductor structure, comprising: forming a first conductive via on a first integrated circuit die; bonding a second integrated circuit die to the first integrated circuit die using a first reflowable connector, the second integrated circuit die being adjacent to the first conductive via; sealing the first conductive via and the second integrated circuit die with a first molding compound; singulating the first molding compound and the first integrated circuit die to form a die stack; placing the die stack adjacent to a second conductive via; sealing the second conductive via and the die stack with a second molding compound; as well as The second molding compound and a first redistribution structure on the die stack are formed, the first redistribution structure including a first redistribution line connected to the first conductive via and the second conductive via.

16. The method according to claim 15, wherein: The first integrated circuit die includes a first die connector, the second integrated circuit die includes a second die connector, and the bonding the second integrated circuit die to the first integrated circuit die includes: depositing a dielectric layer on the first integrated circuit die; patterning the dielectric layer with first openings, the first openings exposing a first subset of the first die connectors; placing the second integrated circuit die in the first opening; and The second die connector is connected to the first subset of the first die connectors using the first reflowable connector.

17. The method according to claim 16, further comprising: patterning the dielectric layer with second openings, the second openings exposing a second subset of the first die connectors; placing a passive component in the second opening, the passive component comprising a third die connector; as well as The third die connector is connected to the second subset of the first die connectors using a second reflowable connector.

18. The method according to claim 15, wherein: The second integrated circuit die includes a semiconductor substrate and a through substrate via (TSV) extending through the semiconductor substrate, and further includes: After sealing the second conductive via and the die stack with the second mold compound, the second mold compound is planarized, wherein after the planarization, the first conductive via, the second conductive via, and the through-substrate via are exposed.

19. The method according to claim 18, wherein: The planarization includes: thinning the second molding compound using a first grinding process to expose the semiconductor substrate; thinning the semiconductor substrate using a second grinding process, the second grinding process having a smaller removal rate than the first grinding process; and The semiconductor substrate is thinned using a third grinding process to expose the through-substrate via, the third grinding process having a smaller removal rate than the second grinding process.

20. The method according to claim 19, further comprising: After the third grinding process, recessing the semiconductor substrate to expose a sidewall portion of the through-substrate via hole; as well as A barrier layer is deposited around the sidewall portion of the through substrate via.

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