A receiver demodulator, a peak detector and a signal demodulation method

Abstract

The invention discloses a receiver demodulator, a peak detector and a signal demodulation method, which can improve the anti-blocking and anti-interference capabilities of the receiver and reduce the area and cost of the entire device. The demodulator comprises an automatic gain control circuit, a peak detection circuit, a limiter circuit, a gain control voltage adjustment circuit, a gain control filter capacitor, a dynamic threshold extraction circuit and a high-speed comparator. The peak detector applied to the demodulator comprises a second comparator, a switch, a voltage-dividing resistor, a capacitor and an RC filter. The method for signal demodulation using the demodulator including the peak detector comprises: amplifying an intermediate frequency signal through an automatic gain control circuit, performing envelope detection through a peak detection circuit, filtering a baseband signal through a limiter circuit, adjusting the gain of a gain control voltage adjustment circuit, adjusting an AC signal through a dynamic threshold extraction circuit, and converting a signal to be compared into a digital signal through a high-speed comparator.

Description

Technical Field

[0001] The present invention relates to the field of electronic communication technology, in particular to a receiver demodulator, a peak detector and a signal demodulation method, which use a standard CMOS process to implement intermediate frequency signal demodulation of an OOK receiver. Background Art

[0002] With the continuous development of communication and Internet of Things technology, wireless communication technology has been widely used. Currently, commonly used wireless communication technologies include Bluetooth, WIFI, IrDA, etc., among which short-range wireless communication is more widely used. At present, short-range wireless communication technology mostly adopts OOK communication mode, especially in low-cost application fields, by integrating the RF front end and baseband chip system-level into the wireless receiver to achieve data demodulation.

[0003] Currently, commonly used RF front-ends include mature architectures such as low-IF demodulation (low-IF receiver) and zero-IF demodulation (zero-IF demodulation receiver). However, existing low-IF receivers have problems such as large occupied area and poor stability. An OOK demodulation circuit is provided in the prior art, which includes a transistor amplifier circuit, a diode peak envelope detection circuit and a comparator circuit connected in sequence. The received signal is amplified by a transistor circuit unit, and then passed through a diode peak envelope detection unit. Finally, an integrated operational amplifier is used as a comparator to perform level conversion to achieve demodulated signal output. The demodulation system is generally made of discrete devices, which has a large area and high cost. Discrete devices are prone to interference, resulting in poor stability. Some integrated systems provided in the prior art integrate the amplifier and data sampling circuit into a chip, but the overall structure is still similar to the structure of the above-mentioned OOK demodulation circuit. Its dynamic demodulation range and anti-blocking capability are limited because the amplifier works in an open-loop state, and the turn-on threshold of the passive diode in the diode peak envelope detection unit also leads to amplitude loss. At the same time, the use of a fixed threshold comparator also leads to poor anti-interference capability, affecting the stability of the entire system. Summary of the invention

[0004] In view of the problems existing in the prior art of OOK receiver demodulation circuit, such as poor anti-interference ability, poor stability, large area and high cost, the present invention provides an on-chip integrated OOK receiver demodulation circuit, which can improve the anti-blocking and anti-interference capabilities of the receiver and reduce the area and cost of the entire device.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] An on-chip integrated OOK receiver demodulator is used to demodulate the intermediate frequency signal of the OOK receiver, characterized in that it includes an automatic gain control circuit, a peak detection circuit, a limiter circuit, a gain control voltage adjustment circuit, a gain control filter capacitor, a dynamic threshold extraction circuit and a high-speed comparator, wherein the input end of the automatic gain control circuit is connected to the intermediate frequency signal, and the output end is connected to the input ends of the peak detection circuit and the limiter circuit in sequence, the output end of the limiter circuit is respectively connected to the input end of the high-speed comparator, the input end of the dynamic threshold extraction circuit, and the input end of the gain control voltage adjustment circuit, the output end of the gain control voltage adjustment circuit is respectively connected to the gain control filter capacitor and the automatic gain control circuit, the output end of the dynamic threshold extraction circuit is connected to the input end of the high-speed comparator, and the output end of the high-speed comparator is the signal output of the demodulation circuit.

[0007] Its further characteristic is that

[0008] The automatic gain control circuit comprises five stages of variable gain amplifiers and one stage of fixed gain amplifier circuit connected in sequence, and an AC coupling capacitor is connected in series between the input end of each stage of the variable gain amplifier, the fifth stage of the variable gain amplifier and the fixed gain amplifier circuit;

[0009] The gain control voltage adjustment circuit comprises a first comparator, a charge pump, and the gain control filter capacitor, wherein the inverting input terminal of the first comparator is connected to the output of the limiter circuit, the non-inverting input terminal of the first comparator is connected to the reference voltage VREF, and the output terminal of the first comparator is connected to the switch of the charge pump;

[0010] The limiting circuit is a diode, a MOS tube with a diode structure or a buffer structure;

[0011] A dynamic threshold extraction circuit is applied to the OOK receiver demodulator, characterized in that the dynamic threshold extraction circuit includes a first operational amplifier A1, a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, switches S1, SN1, S2, SN2, capacitors C1, C2, C3, C4, a first NMOS tube M1 and a second NMOS tube M2, wherein the switch S1 and the switch SN1 are complementary switches, and the switch S2 and the switch SN2 are complementary switches; wherein the first operational amplifier A1 and the first NMOS tube form a first active diode structure, and the second operational amplifier A2 and the second NMOS tube M2 form a second active diode structure; the output of the limiter is connected to the first The inverting input terminal of the operational amplifier A1 and the non-inverting input terminal of the second operational amplifier A2; the output terminal of the first active diode is respectively connected to the non-inverting input terminal of the third operational amplifier A3, the switch S1, and the capacitor C3, and the output terminal of the second active diode is respectively connected to the non-inverting input terminal of the fourth operational amplifier A3, the switch S2, and the capacitor C4; the output terminal of the third operational amplifier A3 is connected to the inverting input terminal of the third operational amplifier as a first buffer, and the switch SN2 and the resistor R1 are connected at the same time. The output terminal of the fourth operational amplifier A4 is connected to the inverting input terminal of the fourth operational amplifier as a second buffer, and the switches SN1 and R2 are connected at the same time. The switches S1 and SN1 are connected to the charging capacitor C1, and the switches S2 and SN2 are connected to the discharging capacitor C2. The first voltage-dividing resistor R1 is connected to the second voltage-dividing resistor R2 as the output of the dynamic threshold extraction circuit.

[0012] A peak detector is applied to the OOK receiver demodulator, characterized in that the peak detector includes the peak detection circuit, the peak detection circuit includes two second comparators, switches S10 and S20, voltage dividing resistors R01 and R02, capacitor C0, and RC filter, and the positive input ends of the two second comparators are respectively connected to the intermediate frequency differential signal V INP 、V INN The negative input end is connected to the voltage-dividing resistors R01 and R02, the voltage-dividing resistors R01 and R02 and the positive input ends of the two second comparators form a symmetrical structure, and the output ends of the two second comparators are connected to the capacitor and the RC filter through switches S10 and S20 respectively.

[0013] The following beneficial effects can be achieved by adopting the above structure of the present invention: 1. The receiver demodulator of the present application integrates the automatic gain control circuit, the peak detection circuit, the limiter circuit, the gain control voltage adjustment circuit, the gain control filter capacitor, the dynamic threshold extraction circuit and the high-speed comparator into the same device. Compared with the existing discrete devices, the integration is greatly improved, the area of ​​the entire device is reduced, and the reliability is improved, and the external signal interference is reduced. The receiver demodulator of the present application realizes the automatic gain control range of 0dB to 50dB, which has a very large dynamic range.

[0014] 2. The demodulator of the receiver of the present application integrates a limiting circuit, which has a low-frequency filtering function for the baseband signal, suppresses the interference of glitches on the subsequent digital output, thereby enhancing the anti-blocking and anti-interference capabilities and having good adaptability.

[0015] 3. The receiver demodulator of the present application integrates a peak detection circuit, which includes two low-threshold comparators with complementary outputs. It fully utilizes the signal amplitude of the positive and negative half cycles and reduces the amplitude loss. At the same time, it smoothes the voltage through an RC filter, reduces glitches, improves anti-interference ability, and thus improves the stability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a system block diagram of the present invention;

[0017] Figure 2 is a circuit schematic diagram of the automatic gain control circuit of the present invention;

[0018] Figure 3 is a circuit schematic diagram of a peak detection circuit of the present invention;

[0019] Figure 4 is a circuit schematic diagram of a dynamic threshold extraction circuit of the present invention;

[0020] Figure 5 The figure is a circuit schematic diagram of the gain control voltage regulating circuit of the present invention. DETAILED DESCRIPTION

[0021] See Figure 1, an on-chip integrated OOK receiver demodulator, used for demodulating the intermediate frequency signal of the OOK receiver, comprising an automatic gain control circuit 1, a peak detection circuit 2, a limiter circuit 3, a gain control voltage adjustment circuit 4, a gain control filter capacitor C, a dynamic threshold extraction circuit 6 and a high-speed comparator 7, wherein the input end of the automatic gain control circuit 1 is connected to the intermediate frequency signal, and the output end is connected to the peak detection circuit 2 and the input end of the limiter circuit 3 in sequence, the output end of the limiter circuit 3 is respectively connected to the input end of the high-speed comparator 7, the input end of the dynamic threshold extraction circuit 6, and the input end of the gain control voltage adjustment circuit 4, the output end of the gain control voltage adjustment circuit 4 is respectively connected to the gain control filter capacitor C and the automatic gain control circuit 1, the gain control filter capacitor C is input to the automatic gain control voltage input end as a control voltage as a negative feedback of the gain control voltage, the output end of the dynamic threshold extraction circuit 6 is connected to the input end of the high-speed comparator, and the output end of the high-speed comparator 7 is the signal output of the demodulation circuit.

[0022] See Figure 2 The automatic gain control circuit 1 includes five variable gain amplifiers (VGA1, VGA2, VGA3, VGA4, VGA5) connected in sequence and a fixed gain amplifier circuit. An AC coupling capacitor is connected in series between the input end of each variable gain amplifier, the fifth variable gain amplifier VGA5 and the fixed gain amplifier circuit to eliminate the influence of DC bias. The gain of the five variable gain amplifier is determined by V CAGC Voltage control; the fixed gain amplifier circuit not only provides a fixed gain, but also provides a bias voltage for the five-stage variable gain amplifier. The gain of the variable gain amplifier is determined by the feedback voltage V CAGC The gain of a single-stage variable gain amplifier is changed by controlling a transconductance amplifier link of the amplifier, thereby enhancing the common-mode stability and linearity of each variable gain amplifier.

[0023] The automatic gain control circuit 1 amplifies the input intermediate frequency signal and outputs it to the peak detection circuit 2. The peak detection circuit 2 includes two second comparators, switches S10 and S20, voltage dividing resistors R01 and R02, capacitor C0, and RC filter. The positive input terminals of the two second comparators are respectively connected to the intermediate frequency differential signal V INP , V INN The negative input terminal is connected to the voltage dividing resistors R01 and R02, the voltage dividing resistors R01 and R02 and the positive input terminals of the two second comparators form a symmetrical structure, and the output terminals of the two second comparators are connected to the capacitor and the RC filter through switches S10 and S20 respectively.

[0024] See Figure 5The gain control voltage adjustment circuit 4 includes a first comparator A5, a charge pump, a gain control filter capacitor C, switches S3 and SN3. The inverting input terminal V IN The output of the limiting circuit 3 is connected, and the non-inverting input terminal of the first comparator A5 is connected to the reference voltage V REF The output end of the first comparator A5 is connected to the switches S3 and SN3 of the charge pump, and the gain of the automatic gain control circuit 1 is adjusted by controlling the switches S3 and SN3; the limiter circuit is a diode, a MOS tube with a diode structure, or a buffer structure;

[0025] See Figure 4 The dynamic threshold extraction circuit 6 includes a first operational amplifier A1, a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, switches S1, SN1, S2, SN2 controlled by two-phase non-overlapping clocks, capacitors C1, C2, C3, C4, a first NMOS tube M1 and a second NMOS tube M2, wherein the switch S1 and the switch SN1 are complementary switches, and the switch S2 and the switch SN2 are complementary switches; wherein the first operational amplifier A1 and the first NMOS tube form a first active diode structure, and the second operational amplifier A2 and the second NMOS tube M2 form a second active diode structure; the output of the limiter circuit is connected to the first operational amplifier A1 the inverting input terminal of the first operational amplifier A1 and the non-inverting input terminal of the second operational amplifier A2; the output terminal of the first active diode is respectively connected to the non-inverting input terminal of the third operational amplifier A3, the switch S1, and the capacitor C3, and the output terminal of the second active diode is respectively connected to the non-inverting input terminal of the fourth operational amplifier A3, the switch S2, and the capacitor C4; the output terminal of the third operational amplifier A3 is connected to the reverse input terminal of the third operational amplifier as a first buffer, and the switch SN2 and the resistor R1 are connected at the same time, the output terminal of the fourth operational amplifier A4 is connected to the reverse input terminal of the fourth operational amplifier as a second buffer, and the switches SN1 and R2 are connected at the same time, the switches S1 and SN1 are connected to the charging capacitor C1, the switches S2 and SN2 are connected to the discharging capacitor C2, and the first voltage-dividing resistor R1 is connected to the second voltage-dividing resistor R2 as the output of the dynamic threshold extraction circuit.

[0026] A signal demodulation method for an OOK receiver is applied to the above-mentioned OOK receiver demodulator. The signal demodulation method comprises: S1, inputting an intermediate frequency signal to an input end of an automatic gain control circuit, amplifying the intermediate frequency signal through the automatic gain control circuit, and obtaining an amplified intermediate frequency signal;

[0027] S2. The amplified intermediate frequency signal is input into the peak detection circuit, and the baseband signal on the envelope of the amplified intermediate frequency signal is demodulated through the peak detection circuit envelope detection. The specific demodulation method includes: the peak detector circuit is mainly used for envelope detection, and the baseband signal carried on the envelope of the intermediate frequency signal of the automatic gain control circuit 1 can be restored. In the traditional diode envelope detection, the envelope will be damaged due to the opening threshold of the diode, and it is insensitive to small signals, which reduces the sensitivity of the receiver. According to the above-mentioned shortcomings, the present invention proposes a peak detection circuit (peak detector) with a new structure, such as Figure 3 As shown, the intermediate frequency differential signal V INP 、V INN Each inputs a positive input terminal of a comparator, and the negative input terminal of the comparator is connected to the feedback voltage Vback after resistor voltage division, and the two present a symmetrical structure; the output node V OUT1 Connect the peak voltage storage capacitor C03 and a discharge path, then the output terminal V OUT Connect to RC filter, through RC filter to V OUT1 The voltage is smoothed to reduce burrs. The basic principle is: according to the characteristics of the OOK receiver signal, the intermediate frequency differential signal V INP 、V INN When the intermediate frequency sine wave signal is output to the ports of the two comparators respectively, the amplitude of the intermediate frequency sine wave signal is greater than the static Vback voltage. The switches S10 and S20 are opened alternately to charge the peak voltage temporary storage capacitor C03 with a constant charging current until Vback is greater than V IFP , V IFN When the IF signal envelope is 0, the IF signal is pulled down to 0. At this time, switches S10 and S20 are both turned off, and the discharge path discharges the peak voltage stored in capacitor C03. At this time, the peak detection circuit 2 (envelope detector) outputs a low level, thereby realizing the extraction of the IF signal envelope, that is, demodulating the baseband signal on the amplified IF signal envelope. At the same time, the threshold for the opening of switches S10 and S20 can be achieved by adjusting resistors R01 and R02. The two comparators in the peak detection circuit are low-threshold comparators with complementary outputs, which fully utilize the signal amplitude of the positive and negative half-cycles. At the same time, the use of low-threshold comparators can obtain non-destructive detection peaks, and at the same time, the discharge current of the voltage storage capacitor is appropriately controlled to make its cycle much smaller than the charging cycle, thereby taking out the IF signal envelope and sending it to the next level comparator for output of digital standard signals.

[0028] S3, the peak detection circuit 2 inputs the baseband signal to the limiter circuit 3, and the baseband signal is filtered by the limiter circuit 3 to output three signals: feedback signal, AC signal, and signal to be compared. The feedback signal is output to the gain control voltage adjustment circuit, the AC signal is output to the dynamic threshold extraction circuit, and the signal to be compared is output to the comparator circuit; the function of the limiter circuit 3 is: if the envelope of the peak detection circuit 2 is too large, the gain of the automatic gain control circuit 1 is reduced, and the input of the intermediate frequency signal and its own noise interference will cause serious data loss and misjudgment. At the same time, the limiter circuit 3 has an RC filter, and the RC filter has the function of low-frequency filtering of the baseband signal, thereby suppressing the interference of the burrs on the post-stage digital output and enhancing the anti-blocking ability.

[0029] S4, when the feedback signal is less than the reference voltage V of the gain control voltage adjustment circuit 4 REF When the charge pump charging switch S3 is turned on, the gain control filter capacitor C is discharged, and the reference voltage V CAGC The value of increases, at this time, the gain of the automatic gain control circuit 1 needs to be adjusted to increase its gain. When the output of the limiter is greater than the reference voltage V REF When the charge pump is turned off, the discharge switch SN3 is turned on and the gain control filter capacitor C is discharged. The voltage V CAGC Reduce, at this time reduce the gain of the automatic gain control circuit 1. The gain is automatically adjusted through switches S3 and SN3 to keep the output of the limiter stable at the reference voltage V REF .

[0030] S5. The AC signal is adjusted by a dynamic threshold extraction circuit to extract a dynamic threshold. The adjustment method includes: by controlling switches S1, SN1, S2, and SN2, the AC signal output by the limiter circuit is a high potential or a low potential. The specific control method includes:

[0031] S51, when switch SN1 is closed, switch S1 is opened, and the high level output by the fourth operational amplifier charges capacitor C1; when switch SN1 is opened, switch S1 is closed, capacitor C1 discharges capacitor C3, and the voltage of capacitor C3 increases. The voltage of the non-inverting input terminal of the first operational amplifier is greater than the voltage of the inverting input terminal of the first operational amplifier A1, the first NMOS tube M1 is turned on, and capacitor C3 discharges to the first current source again until the voltage on capacitor C3 is less than the voltage of the inverting input terminal of the first operational amplifier A1 again. The first NMOS tube M1 is turned off, and the AC signal output by the limiter circuit remains at a low potential.

[0032] When the AC signal output by the limiter circuit is at a high potential, the output of the second operational amplifier A2 is high, and the initial potential of the capacitor C4 is low, that is, the gate potential of the second NMOS tube M2 is high, so the second NMOS tube M2 is turned on, and the second current source VDD charges the capacitor C4 until the voltage on the capacitor C4 is greater than the voltage at the non-inverting input terminal of the second operational amplifier A2. The second NMOS tube M2 is turned off, and the AC signal output by the limiter circuit is kept at a high potential through the capacitor C4, and is transmitted to the second voltage-dividing resistor R2 through the second buffer.

[0033] S52, when switch S2 is turned on, switch SN2 is closed, and capacitor C2 is discharged; when switch S2 is closed, switch SN2 is turned on, and the high level on capacitor C4 discharges capacitor C2, the voltage of capacitor C4 decreases, the voltage of the inverting input terminal of the second operational amplifier is less than the voltage of the non-inverting input terminal of the second operational amplifier, the second NMOS tube M2 is turned on, and the second current source charges capacitor C4 again until the voltage on capacitor C4 is greater than the voltage of the non-inverting input terminal of the second operational amplifier again, the first NMOS tube M2 is turned off, and the AC signal output by the limiter circuit remains at a high potential.

[0034] When the AC signal output by the limiter circuit is at a low potential, the output of the first operational amplifier is high, and the initial potential of C3 is high, that is, the gate potential of the first NMOS tube M1 is high, so the first NMOS tube M2 is turned on, and the first current source discharges the capacitor C3 until the voltage on the capacitor C3 is less than the voltage of the inverting input terminal of the first operational amplifier A1. The first NMOS tube M1 is turned off, and the AC signal output by the limiter circuit is kept at a low potential through the capacitor C3, and is transmitted to the first voltage-dividing resistor R1 through the first buffer.

[0035] S53, the output voltage V of the dynamic threshold extraction circuit OUT =(V HIGN +V LOW ) / 2, where V LOW is the low level of the limiter circuit output signal, V HIGN is the high level of the output signal of the limiter circuit. When the amplitude of the AC signal output by the limiter circuit changes, since the first active diode is limited to a low level by capacitor C3 and the second active diode is limited to a high level by capacitor C4, V OUT The voltage maintains the size before the signal changes. Therefore, the output voltage V OUT =(V HIGN +V LOW ) / 2 can be adjusted in real time according to the changes of the input signal to achieve the purpose of dynamic threshold extraction.

[0036] S6. The dynamic threshold value output by the dynamic threshold value extraction circuit is used as the intermediate value of the high-speed comparator. The high-speed comparator converts the signal to be compared into a digital signal. The digital signal is the baseband data signal transmitted by the transmitter.

[0037] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A receiver demodulator for demodulating an intermediate frequency signal of an OOK receiver, characterized in that: It includes an automatic gain control circuit, a peak detection circuit, a limiter circuit, a gain control voltage adjustment circuit, a dynamic threshold extraction circuit and a high-speed comparator, wherein the input end of the automatic gain control circuit is connected to an intermediate frequency signal, and the output end is sequentially connected to the input ends of the peak detection circuit and the limiter circuit, the output end of the limiter circuit is respectively connected to the input end of the high-speed comparator, the input end of the dynamic threshold extraction circuit, and the input end of the gain control voltage adjustment circuit, the output end of the gain control voltage adjustment circuit is connected to the automatic gain control circuit, the output end of the dynamic threshold extraction circuit is connected to the input end of the high-speed comparator, and the output end of the high-speed comparator is the signal output of the demodulation circuit; The dynamic threshold extraction circuit includes a first operational amplifier A1, a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, switches S1, SN1, S2, SN2, capacitors C1, C2, C3, C4, a first NMOS tube M1 and a second NMOS tube M2, wherein the switch S1 and the switch SN1 are complementary switches, and the switch S2 and the switch SN2 are complementary switches; wherein the first operational amplifier A1 and the first NMOS tube form a first active diode structure, and the second operational amplifier A2 and the second NMOS tube M2 form a second active diode structure; the output of the limiter is connected to the inverting input terminal of the first operational amplifier A1 and the non-inverting input terminal of the second operational amplifier A2; the first active diode is connected to the first operational amplifier A1 and the second operational amplifier A2; The output end of the active diode is respectively connected to the non-inverting input end of the third operational amplifier A3, the switch S1, and the capacitor C3; the output end of the second active diode is respectively connected to the non-inverting input end of the fourth operational amplifier A4, the switch S2, and the capacitor C4; the output end of the third operational amplifier A3 is connected to the reverse input end of the third operational amplifier as a first buffer, and is also connected to the switch SN2 and the resistor R1; the output end of the fourth operational amplifier A4 is connected to the reverse input end of the fourth operational amplifier as a second buffer, and is also connected to the switches SN1 and R2; the switches S1 and SN1 are connected to the charging capacitor C1; the switches S2 and SN2 are connected to the discharging capacitor C2; the first voltage-dividing resistor R1 is connected to the second voltage-dividing resistor R2 as the output of the dynamic threshold extraction circuit.

2. The receiver demodulator according to claim 1, characterized in that The automatic gain control circuit comprises five stages of variable gain amplifiers and a stage of fixed gain amplifier circuit connected in sequence, and an AC coupling capacitor is connected in series between the input end of each stage of the variable gain amplifier, the fifth stage of the variable gain amplifier and the fixed gain amplifier circuit.

3. The receiver demodulator according to claim 2, characterized in that: The gain control voltage adjustment circuit includes a first comparator, a charge pump and a gain control filter capacitor, the inverting input end of the first comparator is connected to the output of the limiter circuit, the non-inverting input end of the first comparator is connected to the reference voltage VREF, and the output end of the first comparator is connected to the switch of the charge pump.

4. The receiver demodulator according to claim 3, characterized in that: The limiter circuit is a diode, a MOS tube with a diode structure or a buffer structure.

5. A peak detector, applied to the receiver demodulator of claim 3, characterized in that: The peak detector includes the peak detection circuit, which includes two second comparators, switches S1 and S2, voltage-dividing resistors R01 and R02, capacitor C0 and RC filter, and the positive input terminals of the two second comparators are respectively connected to the intermediate frequency differential signal V INP 、V INN , the negative input end is connected to the voltage-dividing resistors R01 and R02, the voltage-dividing resistors R01 and R02 and the positive input ends of the two second comparators form a symmetrical structure, and the output ends of the two second comparators are connected to the capacitor and the RC filter through switches S1 and S2 respectively.

6. A signal demodulation method, applied to a receiver demodulator as claimed in claim 3, or applied to a demodulator comprising a peak detector as claimed in claim 5, characterized in that: The method comprises: S1, inputting an intermediate frequency signal to an input end of the automatic gain control circuit, amplifying the intermediate frequency signal through the automatic gain control circuit, and obtaining an amplified intermediate frequency signal; S2, the amplified intermediate frequency signal is input to the peak detection circuit, and the peak detection circuit performs envelope detection to demodulate the baseband signal on the envelope of the amplified intermediate frequency signal; S3, inputting the baseband signal to the limiter circuit, filtering the baseband signal through the limiter circuit, and outputting three signals: a feedback signal, an AC signal, and a signal to be compared, wherein the feedback signal is output to the gain control voltage adjustment circuit, the AC signal is output to the dynamic threshold extraction circuit, and the signal to be compared is output to the comparator circuit; S4, when the feedback signal is less than the reference voltage VREF of the gain control voltage adjustment circuit, the charge pump is turned off for charging, turned on for discharging and discharges the gain control filter capacitor, and at the same time adjusts the gain of the gain control voltage adjustment circuit so that the feedback signal output by the limiter is stabilized at the reference voltage VREF; S5, adjusting the AC signal through the dynamic threshold extraction circuit to extract a dynamic threshold; S6. Using the dynamic threshold output by the dynamic threshold extraction circuit as the intermediate value of the high-speed comparator, converting the signal to be compared into a digital signal through the high-speed comparator, wherein the digital signal is the baseband data signal transmitted by the transmitter.

7. The signal demodulation method according to claim 6, characterized in that: In step S5, the AC signal is adjusted by the dynamic threshold extraction circuit. The adjustment method includes: controlling the switches S1, SN1, S2, and SN2 so that the AC signal output by the limiter circuit is high potential or low potential. The specific control method includes: S51, the switch SN1 is closed, the switch S1 is opened, and the high level output by the fourth operational amplifier charges the capacitor C1; when the switch SN1 is opened, the switch S1 is closed, the capacitor C1 discharges the capacitor C3, the voltage of the capacitor C3 increases, the voltage of the non-inverting input terminal of the first operational amplifier A1 is greater than the voltage of the inverting input terminal of the first operational amplifier A1, the first NMOS tube M1 is turned on, and the capacitor C3 discharges to the first current source again, until the voltage on the capacitor C3 is less than the voltage of the inverting input terminal of the first operational amplifier A1 again, the first NMOS tube M1 is turned off, so that the AC signal output by the limiter circuit is maintained at a low potential V LOW ; S52, the switch S2 is opened, the switch SN2 is closed, and the capacitor C2 is discharged; when the switch S2 is closed, the switch SN2 is opened, the high level on the capacitor C4 discharges the capacitor C2, the voltage of the capacitor C4 decreases, the voltage of the inverting input terminal of the second operational amplifier A2 is less than the voltage of the non-inverting input terminal of the second operational amplifier A2, the second NMOS tube M2 is turned on, and the second current source charges the capacitor C4 again until the voltage on the capacitor C4 is greater than the voltage of the non-inverting input terminal of the second operational amplifier A2 again, the first NMOS tube M2 is turned off, so that the AC signal output by the limiter circuit is maintained at a high potential V HIGN ; S53, the output voltage V of the dynamic threshold extraction circuit OUT =(V HIGN +V LOW ) / 2, where V LOW The limiter circuit outputs a low level signal, V HIGN is the high level of the limiter circuit output signal.

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