Chip packaging structure and forming method thereof

Abstract

A chip packaging structure and a method for forming the same are provided. The method comprises arranging a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip are separated by a gap. The method further comprises arranging an annular structure on the circuit substrate. The annular structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a chip packaging structure and a method for forming the same, and in particular, to a chip packaging structure having a ring structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are usually manufactured by sequentially depositing insulating layers or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements thereon.

[0003] Typically, many integrated circuits (ICs) are manufactured on semiconductor wafers, and technological advances in integrated circuit materials and design have produced several generations of integrated circuits. Each generation of circuits is smaller and more complex than the previous generation. The processing and packaging of the die of the wafer can be performed at the wafer-level, and various technologies have been developed for chip-level packaging. Since the chip packaging structure may need to contain multiple chips with multiple functions, it is still challenging to form a reliable chip packaging structure with multiple chips. Summary of the invention

[0004] The present disclosure provides a method for forming a chip packaging structure. The method includes arranging a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip are separated by a gap. The method also includes arranging an annular structure on the circuit substrate. The annular structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

[0005] The present disclosure provides a method for forming a chip packaging structure. The method includes arranging a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes arranging an annular structure on the circuit substrate. The annular structure surrounds the first chip structure and the second chip structure, and the annular structure includes a first thinner portion and a first thicker portion connected to each other, and the gap is close to the first thinner portion.

[0006] The present disclosure provides a chip packaging structure. The chip packaging structure includes a circuit substrate. The chip packaging structure includes a first chip structure and a second chip structure located on the circuit substrate. The first chip structure and the second chip structure are separated by a gap. The chip packaging structure includes a ring structure located on the circuit substrate. The circuit substrate has an opening, the first chip structure and the second chip structure are located in the opening, the opening has an inner wall, the inner wall has a recess, and the gap extends toward the recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The content of the disclosed embodiments can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0008] Figure 1A-1E Schematic cross-sectional views of various stages of a process for forming a chip packaging structure according to some embodiments.

[0009] Figure 1A-1 According to some embodiments Figure 1A A top view schematic diagram of a chip packaging structure.

[0010] Figure 1B-1 According to some embodiments Figure 1B A top view schematic diagram of a chip packaging structure.

[0011] Figure 1C-1 According to some embodiments Figure 1C A top view schematic diagram of a chip packaging structure.

[0012] Figure 1D-1 According to some embodiments Figure 1D A top view schematic diagram of a chip packaging structure.

[0013] Figure 1D-2 According to some embodiments Figure 1D A perspective schematic diagram of a chip packaging structure.

[0014] Figure 1D-3 According to some embodiments Figure 1D A top view schematically showing a ring structure of a chip packaging structure.

[0015] Figure 1E-1 According to some embodiments Figure 1E A top view schematic diagram of a chip packaging structure.

[0016] Figure 1E-2 According to some embodiments Figure 1E A perspective schematic diagram of a chip packaging structure.

[0017] Figure 2A is a cross-sectional schematic diagram showing a chip packaging structure according to some embodiments.

[0018] Figure 2B According to some embodiments, Figure 2A A top view schematic diagram of a chip packaging structure.

[0019] Figure 2C According to some embodiments, Figure 2A A perspective schematic diagram of a chip packaging structure.

[0020] Figure 2D According to some embodiments, Figure 2A A perspective diagram of a ring structure.

[0021] Figure 2E According to some embodiments, Figure 2A A top view schematically showing a chip packaging structure without a ring structure.

[0022] Figure 3A is a perspective schematic diagram showing a chip packaging structure according to some embodiments.

[0023] Figure 3B According to some embodiments, Figure 3A A top view schematically showing a chip packaging structure without a ring structure.

[0024] Figure 4A is a cross-sectional schematic diagram showing a chip packaging structure according to some embodiments.

[0025] Figure 4B According to some embodiments, Figure 4A A top view schematic diagram of a chip packaging structure.

[0026] Figure 4C According to some embodiments, Figure 4A A perspective schematic diagram of a chip packaging structure.

[0027] Figure 4D According to some embodiments, Figure 4A A top view schematically showing a chip packaging structure without a ring structure.

[0028] Figure 4E According to some embodiments, Figure 4A Schematic diagram of the ring structure and the expansion of the adhesion layer.

[0029] Figure 5 is a top view schematically showing a chip packaging structure according to some embodiments.

[0030] Figure 6is a top view schematically showing a chip packaging structure according to some embodiments.

[0031] Figure 7 is a top view schematically showing a chip packaging structure according to some embodiments.

[0032] Figure 8 is a top view schematically showing a chip packaging structure according to some embodiments.

[0033] Fig. 9 is a cross-sectional schematic diagram showing a chip packaging structure according to some embodiments.

[0034] Fig.10 is a cross-sectional schematic diagram showing a chip packaging structure according to some embodiments.

[0035] The reference numerals are described as follows:

[0036] 100: Chip packaging structure

[0037] 108: Conductive column

[0038] 110: Rewiring Structure

[0039] 111: Bottom

[0040] 112: Circuit layer

[0041] 114: Conductive vias

[0042] 116: Dielectric layer

[0043] 122: Chip structure

[0044] 122a: Sidewall

[0045] 124: Conductive column

[0046] 130: Bottom filling layer

[0047] 140: Molding layer

[0048] 150: Solder bump

[0049] 160: Circuit board

[0050] 162: Dielectric layer

[0051] 164: Conductive pad

[0052] 166: Circuit layer

[0053] 168: Conductive vias

[0054] 170: Bottom filling layer

[0055] 180: Installation

[0056] 190: Adhesive layer

[0057] 192: Groove

[0058] 194: Opening

[0059] 194a: Inner wall

[0060] 194b: Depression

[0061] 196: Sidewall

[0062] 200: Chip packaging structure

[0063] 210: Ring structure

[0064] 210A: Lower section

[0065] 210B: Upper part

[0066] 211: Bottom

[0067] 211A: Part

[0068] 212: Groove

[0069] 212A: Groove

[0070] 213: Sidewall

[0071] 214: Opening

[0072] 214a: Inner wall

[0073] 214b: Depression

[0074] 214b1: Inner wall

[0075] 214A: Depression

[0076] 215: Strip part

[0077] 215a: End

[0078] 216: Outer Ring

[0079] 216a: Top surface

[0080] 216b: Top surface

[0081] 216A: Thinner part

[0082] 216C: Thinner part

[0083] 216B: Thicker part

[0084] 216D: Thicker part

[0085] 217: Strip part

[0086] 217a: End

[0087] 218: Strip part

[0088] 219: Strip part

[0089] 220: Cover

[0090] 300: Chip packaging structure

[0091] 400: Chip packaging structure

[0092] 410: Adhesive layer

[0093] 412: Groove

[0094] 414: Opening

[0095] 414a: Inner wall

[0096] 414b: Depression

[0097] 500: Chip packaging structure

[0098] 510: Ring structure

[0099] 510A: Narrower part

[0100] 510B: Wider part

[0101] 512: Opening

[0102] 512a: Inner wall

[0103] 512b: Concave

[0104] 600: Chip packaging structure

[0105] 612: Partial

[0106] 614: Part

[0107] 616: Gap

[0108] 700: Chip packaging structure

[0109] 800: Chip packaging structure

[0110] A: Adhesive layer

[0111] D1: Distance

[0112] D2: Distance

[0113] D3: Horizontal distance

[0114] G1: Clearance

[0115] G2: Gap

[0116] P: Package structure

[0117] W122: Width

[0118] W220: Width

[0119] W510A: Line width

[0120] W510B: Line width DETAILED DESCRIPTION

[0121] The following content provides many different embodiments or examples for implementing different components of the disclosed embodiments. Specific embodiments or examples of components and configurations are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to limit the disclosed embodiments. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. For the sake of brevity and clarity, various different components can be displayed arbitrarily in different sizes. In addition, the disclosed embodiments may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0122] In addition, spatially relative terms may be used herein, such as "under," "beneath," "below," "above," "above," and other similar terms may be used herein to describe the relationship between an element or component as shown in the figure and other elements or components. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figure. When the device is rotated to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein may also be interpreted based on the rotated orientation.

[0123] In the description, the term "substantially", such as "substantially flat" or "substantially coplanar", will be understood by those of ordinary skill in the art. In some embodiments, the adjective can be removed substantially. Where applicable, the term "substantially" may also include embodiments with "entirely", "completely", "all". Where applicable, the term "substantially" may also relate to 90% or more, such as 95% or more, in particular 99% or more, or include 100%. Furthermore, the term "substantially parallel" or "substantially perpendicular" will be interpreted as not excluding minor deviations from a specific arrangement, and may include, for example, deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition X that is "substantially free" of Y may be completely free of Y.

[0124] The term "about", when used in connection with a specific distance or dimension, should be interpreted as not excluding minor deviations from the specific distance or dimension and may include, for example, deviations of up to 10°. The term "about" in relation to a numerical value x may mean x±5 or 10%.

[0125] Some embodiments are disclosed herein. Additional steps may be provided before, during, or after the stages mentioned in these embodiments. Some of the stages described may be replaced or deleted for different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or deleted for different embodiments. Although some embodiments are discussed in terms of steps performed in a specific order, these steps may be performed in other logical orders.

[0126] Other components or processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3D-IC device. The test structure may include, for example, a testing pad formed on a redistribution layer or substrate that enables the 3D package or 3D-IC to be tested, a probe or probe card to be used, and the like. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that integrates intermediate verification of identifying good dies to improve yield and reduce costs.

[0127] Figure 1A-1E Schematic cross-sectional views of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 1A-1 According to some embodiments Figure 1A A top view schematic diagram of a chip packaging structure.

[0128] According to some embodiments, a package P is provided, such as Figure 1A and Figure 1A-1 According to some embodiments, the package P includes a redistribution structure 110, a chip structure 122, a conductive pillar 124, an underfill layer 130, and a molding layer 140. According to some embodiments, the redistribution structure 110 includes a wiring layer 112, a conductive via 114, and a dielectric layer 116.

[0129] According to some embodiments, the circuit layers 112 and the conductive vias 114 are formed in the dielectric layer 116. According to some embodiments, the conductive vias 114 are electrically connected between different circuit layers 112, such as Figure 1A According to some embodiments, for simplicity, Figure 1A Only two wiring layers 112 are shown.

[0130] According to some embodiments, dielectric layer 116 is formed of an insulating material, such as a polymer material (eg, polyphenylene sulfide). The present invention may be a photosensitive material such as polybenzoxazole, polyimide, or a photosensitive material), a nitride (eg, silicon nitride), an oxide (eg, silicon oxide), silicon oxynitride, or the like.

[0131] According to some embodiments, a deposition process (e.g., a chemical vapor deposition process or a physical vapor deposition process), a lithography process, and an etching process are used to form the dielectric layer 116. According to some embodiments, the wiring layer 112 and the conductive via 114 are formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or an alloy thereof.

[0132] According to some embodiments, the chip structures 122 are bonded to the redistribution structure 110 through the conductive pillars 124. According to some embodiments, the chip structures 122 are separated from each other by a gap G1. According to some embodiments, the conductive pillars 124 are physically and electrically connected between the chip structures 122 and the redistribution structure 110. According to some embodiments, each chip structure 122 includes a chip, such as a system on chip (SoC).

[0133] According to some embodiments, the chip includes a substrate. In some embodiments, the substrate is formed of an elemental semiconductor material, which includes silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure. In some other embodiments, the substrate is formed of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), an alloy semiconductor (e.g., SiGe, or GaAsP), or a combination of the foregoing. The substrate may also include a multilayer semiconductor, a semiconductor on an insulator (SOI, such as silicon on an insulator or germanium on an insulator), or a combination of the foregoing.

[0134] In some embodiments, the substrate includes various device elements. In some embodiments, the various device elements are formed in and / or on the substrate. For simplicity and clarity, the device elements are not shown in the figure. The various device elements exemplified include active elements, passive elements, other suitable elements, or a combination of the foregoing. The active element may include a transistor or a diode (not shown) formed at the surface of the substrate. The passive element may include a resistor, a capacitor, or other suitable passive element.

[0135] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (pFETs / nFETs), etc. Various processes (e.g., front-end-of-line (FEOL) semiconductor manufacturing processes) may be performed to form various device elements. The front-end semiconductor manufacturing processes may include deposition, etching, implantation, lithography, annealing, planarization, one or more other suitable processes, or a combination of the foregoing.

[0136] In some embodiments, isolation features (not shown) are formed in the substrate. The isolation features are used to define the active region and electrically isolate various device elements formed in the active region and in and / or on the substrate. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0137] In some other embodiments, the chip structure 122 includes a chip packaging structure. In some embodiments, the chip packaging structure includes one chip. In some other embodiments, the chip packaging structure includes multiple chips that are arranged side by side or stacked on each other (such as a 3D package or 3DIC device).

[0138] According to some embodiments, the conductive pillars 124 are formed of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or zinc (Sn). According to some embodiments, the conductive pillars 124 are formed using a plating process, such as an electroplating process.

[0139] According to some embodiments, the bottom filling layer 130 is disposed between the chip structure 122 and the redistribution structure 110. Figure 1A and Figure 1A-1 According to some embodiments, the underfill layer 130 surrounds the conductive pillars 124 and the chip structure 122 .

[0140] According to some embodiments, the underfill layer 130 extends into the gap G1. According to some embodiments, the gap G1 is filled by the underfill layer 130. According to some embodiments, the underfill layer 130 is formed of an insulating material, such as a polymer material.

[0141] According to some embodiments, the mold layer 140 is formed on the redistribution structure 110 and the bottom filling layer 130, such as Figure 1A and Figure 1A-1 According to some embodiments, the mold layer 140 surrounds the chip structure 122, the conductive pillars 124, and the underfill layer 130. According to some embodiments, the mold layer 140 is formed of an insulating material, such as epoxy.

[0142] According to some embodiments, the conductive pillar 108 is formed on the bottom surface 111 of the redistribution structure 110, such as Figure 1A and Figure 1A-1 According to some embodiments, the conductive pillar 108 is formed of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or zinc (Sn). According to some embodiments, the conductive pillar 108 is formed using a plating process, such as an electroplating process.

[0143] According to some embodiments, a solder bump 150 is formed on the conductive pillar 108, such as Figure 1A and Figure 1A-1According to some embodiments, the solder bump 150 is formed of tin (Sin) or other suitable conductive materials having a melting point lower than the melting point of the conductive pillar 108. According to some embodiments, the solder bump 150 is formed using a plating process, such as an electroplating process.

[0144] Figure 1B-1 According to some embodiments Figure 1B According to some embodiments, the package structure P is bonded to a wiring substrate 160 through solder bumps 150, such as Figure 1B and Figure 1B-1 According to some embodiments, the circuit substrate 160 includes a dielectric layer 162 , a conductive pad 164 , a circuit layer 166 , and a conductive via 168 .

[0145] According to some embodiments, conductive pads 164 are formed on dielectric layer 162. According to some embodiments, solder bumps 150 are bonded to conductive pads 164. According to some embodiments, wiring layers 166 and conductive vias 168 are formed in dielectric layer 162.

[0146] According to some embodiments, the conductive vias 168 are electrically connected between different circuit layers 166, and are connected between the circuit layer 166 and the conductive pad 164. According to some embodiments, for simplicity, Figure 1B Only two wiring layers 166 are shown.

[0147] According to some embodiments, dielectric layer 162 is formed of an insulating material, such as a polymer material (eg, polyphenylene sulfide). The dielectric layer 162 may be formed by a deposition process (e.g., a chemical vapor deposition process or a physical vapor deposition process), a lithography process, and an etching process.

[0148] According to some embodiments, the conductive pad 164 is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or an alloy thereof. According to some embodiments, the wiring layer 166 is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or an alloy thereof. According to some embodiments, the conductive via 168 is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or an alloy thereof.

[0149] In some embodiments, the conductive pad 164, the wiring layer 166, and the conductive via 168 are formed of the same material. In other embodiments, the conductive pad 164, the wiring layer 166, and the conductive via 168 are formed of different materials.

[0150] According to some embodiments, a bottom filling layer 170 is formed between the package body P and the circuit substrate 160. Figure 1B and Figure 1B-1 According to some embodiments, the filling layer 170 surrounds the conductive pillars 108 , the solder bumps 150 , and the package body P. According to some embodiments, the underfill layer 170 is formed of an insulating material, such as a polymer material.

[0151] According to some embodiments, the device 180 is bonded to the circuit substrate 160, for example, by surface mount technology (SMT), such as Figure 1B and Figure 1B-1 The device 180 includes a passive device, other suitable devices, or a combination thereof. The passive device includes a resistor, a capacitor, an inductor, or other suitable passive devices.

[0152] Figure 1C-1 According to some embodiments Figure 1C According to some embodiments, an adhesive layer 190 is formed on the circuit substrate 160, such as Figure 1C and 1C-1 According to some embodiments, the adhesive layer 190 has a groove 192 and an opening 194. According to some embodiments, the device 180 is located in the groove 192. According to some embodiments, the package body P is located in the opening 194.

[0153] According to some embodiments, the groove 192 surrounds the opening 194. According to some embodiments, the opening 194 has an inner wall 194a. According to some embodiments, the inner wall 194a has a recess 194b. According to some embodiments, each recess 194b is connected to the corresponding groove 192. According to some embodiments, the gap G1 extends toward the recess 194b. According to some embodiments, the adhesive layer 190 is formed of a polymer material, such as epoxy or silicone.

[0154] Figure 1D-1 According to some embodiments Figure 1D A top view schematic diagram of a chip packaging structure. Figure 1D-2 According to some embodiments Figure 1D A perspective diagram of the chip packaging structure. For simplicity, Figure 1D-2 The underfill layer 170 is omitted.

[0155] According to some embodiments, the annular structure 210 is disposed on the adhesive layer 190, such as Figure 1D , Figure 1D-1 and Figure 1D-2 shown. Figure 1D-3 According to some embodiments Figure 1D 2 is a top view of a ring structure 210 of a chip package structure. According to some embodiments, the ring structure 210 has a groove 212 and an opening 214, such as Figure 1D , Figure 1D-1 , Figure 1D-2 and Figure 1D-3 According to some embodiments, the groove 212 surrounds the opening 214 .

[0156] According to some embodiments, the groove 212 has a substantially rectangular shape. According to some embodiments, the opening 214 has a substantially rectangular shape. According to some embodiments, the groove 212 is respectively adjacent to four inner walls 214a of the opening 214. According to some embodiments, the device 180 is located in the groove 212. According to some embodiments, the groove 212 and the opening 214 are formed using a milling process or a wire cutting process.

[0157] According to some embodiments, the opening 194 of the adhesive layer 190 is located below the opening 214, such as Figure 1D , Figure 1D-1 and Figure 1D-2 As shown. According to some embodiments, the package body P is located in the opening 214. Two of the inner walls 214a have recesses 214b. According to some embodiments, each recess 214b is connected to the corresponding groove 212 and the opening 214. According to some embodiments, the recess 214b has a substantially rectangular shape.

[0158] According to some embodiments, the gap G1 extends toward the recess 214b. According to some embodiments, the recess 194b of the adhesive layer 190 is located below the recess 214b. According to some embodiments, the recesses 214b and 194b have substantially the same width W1.

[0159] According to some embodiments, the ring structure 210 has an outer ring 216 and strip-shaped portions 215, 217, 218 and 219. According to some embodiments, the strip-shaped portions 215, 217, 218 and 219 are also called ribs. According to some embodiments, the strip-shaped portions 215, 217, 218 and 219 are surrounded by the outer ring 216.

[0160] According to some embodiments, the strip portion 215 has a substantially rectangular shape. According to some embodiments, the strip portion 215 has opposite ends 215a connected to the outer ring 216. According to some embodiments, the recess 214b is located in the strip portion 215. According to some embodiments, the recess 214b passes through the strip portion 215.

[0161] According to some embodiments, the strip portion 217 has a substantially rectangular shape. According to some embodiments, the strip portion 217 has opposite ends 217a connected to the outer ring 216. According to some embodiments, the recess 214b is located in the strip portion 217. According to some embodiments, the recess 214b passes through the strip portion 217.

[0162] According to some embodiments, strip portion 218 has a substantially rectangular shape. According to some embodiments, strip portion 218 is interposed between strip portion 215 and strip portion 217. According to some embodiments, strip portion 218 is connected to strip portion 215 and strip portion 217.

[0163] According to some embodiments, the strip portion 219 has a substantially rectangular shape. According to some embodiments, the strip portion 219 is between the strip portion 215 and the strip portion 217. According to some embodiments, the strip portion 219 is connected to the strip portion 215 and the strip portion 217. Therefore, according to some embodiments, the strip portions 218, 215, and 217 together form a first I-shaped structure, and the strip portions 219, 215, and 217 together form a second I-shaped structure. According to some embodiments, the two I-shaped structures are disposed on opposite sides of the package body P.

[0164] In some embodiments, the distance D1 between the chip structure 122 and the strip portion 215 ranges from about 7 centimeters (mm) to about 20 mm. According to some embodiments, if the distance D1 is less than about 7 mm, the stress at the corner of the chip is large, which is undesirable. According to some embodiments, if the distance D1 is greater than about 20 mm, the size of the ring structure 210 is large, which occupies too much surface area of ​​the circuit substrate 160.

[0165] In some embodiments, the distance D2 between the chip structure 122 and the strip portion 218 ranges from about 7 mm to about 20 mm. According to some embodiments, if the distance D2 is less than about 7 mm, the stress at the corner of the chip is large, which is undesirable. According to some embodiments, if the distance D2 is greater than about 20 mm, the size of the ring structure 210 is large, which occupies too much surface area of ​​the circuit substrate 160.

[0166] According to some embodiments, the chip structure 122 has a width W122. According to some embodiments, each chip structure 122 has a sidewall 122a facing the gap G1. In some embodiments, a lateral distance D3 is between the sidewall 122a and the inner wall 214b1 of the recess 214b. In some embodiments, a ratio of the lateral distance D3 to the width W122 ranges from about 0.3 to about 0.7. According to some embodiments, the ratio (D3 / W122) ranges from about 0.5 to about 0.7. In some embodiments, a distance D4 between the sidewalls 122a ranges from about 40 nanometers (nm) to about 120 nm.

[0167] According to some embodiments, the ring structure 210 is formed of a rigid material, such as metal (eg, copper or iron), the aforementioned alloys (eg, stainless steel), or other suitable materials that are harder than the circuit substrate 160 .

[0168] Figure 1E-1 According to some embodiments Figure 1E A top view schematic diagram of a chip packaging structure. Figure 1E-2 According to some embodiments Figure 1E A perspective diagram of the chip packaging structure. For simplicity, Figure 1E-2 The underfill layer 170 and the adhesive layer A are omitted.

[0169] According to some embodiments, a lid 220 is disposed on the chip structure 122, such as Figure 1E , Figure 1E-1 and Figure 1E-2 According to some embodiments, in this step, the chip package structure 100 is basically formed. According to some embodiments, the cover 220 is narrower than the chip structure 122 below. That is, according to some embodiments, the width W220 of the cover 220 is smaller than the width W122 of the chip structure 122.

[0170] According to some embodiments, the cover 220 is formed of a high thermal conductivity material, such as a metal material (eg, aluminum or copper), an alloy material (eg, stainless steel), or aluminum-silicon carbide (AlSiC).

[0171] In some embodiments, an adhesive layer A is formed between the cover 220 and the chip structure 122. Figure 1E According to some embodiments, the adhesive layer A is formed of a conductive polymer and a metal (eg, silver glue) or a polymer (eg, epoxy or silicone). For simplicity, Figure 1E-2 The underfill layer 170 and the adhesive layer A are omitted.

[0172] According to some embodiments, when a ring structure is used to reduce the warpage of the circuit substrate 160, stress is easily concentrated in the bottom filling layer 130 in the gap G1. According to some embodiments, stress is easy to cause cracks or delamination in the bottom filling layer 130 in the gap G1. Therefore, according to some embodiments, the method of the embodiment of the present disclosure removes the portion of the ring structure 210 close to the gap G1 to reduce the anti-warpage ability of the ring structure 210 close to the gap G1. In this way, according to some embodiments, the stress of the bottom filling layer 130 concentrated in the gap G1 is reduced. According to some embodiments, because the method of the embodiment of the present disclosure only removes the portion of the ring structure 210 close to the gap G1, the anti-warpage ability of the entire ring structure 210 is roughly maintained within an acceptable range. According to some embodiments, the yield of the chip packaging structure 100 is thus improved.

[0173] According to some embodiments, the cover 220 can reduce the warping of the chip structure 122, which can reduce the warping of the circuit substrate 160. According to some embodiments, the chip package structure 100 is thus improved.

[0174] In some embodiments, the sidewall 196 of the adhesive layer 190 is aligned with or coplanar with the sidewall 213 of the annular structure 210. In other embodiments, the sidewall 196 of the adhesive layer 190 is recessed from the sidewall 213 of the annular structure 210, such as Fig. 9 In some other embodiments, the side wall 196 of the adhesive layer 190 protrudes from the side wall 213 of the annular structure 210, as shown in FIG. Fig.10 shown.

[0175] Figure 2A According to some embodiments, a chip package structure 200 is shown. Figure 2B According to some embodiments, Figure 2A FIG. 2 is a top view of a chip package structure 200 . Figure 2C According to some embodiments, Figure 2A Schematic diagram of a chip package structure 200. For simplicity, Figure 2C The underfill layer 170 and the adhesive layer A are omitted.

[0176] Figure 2D According to some embodiments, Figure 2A According to some embodiments, Figure 2D It is observed from the bottom surface 211 of the annular structure 210 . Figure 2E According to some embodiments, Figure 2A A top view of a chip package structure 200 without the ring structure 210

[0177] According to some embodiments, the chip package structure 200 is similar to Figure 1E The chip package structure 100 has a lower portion 210A and an upper portion 210B, and the two portions have different structures, such as Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E According to some embodiments, the ring structure 210 has an opening 214 . According to some embodiments, the package body P is located in the opening 214 .

[0178] According to some embodiments, the structure of the lower portion 210A is similar to Figure 1E According to some embodiments, the lower portion 210A has a groove 212A and a recess 214A, as shown in FIGS. 2B and 2D. According to some embodiments, the groove 212A surrounds the opening 214. According to some embodiments, each recess 214A is connected to the corresponding groove 212A and the opening 214. According to some embodiments, the device 180 is located in the groove 212A, as shown in FIGS. Figure 2A shown.

[0179] According to some embodiments, the upper portion 210B is a continuous plate that is located above the lower portion 210A and covers the grooves 212A and the recesses 214A, such as Figure 2A , Figure 2B and Figure 2D According to some embodiments, the upper portion 210B is thinner than the lower portion 210A.

[0180] According to some embodiments, the ring structure 210 includes thinner portions 216A and 216C and thicker portions 216B and 216D, such as Figure 2A , Figure 2B and Figure 2D According to some embodiments, thinner portion 216A is opposite to thinner portion 216C. According to some embodiments, thinner portion 216A is connected between thicker portions 216B and 216D. According to some embodiments, thinner portion 216C is connected between thicker portions 216B and 216D.

[0181] According to some embodiments, the gap G1 between the chip structures 122 extends toward the thinner portions 216A and 216C, such as Figure 2B , Figure 2C According to some embodiments, the gap G1 is close to the thinner portions 216A and 216C. According to some embodiments, the top surface 216a of the thinner portion 216A is substantially coplanar with the top surface 216b of the thicker portion 216B, as shown in FIG. Figure 2C shown.

[0182] Figure 3A is a perspective view of a chip package structure 300 according to some embodiments. Figure 3B According to some embodiments, Figure 3A The chip packaging structure 300 is a top view without the ring structure 210. For simplicity, Figure 3A The underfill layer 170 and the adhesive layer A are omitted.

[0183] According to some embodiments, the chip package structure 300 is similar to Figure 2C and Figure 2E The chip package structure 200, except Figure 3A and Figure 3B The depression 194b of the adhesive layer 190 is greater than Figure 2C and Figure 2E The width of the depression 194b of the adhesive layer 190 is as follows: Figure 3A and Figure 3B shown.

[0184] According to some embodiments, the depression 194b is wider than the depression 214A of the lower portion 210A, such as Figure 3A and Figure 3B Therefore, according to some embodiments, the portion 211A of the lower portion 210A is not bonded to the circuit substrate 160 through the adhesive layer 190 . According to some embodiments, there is a gap G2 between the portion 211A and the circuit substrate 160 .

[0185] Figure 4A is a cross-sectional schematic diagram showing a chip package structure 400 according to some embodiments. Figure 4B According to some embodiments, Figure 4A FIG. 4 is a top view of a chip packaging structure 400 .

[0186] Figure 4C According to some embodiments Figure 4A 4 is a perspective schematic diagram of a chip packaging structure 400. For simplicity, Figure 4C The underfill layer 170 and the adhesive layer A are omitted. Figure 4D According to some embodiments, Figure 4A FIG. 4 is a top view of a chip package structure 400 without the ring structure 210 . Figure 4E According to some embodiments, Figure 4A Schematic diagram of the expansion of the annular structure 210 and the adhesive layer 190.

[0187] According to some embodiments, the chip package structure 400 is similar to Figure 2A , Figure 2B and Figure 2CThe chip package structure 200 has an adhesive layer 410 located between the lower portion 210A and the upper portion 210B in addition to the ring structure 210 of the chip package structure 400. Figure 4A , Figure 4B and Figure 4C shown.

[0188] According to some embodiments, the adhesive layer 410 has a groove 412 and an opening 414, such as Figure 4D and Figure 4E According to some embodiments, the device 180 is located in the groove 412. According to some embodiments, the groove 412 surrounds the opening 414. According to some embodiments, the opening 414 has an inner wall 414a.

[0189] According to some embodiments, the inner wall 414a has a recess 414b. According to some embodiments, each recess 414b is connected to the corresponding groove 412. According to some embodiments, the gap G1 extends toward the recess 414b. According to some embodiments, the adhesive layer 410 is formed of a polymer material, such as epoxy or silicone.

[0190] Figure 5 FIG. 5 is a top view of a chip package structure 500 according to some embodiments. According to some embodiments, the chip package structure 500 is similar to Figure 1E-1 The chip package structure 100 has no ring structure 510 except that the chip package structure 500 has no Figure 1E-1 The groove 212 of the chip package structure 100 is as follows: Figure 5 shown.

[0191] According to some embodiments, the annular structure 510 has an opening 512. According to some embodiments, the opening 512 has an inner wall 512a. According to some embodiments, the inner wall 512a has a recess 512b. According to some embodiments, the recesses 512b are opposite to each other. According to some embodiments, the gap G1 between the chip structures 122 extends toward the recess 512b.

[0192] According to some embodiments, the ring structure 510 has a narrower portion 510A and a wider portion 510B. According to some embodiments, a line width W510A of the narrower portion 510A is less than a line width W510B of the wider portion 510B. According to some embodiments, the gap G1 between the chip structures 122 extends toward the narrower portion 510A.

[0193] Figure 6 6 is a top view of a chip package structure 600 according to some embodiments. According to some embodiments, the chip package structure 600 is similar to Figure 5The chip package structure 500 is shown in FIG. 5 , except that the ring structure 610 of the chip package structure 600 is divided into parts 612 and 614 by a gap 616, as shown in FIG. Figure 6 According to some embodiments, portions 612 and 614 are spaced apart from each other. According to some embodiments, gap G1 extends toward gap 616.

[0194] Figure 7 is a top view schematically showing a chip package structure 700 according to some embodiments. According to some embodiments, the chip package structure 700 is similar to Figure 1E-1 The chip package structure 100 has the exception that the recess 194b does not pass through the strip portions 215 and 217. Figure 7 shown.

[0195] Figure 8 FIG. 8 is a top view of a chip package structure 800 according to some embodiments. According to some embodiments, the chip package structure 800 is similar to Figure 1E-1 The chip package structure 100 has the recess 194b extending into the outer ring 216, as shown in FIG. Figure 8 shown.

[0196] The processes and materials used to form the chip package structures 200 , 300 , 400 , 500 , 600 , 700 , and 800 may be similar to or equal to the processes and materials used to form the chip package structure 100 .

[0197] According to some embodiments, a chip packaging structure and a method for forming the same are provided. The method for forming the chip packaging structure removes a portion of the anti-warping annular structure near the gap between the chip structures to reduce the anti-warping ability of the annular structure near the gap between the chip structures. As a result, the stress concentrated on the bottom filling layer is reduced. Because this method only removes the portion of the annular structure near the gap, the anti-warping ability of the entire annular structure is roughly maintained within an acceptable range. Therefore, the yield of the chip packaging structure is improved.

[0198] This method arranges a cover on the chip structure to reduce the warping of the chip structure, thereby reducing the warping of the circuit substrate carrying the chip structure, thereby improving the yield of the chip packaging structure.

[0199] In some embodiments, a method for forming a chip package structure is provided. The method includes arranging a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip are separated by a gap. The method also includes arranging a ring structure on the circuit substrate. The ring structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess. In some embodiments, the step of arranging the first chip structure and the second chip structure on the circuit substrate includes arranging a package body on the circuit substrate. The package body includes a rewiring structure, and the first chip structure, the second chip structure and the bottom filling layer located on the rewiring structure. The bottom filling layer is located in the gap, between the first chip structure and the rewiring structure, and between the second chip structure and the rewiring structure. In some embodiments, the method also includes forming an adhesive layer on the circuit substrate before arranging the ring structure on the circuit substrate. The chip structure is located on the adhesive layer. In some embodiments, the adhesive layer has a second opening below the first opening, the second opening has a second inner wall, and the second inner wall has a second recess below the first recess. In some embodiments, the first recess and the second recess have substantially the same width. In some embodiments, the second recess is wider than the first recess. In some embodiments, the annular structure has an upper portion and a lower portion, and the first recess is located in the lower portion. In some embodiments, the annular structure further includes an adhesive layer between the upper portion and the lower portion. In some embodiments, the method further includes disposing a cover member on the first chip structure. In some embodiments, the cover member is narrower than the first chip structure.

[0200] In some embodiments, a method for forming a chip packaging structure is provided. The method includes setting a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes setting an annular structure on the circuit substrate. The annular structure surrounds the first chip structure and the second chip structure, and the annular structure includes a first thinner portion and a first thicker portion connected to each other, and the gap is close to the first thinner portion. In some embodiments, the annular structure includes a second thinner portion and a second thicker portion, the first thinner portion is between the first thicker portion and the second thicker portion and is connected to the first thicker portion and the second thicker portion, and the second thinner portion is between the first thicker portion and the second thicker portion and is connected to the first thicker portion and the second thicker portion. In some embodiments, the gap is close to the second thinner portion. In some embodiments, the first thinner portion is relative to the second thinner portion. In some embodiments, the first top surface of the first thinner portion is roughly coplanar with the second top surface of the first thicker portion.

[0201] In some embodiments, a chip packaging structure is provided. This chip packaging structure includes a circuit substrate. This chip packaging structure includes a first chip structure and a second chip structure located on the circuit substrate. The first chip structure and the second chip structure are separated by a gap. This chip packaging structure includes an annular structure located on the circuit substrate. The circuit substrate has an opening, the first chip structure and the second chip structure are located in the opening, the opening has an inner wall, the inner wall has a recess, and the gap extends toward the recess. In some embodiments, the annular structure has an outer ring and a first strip-shaped portion surrounding the outer ring, the first strip-shaped portion has a first end and a second end connected to the outer ring, and the recess is located in the first strip-shaped portion. In some embodiments, the recess passes through the first strip-shaped portion. In some embodiments, the annular structure has an upper portion and a lower portion, and the recess is located in the lower portion. In some embodiments, the annular structure further includes an adhesive layer between the upper portion and the lower portion.

[0202] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present disclosure belongs can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined as defined by the appended claims.

Claims

1. A method for forming a chip packaging structure, comprising: Disposing a first chip structure and a second chip structure on a circuit substrate, wherein the first chip structure and the second chip structure are separated by a gap; An annular structure is disposed on the circuit substrate, wherein the annular structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess; as well as Before setting the annular structure on the circuit substrate, an adhesive layer is formed on the circuit substrate, wherein the annular structure is located on the adhesive layer, wherein the adhesive layer has a second opening below the first opening, the second opening has a second inner wall, and the second inner wall has a second recess below the first recess.

2. The method for forming a chip packaging structure according to claim 1, wherein: The step of arranging the first chip structure and the second chip structure on the circuit substrate includes: A package is disposed on the circuit substrate, wherein the package includes: a redistribution structure, and the first chip structure, the second chip structure and a bottom filling layer located on the redistribution structure, and the bottom filling layer is located in the gap, between the first chip structure and the redistribution structure, and between the second chip structure and the redistribution structure.

3. The method for forming a chip packaging structure according to claim 1, wherein: The first recess and the second recess have the same width.

4. The method for forming a chip packaging structure according to claim 1, wherein: The second recess is wider than the first recess.

5. The method for forming a chip packaging structure according to claim 1, wherein: The annular structure has an upper portion and a lower portion, and the first recess is located in the lower portion.

6. The method for forming a chip packaging structure according to claim 5, wherein: The ring structure also includes: An adhesive layer is disposed between the upper portion and the lower portion.

7. The method for forming a chip packaging structure according to claim 1, further comprising: A cover is disposed on the first chip structure.

8. The method for forming a chip packaging structure according to claim 7, wherein: The cover is narrower than the first chip structure.

9. A method for forming a chip packaging structure, comprising: Disposing a first chip structure and a second chip structure on a circuit substrate, wherein the first chip structure and the second chip structure are separated by a gap; An annular structure is disposed on the circuit substrate, wherein the annular structure surrounds the first chip structure and the second chip structure, and the annular structure includes: a first thinner portion and a first thicker portion connected to each other, and the gap is close to the first thinner portion; as well as Before setting the annular structure on the circuit substrate, an adhesive layer is formed on the circuit substrate, wherein the annular structure is located on the adhesive layer, the annular structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the adhesive layer has a second opening below the first opening, the second opening has an inner wall, and the inner wall has a recess below the first thinner portion.

10. The method for forming a chip packaging structure according to claim 9, wherein: The annular structure includes: a second thinner portion and a second thicker portion, the first thinner portion is between and connected to the first thicker portion and the second thicker portion, and the second thinner portion is between and connected to the first thicker portion and the second thicker portion.

11. The method for forming a chip packaging structure according to claim 10, wherein: The gap is adjacent to the second thinner portion.

12. The method for forming a chip packaging structure according to claim 11, wherein: The first thinner portion is opposite to the second thinner portion.

13. The method for forming a chip packaging structure according to claim 9, wherein: A first top surface of the first thinner portion is coplanar with a second top surface of the first thicker portion.

14. A chip packaging structure, comprising: a circuit substrate; A first chip structure and a second chip structure are located on the circuit substrate, wherein the first chip structure is separated from the second chip structure by a gap; an annular structure, located on the circuit substrate, wherein the circuit substrate has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess; as well as An adhesive layer is located on the circuit substrate, wherein the annular structure is located on the adhesive layer, the adhesive layer has a second opening below the first opening, the second opening has a second inner wall, and the second inner wall has a second recess below the first recess.

15. The chip packaging structure according to claim 14, wherein: The annular structure has an outer ring and a first strip-shaped portion surrounded by the outer ring. The first strip-shaped portion has a first end and a second end connected to the outer ring, and the recess is located in the first strip-shaped portion.

16. The chip packaging structure according to claim 15, wherein: The recess passes through the first strip portion.

17. The chip packaging structure according to claim 14, wherein: The annular structure has an upper portion and a lower portion, and the recess is located in the lower portion.

18. The chip packaging structure according to claim 17, wherein: The ring structure also includes: An adhesive layer is disposed between the upper portion and the lower portion.

Images