Memory array and method of forming a memory array

Abstract

This application relates to memory arrays and methods of forming memory arrays. A memory array including strings of memory cells includes laterally spaced-apart memory blocks individually including a vertical stack including alternating insulative layers and electrically conductive layers. A horizontal pattern of operative memory cell pillars extends through the insulative layers and the electrically conductive layers in individual ones of the memory blocks. The operative memory cell pillars have an intrinsic compressive mechanical stress. At least one dummy structure in the individual memory blocks extends through at least upper ones of the insulative layers and the electrically conductive layers. The at least one dummy structure is at least one of (a) at a lateral edge of the horizontal pattern and (b) at a longitudinal end of the horizontal pattern. The at least one dummy structure has an intrinsic tensile mechanical stress. Other embodiments including methods are disclosed.

Description

TECHNICAL FIELD

[0001] Embodiments disclosed herein relate to memory arrays and methods of forming memory arrays. BACKGROUND

[0002] Memory is a type of integrated circuitry and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines, which can also be referred to as bit lines, data lines, or sense lines, and access lines, which can also be referred to as word lines. Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of a sense line and an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without being powered. Non-volatile memory is often designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and thus is refreshed / re-written to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store storage content in at least two different, selectable states. In binary systems, the states are considered a “0” or a “1”. In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. Field effect transistors can also include additional structures, such as a reversible programmable charge storage region as part of a gate structure between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is used extensively in modern computers and devices. For example, modern personal computers can store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid state drives in place of conventional hard disk drives. As yet another example, flash memory is pervasive in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of integrated flash memory. A NAND cell device includes at least one select device coupled in series with a series combination of memory cells (and the series combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include a reversibly programmable vertical transistor. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines can occur in so-called “staircase structures” at the ends or edges of an array of vertically stacked memory cells. The staircase structures include individual “steps” (alternatively referred to as “stages” or “staircases”) that define contact regions for individual word lines that are contacted by vertically extending conductive vias to provide electrical access to the word lines. SUMMARY

[0008] In some embodiments, a memory array including strings of memory cells includes laterally spaced-apart memory blocks individually including a vertical stack including alternating insulative tiers and electrically conductive tiers. A horizontal pattern of operative memory cell pillars extends through the insulative tiers and electrically conductive tiers in individual ones of the memory blocks. The operative memory cell pillars have an intrinsic compressive mechanical stress. At least one dummy structure in an individual memory block extends through at least upper insulative tiers and electrically conductive tiers of the insulative tiers and electrically conductive tiers. The at least one dummy structure is at least one of (a) at a lateral edge of the horizontal pattern and (b) at a longitudinal end of the horizontal pattern. The at least one dummy structure has an intrinsic tensile mechanical stress.

[0009] In some embodiments, a memory array including strings of memory cells includes laterally spaced-apart memory blocks individually including a vertical stack including alternating insulative tiers and electrically conductive tiers. Operative memory cell pillars extend through the insulative tiers and electrically conductive tiers in individual ones of the memory blocks. At least one dummy structure is in an individual memory block. The at least one dummy structure extends through uppermost insulative tiers and electrically conductive tiers of the insulative tiers and electrically conductive tiers and does not extend through lowermost insulative tiers and electrically conductive tiers of the insulative tiers and electrically conductive tiers.

[0010] In some embodiments, a memory array including strings of memory cells includes laterally spaced-apart memory blocks individually including a vertical stack including alternating insulative tiers and electrically conductive tiers. A horizontal pattern of operative memory cell pillars extends through the insulative tiers and electrically conductive tiers in individual ones of the memory blocks. A plurality of insulative dummy pillars is in an individual memory block. The insulative dummy pillars extend through at least upper insulative tiers and electrically conductive tiers of the insulative tiers and electrically conductive tiers and comprise at least predominantly AIO x . The insulative dummy pillars are longitudinally spaced apart along opposing lateral edges of the horizontal pattern that are longitudinally along the individual memory block.

[0011] In some embodiments, a method of forming a memory array including strings of memory cells includes forming a dummy structure in a channel opening and in a dummy structure opening with a stack including vertically alternating first tiers and second tiers. The dummy structure is removed from the channel opening to leave the dummy structure in the dummy structure opening. After the removal, operative memory cell pillars are formed in the channel opening. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1 to 9 is a view of a memory array including strings of memory cells according to an embodiment of the application.

[0013] Figure 10and 11 is a view of a memory array including strings of memory cells according to an embodiment of the invention.

[0014] Figure 12 and 13 is a view of a memory array including strings of memory cells according to an embodiment of the invention. DETAILED DESCRIPTION

[0015] Embodiments of the invention encompass memory arrays, such as arrays of NAND or other memory cells with peripheral control circuitry under the array (e.g., CMOS-under-array). Some aspects of the invention aim to overcome problems associated with so-called "block warping" (stacks of blocks tipping / tilting laterally with respect to their longitudinal orientation during fabrication), but the invention is not limited to this. Block warping can be adversely affected by lateral outward bowing or bending of operative memory cell pillars. Such bowing / bending can occur primarily at longitudinal ends or lateral edges of blocks / sub-blocks where the 2D horizontal pattern of memory cell pillars stops. This can occur when the intrinsic compressive mechanical stress of the memory cell pillars is greater than that of the material adjacent thereto, if any. Some aspects of the invention aim to overcome problems associated with such lateral outward bowing / bending of operative memory cell pillars, but the invention is not limited to this.

[0016] Reference is made to Figures 1 to 9 A first example embodiment is described. Figure 1 An example embodiment construction 10 including a die or die region 100 comprising a memory array 12 is shown diagrammatically. The die or die region 100 can be a portion of a larger substrate, such as a semiconductor wafer, and not shown in the figures. Alternatively, and merely by way of example, the die or die region 100 can be a portion of an integrated circuit chip or a portion of a package containing an integrated circuit chip. The example die 100 includes at least one memory plane region 105 (four are shown), laterally spaced-apart memory blocks 58 in individual memory plane regions 105, an array via region 21, a staircase region 60 (two are shown at the juxtaposed paired opposite longitudinal ends of the memory planes), and a peripheral circuitry region PC (two are shown). In this document, a "block" generally includes a "sub-block". The staircase region 60 can be considered to include a terrace region 62. Figures 7 to 9 is a larger and differently scaled diagrammatic view of a portion of the die or die region 100.

[0017] The memory array 12 includes strings 49 of vertically extending memory cells 56, shown by way of example only above a substrate 11, which includes one or more of conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulatory (i.e., electrically) materials. Various materials have been vertically formed above the substrate 11. The materials may be... Figures 1 to 9 The material depicted may be located beside, vertically inside, or vertically outside. For example, components manufactured or fully manufactured in other parts of the integrated circuit system may be disposed above, around, or inside the substrate 11. Control circuitry and / or other peripheral circuitry systems for operating components within the array 12 of vertically extending memory cell strings may also be manufactured, and these circuitry systems may be partially or fully within the array or subarrays. Furthermore, multiple subarrays may be manufactured and operated relatively independently, sequentially, or otherwise. In this document, "subarray" may also be considered as an array.

[0018] An example of a conductor layer 16, including conductive material 17, is located above the substrate 11. Conductor layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuit system and / or common source line or board) for controlling read and write access to memory cells 56 within the array 12. An example of a vertical stack 18 is located above conductor layers 16 within individual, laterally spaced memory blocks 58. The vertical stack includes vertically alternating insulating layers 20 and conductive layers 22. The thickness of each of layers 20 and 22 is typically 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown; stack 18 is more likely to include tens, hundreds, or more layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be located between conductor layers 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material in such circuitry may be below the lowest conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the lowest conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22. Example insulating layer 20 includes insulating material 24 (e.g., silicon dioxide and / or silicon nitride). Example conductive layer 22 includes conductive material 48, which, for example, forms individual conductive lines 29 (e.g., word lines). A thin insulating liner (e.g., Al2O3 and not shown) may surround conductive material 48. Example memory cell string 49, including memory cells 56, is within channel opening 25 and extends into conductor layer 16. Memory cell string 49 may partially enter the conductive material 17 of conductor layer 16, as shown.

[0019] Memory blocks 58 can be elongated and oriented, e.g., in a longitudinal direction along direction 55. Such memory blocks are shown separated or spaced apart by intervening material 57 in horizontally elongated trenches 40. Intervening material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks 58. Intervening material 57 can include one or more of insulative, semiconductive, and conductive materials, and in any event can facilitate shorting of conductive layers 22 relative to one another. Example insulative materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. As other examples, intervening material 57 can include a laterally outermost insulative material (e.g., silicon dioxide and not shown in the figures) and a laterally inner material (e.g., undoped polysilicon and not shown in the figures) that is different in composition from the laterally outermost insulative material. In addition, and / or alternatively, intervening material 57 can include one or more arrays of through array vias (TAVs) (not shown in the figures).

[0020] The transistor channel material is in individual channel openings vertically along the insulative and conductive layers, and includes at least portions of individual operative memory cell pillars directly electrically coupled with conductive material in the conductor layers. Individual memory cells of the memory array can include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulative charge transfer material. The storage material (e.g., a floating gate material, e.g., doped or undoped silicon, or a charge trapping material, e.g., silicon nitride, metal dots, etc.) of the individual memory cells is vertically along the individual charge blocking regions. The insulative charge transfer material (e.g., a bandgap engineered structure with a nitrogen-containing material, e.g., silicon nitride, sandwiched between two insulator oxides, e.g., silicon dioxide) is laterally between the channel material and the storage material.

[0021] Figures 2 to 6 One embodiment is shown in which memory cell string 49 includes charge blocking material 30, storage material 32, and charge transfer material 34 vertically along individual channel openings 25 of insulative layers 20 and conductive layers 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed by, e.g., depositing respective thin layers thereof over stack 18 and within individual channel openings 25, and then planarizing such transistor materials back at least to a top surface of stack 18. Memory cell string 49 also includes channel material 36 vertically along channel openings 25 of insulative layers 20 and conductive layers 22, and thus includes individual operative memory cell pillars 53. Due to scale, materials 30, 32, 34, and 36 are not shown in the figures as being vertically along channel openings 25 of insulative layers 20 and conductive layers 22. Figure 2 and 3Commonly exhibited as and designated only as material 37. Example channel material 36 includes a suitably doped crystalline semiconductor material such as one or more of silicon, germanium, and so-called Group III / Group V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 Angstroms. As exhibited, a punch etch can be performed to remove materials 30, 32, and 34 from the bottom of channel opening 25 to expose conductor layer 16 such that channel material 36 is directly against conductive material 17 of conductor layer 16. Such a punch etch can be performed individually with respect to each of materials 30, 32, and 34 (as exhibited), or can be performed collectively with respect to all materials after deposition of material 34 (not shown in the figures). Alternatively and by way of example only, a punch etch can not be performed and channel material 36 can be directly electrically coupled to conductive material 17 of conductor layer 16 by a separate conductive interconnect (not shown in the figures). Operational memory cell pillar 53 is exhibited as including a radially central solid dielectric material 38 such as spin-on dielectric, silicon dioxide, and / or silicon nitride. Alternatively and by way of example only, a radially central portion within channel opening 25 can include void space (not shown in the figures) and / or be free of solid material (not shown in the figures). A conductive plug (not shown in the figures) can be formed on the top of operational memory cell pillar 53 for better conductive connection with overlying circuitry (not shown in the figures). Regardless, in some embodiments, operational memory cell pillar 53 has an intrinsic compressive mechanical stress (i.e., overall when having multiple different materials / structures; e.g., in negative megaPascals / gigaPascals).

[0022] The approximate locations of transistors and / or memory cells 56 are indicated in Figure 6 some of the figures with brackets, and some are indicated in Figures 2 to 5 the figures with dashed outlines, where transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted examples. Alternatively, transistors and / or memory cells 56 can not be completely annular with respect to individual channel openings 25 such that each channel opening 25 can have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells around individual channel openings in individual conductive layers, where there can be multiple word lines per channel opening in individual conductive layers, and not shown in the figures). Conductive material 48 can be considered to have ends 50 Figure 6 corresponding to control gate regions 52 of individual transistors and / or memory cells 56. In the depicted embodiments, control gate regions 52 include individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered to be memory structures 65 laterally between control gate regions 52 and channel material 36.

[0023] A charge-blocking region (e.g., charge-blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge blocker can have the following function in a memory cell: in a program mode, the charge blocker can prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge-trapping material, etc.) into the control gate, and in an erase mode, the charge blocker can prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocker can be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge-blocking region includes insulator material 30 as shown. As a further example, the charge-blocking region can include a laterally (e.g., radially) outer portion of the storage material (e.g., material 32), where such storage material is insulative (e.g., in the absence of any distinct insulator material 30 between the insulative storage material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate can be sufficient to act as a charge-blocking region in the absence of any separate insulator material 30. Moreover, the interface of the conductive material 48 and material 30 (if present) in conjunction with the insulator material 30 can together act as a charge-blocking region, and alternatively or additionally, can act as a laterally outer region of insulative storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0024] The conductive layers 22 and insulative layers 20 of the memory block 58 extend into a staircase region 60 Figure 8 ). The example staircase region 60 includes laterally spaced apart terrace regions 62 and laterally spaced apart staircase structures 64 Figure 7 and 8 ). The example terrace region 62 associated with the staircase structure 64 includes a terrace peak 66X and a terrace foot 66Z. The staircase structure 64 includes a stair 63. The example operable TAV 45 is shown as extending through the stack 18 in the terrace peak 66X. One or more circuit- operatively conductive vias 39 extend down to a conductive surface of the individual stair 63. The example TAV 45 and via 39 are shown as including a core 59 of conductive material surrounded by insulative material 61 (e.g., silicon dioxide and / or silicon nitride). Insulative material 51 (e.g., silicon dioxide) is shown as on top of the staircase structure 64.

[0025] The operative memory cell pillars 53 are shown as arranged in a horizontal pattern 67 (e.g., a 2D lattice which can be a Bravais or non-Bravais, with an example Bravais rectangular lattice shown). The example horizontal pattern 67 includes lateral edges 68 (two opposite lateral edges 68 shown) and longitudinal ends 70 (two shown in Figure 9 ). As an example and for brevity only, the horizontal pattern 67 results from operative memory cell pillars 53 arranged in groups or columns of five per row. Any alternative existing or future-developed arrangement and configuration can be used.

[0026] At least one dummy structure 75 is in an individual memory block 58 and extends through at least an upper (e.g., uppermost) insulative layer 20 and a conductive layer 22 (e.g., dummy structure 75 is in a dummy structure opening 80). Herein, a "dummy structure opening" is an opening in which a "dummy structure" has been or will be formed. A "dummy structure" is a circuit-ineffective structure that can be in a finished circuitry construction and thereby has no current flow therethrough in all operations of the circuitry, and that can be a circuit-ineffective blind end, not part of a current flow path of the circuit, even if extending to or from an electronic component. At least one dummy structure 75 is at least one of (a) and (b), where (a): at a lateral edge 68 of horizontal pattern 67, and (b): at a longitudinal end 70 of horizontal pattern 67. In one embodiment, at least one dummy structure has an intrinsic tensile mechanical stress (i.e., overall when having multiple different physical or chemical constituent materials / structures; e.g., in positive megaPascals / gigaPascals). Memory array 12 can include (a) (e.g., only (a)), (b) (e.g., only (b)), or both (a) and (b). Figure 2 、 3 And 7-9 show example embodiments in which at least one dummy structure 75 includes both (a) and (b). In addition, Figure 2 、 3 And 7-9 show example embodiments in which another of at least one dummy structure 75 is at both opposing lateral edges 68 of horizontal pattern 67. Furthermore, Figure 2 、 3 And 7-9 also show example embodiments in which individual memory block 58 includes multiple dummy structures 75 in at least one of (a) and (b) (e.g., in both (a) and (b) as shown).

[0027] Example dummy structure 75 includes material 71 that can be uniform (i.e., in composition and physically, e.g., physically: amorphous or same crystalline structure) or non-uniform (i.e., at least one of different composition or different intrinsic physical properties; e.g., amorphous or different crystalline structure). Regardless, and in one embodiment, dummy structure 75 includes an insulative material, and in one embodiment, includes a conductive material. Just as an example, example materials that can have an intrinsic tensile mechanical stress include A10 x (e.g., AI2O3), Si3N4, polysilicon, TiN, TiO2, WN, and W2N. In one ideal embodiment, the insulative material includes A10 x (e.g., AI2O3), and in one embodiment, all dummy structures 75 are insulative material.

[0028] In one embodiment, all of the material 71 of the dummy structure 75 has an inherent tensile mechanical stress, and in another embodiment, some material of the dummy structure 75 has an inherent compressive mechanical stress. In one such subsequent embodiment, at least the laterally outermost material of the dummy structure 75 has an inherent tensile mechanical stress. By way of example, and by way of example only, a laterally or radially inner core of the dummy structure can have an inherent compressive mechanical stress, while a laterally or peripherally outermost portion thereof can have an inherent tensile mechanical stress, with the dummy structure as a whole exhibiting an inherent tensile mechanical stress, even if all portions thereof can not locally so exhibit.

[0029] In one embodiment and as shown, the dummy structure 75 is a dummy pillar 75, and in one such embodiment, the individual memory block 58 includes a plurality of such dummy pillars in at least one of (a) and (b) (in both of the shown (a) and (b)). By way of example only, the dummy pillar 75 is shown as extending in a single row and / or a single column relative to each of the lateral edges 68 and longitudinal ends 70 of the horizontal pattern 67, and in one embodiment, completely horizontally around the horizontal pattern 67. Further, by way of example, the dummy structure / pillar 75 is shown as extending all along the individual lateral edges 68 and all along the longitudinal ends 70 of the horizontal pattern 67, although neither is necessary. Further and in any event, the dummy structure / pillar 75 can extend along only one lateral edge 68 and / or along only one longitudinal end 70 of the horizontal pattern 67. Further and in any event, multiple rows / columns of the dummy structure / pillar 75 can extend along one or more lateral edges 68 and / or along one or more longitudinal ends 70 of the horizontal pattern 67 (not shown).

[0030] Further and by way of example only, the operative memory cell pillars 53 are shown as having a common horizontal peripheral shape (as shown, circular) and a common peripheral size at the horizontal levels of the vertical stack 18. With reference to a given horizontal level of the vertical stack 18, as one or both of the peripheral shape and peripheral size can vary vertically within the stack 18 (not shown), e.g., if the operative memory cell pillars taper to be narrower (not shown) deeper within the stack. In any event, and in one embodiment as shown, the dummy pillars 75 have a common horizontal peripheral shape and a common peripheral size at the horizontal levels of the vertical stack, the same as the common horizontal peripheral shape and common peripheral size of the operative memory cell pillars 53 at the horizontal levels of the vertical stack. Further, in one such embodiment and as shown, the dummy pillars 75 have a pitch P Figure 9The spacing is the same as the spacing of the operational memory cell pillars 53. Alternatively, and only as an example, the dummy pillars may have a horizontal outer perimeter shape and outer perimeter size that is at least different from the common horizontal outer perimeter size at the vertically stacked horizontal level, and may be smaller or larger than the common horizontal outer perimeter size. For example, and only as an example, when all the corresponding outer perimeter shapes are circular, the circle of the dummy pillar may be larger or smaller than the common horizontal outer perimeter size of the circle of the operational memory cell pillars.

[0031] Any other properties or aspects shown and / or described herein with respect to other embodiments may be used for reference. Figures 1 to 9 The embodiments shown and described.

[0032] refer to Figure 10 and 11 (corresponding to respectively in position) Figure 2 and 9 The following describes an alternative example construction 10a of the memory array 12. The same reference numerals as those used in the embodiments described above are used where appropriate, with some construction differences indicated by the suffix "a" or by different reference numerals. The memory array 12 includes at least one dummy structure 75a, which is a horizontally elongated wall 75a. In one such embodiment, and as shown, the dummy structure / wall 75a completely surrounds the horizontal pattern 67. Figure 10 and 11 Example embodiments are also shown in which individual memory blocks 58 include only one dummy structure 75a (e.g., only one wall at each at least one side 68 or at least one end 70) in at least one of (a) and (b). By way of example only, the dummy structure / wall 75a is shown to have the same width as the dummy pillar 75, although this is not required. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0033] Figure 3 and 8 An example embodiment is shown in which at least one dummy structure 75 extends through all insulating layers 20 and conductive layers 22 through which the operational memory cell post 53 extends. Figure 12 and 13 (corresponding to respectively in position) Figure 3 and 8 An alternative example configuration 10b of the memory array 12 is shown in the figure. The same reference numerals from the embodiments described above have been used where appropriate, wherein certain construction differences are indicated by the suffix "b" or by different reference numerals. Figure 12 and 13Dummy structures 75b are shown extending through the uppermost insulating layers 20 and conductive layers 22 and not through the lowermost of the insulating layers 20 and 22. Example void spaces 79 can be below the material 71, as shown. Any other properties or aspects as shown and / or described herein with respect to other embodiments can be used.

[0034] Depending on the deposition technique and certain materials under the substrate material can be deposited over the substrate to have an intrinsic tensile mechanical stress at the time of deposition, to have an intrinsic compressive mechanical stress at the time of deposition, or to have a neutral intrinsic mechanical stress / no intrinsic mechanical stress at the time of deposition. Also, the intrinsic mechanical stress of the deposited material can change after the deposition of the material is deposited. For example, heating the substrate will tend to reduce the degree of tensile intrinsic mechanical stress of a layer subject to intrinsic tensile mechanical stress and increase the compressive intrinsic mechanical stress of a layer subject to intrinsic compressive mechanical stress. The skilled artisan is able to select materials, deposition parameters, and subsequent processing when a dummy structure is desired to have an intrinsic tensile mechanical stress, for example as disclosed in U.S. Patent No. 8,492,278.

[0035] Providing a dummy structure that has an intrinsic tensile mechanical stress when the memory cell pillars have an intrinsic compressive mechanical stress desirably creates a bowing or bending force that is opposite to the bowing or bending force of the memory cell pillars at the ends and / or edges of the pattern of memory cell pillars. The skilled artisan can determine materials, dummy structure size, dummy structure shape, and / or number of dummy structures that are desirably offset from the opposite bowing / bending force of the memory cell pillars, with several examples provided herein.

[0036] Embodiments of the invention include a memory array including strings of memory cells including laterally spaced-apart memory blocks individually including a vertical stack including alternating insulating layers and conductive layers. Operative memory cell pillars extend through the insulating layers and conductive layers in individual ones of the memory blocks regardless of whether the operative memory cell pillars are formed in a horizontal pattern and regardless of whether they have an intrinsic compressive mechanical stress. At least one dummy structure is in individual memory blocks, where such at least one dummy structure extends through the uppermost of the insulating layers and conductive layers and does not extend through the lowermost of the insulating layers and conductive layers regardless of whether the at least one dummy structure is at least one of (a) and (b) and regardless of whether it has an intrinsic tensile mechanical stress. Any other properties or aspects as shown and / or described herein with respect to other embodiments can be used.

[0037] Embodiments of the invention include a memory array including strings of memory cells including laterally spaced-apart memory blocks individually including a vertical stack including alternating insulative and conductive tiers. A horizontal pattern of operative memory cell pillars extends through the insulative and conductive tiers, and in individual ones of the memory blocks, regardless of whether the operative memory cell pillars have intrinsic compressive mechanical stress. A plurality of insulative dummy pillars are in the individual memory blocks, and such insulative dummy pillars extend through at least upper insulative and conductive tiers of the insulative and conductive tiers and at least primarily include AIO x and regardless of whether they have intrinsic tensile mechanical stress. The insulative dummy pillars are longitudinally spaced-apart along opposing lateral edges of the horizontal pattern, which are longitudinally along the individual memory blocks, regardless of (b). Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used.

[0038] Embodiments of the invention encompass methods for forming a memory array. Such embodiments encompass so-called "gate-first" processing, and other processing, existing or future developed, regardless of when a transistor gate is formed. A memory array formed according to a method embodiment can incorporate, form, and / or have any of the attributes described with respect to a device embodiment.

[0039] In one embodiment, a method of forming a memory array including strings of memory cells includes forming a dummy structure (e.g., 75) in a channel opening (e.g., 25) and in a dummy structure opening (e.g., 80) with a stack (e.g., 18) including vertically alternating first (e.g., 22) and second (e.g., 20) tiers. The dummy structure is removed from the channel opening to leave the dummy structure in the dummy structure opening. After the removal, operative memory cell pillars (e.g., 53) are formed in the channel opening. In one such embodiment, the removal is by etching that is selective with respect to a mask material (e.g., photoresist and / or hard mask material) that covers the dummy structure in the dummy structure opening during such etching. In one embodiment, the dummy structure in the channel opening and the dummy structure in the dummy structure opening are formed simultaneously. In one embodiment, the channel opening and the dummy structure opening are formed simultaneously.

[0040] The above-described processes or constructions can be considered as related to an array of components formed as a single stack or single deck of such components over or as part of a base substrate that is a bottom layer (but the single stack / deck can have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the finished construction in any location, and in some embodiments can be below the array (e.g., CMOS under array). Regardless, one or more additional such stacks / decks can be provided or fabricated above and / or below the stack / deck shown in the figures or described above. Moreover, the arrays of components can be the same or different relative to each other in different stacks / decks, and different stacks / decks can have the same or different thicknesses relative to each other. Intervening structures can be provided between vertically adjacent stacks / decks (e.g., additional circuitry and / or dielectric layers). Also, different stacks / decks can be electrically coupled relative to each other. Multiple stacks / decks can be fabricated individually and sequentially (e.g., one on top of the other), or two or more stacks / decks can be fabricated substantially simultaneously.

[0041] The assemblies and structures discussed above can be used in integrated circuits / circuitry and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and business machines, and can include multilayer, multichip modules. The electronic systems can be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0042] Herein, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "topmost," "bottom," "above," "below," "under," "beneath," "upward," and "downward" refer generally to the vertical direction. "Horizontal" refers to a direction generally along the major substrate surface (i.e., within 10 degrees) and can be relative to the processing of the substrate during fabrication, and vertical is a direction generally orthogonal thereto. Reference to "exactly horizontal" refers to a direction along the major substrate surface (i.e., forming no degrees with the surface) and can be relative to the processing of the substrate during fabrication here. Also, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other, and independent of the orientation of the substrate in three-dimensional space. Further, "vertically extending" and "extends vertically" refer to a direction that deviates at least 45° from exactly horizontal. Also, "vertically extending," "extends vertically," "horizontally extending," "extends horizontally," and the like with respect to a field effect transistor refer to the orientation of the channel length of the transistor along which current flows between source / drain regions in operation. For bipolar junction transistors, "vertically extending," "extends vertically," "horizontally extending," "extends horizontally," and the like refer to the orientation of the base length along which current flows between emitter and collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0043] Further, "directly above," "directly beneath," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. Also, use of "above" without the "directly" preceding it only requires that some portion of the stated region / material / component above the other stated region / material / component be vertically outward of the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, use of "below" and "beneath" without the "directly" preceding it only requires that some portion of the stated region / material / component below / under the other stated region / material / component be vertically inward of the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components).

[0044] Any of the materials, regions, and structures described herein can be uniform or non-uniform, and can be continuous or discontinuous over any material on which it is over. Where one or more example compositions are provided for any material, the material can comprise, consist primarily of, or consist of such one or more compositions. Further, each material can be formed using any suitable existing or future-developed technique, unless otherwise specified, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0045] In addition, "thickness" (without a directional adjective preceding it) used alone is defined as the average straight-line distance normal through a given material or region from the closest surface of an immediately-adjacent material or region of different composition. In addition, various materials or regions described herein can have a substantially constant thickness or a variable thickness. If having a variable thickness, thickness refers to average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those portions of two stated materials or regions that can be directly against each other be chemically and / or physically different, e.g., in the case of non-uniformity in the materials or regions. If two stated materials or regions are not directly against each other, "different composition" only requires that those portions of the two stated materials or regions that are closest to each other be chemically and / or physically different, in the case of non-uniformity in such materials or regions. Herein, materials, regions, or structures are "directly against" another material, region, or structure when there is at least some physical contact of the stated materials, regions, or structures relative to each other. In contrast, "over," "on," "adjacent," "along," and "against" without the "directly" encompass both "directly against" and configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact relative to each other.

[0046] Herein, zone-material-assemblies are "electrically coupled" relative to each other if, in normal operation, current is able to flow continuously from one zone-material-assembly to another zone-material-assembly, and the flow is primarily through movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic assembly can be between and electrically coupled to the zone-material-assemblies. In contrast, when zone-material-assemblies are said to be "directly electrically coupled," there is no intervening electronic assembly (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled zone-material-assemblies.

[0047] Any use of "row" and "column" herein is to facilitate distinguishing one series or orientation of features from another series or orientation of features, and assemblies have been or can be formed along the "rows" and "columns." "Row" and "column" are used synonymously with respect to any series of zones, assemblies, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, as can columns. In addition, rows and columns can intersect relative to each other at 90° or at one or more other angles (i.e., other than a right angle).

[0048] The components of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconducting materials. “Metallic material” is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0049] In this document, any use of "selective" in relation to etching, removal, deposition, forming, and / or formation is an action in which a stated material is performed relative to another stated material at a volume ratio of at least 2:1. Furthermore, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1, reaching a deposition, growth, or formation of at least a first 75 angstroms.

[0050] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0051] Conclusion

[0052] As per the provisions, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A memory array comprising strings of memory cells, comprising: laterally spaced-apart memory blocks individually comprising a vertical stack comprising alternating insulative tiers and electrically conductive tiers, a horizontal pattern of operative memory cell pillars extending through the insulative tiers and the electrically conductive tiers in individual ones of the memory blocks, the operative memory cell pillars having an intrinsic compressive mechanical stress; at least one dummy structure in the individual memory blocks extending through at least upper ones of the insulative tiers and the electrically conductive tiers; the at least one dummy structure being at least one of (a) at a lateral edge of the horizontal pattern, and (b) at a longitudinal end of the horizontal pattern; the at least one dummy structure having an intrinsic tensile mechanical stress; and wherein the at least one dummy structure extends through uppermost ones of the insulative tiers and the electrically conductive tiers and does not extend through lowermost ones of the insulative tiers and the electrically conductive tiers, a void space being located directly below the at least one dummy structure.

2. The memory array of claim 1 comprising NAND.

3. A memory array comprising strings of memory cells, comprising: laterally spaced-apart memory blocks individually comprising a vertical stack comprising alternating insulative tiers and electrically conductive tiers, operative memory cell pillars extending through the insulative tiers and the electrically conductive tiers in individual ones of the memory blocks; and at least one dummy structure in the individual memory blocks, the at least one dummy structure extending through uppermost ones of the insulative tiers and the electrically conductive tiers and not extending through lowermost ones of the insulative tiers and the electrically conductive tiers, a void space being located directly below the at least one dummy structure.

4. The memory array of claim 3 wherein the operative memory cell pillars have an intrinsic compressive mechanical stress.

5. The memory array of claim 3 wherein the at least one dummy structure has an intrinsic tensile mechanical stress.

6. The memory array of claim 3 wherein the operative memory cell pillars are in a horizontal pattern, the at least one dummy structure being at least one of (a) at a lateral edge of the horizontal pattern, and (b) at a longitudinal end of the horizontal pattern.

7. The memory array of claim 3 wherein the at least one dummy structure is a dummy pillar.

8. The memory array of claim 3 wherein the at least one dummy structure is a horizontally elongated wall.

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