E / D NMOS Reference Voltage Source and Low Dropout Voltage Regulator

Abstract

The present invention provides an E / D NMOS reference voltage source and a low dropout voltage regulator. In the E / D NMOS reference voltage source, regardless of how the externally applied power supply voltage changes, the pre-reference output voltage can be stabilized to a fixed value by a pre-reference source circuit based on an N-channel junction field effect transistor. The range of the pre-reference output voltage is wide and the process adjustment is convenient. Due to the withstand voltage and preliminary voltage regulation of the pre-reference source circuit, the input voltage of the E / D NMOS reference source circuit is little affected by the change of the power supply voltage, greatly improving the wide input voltage range and power supply rejection ratio of the E / D NMOS reference source circuit and simultaneously having the property of low power consumption of the E / D NMOS reference. Moreover, the circuit structure of the E / D NMOS reference voltage source is simple and reasonable, without the need for triodes, resistors, capacitors, etc. Its manufacturing process only adds the manufacture of N-channel junction field effect transistors on the basis of the silicon gate P-well E / D CMOS process. Only the threshold voltage of the N-channel junction field effect transistor needs to be adjusted in the process, greatly simplifying the process and reducing the cost.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and particularly to an E / D NMOS reference voltage source and a low dropout voltage regulator. Background Art

[0002] In the design of power management circuits for analog integrated circuits, the reference voltage source determines the performance indicators of the low dropout power supply. Currently, there are various types of reference voltage sources, such as Zener reference sources, bandgap reference sources, bandgap reference sources with second-order compensation, and E / D NMOS reference sources with high power supply rejection ratio, etc.

[0003] Among them, the Zener reference voltage source uses a bipolar circuit structure combined with a Zener diode with process characteristics to achieve high performance of the Zener reference source; the bandgap reference source uses a standard bandgap structure to achieve high-performance bandgap reference output; the bandgap reference source with second-order compensation designed on the basis of the bandgap reference source further improves the temperature performance of the bandgap reference; while the E / D NMOS reference voltage source with high power supply rejection ratio realizes a micro-power reference voltage source with high power supply rejection ratio through a two-stage structure of series-connected enhancement-type and depletion-type NMOS transistors.

[0004] However, it is difficult for the above reference voltage sources to simultaneously meet the requirements of high voltage (40V), high power supply rejection ratio (60dB), and low power consumption (≤10uA), which further limits the application of the above reference voltage sources in low dropout voltage regulators with high voltage, high power supply rejection ratio, and micro-power consumption. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an E / D NMOS reference voltage source with a wide input voltage range to solve the above technical problems.

[0006] To achieve the above purpose and other related purposes, the present invention provides an E / D NMOS reference voltage source, including:

[0007] A pre-reference source circuit, including an N-channel junction field effect transistor, the gate of the N-channel junction field effect transistor is grounded, the drain is connected to the power supply voltage, and the source outputs a pre-reference voltage;

[0008] An E / D NMOS reference source circuit, connected to the pre-reference source circuit, receiving the pre-reference voltage and outputting a reference voltage externally.

[0009] Optionally, the N-channel junction field effect transistor includes a depletion-type N-channel junction field effect transistor.

[0010] Optionally, the E / D NMOS reference source circuit includes:

[0011] A reference voltage startup sub - circuit, connected to the pre - reference source circuit, receives the pre - reference voltage and outputs the reference voltage externally;

[0012] A reference voltage regulation sub - circuit, connected to the reference voltage startup sub - circuit, regulates the reference voltage.

[0013] Optionally, the reference voltage startup sub - circuit includes a plurality of series - connected NMOS transistors, and the reference voltage regulation sub - circuit includes a plurality of series - connected NMOS transistors.

[0014] Optionally, the reference voltage startup sub - circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the drain of the first NMOS transistor is connected to the source of the N - channel junction field - effect transistor, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, and the source of the fourth NMOS transistor serves as the reference voltage output terminal; the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected together and connected to the reference voltage output terminal; the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected together and connected to the reference voltage output terminal.

[0015] Optionally, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor include depletion - type NMOS transistors.

[0016] Optionally, the reference voltage startup sub - circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the drain of the fifth NMOS transistor is connected to the reference voltage output terminal, the drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor, the drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor is grounded; the gates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are connected together and connected to the reference voltage output terminal; the substrates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are connected together and grounded.

[0017] Optionally, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor include enhancement - type NMOS transistors.

[0018] In addition, to achieve the above and other related objectives, the present invention also provides a low dropout voltage regulator, including the E / D NMOS reference voltage source described in any one of the above.

[0019] As described above, the E / D NMOS reference voltage source of the present invention has the following beneficial effects:

[0020] In the pre-reference source circuit, the drain of the N-channel junction field effect transistor with its gate grounded bears the power supply voltage. When the N-channel junction field effect transistor is turned on, the pre-reference voltage output by its source is equal to its threshold voltage, which is a fixed value. When the power supply voltage varies within a wide range (high level), the N-channel junction field effect transistor remains turned on, and the pre-reference voltage output by the gate of the N-channel junction field effect transistor is always a constant threshold voltage, avoiding the fluctuation of the power supply of the subsequent E / D NMOS reference source circuit with the external power supply voltage, and improving the operating voltage range and high power supply rejection ratio of the E / D NMOS reference source circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It shows the circuit diagram of the E / D NMOS reference voltage source in the embodiment of the present invention.

[0022] Figure 2 Shown as Figure 1 the equivalent circuit diagram of the E / D NMOS reference voltage source in

[0023] DESCRIPTION OF THE REFERENCE NUMERALS

[0024] N1 The first NMOS transistor

[0025] N2 The second NMOS transistor

[0026] N3 The third NMOS transistor

[0027] N4 The fourth NMOS transistor

[0028] N5 The fifth NMOS transistor

[0029] N6 The sixth NMOS transistor

[0030] N7 The seventh NMOS transistor

[0031] N8 The eighth NMOS transistor

[0032] NJ N-channel junction field effect transistor

[0033] N1* The first equivalent NMOS transistor

[0034] N2* The second equivalent NMOS transistor

[0035] V IN Power supply voltage

[0036] V pre-vref Pre-reference voltage

[0037] V ref Reference voltage

[0038] GND Ground Detailed implementation manners

[0039] As described in the background art above, it is difficult for existing reference voltage sources such as Zener reference sources, bandgap reference sources, bandgap reference sources with second-order compensation, and E / D NMOS reference sources with high power supply rejection ratio to simultaneously meet requirements such as high voltage, high power supply rejection ratio, and low power consumption, thereby restricting the application of reference voltage sources in low-dropout voltage regulators with high voltage, high power supply rejection ratio, and micro-power consumption.

[0040] Based on this, the present invention proposes an E / D NMOS reference voltage source with a brand-new structure, which includes a pre-reference source circuit and an E / D NMOS reference source circuit based on an N-channel junction field-effect transistor. The gate of the N-channel junction field-effect transistor is grounded, and the drain is connected to the power supply voltage. The N-channel junction field-effect transistor withstands the breakdown voltage. When the power supply voltage varies within a wide range, the pre-reference voltage output by its gate is always a constant threshold voltage, avoiding the fluctuation of the input power supply of the E / D NMOS reference source circuit with the external power supply voltage, and improving the operating voltage range and high power supply rejection ratio of the E / D NMOS reference source circuit.

[0041] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please refer to Figures 1 to 2 . It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex. The structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions under which the present invention can be implemented. Therefore, they do not have technical essence. Any modification of the structure, change of the proportional relationship, or adjustment of the size should still fall within the scope that can be covered by the technical content disclosed in the present invention without affecting the effects that the present invention can produce and the purposes that can be achieved.

[0043] As Figure 1 shown, the present invention provides an E / D NMOS reference voltage source, which includes:

[0044] A pre-reference source circuit, including an N-channel junction field effect transistor NJ, the gate of the N-channel junction field effect transistor NJ is grounded to GND, the drain is connected to the power supply voltage V IN , and the source outputs a pre-reference voltage V pre-vref ;

[0045] An E / D NMOS reference source circuit, connected to the pre-reference source circuit, receives the pre-reference voltage V pre-vref and externally outputs a reference voltage V ref .

[0046] Optionally, the N-channel junction field effect transistor NJ includes a depletion-type N-channel junction field effect transistor, that is, there is a conducting channel when its gate voltage is zero.

[0047] As Figure 1 shown, the gate of the N-channel junction field effect transistor NJ is grounded to GND, the drain is connected to the power supply voltage V IN , when the power supply voltage V IN is at a high level, the N-channel junction field effect transistor NJ conducts, and the pre-reference voltage V pre-vref output by its gate is a constant threshold voltage V TH , even if the power supply voltage V IN varies within a wide range, the pre-reference voltage V pre-vref output by its gate is always a fixed value. Among them, the value of the threshold voltage V TH in the N-channel junction field effect transistor NJ can be adjusted by process, usually (-4.8V to -6.8V).

[0048] Specifically, the E / D NMOS reference source circuit includes:

[0049] A reference voltage startup sub-circuit, connected to the pre-reference source circuit, receives the pre-reference voltage V pre-vref and externally outputs a reference voltage V ref ;

[0050] A reference voltage regulation sub-circuit, connected to the reference voltage startup sub-circuit, adjusts the value and temperature characteristic parameters of the reference voltage V ref .

[0051] Among them, the reference voltage startup sub-circuit serves as the startup circuit of the E / D NMOS reference source circuit to determine the current of the E / D NMOS reference source circuit; the reference voltage regulation sub-circuit performs a pull-down adjustment on the reference voltage V ref ; the reference voltage startup sub-circuit includes multiple series-connected NMOS transistors, and the reference voltage regulation sub-circuit includes multiple series-connected NMOS transistors.

[0052] Optionally, in an embodiment of the present invention, as Figure 1 shown, the reference voltage promoter circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; the drain of the first NMOS transistor N1 is connected to the source of the N-channel junction field effect transistor NJ (i.e., connected to the pre-reference voltage V pre-vref ), the drain of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1, the drain of the third NMOS transistor N3 is connected to the source of the second NMOS transistor N2, the drain of the fourth NMOS transistor N4 is connected to the source of the third NMOS transistor N3, and the source of the fourth NMOS transistor N4 serves as the reference voltage output terminal, outputting the reference voltage V ref ; the gates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are connected together and connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4); the substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are connected together and connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4).

[0053] Among them, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are all depletion-type NMOS transistors.

[0054] Optionally, in an embodiment of the present invention, as Figure 1 shown, the reference voltage promoter circuit includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; the drain of the fifth NMOS transistor N5 is connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4), the drain of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5, the drain of the seventh NMOS transistor N7 is connected to the source of the sixth NMOS transistor N6, the drain of the eighth NMOS transistor N8 is connected to the source of the seventh NMOS transistor N7, and the source of the eighth NMOS transistor N8 is grounded to GND; the gates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are connected together and connected to the reference voltage output terminal (i.e., the source of the fourth NMOS transistor N4); the substrates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are connected together and grounded to GND.

[0055] Among them, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are all enhancement-type NMOS transistors.

[0056] Specifically, as Figure 1 andFigure 2 As shown in the figure, the working principle of this E / D NMOS reference voltage source is as follows:

[0057] The pre-reference source circuit is composed of an N-channel junction field-effect transistor NJ. The drain of the N-channel junction field-effect transistor NJ is connected to the power supply voltage V IN , the gate is grounded to GND, and the source outputs the pre-reference voltage V pre-vref . Regardless of how the externally applied power supply voltage V IN changes, the pre-reference voltage V pre-vref output from its source is the stable threshold voltage V TH ;

[0058] At the same time, for the convenience of calculation, as Figure 2 shown, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are equivalent to a first equivalent NMOS transistor N1*, whose threshold voltage is V T1 , the channel width is W N1 , and the channel length is L N1 ; similarly, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are equivalent to a second equivalent NMOS transistor N2*, whose threshold voltage is V T2 , the channel width is W N2 , and the channel length is L N2 ; when the circuit works, the output reference voltage is V ref , and it is assumed that the current flowing through all NMOS transistors is I dd ;

[0059] For the first equivalent NMOS transistor N1*: Since V GS1 - V T1 ≤ V DS1 , the following equation (1) holds:

[0060] I dd = k p1 × (V GS1 - V T1 ) 2 (1)

[0061] In equation (1), V GS1 represents the gate-source voltage of the first equivalent NMOS transistor N1*, V DS1 represents the drain-source voltage of the first equivalent NMOS transistor N1*, and the corresponding coefficient

[0062] For the second equivalent NMOS transistor N2*: Since V GS2 - V T2 ≤ V DS2 , the following equation (2) holds:

[0063] I dd = k p2 ×(V GS2 - V T2 ) 2 (2)

[0064] (In equation (2), V GS2 represents the gate-source voltage of the second equivalent NMOS transistor N2*, and V DS2 represents the drain-source voltage of the second equivalent NMOS transistor N2*. The corresponding coefficient

[0065] From equations (1) and (2), it can be obtained that:

[0066] k p1 ×(V GS1 - V T1 ) 2 = k p2 ×(V GS2 - V T2 ) 2 (3)

[0067] From Figure 2 it can be seen that V GS1 = 0, V GS2 = V ref , and equation (3) can be simplified to:

[0068] k p1 ×V T1 2 = k p2 ×(V ref - V T2 ) 2

[0069]

[0070] Since the second equivalent NMOS transistor N2* needs to conduct, V ref must be higher than the threshold voltage V T2 of the second equivalent NMOS transistor N2*. Therefore, for V ref , the smaller value is discarded and the larger value is taken:

[0071]

[0072] At the moment when the entire circuit is powered on, the N-channel junction field effect transistor NJ conducts, and the pre-reference voltage V pre_vref output from its source is equal to its threshold voltage V TH . This voltage serves as the power supply voltage for the reference voltage startup sub-circuit; in the reference voltage startup sub-circuit, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 conduct, enabling the reference voltage Vref Output high level; Since the reference voltage V ref is high level, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 in the reference voltage regulating sub-circuit are turned on, pulling down the reference voltage V ref , and then gradually reaching equilibrium, and finally reaching a stable value. The magnitude of this value is related to the sizes and threshold voltages of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8, and is independent of the input power supply voltage V IN and the threshold voltage V TH of the N-channel junction field effect transistor NJ.

[0073] It can be seen from the above analysis that the reference voltage V ref output by this E / D NMOS reference voltage source is only related to the threshold voltage of the NMOS transistor and the size parameters of the NMOS transistor. As long as the parameters of the NMOS transistor are designed correctly, the required reference voltage V ref can be obtained.

[0074] Optionally, in an embodiment of the present invention, the basic parameter requirements are as follows:

[0075] 1), The threshold voltage V TH of the N-channel junction field effect transistor NJ: -4.8V to 6.8V, and the source-drain breakdown voltage V DS ≥40V;

[0076] 2), The threshold voltages of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4: -0.8 to -1.6V, and the source-drain voltage ≥16V;

[0077] 3), The threshold voltages of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8: 0.8 to 1.2V, and the source-drain voltage ≥16V;

[0078] 4), The gate oxide thicknesses of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are 35nm to 45nm;

[0079] 5), The output voltage V pre-vref of the pre-reference source circuit: 5.8V ± 1.0V (the typical value is 5.8V);

[0080] 6) Output voltage V of the E / D NMOS reference source circuit ref : 1.66V ± 0.1V;

[0081] 7) Power supply rejection ratio of the E / D NMOS reference voltage source: ≥ 75dB;

[0082] 8) Quiescent current of the E / D NMOS reference voltage source: ≤ 10μA.

[0083] It can be understood that the number of NMOS transistors in the reference voltage startup sub - circuit and the reference voltage regulation sub - circuit is not necessarily the same, and the number of corresponding NMOS transistors is not limited to Figure 1 the four in, and can be flexibly selected according to the design requirements of the circuit.

[0084] In addition, the present invention also provides a low - dropout voltage regulator, which includes the above - mentioned E / D NMOS reference voltage source. When the above - mentioned E / D NMOS reference voltage source provides a reference voltage for the low - dropout voltage regulator, it can meet the requirements of high voltage (wide input voltage range), high power supply rejection ratio, micro - power consumption, etc. Among them, the detailed structure of the low - dropout voltage regulator can refer to the prior art and will not be limited here.

[0085] In summary, in the E / D NMOS reference voltage source provided by the present invention, regardless of how the externally applied power supply voltage changes, the pre - reference source circuit composed of N - channel junction field - effect transistors with the gate grounded and the drain connected to the power supply voltage can stabilize the pre - reference output voltage to the threshold voltage of the N - channel junction field - effect transistor. The range of the pre - reference output voltage is wide and the process adjustment is convenient; due to the withstand voltage and preliminary voltage stabilization of the pre - reference source circuit, the input voltage of the E / D NMOS reference source circuit is little affected by the change of the power supply voltage, greatly improving the wide input voltage range, power supply rejection ratio of the E / D NMOS reference source circuit and simultaneously having the property of micro - power consumption of the E / D NMOS reference; the reference voltage startup sub - circuit, as the startup circuit of the E / D NMOS reference source circuit, can determine the current of the E / D NMOS reference source circuit, and the reference voltage regulation sub - circuit can adjust the output voltage performance of the E / D NMOS reference source circuit, facilitating the adjustment of the values and temperature characteristic parameters of the E / D NMOS reference source circuit; and the circuit structure of the E / D NMOS reference voltage source is simple and reasonable, without the need for triodes, resistors, capacitors, etc. Its manufacturing process only adds the manufacturing of N - channel junction field - effect transistors on the basis of the silicon - gate P - well E / D CMOS process. The process only needs to adjust the threshold voltage of the N - channel junction field - effect transistor, greatly simplifying the process and reducing the cost.

[0086] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An E / D NMOS reference voltage source, characterized in that, Comprising: A pre-reference source circuit, including an N-channel junction field effect transistor, where the gate of the N-channel junction field effect transistor is grounded, the drain is connected to the power supply voltage, and the source outputs a pre-reference voltage; An E / D NMOS reference source circuit, connected to the pre-reference source circuit, receiving the pre-reference voltage and outputting a reference voltage externally; The E / D NMOS reference source circuit includes: a reference voltage startup sub-circuit, connected to the pre-reference source circuit, receiving the pre-reference voltage and outputting the reference voltage externally; a reference voltage regulation sub-circuit, connected to the reference voltage startup sub-circuit, for regulating the reference voltage; The reference voltage startup sub-circuit includes multiple series-connected NMOS transistors, and the reference voltage regulation sub-circuit includes multiple series-connected NMOS transistors; The reference voltage startup sub-circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the drain of the first NMOS transistor is connected to the source of the N-channel junction field effect transistor, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, and the source of the fourth NMOS transistor serves as the reference voltage output terminal; the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected together and connected to the reference voltage output terminal; the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected together and connected to the reference voltage output terminal; The reference voltage startup sub-circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the drain of the fifth NMOS transistor is connected to the reference voltage output terminal, the drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor, the drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor is grounded; the gates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are connected together and connected to the reference voltage output terminal; the substrates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are connected together and grounded.

2. The E / D NMOS reference voltage source according to claim 1, wherein The N-channel junction field effect transistor includes a depletion-type N-channel junction field effect transistor.

3. The E / D NMOS reference voltage source according to claim 1, wherein The first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor include: depletion-type NMOS transistors.

4. The E / D NMOS reference voltage source according to claim 1, wherein The fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor include: enhancement-type NMOS transistors.

5. A low dropout voltage regulator, characterized in that, Including the E / D NMOS reference voltage source according to any one of claims 1-4.

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