Storage management of multi-plane parity data in memory subsystems

Abstract

The present application relates to storage management of multi-plane parity data in a memory subsystem. Host data to be written to a storage area of ​​a set of multiple planes comprising a memory device is received. A first parity generation operation is performed based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data. The set of multi-plane parity data is stored in a cache memory of a controller of the memory subsystem. A second parity generation operation is performed based on the set of multiple planes of the host data to generate a set of multi-page parity data. The set of multi-page parity data is stored in the cache memory of the controller of the memory subsystem. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to storage management of multi-plane parity data in a memory subsystem. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present disclosure provides a method comprising: receiving, by a processing device, host data to be written to a storage area comprising a set of multiple planes; performing a first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data; storing the set of multi-plane parity data in a cache memory of a controller of a memory subsystem; performing a second parity generation operation based on the set of multiple planes of the host data to generate a set of multi-page parity data; storing the set of multi-page parity data in the cache memory of the controller of the memory subsystem; and performing a data recovery operation based on the set of multi-plane parity data and the set of multi-page parity data.

[0004] In another aspect, the present disclosure further provides a non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting errors associated with host data of a page written to a storage area of ​​a memory subsystem comprising a set of multiple planes; retrieving a first set of parity data from a cache memory of a controller of the memory subsystem, wherein the first set of parity data is generated based on a total number of planes that is less than the host data; and performing a data recovery operation based at least in part on the first set of parity data.

[0005] On the other hand, the present disclosure further provides a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: receiving host data to be written to a storage area comprising a set of multiple planes; performing a first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data; storing the set of multi-plane parity data in a cache memory of a controller of a memory subsystem; performing a second parity generation operation based on the set of multiple planes of the host data to generate a set of multi-page parity data; storing the set of multi-page parity data in the cache memory of the controller of the memory subsystem; and performing a data recovery operation based on the set of multi-plane parity data and the set of multi-page parity data. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example parity data management component is described that manages a cache memory of a controller to store parity data in accordance with some embodiments.

[0009] Figure 3 Example parity data generated according to some embodiments is illustrated.

[0010] Figure 4 An example parity data management component is described that manages a cache memory of a controller to store parity data in accordance with some embodiments.

[0011] Figure 5 Example parity data generated according to some embodiments is illustrated.

[0012] Figure 6 is a flow chart of an example method for performing data recovery operations using parity data, generated in accordance with some embodiments.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to storage management of multi-plane parity data in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may employ techniques for performing data recovery in the event of a memory defect associated with programming user data (e.g., data written by a host system) to a memory device of the memory subsystem. Conventionally, memory defects may be managed by a controller of the memory subsystem by generating parity data (e.g., exclusive-OR (XOR) parity data) based on the written host data. The generated parity data (e.g., XOR parity data) is written by the controller to a cache memory of the controller (e.g., a volatile memory device such as a random access memory (RAM), a dynamic random access memory (DRAM), or a synchronous dynamic random access memory (SDRAM)).

[0016] In a plurality of electronic devices (e.g., mobile devices) that include a memory device having a memory cell array that stores multiple bits per cell (e.g., quad-level cell (QLC)) that employs both multiple page (multi-page) parity protection and multiple plane (multi-plane) parity protection (e.g., protection against failure of all planes of the memory device). In such systems, a large amount of cache memory storage space is required to store both the multi-page parity data and the multi-plane parity data. For example, for multi-page parity protection, 16KB of parity data is generated for each page row of the memory subsystem. Additionally, a conventional memory subsystem may have a multi-plane memory die (e.g., N planes) that includes multiple memory cell blocks arranged in the multiple planes that may employ multi-plane parity protection for multiple planes (e.g., a multi-plane memory device). Each block may be divided into multiple sub-blocks that each include multiple pages (e.g., three pages per sub-block).

[0017] A memory subsystem with multiple planes (e.g., N planes per memory die) needs to generate and store multi-plane parity data to protect against multi-plane failures (e.g., failures of all planes of the memory device). For example, for a multi-plane arrangement (e.g., a memory die with N planes), a conventional system can generate multi-plane parity data by performing an exclusive OR operation (XOR) based on data (also referred to as resource values ​​(R)) written by a host system to a plurality of logical units (e.g., logical unit 1 to logical unit Y) of the memory subsystem, where each logical unit includes multiple planes (e.g., plane 0, plane 1, ... plane N-1). The multi-plane parity data for each plane is stored in a cache memory of a controller (e.g., RAM). Conventionally, the controller performs an additional XOR operation on the data associated with all planes (e.g., N planes) to generate multi-page parity data from each page or page row. This multi-page parity data is also stored in the cache memory of the controller.

[0018] For example, for a multi-plane memory die with N planes having two sub-blocks, where each sub-block contains three pages, 16KB of parity data is generated and stored per plane. Therefore, approximately 48KB of parity data storage is required per sub-block per N planes.

[0019] In addition, an additional sub-block of cache memory is required for each sub-block of multi-plane memory in order to generate the multi-plane parity data. For example, in a conventional system that manages parity data for a multi-plane memory having four planes (N=4), the total controller cache memory requirement for one sub-block of multi-plane parity protection is 96KB per plane, resulting in a cache memory requirement of 384KB (e.g., 96KB×4 planes). This represents a significant controller cache memory consumption associated with conventional management of multi-page and multi-plane parity protection. Therefore, there is a need to reduce the controller cache memory consumption associated with the storage of multi-page parity data and multi-plane parity data used to perform data recovery operations in the event of host write data loss.

[0020] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem in which storage of multi-page parity data and multi-plane parity data is managed by a cache memory storage area of ​​a controller of the memory subsystem. In an embodiment, for a memory subsystem having multiple planes (N planes), a first parity data generation operation (e.g., an exclusive OR (XOR) operation) is performed on a portion of multiple planes (N-1 planes) of host data stored in a logical unit (LUN) of the memory subsystem to generate a first set of multi-plane parity data (P) for storage in a controller cache memory (e.g., a RAM of the controller). For example, for a memory subsystem having four planes (e.g., N=4), multi-plane parity data is generated by performing an XOR operation using a portion (N-1 planes) of multiple planes (e.g., plane 0 to plane 2 (i.e., plane N-2)) to generate multi-plane parity data. For example, for a system with N=4 planes, the multi-plane parity data includes a set of multi-plane parity data values, including: "P00" representing parity data for page 0, plane 0; "P10" representing parity data for page 1, plane 0; "P20" representing parity data for page 2, plane 0, ...; "P50" representing parity data for page 5, plane 0; "P0N-1" representing parity data for page 0, plane 3; "P1N-1" representing parity data for page 1, plane 3, etc. Advantageously, less controller cache is utilized to store the multi-plane parity data generated by performing parity operations using a portion (e.g., plane N-1) of multiple planes (e.g., planes 0 to N-2), resulting in a cache memory savings of approximately 48KB compared to the conventional approach described above. In this embodiment, a controller cache savings of 1 / N is achieved for a multi-plane system with multi-plane multi-subblock parity protection as described herein. For example, a memory device with four planes achieves a 25% controller cache savings (e.g., a 96KB savings), and a memory device with two planes achieves a 50% controller cache savings (192KB savings) associated with storage of multi-plane multi-subblock parity data.

[0021] In an embodiment, a second parity data generation operation is performed using multiple planes (N planes) of host data stored in a logical unit (LUN) of a memory subsystem to generate a set of multi-page parity data for storage in a controller cache memory (e.g., RAM of the controller).

[0022] In the event of a data failure, multi-plane parity data corresponding to N-1 planes and multi-page parity data may be retrieved from the controller's cache memory for a data recovery operation. In an embodiment, the data recovery operation may use the multi-plane parity data (corresponding to the N-1 planes of host data) and the multi-page parity data to retrieve host data corresponding to the Nth plane (e.g., the last plane).

[0023] In an embodiment, additional protection is provided to protect sub-blocks of host data. To protect sub-blocks of host data, a parity data generation operation is performed using two sub-blocks of data to generate multi-plane, multi-sub-block protection (e.g., generating parity data for multiple sub-blocks of host data (e.g., sub-block 0 and sub-block 1). In this embodiment, as in a conventional system, cache requirements are reduced from two sub-blocks of parity data to one sub-block of parity data (e.g., multi-plane, multi-sub-block parity data) generated by the parity data generation operation for combining the first sub-block and the second sub-block. In the event of a multi-plane failure of a sub-block, a parity data generation operation can be performed on the multi-plane parity data of the first sub-block and the data of the second sub-block stored in a memory device cache memory (e.g., NAND latches) to retrieve the parity data for the first sub-block (e.g., sub-block 0) and recover the host data for the previous sub-block.

[0024] In this embodiment, another controller cache savings of 1 / N is generated for a multi-plane system with multi-plane multi-sub-block parity protection as described herein. For example, a memory device with four planes achieves a 25% controller cache savings (e.g., a 96KB savings), and a memory device with two planes achieves a 50% controller cache savings (192KB savings) associated with the storage of multi-plane multi-sub-block parity data.

[0025] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0026] The memory subsystem 110 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0027] Computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or such a computing device that includes a memory and a processing device.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0029] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0030] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although nonvolatile memory devices such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] The memory subsystem 110 includes a parity data management component 113 that is operable to generate parity data and store the parity data in a cache memory of a controller of the memory subsystem 110 for use in data recovery operations associated with data written by a host system 120. In a memory subsystem having multiple planes (N planes), the parity data management component 113 performs a first parity data operation using a portion of the multiple planes (N-1 planes) stored in logical units (LUN 1 to LUN Y) of the memory subsystem to generate a first set of multi-plane parity data (P) for storage in a controller cache memory (e.g., a RAM of the controller). For example, for a memory subsystem having four planes (e.g., N=4), multi-plane parity data is generated by performing an XOR operation using host data associated with planes 0 to plane N-2 (e.g., a portion of the multiple planes) and stored in a controller cache memory (e.g., a RAM of the controller).

[0042] In one embodiment, a second parity data generation operation is performed using multiple planes (N planes) of host data stored in a logical unit (LUN) of the memory subsystem to generate a set of multi-page parity data for storage in the controller cache. In one embodiment, 16KB of multi-page parity data is generated from each page row (e.g., page 0, page 1, page 2, page 3, page 4, and page 5 of a memory device having two sub-blocks, where each sub-block contains three pages). In one embodiment, the parity data management component 113 can perform data recovery operations using the parity data stored in the controller cache to implement multi-page and multi-plane parity protection while saving controller cache storage space.

[0043] In an embodiment, the parity data management component 113 may generate a set of multi-plane, multi-sub-block parity data for a first sub-block (e.g., SB X-1, where X=1, 2, or 3, for a memory device having two sub-blocks each having three pages) and a second sub-block (SB X) of a group of sub-blocks based on a subset of the plurality of planes (N-1 planes) to generate the multi-plane, multi-sub-block parity data for storage in the controller cache. In this embodiment, storage savings are achieved by storing the multi-plane, multi-sub-block parity data for the current sub-block (sub-block X) and the previous sub-block (SB X-1) in the controller cache (e.g., a storage savings of 48KB per N planes for each sub-block).

[0044] In a first embodiment, the parity data management component 113 may generate multi-plane parity data (e.g., using a first parity data generation operation). In a second embodiment, the parity data management component 113 may generate multi-plane multi-sub-block parity data. In a third embodiment, the parity data management component 113 may generate both multi-plane parity data and multi-plane multi-sub-block parity data.

[0045] In some embodiments, the memory subsystem controller 115 includes at least a portion of the parity data management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the parity data management component 113 is part of the host system 120, an application, or an operating system. In the same or alternative embodiments, portions of the parity data management component 113 are part of the host system 120, while other portions of the parity data management component 113 are executed at the memory subsystem controller 115.

[0046] Figure 2 An example system is illustrated that includes a controller 115 operatively coupled to a host system 120. As shown, the controller 115 is configured to write host data to a memory device array 262 of a high-density memory device (e.g., QLC NAND device) 260. In an embodiment, the host data is written to a write buffer 255 of the controller 115 before being written or programmed to a memory device cache 261 (e.g., NAND latches) of the high-density memory device 260.

[0047] In an embodiment, the plurality of LUNs store a logical association between host data and the physical memory device array 262. The controller 115 includes a parity data management component 113 configured to generate a set of multi-plane parity data and a set of multi-page parity data for storage in the controller cache 250 based on the host data stored in the plurality of LUNs.

[0048] Figure 3 An example data structure 300 is illustrated that includes multiple LUNs (LUN 1 through LUN Y) storing host data corresponding to a memory device array having multiple planes (e.g., a multi-plane memory device). In the illustrated example, the memory device includes N planes, each including two sub-blocks (e.g., sub-block 0 and sub-block 1) each having three pages. As shown, LUN 1 includes host data or resource values ​​(R) for each page (e.g., page 0 through page 5) of each plane (plane 0 through plane N-1). In the illustrated example, LUN 1 stores "R00" representing host data for page 0, plane 0; "R10" representing host data for page 1 plane 0, page 1...; and "R5N-1" representing host data for page 5, plane N-1. As shown in Figure 3 As illustrated in the example shown in , data structure 300 includes host data (R values) for each page (Page 0 through Page 5) and each plane (Plane P0 through Plane PN-1) stored in multiple LUNs (eg, LUN 1 through LUN Y).

[0049] like Figure 2 As shown, host data 230 may include a first host data group 232 corresponding to plane 0 through plane N-2 (i.e., the "penultimate plane") of a plurality of LUNs (LUN 1 through LUN Y), which is written from write buffer 255 to high-density memory device 260 in a first write operation 233. Host data 230 may include a second host data group 234 corresponding to plane N-1 of the plurality of LUNs (LUN 1 through LUN Y), which is written from write buffer 255 to high-density memory device 260 in a second write operation 235.

[0050] In an embodiment, Figure 2 and 3As shown in FIG, the parity data management component 113 performs a first parity data operation to generate a set of multi-plane parity data 210 using a first host data group 232. The set of multi-plane parity data 210 is stored in the controller cache 250 (e.g., a RAM of the controller 115). In an embodiment, the first parity data operation is an XOR operation of the first set of host data (e.g., plane 0 to plane N-2) for all LUNs (LUN 1 to LUN Y). For example, the first parity data operation can be represented by the following expression:

[0051] XOR [LUN 1 (plane 0 to plane N-2) to LUN Y (plane 0 to plane N-2)]

[0052] In an embodiment, a first parity data operation may be performed during or in response to a first write operation from the write buffer 255 to the high density memory device 260 (i.e., during writing of a first set of host data (e.g., Plane 0 to Plane N-2)). Figure 3 As shown, a set of multi-plane parity data 210 includes a set of parity data values ​​for planes 0 to N-2, wherein the set of parity data values ​​includes "P00" representing page 0, plane 0; "P10" representing page 1, plane 0; ... and "P5N-2" representing page 5, plane N-2. Advantageously, compared to a conventional system that stores multi-plane parity data based on N-1 data planes in a controller's cache memory, the controller cache memory 250 generates and stores a set of multi-plane parity data based on N-1 data planes to achieve a multi-plane parity check corresponding to a data plane (e.g., 1 / N of the controller cache memory). * 100%, where N is the number of planes).

[0053] In an embodiment, the parity data management component 113 generates a set of multi-page parity data 220 including page row parity data (e.g., P0, P1, P2, P3, P4, and P5) for each page (page 0 to page 5) by performing a second parity data operation 320. In an embodiment, the second parity data operation is an XOR operation using all N planes of host data for each page or page row. For example, according to the following example expression, the second parity data operation is performed to generate page row parity data for page 0 (in Figure 3 Indicated as parity value "P0"):

[0054] XOR [Host data (P00 to P0N-1)] = P0.

[0055] In an embodiment, a second parity data operation may be performed during or in response to a second write operation from write buffer 255 to high density memory device 260 (ie, during writing of a second set of host data (eg, Plane N-1)).

[0056] In an embodiment, in the event of a data failure, a set of multi-plane parity data corresponding to the N-1 plane 210 may be retrieved from the controller's cache memory for use in a data recovery operation. The data recovery operation may retrieve data for the Nth plane using the set of multi-plane parity data 210 and the multi-page parity data 220. Advantageously, the above-described method achieves a 1 / N reduction in the amount of cache memory required to provide multi-plane protection (e.g., failure of all planes).

[0057] Figure 4 An example system is illustrated that includes a controller 115 operatively coupled to a host system 120. As shown, the controller 115 is configured to write host data to a memory device array 262 of a high-density memory device (e.g., QLC NAND device) 260. In an embodiment, the host data is written to a write buffer 255 of the controller 115 before being written or programmed to a memory device cache 261 (e.g., NAND latches) of the high-density memory device 260. Figure 4 As shown, the host data includes multiple sub-blocks (SB) of data (e.g., SB X-1 data, SB X data, ..., and SB X+Z data), where each sub-block includes multiple pages (e.g., three pages). In one embodiment, a first set of host data corresponding to the first sub-block (SB X-1 data) and the second sub-block (SB X data) is stored in the controller write buffer 155.

[0058] Figure 5 An example data structure 500 is illustrated that includes multiple LUNs (LUN 1 through LUN Y) storing host data corresponding to a memory device array having multiple planes with multiple sub-blocks (e.g., SB 0, SB 1). In the illustrated example, the memory device includes N planes, each including three sub-blocks (e.g., SB 0 and SB 3), each having three pages. As shown, LUN 1 includes host data or resource values ​​(R) for each page (e.g., page 0 through page 5) of each plane (plane 0 through plane N-1). In the illustrated example, LUN 1 stores "R00" representing host data for page 0, plane 0; "R10" representing page 1, plane 0, page 1, ...; and "R5N-1" representing page 5, plane N-1.

[0059] In an embodiment, Figure 4As shown, in operation 401, data of a first sub-block (e.g., sub-block X-1) is transferred from the controller write buffer 155 to a memory device cache 461 (e.g., NAND latches) of a high-density memory device 460 (e.g., QLC NAND). During or in response to operation 401, the parity data management component 113 performs a parity data operation to generate first multi-plane sub-block parity data corresponding to the first sub-block data (referred to herein as "multi-plane sub-block parity data"). The multi-plane sub-block parity data (e.g., multi-plane parity data of SB X-1) is stored in the controller cache 150. In an embodiment, a first multi-plane sub-block parity data (e.g., parity data of SBX-1) is generated by performing an XOR operation using a portion of host data (e.g., R00, R10, R20, ..., R2N-2) corresponding to pages (e.g., Page 0, Page 1, Page 2) of a corresponding sub-block (e.g., SB 0, where X=1). In an embodiment, advantageously, compared to a conventional system that generates parity data using all planes (e.g., P0 to PN-1), multi-plane sub-block parity data can be generated using planes P0 to PN-2, thereby reducing consumption of the controller cache memory 150.

[0060] In an embodiment, in operation 403, sub-block X-1 data is programmed from memory device cache 461 to memory device array 462. During or in response to operation 403, in operation 404, a second set of host data corresponding to a second sub-block (e.g., SB X data) is transferred from controller write buffer 155 to memory device cache 461 of high-density memory device 460. Additionally, during or in response to operation 403, a second set of multi-plane sub-block parity data (corresponding to sub-block X 405) is generated and stored in controller cache 150. In an embodiment, since the multi-plane sub-block SB X parity data 405 is involved in operation 404, the multi-plane sub-block SB X parity data is referred to as “current sub-block parity data,” and since the corresponding host data (e.g., sub-block X-1 data) has already been programmed to the memory device array 462 in operation 403, the multi-plane sub-block SB X-1 parity data is referred to as “previous sub-block parity data.”

[0061] In operation 406, the parity data management component 113 performs a parity data generation operation based on the multi-plane sub-block parity data of SBX (the current sub-block, e.g., sub-block 1) and SBX-1 (the previous sub-block, e.g., sub-block 0) to generate multi-plane multi-sub-block parity data 407. In an embodiment, the parity data generation operation is an XOR operation of the multi-plane sub-block parity data of SBX and SBX-1. In an embodiment, the multi-plane multi-sub-block parity data is stored in the controller cache 150.

[0062] like Figure 4 and 5 As shown in FIG, the parity data management component 113 performs parity data operations to generate multi-page parity data for each page row. As described above, the page row parity data (e.g., P0, P1, P2, P3, P4, and P5) for each page (page 0 to page 5) is generated by performing parity data operations using host data of all planes (e.g., plane 0 to plane N-1). For example, the parity data operations are performed to generate page row parity data for page 0 ( Figure 5 The parity value "P0" in the example above can be represented by the following expression: XOR[host data (plane 0 to plane N-1)] = P0.

[0063] In an embodiment, the parity data management component 113 system may perform a data recovery operation in response to a sub-block multi-plane failure. In an embodiment, the data recovery operation is performed by performing an XOR operation using the sub-block X data in the memory device cache 461 and the multi-plane multi-sub-block parity data 407 to retrieve the previous sub-block (e.g., SBX-1) parity data and recover the previous sub-block data (e.g., SBX-1 data). Advantageously, in combination with Figure 4 and 5 The illustrated and described method can result in a 50% controller cache memory storage savings compared to conventional methods. For example, the multi-plane parity data of sub-block 0 (e.g., three pages of parity data) can be combined with the multi-plane parity data of sub-block 1 (e.g., three pages of parity data), wherein the resulting three pages of multi-plane parity data are stored in the controller cache memory, thereby resulting in a storage savings equivalent to three pages of data in the controller cache memory.

[0064] In an embodiment, a parity data generation operation (e.g., an XOR operation) may be repeatedly performed using the current sub-block and the previous sub-block. For example, the multi-plane parity data of sub-block 0 may be combined with the multi-plane parity data of sub-block 1, the multi-plane parity data of sub-block 1 may be combined with the multi-plane parity data of sub-block 2, the multi-plane parity data of sub-block 2 may be combined with the multi-plane parity data of sub-block 3, and so on.

[0065] In an embodiment, the parity data management component 113 may perform a combination of Figure 2 and 3 The method described is performed in a second embodiment in conjunction with Figure 4 and 5 The described method, or in a third embodiment, both methods are performed together.

[0066] Figure 6 is a flow chart of an example method 600 for performing a data recovery operation using parity data managed by a parity data management component according to an embodiment of the present disclosure. The method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1 、 2 and 4 are executed by the parity data management component 113. In an embodiment, method 600 relates to the management of parity data stored in a cache memory of a controller of a memory subsystem. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible. In an embodiment, as shown, the operations represented by dashed lines (e.g., operations 651-655) represent the operations described above in conjunction with Figure 4 and 5 Another embodiment is described in detail.

[0067] like Figure 6 As shown, at operation 610, processing logic receives host data to be written to a storage area comprising a set of multiple planes of a memory device. In an embodiment, the storage area is a high-density storage area having multiple planes (e.g., QLC NAND). The set of multiple planes may include N planes (e.g., where N=4). In an embodiment, multiple logical units (e.g., multiple LUNs) are used to store data corresponding to the host data in a data structure comprising the multiple planes.

[0068] At operation 620, processing logic performs a first parity generation operation based on a portion of the plurality of planes of host data to generate a set of multi-plane parity data. In an embodiment, the first parity generation operation is an XOR operation based on N-1 planes of host data. The portion of the plurality of planes is smaller than the entire set of planes. For example, for the entire set of N planes, the portion includes N-1 planes of host data. In an embodiment, the portion of the plurality of planes does not include the last plane of host data. In an embodiment, the set of multi-plane parity data includes parity values ​​based on the N-1 planes of host data. For example, for a set of four planes, the set of multi-plane parity data is based on three planes of host data (e.g., plane 0, plane 1, and plane 2).

[0069] At operation 630, processing logic stores the set of multi-plane parity data in a cache memory of a controller of the memory subsystem. In an embodiment, storing the set of multi-plane parity data in the cache memory (based on N-1 planes of host data) requires less storage than storing the parity data based on all N planes of host data.

[0070] At operation 640, a second parity generation operation is performed based on a set of multiple planes of host data to generate a set of multi-page parity data. In an embodiment, multi-page parity data is generated for each page row based on all planes (N planes) of host data. Figure 3 At operation 650, processing logic stores the multi-page parity data in a cache memory of a controller of the memory subsystem.

[0071] At operation 660, processing logic performs a data recovery operation based on the set of multi-plane parity data and the set of multi-page parity data. In an embodiment, the data recovery operation is applied to the set of multi-plane parity data and the set of multi-page parity data to recover or reconstruct host data that contains errors due to a failure (e.g., one or more damaged data pages or blocks). Advantageously, the data recovery operation can be performed to provide multi-plane and multi-page parity protection using parity data stored in a cache memory of a controller with lower storage requirements compared to conventional systems. Because the multi-plane parity data is stored based on a portion (e.g., N-1 planes) of the total number of planes (e.g., N planes) of the data, a storage saving benefit is achieved.

[0072] In an embodiment, processing logic may perform operations 651-655 to generate and store multi-plane multi-sub-block parity data, as described above in conjunction with Figure 4 and 5 In operation 651, processing logic performs a third parity generation operation based on a first sub-block of a portion of a set of multiple planes of host data to generate a first set of multi-plane sub-block parity data. In an embodiment, each plane of the multiple planes includes multiple sub-blocks (e.g., sub-block (SB) 0, SB 1, etc.), wherein each sub-block includes multiple pages (e.g., three pages per sub-block). In an embodiment, the third parity generation operation is performed on a first sub-block of a portion of a set of multiple planes stored in a cache memory of a controller. The first sub-block is Figure 4 and 5 In the embodiment, the first sub-block is SB 0 (where X=1). In the embodiment, the third parity generation operation is an XOR operation using multiple planes.

[0073] In operation 652, processing logic performs a fourth parity generation operation based on a second sub-block of a portion of a set of multiple planes of host data to generate a second set of multi-plane sub-block parity data. In an embodiment, the second sub-block is Figure 4 and 5 denoted as SB X. In an embodiment, the second sub-block is SB 1 (where X=1). In an embodiment, the fourth parity generation operation is performed during or in response to the transfer of the second sub-block data from the controller write buffer to the memory device cache memory of the high-density memory device. Therefore, the second sub-block (SB 1) can be referred to as the "current" sub-block, and the first sub-block (SB 0) can be referred to as the "previous" sub-block. In an embodiment, the first sub-block and the second sub-block are a sub-block pair including the previous sub-block and the current sub-block (e.g., SB 0 and SB 1; SB 1 and SB 2; SB 2 and SB 3, etc.).

[0074] In operation 653 , processing logic performs a fifth parity generation operation based on the first set of multi-plane sub-block parity data and the second set of multi-plane sub-block parity data to generate a set of multi-plane multi-sub-block parity data.

[0075] In operation 654 , processing logic stores a set of multi-plane multi-sub-block parity data in a cache memory of a controller of the memory subsystem.

[0076] In operation 655, processing logic performs a data recovery operation based on the set of multi-plane multi-subblock parity data and the set of multi-page parity data. Note that in embodiments, operation 655 may be performed in response to identification of a failure in place of operation 660 to enable data recovery.

[0077] Figure 7An example machine of a computer system 700 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 host system 120) or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 The host system includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, digital or non-digital circuitry, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0080] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communicating over a network 720.

[0081] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, with the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0082] In one embodiment, instructions 726 include implementing instructions corresponding to a data protection component (e.g., Figure 1 The data protection component 113) is provided with functional instructions for the machine-readable storage medium 724. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods disclosed herein. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0083] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general purposes, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0084] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0085] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods. Structures for various such systems will be presented as shown in the following description. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0087] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0088] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for storage management of multi-plane parity check data, wherein include: receiving, by a processing device, host data to be written to a storage area comprising a set of a plurality of planes; performing a first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data; storing the set of multi-plane parity data in a cache memory of a controller of the memory subsystem; performing a second parity generation operation based on the set of multiple planes of the host data to generate a set of multi-page parity data; storing the set of multi-page parity data in the cache memory of the controller of the memory subsystem; as well as A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data. 2 . The method of claim 1 , wherein the portion of the set of multiple planes comprises less than a total number of planes of the host data.

3. The method of claim 1, further comprising performing a third parity generation operation based on a first sub-block of the portion of the set of multiple planes of the host data to generate a first set of multi-plane sub-block parity data.

4. The method of claim 3, further comprising performing a fourth parity generation operation based on a second sub-block of the portion of the set of multiple planes of the host data to generate a second set of multi-plane sub-block parity data.

5. The method of claim 4, further comprising performing a fifth parity generation operation based on the first set of multi-plane sub-block parity data and the second set of multi-plane sub-block parity data to generate a set of multi-plane multi-sub-block parity data.

6. The method of claim 1, wherein the first parity generation operation comprises an exclusive-OR (XOR) operation, and wherein the set of multi-plane parity data comprises a set of XOR parity values.

7. The method of claim 1, wherein the data recovery operation is performed to recover the host data in response to a failure.

8. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting errors associated with host data written to a page of a memory region of a memory subsystem comprising a set of a plurality of planes; performing a first parity generation operation based on a portion of the set of the plurality of planes of the host data to generate a first set of parity data; performing a second parity generation operation using the host data corresponding to a total number of the set of the plurality of planes to generate a second set of parity data; as well as A data recovery operation is performed based at least in part on the first set of parity data and the second set of parity data.

9. The non-transitory computer-readable medium of claim 8, wherein a first parity generation operation is performed using the host data corresponding to less than a total number of the set of multiple planes.

10. The non-transitory computer-readable medium of claim 8, wherein the second parity generation operation comprises the second set of parity data retrieved from a cache memory of a controller.

11. The non-transitory computer-readable medium of claim 10, wherein the second set of parity data comprises multiple pages of parity data.

12. The non-transitory computer-readable medium of claim 8, wherein the first set of parity data comprises a set of XOR parity values ​​corresponding to a portion of the host data comprising less than a total number of the set of multiple planes of the host data.

13. The non-transitory computer readable medium of claim 12, the operations further comprising: include: generating a third set of parity data based on the first sub-block of the portion of the host data; generating a fourth set of parity data based on a second sub-block of the portion of the host data; as well as A fifth set of parity data is generated based on the third set of parity data and the fourth set of parity data, wherein the data recovery operation is performed using the fifth set of parity data.

14. A computing system, include: Memory device; as well as a processing device operatively coupled to the memory device to perform operations including: receiving host data to be written to a storage area comprising a set of a plurality of planes; performing a first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data; storing the set of multi-plane parity data in a cache memory of a controller of the memory subsystem; performing a second parity generation operation based on the set of multiple planes of the host data to generate a set of multi-page parity data; storing the set of multi-page parity data in the cache memory of the controller of the memory subsystem; as well as A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

15. The computing system of claim 14, wherein the portion of the set of multiple planes comprises less than a total number of planes of the host data.

16. The computing system of claim 14, the operations further comprising performing a third parity generation operation based on a first sub-block of the portion of the set of multiple planes of the host data to generate a first set of multi-plane sub-block parity data.

17. The computing system of claim 16, the operations further comprising performing a fourth parity generation operation based on a second sub-block of the portion of the set of multiple planes of the host data to generate a second set of multi-plane sub-block parity data.

18. The computing system of claim 17, the operations further comprising performing a fifth parity generation operation based on the first set of multi-plane sub-block parity data and the second set of multi-plane sub-block parity data to generate a set of multi-plane multi-sub-block parity data.

19. The computing system of claim 14, wherein the first parity generation operation comprises an exclusive-OR (XOR) operation, and wherein the set of multi-plane parity data comprises a set of XOR parity values.

20. The computing system of claim 14, wherein the data recovery operation is performed to recover the host data in response to a failure.

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