Display device

Abstract

A display device includes: a display panel having a plurality of sub-pixels to display an image; a data driver for supplying image data to the plurality of sub-pixels; a gate driver for supplying a gate signal to the plurality of sub-pixels; a controller configured to convert a driving frequency of each of the data driver and the gate driver in a high frame rate mode; and a gamma voltage generator for generating a gamma voltage based on each driving frequency, respectively, wherein the controller is configured to generate a horizontal synchronization signal based on the driving frequency in the high frame rate mode. Therefore, even when a driving frequency conversion occurs, the image quality levels corresponding to the various driving frequencies can be kept consistent by applying the same operation duration to the various driving frequencies.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device that prevents brightness and color coordinates from being distorted during driving frequency conversion. Background Art

[0002] Image display devices that use screens to display various information are key technologies in the information communication era, and are developing towards thinner, lighter, portable and high-performance devices. Therefore, display devices that can be manufactured in a thin and light form are attracting attention. This display device is implemented as a flat self-luminous device, which not only has advantages in power consumption based on low voltage drive, but also has high response speed, high luminous efficiency, excellent viewing angle and excellent contrast, and is therefore being studied as a next-generation display. This display device uses a plurality of sub-pixels arranged in a matrix form to realize an image. Each of the plurality of sub-pixels includes a light-emitting element and a plurality of transistors that independently drive the light-emitting element.

[0003] Specific examples of flat panel display devices include liquid crystal display devices (LCD), quantum dot display devices (QD), field emission display devices (FED), organic light emitting display devices (OLED), etc. Among these flat panel display devices, organic light emitting display devices, which do not require a separate light source and are attracting attention as devices that are compact and display clear colors, have a fast response speed, high contrast, high luminous efficiency, high brightness, and a wide viewing angle due to the use of organic light emitting diodes (OLED).

[0004] The driving frequency can be automatically switched from SFR (Standard Frame Rate) to HFR (High Frame Rate) based on the type of image such as a still image or a moving image.

[0005] When the display device is driven at a standard frame rate, the period of each of the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be changed due to the switching of the driving frequency. For example, the period of each of the vertical synchronization signal and the horizontal synchronization signal when operating at a high frame rate of 90 Hz can be shorter than the period of each of the vertical synchronization signal and the horizontal synchronization signal when operating at a standard frame rate of 60 Hz.

[0006] In this way, as the period of each of the vertical synchronization signal and the horizontal synchronization signal changes, the duration of a horizontal period 1H may change, so that the operation duration of the sub-pixel may change. Therefore, even when the same gamma value is applied to the same RGB image data, the brightness and color coordinates may change due to the switching of the driving frequency. In other words, in order to prevent defects caused by changes in brightness and color coordinates during the driving frequency conversion, separate optical compensation for brightness and color coordinates should be performed for standard frame rate and high frame rate, respectively, to compensate for the brightness and color coordinate changes. Therefore, when separate optical compensation is performed at standard frame rate and high frame rate, respectively, the manufacturing process time of the display device is extended. Summary of the invention

[0007] An object of the present disclosure is to provide a display device configured to solve the above-mentioned problems, wherein a horizontal synchronization signal of the display device is generated based on a driving frequency of a high frame rate, and an intermediate frequency and an interpolated gamma voltage corresponding to the intermediate frequency are generated during a driving frequency conversion, thereby suppressing brightness and color coordinate distortion.

[0008] The purpose of the present disclosure is not limited to the above-mentioned purpose. Other purposes and advantages of the present disclosure not mentioned above can be understood from the following description and can be more clearly understood from the embodiments of the present disclosure. In addition, it will be easily understood that the purposes and advantages of the present disclosure can be achieved by the features disclosed in the claims and their combinations.

[0009] A display device according to an embodiment of the present disclosure includes: a display panel having a plurality of sub-pixels to display an image; a data driver for supplying image data to the plurality of sub-pixels; a gate driver for supplying a gate signal to the plurality of sub-pixels; a controller configured to convert a driving frequency of each of the data driver and the gate driver in a high frame rate mode; and a gamma voltage generator for generating a gamma voltage based on each driving frequency, respectively, wherein the controller is configured to generate a horizontal synchronization signal based on the driving frequency in the high frame rate mode.

[0010] In addition, a display device according to an embodiment of the present disclosure includes: a frequency converter, which is used to generate an intermediate frequency between the first driving frequency and the second driving frequency when converting the driving frequency from the first driving frequency to the second driving frequency; and a gamma voltage generator, which is used to generate a gamma voltage based on each of the first driving frequency and the second driving frequency, respectively, and store the gamma voltage based on each of the first driving frequency and the second driving frequency, respectively, in the gamma voltage generator, wherein the gamma voltage based on each of the first driving frequency and the second driving frequency, respectively, is stored as a pre-compensation value, wherein the gamma voltage corresponding to the intermediate frequency is a value interpolated between a first gamma voltage corresponding to the first driving frequency and a second gamma voltage corresponding to the second driving frequency.

[0011] According to the embodiments of the present disclosure, even when the driving frequency conversion occurs, it is possible to respectively keep the image quality levels corresponding to the various driving frequencies consistent by applying the same operation duration to the various driving frequencies.

[0012] Furthermore, by performing optical compensation only on a portion of various driving frequencies, the manufacturing process time of the device can be shortened to improve process efficiency.

[0013] Further specific effects of the present disclosure as well as the effects described above will be described in conjunction with illustrations of specific details for carrying out the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0015] Figure 2 is a diagram of a pixel circuit of a sub-pixel in a display device according to an embodiment of the present disclosure.

[0016] Figure 3 is a waveform diagram of each driving frequency in the display device according to an embodiment of the present disclosure.

[0017] Figure 4 is a diagram of a driving frequency conversion operation in a display device according to an embodiment of the present disclosure.

[0018] Figure 5 is a block diagram of the operation of each functional block in the display device according to an embodiment of the present disclosure.

[0019] Figure 6 is a diagram of an operation of a gamma voltage interpolator in a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] For simplicity and clarity of illustration, the elements in the figures are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements, and thus perform similar functions. The shapes, sizes, proportions, angles, quantities, etc., as disclosed in the drawings to illustrate examples of the present disclosure are exemplary and are not limited to the details shown in the present disclosure.

[0021] In addition, for simplicity of description, descriptions and details of well-known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, steps, components and circuits are not described in detail to avoid unnecessarily making various aspects of the present disclosure unclear.

[0022] Examples of various embodiments are further shown and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0023] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "an" are also intended to include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include", "comprise" and "have" when used in this specification specify the presence of the features, integers, operations, elements and / or components, but do not exclude the presence or increase of one or more other features, integers, operations, elements, components and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. When before a series of elements, expressions such as "at least one" can modify the entire column of elements, and the single element of the series may not be modified.

[0024] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0025] In addition, it will also be understood that when a first element is referred to as being “on” or “under” a second element, the first element may be directly disposed on or under the second element, or may be indirectly disposed on or under the second element via a third element disposed between the first element and the second element or between the first layer and the second layer.

[0026] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly on, connected to or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0027] In interpreting numerical values ​​in this disclosure, there can be an inherent range of error even if not individually expressly recited.

[0028] In the description of a temporal relationship, for example, when "after", "thereafter", "subsequently", "before", etc. is used, but when "immediately" or "right away" or "immediately" is not used, another event may occur between events that are adjacent in time.

[0029] The features of various examples of the present disclosure may be combined with each other in part or in whole and may be functionally related to each other. Various examples of the present disclosure may be implemented individually or in combination with each other.

[0030] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0031] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0032] Reference Figure 1According to an embodiment of the present disclosure, a display device 100 includes: a display panel 110, the display panel 110 includes a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, and a plurality of sub-pixels SP; a data driver 120, the data driver 120 is connected to the top or bottom of the display panel 110 and drives the plurality of data lines DL1 to DLm; a gate driver 130, the gate driver 130 is used to drive the plurality of gate lines GL1 to GLn; a ​​controller 140, the controller 140 is used to control the data driver 120 and the gate driver 130; a frequency converter 150, the frequency converter 150 is used to generate a driving frequency conversion signal Sf using a timing signal TS received from the controller 140; and a gamma voltage generator 160, the gamma voltage generator 160 is used to generate a gamma voltage based on the driving frequency conversion signal Sf and supply the gamma voltage to the data driver 120.

[0033] Reference Figure 1 , a plurality of sub-pixels SP are arranged in a matrix form on the display panel 110 .

[0034] Therefore, there are a plurality of sub-pixel lines in the display panel 110. The sub-pixel lines may be sub-pixel rows or sub-pixel columns. Hereinafter, the sub-pixel lines are referred to as sub-pixel rows.

[0035] The data driver 120 drives the plurality of data lines DL1 to DLm by supplying data voltages to the plurality of data lines DL1 to DLm. For this reason, the data driver 120 is referred to as a source driver. The gate driver 130 sequentially drives the plurality of gate lines GL1 to GLn by sequentially supplying scan signals to the plurality of gate lines GL1 to GLn. For this reason, the gate driver 130 is referred to as a scan driver.

[0036] The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 .

[0037] The controller 140 starts scanning based on the timing implemented in each frame, and converts the RGB image data RGB Data input from the outside into a data signal format suitable for use in the data driver 120, and outputs the converted RGBG image data RGBG Data, and controls data-related operations at appropriate scanning timing.

[0038] The gate driver 130 sequentially drives the plurality of gate lines GL1 to GLn by sequentially supplying scan signals to the plurality of gate lines GL1 to GLn under the control of the controller 140 .

[0039] According to the driving scheme or panel design scheme, the gate driver 130 may be located only on one side of the display panel 110 (eg Figure 1 As shown), or may be located at both sides of the display panel 110. In addition, the gate driver 130 may include at least one gate driver integrated circuit GDIC.

[0040] The data driver 120 may convert RGB image data RGB Data received from the controller 140 into data voltages in an analog form when a specific gate line is turned on, and may supply the data voltages to the plurality of data lines DL1 to DLm, thereby driving the plurality of data lines DL1 to DLm.

[0041] The data driver 120 may include at least one source driver integrated circuit SDIC to drive a plurality of data lines.

[0042] Each of the aforementioned gate driver integrated circuit and the aforementioned source driver integrated circuit can be connected to the bonding pad of the display panel 110 in a tape automated packaging (TAB) manner or a chip on glass (COG) manner, or can be directly set on the display panel 110, or can be integrated into the display panel 110.

[0043] Each source driver integrated circuit may include: a logic unit including a shift register, a latch circuit, etc., a digital-to-analog converter (DAC), an output buffer, etc. In some cases, the source driver integrated circuit may further include a sensing controller for sensing the characteristics of the sub-pixel to compensate for the characteristics of the sub-pixel (e.g., a threshold voltage Vth of a transistor, a threshold voltage Vth of an organic light emitting diode, brightness of a sub-pixel, etc.).

[0044] In addition, each source driver integrated circuit may be implemented in a chip on film (COF) manner. In this case, one end of each source driver integrated circuit is coupled to at least one source printed circuit board, and the other end thereof is coupled to the display panel 110.

[0045] In an example, the controller 140 may receive various timing signals TS including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, a clock signal (CLK), etc., and RGB image data RGB Data from an external component (eg, a host system).

[0046] As described above, the controller 140 converts the externally input RGB image data RGB Data into a data signal format suitable for use in the data driver 120, and outputs the converted RGBG image data RGBG Data. In addition, in order to control the data driver 120 and the gate driver 130, the controller 140 may receive a timing signal TS such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal, a clock signal CLK, and generate various control signals and output the control signals to the data driver 120 and the gate driver 130.

[0047] For example, in order to control the gate driver 130 , the controller 140 may output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc. to the gate driver 130 .

[0048] To this end, the gate start pulse GSP controls the operation start timing of at least one gate driver integrated circuit constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to at least one gate driver integrated circuit and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of at least one gate driver integrated circuit.

[0049] Furthermore, in order to control the data driver 120 , the controller 140 may output various data control signals DCS including a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, etc. to the data driver 120 .

[0050] To this end, the source start pulse SSP controls the data sampling start timing of at least one source driver integrated circuit constituting the data driver 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each source driver integrated circuit. The source output enable signal SOE controls the output timing of the data driver 120.

[0051] The controller 140 may be disposed on a control printed circuit board connected via a source printed circuit board to which at least one source driver integrated circuit is coupled through a flexible flat cable (FFC) or a flexible printed cable (FPC).

[0052] In addition, the controller 140 may be formed separately from the substrate, and as described above, the controller 140 may be disposed outside the substrate or may be formed integrally with the data driver 120. To this end, the data driver 120 may be implemented as a source driver integrated circuit formed on the substrate in a chip on film (COF) manner or in a chip on glass (COG) manner.

[0053] The inverter 150 may control the operation signal based on the driving frequency conversion signal Sf received from the controller 140 to apply the operation signal to the gate driver 130. The inverter 150 may be provided in the controller 140. However, the present disclosure is not limited thereto. According to design, the inverter 150 may be provided separately from the controller 140.

[0054] Based on the driving frequency conversion signal Sf, the gamma voltage generator 160 can supply a gamma voltage corresponding to the driving frequency to the data driver 120. For ease of explanation, the gamma voltage generator 160 is shown as being disposed separately from the data driver 120. However, the present disclosure is not limited thereto. According to design, the gamma voltage generator 160 can be disposed inside the data driver 120.

[0055] The display device 100 according to an embodiment of the present disclosure is implemented as an organic light emitting display device. Each sub-pixel SP thereof includes an organic light emitting diode OLED and a circuit element such as a transistor TFT to drive the diode. The type and number of circuit elements constituting each sub-pixel SP may be determined differently based on the provided functions and design choices.

[0056] Figure 2 is a diagram of a pixel circuit of a sub-pixel in a display device according to an embodiment of the present disclosure.

[0057] Reference Figure 2 , each sub-pixel SP arranged in the nth (n is a natural number) row may include a light emitting element EL, a driving transistor D-TFT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor Cstg. Each of the first to sixth transistors may be used as a switching transistor.

[0058] The light emitting element EL emits light using a driving current supplied by the driving transistor D-TFT. A multilayer organic compound stack may be formed between the anode and cathode of the light emitting element EL. The organic compound stack may include at least one hole transfer layer, at least one electron transfer layer and a light emitting layer EML. To this end, the hole transfer layer is used as a layer for injecting or transporting holes to the light emitting layer. For example, the hole transfer layer may include a hole injection layer HIL, a hole transport layer HTL, and an electron blocking layer EBL. The electron transfer layer is used as a layer for injecting or transporting electrons to the light emitting layer. For example, the electron transfer layer may include an electron transport layer ETL, an electron injection layer EIL, and a hole blocking layer HBL. The anode of the light emitting element EL may be connected to a third node N3. The cathode of the organic light emitting element may be connected to an input of a low level driving voltage EVSS.

[0059] The driving transistor DT may control a driving current to be applied to the light emitting element EL based on its source-gate voltage Vsg. A gate of the driving transistor D-TFT may be connected to a first node N1, a source of the driving transistor D-TFT may be connected to a fourth node N4, and a drain of the driving transistor D-TFT may be connected to a second node N2.

[0060] The first transistor T1 may be connected to the first node N1 and the second node N2 and disposed between the first node N1 and the second node N2, and may be turned on / off based on the nth scan signal SCAN(n). The gate of the first transistor T1 may be connected to the nth scan line to which the nth scan signal SCAN(n) is applied. The source of the first transistor T1 may be connected to the first node N1. The drain of the first transistor T1 may be connected to the second node N2. For this reason, the first transistor T1 may be referred to as a sampling transistor.

[0061] The second transistor T2 may be connected to the data line D(n) and the fourth node N4 and disposed between the data line D(n) and the fourth node N4, and may be turned on / off based on the nth scan signal SCAN(n). The gate of the second transistor T2 may be connected to the nth scan line to which the nth scan signal SCAN(n) is applied. The source of the second transistor T2 may be connected to the data line D(n). The drain of the second transistor T2 may be connected to the fourth node N4.

[0062] The third transistor T3 can be connected to the fourth node N4 and the input terminal of the high-level driving voltage EVDD and is arranged between the fourth node N4 and the input terminal of the high-level driving voltage EVDD, and can be turned on / off based on the nth emission control signal EM(n). The gate of the third transistor T3 can be connected to the nth emission line to which the nth emission control signal EM(n) is applied. The source of the third transistor T3 can be connected to the input terminal of the high-level driving voltage EVDD. The drain of the third transistor T3 can be connected to the fourth node N4.

[0063] The fourth transistor T4 may be connected to the second node N2 and the third node N3 and disposed between the second node N2 and the third node N3, and may be turned on / off based on the nth emission control signal EM(n). The gate of the fourth transistor T4 may be connected to the nth emission line to which the nth emission control signal EM(n) is applied. The source of the fourth transistor T4 may be connected to the second node N2. The drain of the fourth transistor T4 may be connected to the third node N3. For this reason, the fourth transistor T4 may be referred to as an emission transistor.

[0064] The fifth transistor T5 may be connected to the first node N1 and the input terminal of the initialization voltage Vini and be arranged between the first node N1 and the input terminal of the initialization voltage Vini, and may be turned on / off based on the (n-1)th scan signal SCAN(n-1). The gate of the fifth transistor T5 may be connected to the (n-1)th scan line to which the (n-1)th scan signal SCAN(n-1) is applied. The source of the fifth transistor T5 may be connected to the first node N1. The drain of the fifth transistor T5 may be connected to the input terminal of the initialization voltage Vini. For this reason, the fifth transistor T5 may be referred to as a first initialization transistor.

[0065] The sixth transistor T6 can be connected to the input terminal of the initialization voltage Vini and the third node N3 and arranged between the input terminal of the initialization voltage Vini and the third node N3, and can be turned on / off based on the nth scan signal SCAN(n). The gate of the sixth transistor T6 can be connected to the nth scan line to which the nth scan signal SCAN(n) is applied. The source of the sixth transistor T6 can be connected to the third node N3. The drain of the sixth transistor T6 can be connected to the input terminal of the initialization voltage Vini. For this reason, the sixth transistor T6 can be referred to as a second initialization transistor.

[0066] In addition, the capacitor Cstg may be connected to and disposed between the first node N1 and the input terminal of the initialization voltage Vini.

[0067] In the display device according to the embodiment of the present disclosure, each sub-pixel SP may include a light emitting element EL, a driving transistor D-TFT, first to sixth switching transistors, and a capacitor Cstg. However, the present disclosure is not limited thereto. The configuration of the sub-pixel SP may be freely modified according to the design.

[0068] Figure 3 is a waveform diagram of each driving frequency in the display device according to an embodiment of the present disclosure.

[0069] Figure 3 (a) in FIG. 1 is a waveform diagram of a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync in each of the SFR mode and the HFR mode. Figure 3 (b) is a waveform diagram of the horizontal synchronization signal Hsync and the light emitting operation in the standard frame rate (SFR) mode. Figure 3 (c) is a waveform diagram of the horizontal synchronization signal Hsync and the light emitting operation in the high frame rate (HFR) mode.

[0070] Reference Figure 3(a) in which the horizontal synchronization signal Hsync is generated according to the vertical synchronization signal Vsync. In the standard frame rate (SFR) mode, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are generated based on the corresponding driving frequency. Therefore, when the driving frequency changes, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can change. For example, when the driving frequency of 60Hz is switched to the driving frequency of 90Hz, the period of each of the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can change. Therefore, the duration of a single horizontal period 1H can change. Therefore, the operation duration of each sub-pixel SP can change.

[0071] On the other hand, in the high frame rate (HFR) mode, the horizontal synchronization signal Hsync can be generated according to the high frame rate (HFR) of 90Hz. Therefore, the period of the vertical synchronization signal Vsync when the display device is driven at a driving frequency of 60Hz is different from the period of the vertical synchronization signal Vsync when the display device is driven at a driving frequency of 90Hz. However, the horizontal synchronization signal Hsync can remain unchanged. To this end, within one cycle of the vertical synchronization signal Vsync, the duration after the horizontal synchronization signal Hsync generated according to the high frame rate (HFR) is terminated can be the holding duration of the previous frame being maintained, or it can be the blank duration during which no image is displayed.

[0072] Reference Figure 3 (b) to Figure 3 (c), the operation duration of the sub-pixel SP includes an initialization duration I, a sampling duration S, and a light emission duration E. The operation duration can be defined based on the (n-1)th scan signal SCAN(n-1), the nth scan signal SCAN(n), and the nth light emission control signal EM(n) applied to the sub-pixel SP. Each transistor constituting the sub-pixel SP is implemented as a PMOS transistor. Therefore, the low level is the on level, and the high level is the off level. In the following, for ease of description, the low level is defined as the on level, and the high level is defined as the off level.

[0073] The initialization duration I is included in the (n-1)th horizontal period H(n-1) allocated for writing data to the n-1th pixel row. For the initialization duration I, the (n-1)th scan signal SCAN(n-1) may be applied at an on level, and each of the nth scan signal SCAN(n) and the nth light emitting control signal EM(n) may be applied at an off level. The sampling duration S is included in the nth horizontal period H(n) allocated for writing data to the nth pixel row. For the sampling duration S, the nth scan signal SCAN(n) may be applied at an on level, and each of the (n-1)th scan signal SCAN(n-1) and the nth light emitting control signal EM(n) may be applied at an off level. The light emitting duration E may correspond to the remaining durations in one frame period except for the initialization duration I and the sampling duration S. For the light emission duration E, the nth light emission control signal EM(n) may be applied at a turn-on level, and each of the (n-1)th scan signal SCAN(n-1) and the nth scan signal SCAN(n) may be applied at a turn-off level.

[0074] The period of the horizontal synchronization signal Hsync generated based on the standard frame rate SFR and the period of the horizontal synchronization signal Hsync generated based on the high frame rate HFR are different from each other. When the horizontal synchronization signal Hsync is generated based on the high frame rate HFR and then applied to each of all driving frequencies, all signal operations thereof can be performed according to the same horizontal synchronization signal Hsync generated. Therefore, even when the driving frequency changes, the same operation duration can be applied. For example, when the horizontal synchronization signal Hsync is generated based on a driving frequency of 90Hz and applied to a driving frequency of 60Hz, the device can operate according to the same horizontal synchronization signal Hsync generated at a driving frequency of 60Hz. In addition, when the horizontal synchronization signal Hsync is generated based on a frequency of 120Hz and applied to driving frequencies of 60Hz and 90Hz, the device can operate according to the same horizontal synchronization signal Hsync generated at driving frequencies of 90Hz and 60Hz.

[0075] In other words, even when the driving frequency is switched between various driving frequencies, applying the same operation time period to all driving frequencies can make the image quality level at the various driving frequencies uniform.

[0076] In one example, a dummy duration D may be further included between the initialization duration I and the light emission duration E. For the dummy duration D, the nth scan signal SCAN(n) may be applied at an off level, and each of the (n-1)th scan signal SCAN(n-1) and the nth light emission control signal EM(n) may be applied at an off level. For the dummy duration D, the nth light emission control signal EM(n) is not applied at an on level, but is maintained at an off level for a certain duration, while the nth scan signal SCAN(n) is applied at an off level. Therefore, noise caused by a current change or a voltage change that may occur when the nth scan signal SCAN(n) and the nth light emission control signal EM(n) are synchronized with each other can be prevented.

[0077] Figure 4 is a diagram of a driving frequency conversion operation in a display device according to an embodiment of the present disclosure.

[0078] Reference Figure 4 , when performing driving frequency conversion, the display device 100 may have a transition duration for which a plurality of intermediate frequencies are generated and applied to a smooth image conversion.

[0079] In other words, it can be assumed that the driving frequencies of 60 Hz, 90 Hz and 120 Hz are respectively referred to as the first driving frequency f1, the second driving frequency f2 and the third driving frequency f3. When the first driving frequency f1 is changed to the second driving frequency f2, the frame switching is rapidly accelerated. Therefore, the change between the images displayed on the display panel 110 is not smooth. Therefore, noise, etc. may be observed. For this reason, a first intermediate frequency f12 greater than the first driving frequency f1 and less than the second driving frequency f2 or a second intermediate frequency f23 greater than the second driving frequency f2 and less than the third driving frequency f3 may be generated.

[0080] For example, when the first driving frequency f1 of 60 Hz is converted to the second driving frequency f2 of 90 Hz, the first intermediate frequency f12 of 75 Hz is generated and used to prevent sudden changes between the driving frequencies. In addition, when the second driving frequency f2 of 90 Hz is converted to the third driving frequency f3 of 120 Hz, the second intermediate frequency f23 of 105 Hz can be generated and used. On the contrary, in the conversion from the third driving frequency f3 to the second driving frequency f2 or from the second driving frequency f2 to the first driving frequency f1, the first intermediate frequency f12 or the second intermediate frequency f23 can be generated and applied.

[0081] To this end, optical compensation may be applied to the first to third driving frequencies f1, f2, and f3 of 60 Hz, 90 Hz, and 120 Hz, respectively, during the manufacturing process of the device. Therefore, the first to third gamma voltages corresponding to the first to third driving frequencies f1, f2, and f3, respectively, may be stored in the gamma voltage generator ( Figure 5 160). Therefore, the device can operate based on the first to third gamma voltages at the first to third driving frequencies f1, f2 and f3, respectively. However, the gamma voltage corresponding to the first intermediate frequency f12 and the second intermediate frequency f23 between the first to third driving frequencies f1, f2 and f3 can adopt the first value and the second value interpolated between the first to third gamma voltages corresponding to the first to third driving frequencies f1, f2 and f3, respectively. Then, the interpolated first value and the second value can be applied at the first intermediate frequency f12 and the second intermediate frequency f23, respectively. A scheme for generating interpolated gamma voltages corresponding to the intermediate frequencies will be described later.

[0082] Figure 5 is a block diagram of the operation of each functional block in the display device according to an embodiment of the present disclosure.

[0083] Reference Figure 5 The controller 140 receives various timing signals TS such as a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync, and RGB image data RGB Data from an external host system.

[0084] The controller 140 converts the RGB image data RGB Data into RGBG image data RGBG Data as a data signal format suitable for use in the data driver 120 and outputs the RGBG image data, and controls the data drive with an appropriate scanning timing. To this end, the RGBG image data RGBG Data can be a data signal format for a Pentile pixel structure. However, the present disclosure is not limited to this. The RGBG image data RGBG Data can have various data signal formats according to the design. In addition, the controller 140 can change the driving frequency based on the received RGB image data RGB Data and the timing signal TS.

[0085] The frequency converter 150 may generate a driving frequency conversion signal Sf using the timing signal TS received from the controller 140, and then may use the driving frequency conversion signal Sf to control the operation signal to be applied to the gate driver 130. The frequency converter 150 may be provided in the controller 140. However, the present disclosure is not limited thereto. The frequency converter 150 may be provided separately from the controller 140 according to design.

[0086] When the horizontal synchronization signal Hsync is generated based on the standard frame rate (SFR), all operation signals to be applied to the gate driver 130 may be changed based on the driving frequency conversion signal Sf. In addition, when the horizontal synchronization signal Hsync is generated based on the high frame rate (HFR), all operation signals to be applied to the gate driver 130 may be changed so that a certain duration in one cycle of the vertical synchronization signal Vsync is a hold duration or a blank duration.

[0087] The gamma voltage generator 160 may be configured to include a gamma voltage setter 161, an interpolation gamma voltage setter 162, and a gamma voltage selector 163. For ease of explanation, the gamma voltage generator 160 is shown as being configured separately from the data driver 120. However, the present disclosure is not limited thereto. The gamma voltage generator 160 may be disposed inside the data driver 120 according to design.

[0088] The gamma voltage setter 161 may include a first memory 1611 and a first selector 1612. The first memory 1611 may store a gamma voltage set GMA Setn corresponding to each driving frequency obtained via optical compensation. Based on the driving frequency conversion signal Sf, the first selector 1612 may select one of the gamma voltage sets GMA Setn stored in the first memory 1611, and output one of the selected gamma voltage sets GMA Setn to the gamma voltage selector 163.

[0089] The interpolation gamma voltage setter 162 may include a gamma voltage interpolator 1621, a second memory 1622, and a second selector 1623. The second memory 1622 may store an interpolation gamma voltage set IP GMA Setn-1 corresponding to each intermediate frequency between driving frequencies obtained via an interpolation method. Based on the driving frequency conversion signal Sf, the second selector 1623 may select one of the interpolation gamma voltage sets IP GMA Setn-1 stored in the second memory 1622, and output the selected one of the interpolation gamma voltage sets IP GMA Setn-1 to the gamma voltage selector 163.

[0090] Based on the driving frequency conversion signal Sf, the gamma voltage selector 163 may select a gamma voltage or an interpolated gamma voltage suitable for the corresponding driving frequency from the gamma voltages in the gamma voltage setter 161 or the interpolated gamma voltage setter 162 , and may supply the selected gamma voltage or the interpolated gamma voltage to the data driver 120 .

[0091] For example, during the manufacturing process of the display device 100, the gamma voltage setter 161 may apply optical compensation to the first to third driving frequencies f1, f2, and f3, such as 60 Hz, 90 Hz, and 120 Hz, in which a gamma voltage set GMA Setn corresponding to each driving frequency obtained through optical compensation is pre-stored. When driving the display device, the gamma voltage setter 161 may select a gamma voltage set based on the corresponding driving frequency, and may output one of the selected gamma voltage sets.

[0092] To this end, when the display device 100 is powered on, the interpolation gamma voltage setter 162 may generate interpolation gamma voltage sets IP GMA Set1 and IP GMA Set2 corresponding to the first intermediate frequency f12 and the second intermediate frequency f23 between the first to third driving frequencies f1, f2, and f3 with reference to each of the gamma voltage sets GMA Set1, GMA Set2, and GMA Set3 stored in the gamma voltage setter 161, and pre-store the interpolation gamma voltage sets IP GMA Set1 and IP GMA Set2 therein. Therefore, even when the driving frequency changes during driving, the pre-stored interpolation gamma voltage sets IP GMA Set1 and IP GMA Set2 may be immediately applied, thereby preventing operation delay.

[0093] The number of driving frequencies to which optical compensation is applied and the number of intermediate frequencies between adjacent driving frequencies may not be limited to the above examples. The number of driving frequencies to which optical compensation is applied may be n, and the number of intermediate frequencies between adjacent driving frequencies may be n-1.

[0094] Therefore, it is not necessary to optically compensate all driving frequencies in each step of driving frequency conversion. Therefore, the processing time can be shortened. In this way, efficient production of the device can be achieved.

[0095] Figure 6 is a diagram of an operation of a gamma voltage interpolator in a display device according to an embodiment of the present disclosure.

[0096] Figure 6 (a) in FIG. 1 is a table for explaining a scheme of calculating a compensation coefficient K using a proportional expression between driving frequencies and generating an interpolation gamma voltage set IP GMA Setn-1 using the compensation coefficient K. Figure 6 (b) in FIG. 1 is a table for explaining a scheme of directly receiving a compensation coefficient K from the outside and generating an interpolation gamma voltage set IP GMA Setn-1 using the compensation coefficient K.

[0097] Reference Figure 6In (a), the gamma voltage compensation coefficient K of the intermediate frequency can be calculated based on the difference between the frequency of the driving frequency and the intermediate frequency and the difference between the frequencies of adjacent driving frequencies. For example, the gamma voltage sets GMA Setn corresponding to the first to third driving frequencies f1, f2 and f3 to which optical compensation is applied are respectively referred to as α, β and γ. To this end, the compensation coefficient K of the first intermediate frequency f12 generated between the first driving frequency f1 and the second driving frequency f2 can be a value obtained by dividing the difference between the first driving frequency f1 and the first intermediate driving frequency f12 by the difference between the first driving frequency f1 and the second driving frequency f2. In other words, the compensation coefficient K of the first intermediate frequency f12 can be (f12-f1) / (f2-f1). The compensation coefficient K of the second intermediate frequency f23 generated between the second driving frequency f2 and the third driving frequency f3 can be calculated in the same manner.

[0098] The interpolation gamma voltage set IP GMA Setn-1 corresponding to the first and second intermediate frequencies f12 and f23 may be obtained by applying the calculated compensation coefficient K to the gamma voltage sets GMA Set corresponding to the first to third driving frequencies f1, f2, and f3.

[0099] Reference Figure 6 In (b), the compensation coefficient K of the intermediate frequency can be set by the user and input to the device. The compensation coefficients K corresponding to the first intermediate frequency f12 and the second intermediate frequency f23 input by the user can be i and j, respectively. The interpolation gamma voltage set IP GMA Setn-1 corresponding to the first intermediate frequency f12 and the second intermediate frequency f23 can be obtained by applying i and j to the gamma voltage set GMA Set corresponding to the first to third driving frequencies f1, f2 and f3.

[0100] The display device according to an embodiment of the present disclosure generates an intermediate frequency when the driving frequency is converted. To this end, the device can generate and apply an interpolated gamma voltage set corresponding to the intermediate frequency. This can prevent abrupt frequency conversion to achieve a smooth image conversion. In addition, optical compensation is only applied to a portion of all driving frequencies, thereby shortening the manufacturing process of the device and improving the manufacturing process of the device.

[0101] A display device according to the present disclosure may include the following aspects and embodiments.

[0102] A first aspect of the present disclosure provides a display device, comprising: a display panel having a plurality of sub-pixels for displaying an image; a data driver for supplying image data to the plurality of sub-pixels; a gate driver for supplying a gate signal to the plurality of sub-pixels; a controller configured to convert a driving frequency of each of the data driver and the gate driver in a high frame rate mode; and a gamma voltage generator for generating a gamma voltage based on each driving frequency, respectively, wherein the controller is configured to generate a horizontal synchronization signal based on the driving frequency in the high frame rate mode.

[0103] In one embodiment of the first aspect, the driving frequency includes a first driving frequency and a second driving frequency higher than the first driving frequency, wherein each of the gate driver and the data driver is configured to operate at the first driving frequency using a horizontal synchronization signal generated based on the second driving frequency.

[0104] In one embodiment of the first aspect, the controller includes a frequency converter, wherein the frequency converter is configured to generate a first intermediate frequency between the first driving frequency and the second driving frequency during a driving frequency conversion between the first driving frequency and the second driving frequency.

[0105] In one embodiment of the first aspect, a gamma voltage corresponding to the first intermediate frequency is obtained by: dividing a difference between the first driving frequency and the first intermediate driving frequency by a difference between the first driving frequency and the second driving frequency to obtain a compensation coefficient; and applying the compensation coefficient to a gamma voltage corresponding to the second driving frequency to obtain an interpolated gamma voltage, wherein the interpolated gamma voltage is a gamma voltage corresponding to the first intermediate frequency.

[0106] In one implementation of the first aspect, the gamma voltage generator includes a gamma voltage setter, an interpolation gamma voltage setter, and a gamma voltage selector.

[0107] In one embodiment of the first aspect, the gamma voltage setter includes a first memory and a first selector, wherein the first memory stores a plurality of gamma voltage sets corresponding to a plurality of driving frequencies, and wherein the first selector selects and outputs one of the plurality of gamma voltage sets based on a driving frequency selection signal.

[0108] In one implementation of the first aspect, the interpolated gamma voltage setter includes a gamma voltage interpolator, a second memory, and a second selector, wherein the gamma voltage interpolator generates an interpolated gamma voltage set corresponding to the intermediate frequency using a plurality of gamma voltage sets stored in the gamma voltage setter.

[0109] In one embodiment of the first aspect, each of the data driver and the gate driver is configured to operate at a plurality of driving frequencies based on the same horizontal synchronization signal.

[0110] In an implementation of the first aspect, the display panel has the same operation duration corresponding to the same horizontal synchronization signal at multiple driving frequencies.

[0111] In one implementation of the first aspect, the initialization voltage is equal to or lower than the low-level driving voltage.

[0112] A first aspect of the present disclosure provides a display device, comprising: a frequency converter, the frequency converter being used to generate a first intermediate frequency between a first driving frequency and a second driving frequency when converting a driving frequency from a first driving frequency to a second driving frequency; and a gamma voltage generator, the gamma voltage generator being used to generate a gamma voltage based on each of the first driving frequency and the second driving frequency, respectively, and to store the gamma voltages based on each of the first driving frequency and the second driving frequency, respectively, in the gamma voltage generator, wherein each gamma voltage based on each of the first driving frequency and the second driving frequency is stored as a pre-compensation value, wherein the gamma voltage corresponding to the intermediate frequency is a value interpolated between a first gamma voltage corresponding to the first driving frequency and a second gamma voltage corresponding to the second driving frequency.

[0113] In an embodiment of the second aspect, the second driving frequency is higher than the first driving frequency, wherein each of the gate driver and the data driver is configured to operate at the first driving frequency using a horizontal synchronization signal generated based on the second driving frequency.

[0114] In one implementation of the second aspect, the sub-pixels have the same operation duration at the first driving frequency and the second driving frequency.

[0115] In one embodiment of the second aspect, the gamma voltage corresponding to the first intermediate frequency is obtained by: dividing the difference between the first driving frequency and the first intermediate driving frequency by the difference between the first driving frequency and the second driving frequency to obtain a compensation coefficient; and applying the compensation coefficient to the gamma voltage corresponding to the second driving frequency to obtain an interpolated gamma voltage, wherein the interpolated gamma voltage is a gamma voltage corresponding to the first intermediate frequency.

[0116] In one implementation of the second aspect, the compensation coefficient is not calculated based on the driving frequency, but is preset.

[0117] In an implementation of the second aspect, the gamma voltage generator includes a gamma voltage setter, an interpolation gamma voltage setter, and a gamma voltage selector.

[0118] In one embodiment of the second aspect, the gamma voltage setter includes a first memory and a first selector, wherein the first memory stores multiple gamma voltage sets corresponding to multiple driving frequencies, and wherein the first selector selects and outputs one of the multiple gamma voltage sets based on a driving frequency selection signal.

[0119] In one implementation of the second aspect, the interpolated gamma voltage setter includes a gamma voltage interpolator, a second memory, and a second selector, wherein the gamma voltage interpolator generates an interpolated gamma voltage set corresponding to the intermediate frequency using a plurality of gamma voltage sets stored in the gamma voltage setter.

[0120] In one embodiment of the second aspect, the gamma voltage selector is configured to: select and output a gamma voltage from a gamma voltage set in a gamma voltage setter based on a driving frequency conversion signal; and / or select and output an interpolation gamma voltage from an interpolation gamma voltage set in an interpolation gamma voltage setter.

[0121] In one embodiment of the second aspect, the controller is configured to convert RGB image data received from an external host system into RGBG image data and then output the RGBG image data.

[0122] The features, structures, effects, etc. described above in the present disclosure are included in at least one example of the present disclosure and are not necessarily limited to one example. In addition, the features, structures, effects, etc. illustrated in at least one example of the present disclosure may be applied to other examples by those skilled in the art in a combined or modified manner. These combinations and modifications should be interpreted as being included within the scope of the present disclosure.

[0123] The present disclosure as described above is not limited to the above-described embodiments and drawings. It will be apparent to those skilled in the art that various substitutions, modifications and variations may be made thereto without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure is indicated by the appended claims. The meaning and scope of the claims and variations or modifications derived therefrom shall be interpreted as being included within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel having a plurality of sub-pixels for displaying an image; a data driver configured to supply image data to the plurality of sub-pixels; a gate driver configured to supply a gate signal to the plurality of sub-pixels; a controller configured to convert a driving frequency of each of the data driver and the gate driver in a high frame rate mode; as well as a gamma voltage generator for generating a gamma voltage based on each driving frequency, respectively, wherein the controller is configured to generate a horizontal synchronization signal based on the driving frequency in the high frame rate mode, The driving frequency includes a first driving frequency and a second driving frequency higher than the first driving frequency, and Wherein, each of the gate driver and the data driver is configured to operate at the first driving frequency using the horizontal synchronization signal generated based on the second driving frequency.

2. The display device according to claim 1, wherein: The controller includes a frequency converter, and The frequency converter is configured to generate an intermediate frequency between the first driving frequency and the second driving frequency during a driving frequency conversion between the first driving frequency and the second driving frequency.

3. The display device according to claim 2, wherein: The gamma voltage corresponding to the intermediate frequency is obtained by: dividing a difference between the first driving frequency and the first intermediate driving frequency by a difference between the first driving frequency and the second driving frequency to obtain a compensation coefficient; and The compensation coefficient is applied to a gamma voltage corresponding to the second driving frequency to obtain an interpolated gamma voltage, wherein the interpolated gamma voltage is the gamma voltage corresponding to the intermediate frequency.

4. The display device according to claim 1, wherein: The gamma voltage generator includes a gamma voltage setter, an interpolation gamma voltage setter, and a gamma voltage selector.

5. The display device according to claim 4, wherein: The gamma voltage setter includes a first memory and a first selector, The first memory stores a plurality of gamma voltage sets corresponding to a plurality of driving frequencies. The first selector selects and outputs one of the plurality of gamma voltage sets based on a driving frequency selection signal.

6. The display device according to claim 5, wherein: The interpolation gamma voltage setter includes a gamma voltage interpolator, a second memory, and a second selector. The gamma voltage interpolator generates an interpolated gamma voltage set corresponding to an intermediate frequency using the plurality of gamma voltage sets stored in the gamma voltage setter.

7. The display device according to claim 1, wherein: Even if the driving frequency is changed, each of the data driver and the gate driver is configured to operate based on the same horizontal synchronization signal.

8. The display device according to claim 7, wherein: The display panels have the same operation duration corresponding to the same horizontal synchronization signal.

9. The display device according to claim 1, wherein: The initialization voltage is equal to or lower than the low-level driving voltage.

10. A display device, comprising: a frequency converter, the frequency converter being configured to generate an intermediate frequency between the first driving frequency and the second driving frequency when converting the driving frequency from the first driving frequency to the second driving frequency; as well as a gamma voltage generator for generating a gamma voltage based on each of the first driving frequency and the second driving frequency, respectively, and for storing the gamma voltage based on each of the first driving frequency and the second driving frequency, respectively, in the gamma voltage generator, wherein a gamma voltage based on each of the first driving frequency and the second driving frequency is stored as a pre-compensation value, wherein the gamma voltage corresponding to the intermediate frequency is a value interpolated between a first gamma voltage corresponding to the first driving frequency and a second gamma voltage corresponding to the second driving frequency, Wherein, the second driving frequency is higher than the first driving frequency, Wherein, each of the gate driver and the data driver is configured to operate at the first driving frequency using a horizontal synchronization signal generated based on the second driving frequency.

11. The display device according to claim 10, wherein: The sub-pixel has the same operation duration at the first driving frequency and the second driving frequency.

12. The display device according to claim 10, wherein: The gamma voltage corresponding to the intermediate frequency is obtained by: dividing a difference between the first driving frequency and the first intermediate driving frequency by a difference between the first driving frequency and the second driving frequency to obtain a compensation coefficient; and The compensation coefficient is applied to a gamma voltage corresponding to the second driving frequency to obtain an interpolated gamma voltage, wherein the interpolated gamma voltage is the gamma voltage corresponding to the intermediate frequency.

13. The display device according to claim 12, wherein: The compensation coefficient is not calculated based on the driving frequency but is preset.

14. The display device according to claim 10, wherein: The gamma voltage generator includes a gamma voltage setter, an interpolation gamma voltage setter, and a gamma voltage selector.

15. The display device according to claim 14, wherein: The gamma voltage setter includes a first memory and a first selector, The first memory stores a plurality of gamma voltage sets corresponding to a plurality of driving frequencies. The first selector selects and outputs one of the plurality of gamma voltage sets based on a driving frequency selection signal.

16. The display device according to claim 15, wherein: The interpolation gamma voltage setter includes a gamma voltage interpolator, a second memory, and a second selector. The gamma voltage interpolator generates an interpolated gamma voltage set corresponding to the intermediate frequency using the plurality of gamma voltage sets stored in the gamma voltage setter.

17. The display device according to claim 16, wherein: The gamma voltage selector is configured as: selecting and outputting a gamma voltage from the gamma voltage set in the gamma voltage setter based on a driving frequency conversion signal; and / or An interpolation gamma voltage is selected and output from the interpolation gamma voltage set in the interpolation gamma voltage setter.

18. The display device according to claim 10, wherein: The controller is configured to convert RGB image data received from an external host system into RGBG image data and then output the RGBG image data.

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